M443929 t . • 五、新型說明： !. 【新型所屬之技術領域】 < 本創作為一種薄膜電晶體基板，特別是有關於一種低 線路阻抗的薄膜電晶體基板。 【先前技術】 - 近年來’隨半導體製程技術的進步，薄膜電晶體基板 . 的製造越來越容易及快速。 φ 圖1 a為習知薄膜電晶體基板部份平面示意圖。圖1 a 中的AB線段之剖面在圖1 b中顯示。圖1 a中的CD線段之 4面在圖lc中顯示。如圖ia所示，薄臈電晶體基板9包 括複數條資料線91以及複數條掃描線92。每相鄰兩條的 資料線91和每相鄰兩條的掃描線92所圍成之區域為一畫 素93 ’每一畫素93都有一薄膜電晶體。 凊同時參閱圖lb及圖lc。在基板94上形成掃描線 92。然後，閘極絕緣層（㈣以麵㈣的㈣叫的形成在基板 φ 94上，並覆蓋該掃描線92。然後，於閘極絕緣層95上形 成:貝料線91。最後，保護層（passivation layer)96形成在閘 極絕緣層95上’並覆蓋資料線91。 然而，隨著液晶顯示器的尺寸越做越大，其解析度越 尚，薄膜電晶體基板上的資料線及掃描線的數量明顯增 加’導致線路的總阻抗因而增加，使整個晝素電路的充放 電時間變長，晝素電路的反應速度變慢。 因此，便有需要提供一種線路電阻較低的薄膜電晶體 基板，以解決前述的問題。 M443929 . ·, 【新型内容】 本創作提供一種薄膜電晶體基板，包括：一基板；複 數條掃描線，形成在該基板上；複數條資料線，與該掃描 線相互垂直；複數個薄膜電晶體，位在該些掃描線上，且 相鄰兩條資料線之間；以及複數段導體，分別電性連接相 對應該些掃描線及/或該些資料線，其中該些導體由圖案化 金屬氧化物層摻雜還原性氣體而形成。 因此，本創作的特點在於最主要是利用製程的過程 中，在沉積保護層時所產生的還原性氣體（例如氫氣）會和 金屬氧化物（例如銦鎵鋅氧化物）產生化學反應，使銦鎵鋅 氧化物因為氩氣的摻雜由原本的半導體變成導體的特性， 將它運用在晝素電路的掃描線和資料線上，使得金屬導線 與導體化的銦鎵鋅氧化物相互電性連接，達到降低晝素電 路的阻抗，使整個畫素電路的充放電時間變短，晝素電路 的反應速度上升，尤其在大尺寸的液晶顯示器上，其畫面 的均勻度提升。 為了讓本創作之上述和其他目的、特徵、和優點能更 明顯，下文將配合所附圖示，作詳細說明如下。 【實施方式】 如圖2a所示，為本創作之第一實施例之薄膜電晶體基 板部份平面示意圖。圖2a中的AB線段之剖面在圖2b中 顯示；圖2a中的CD線段之剖面在圖2c中顯示。 薄膜電晶體基板1包括複數個薄膜電晶體18、複數條 資料線11、複數條掃描線12以及複數段導體170。該些資 4 M443929 . 料線11與該些掃描線12相互垂直。每相鄰兩條資料線11 和每相鄰兩條掃描線12所圍成之區域為一畫素13，每一 晝素13都有一薄膜電晶體18，其中該薄膜電晶體18位在 該掃描線12上與每相鄰兩條該資料線11之間。該導體170 位在該資料線11下方，且該導體170電性連接該資料線 11。但為了方便說明圖2a僅顯示一薄膜電晶體18、一接觸 窗19、一資料線11、一掃描線12、一導體170及一晝素 13，畫素13透過接觸窗19與薄膜電晶體18的汲極lib電 性連接。 如圖2b所示，為薄膜電晶體18之剖面圖。在基板14 上形成閘極12a。掃描線12和閘極12a可藉由同一製程和 材料而形成。然後，於基板14上形成閘極絕緣層15(gate insulation layer)，並覆蓋該閘極12a。接著，於閘極絕緣層 15上形成圖案化金屬氧化物層171a以及在圖案化金屬氧 化物層171a的中間位置上方形成蝕刻停止層173，亦即圖 案化金屬氧化物層171a位在閘極絕緣層15與蝕刻停止層 173之間。而後，在閘極絕緣層15上形成源極11a和汲極 lib，並覆蓋圖案化金屬氧化物層171a以及該蝕刻停止層 173之兩側。最後在源極11a和汲極lib上形成保護層 (passivation layer)，並覆蓋钱刻停止層173。畫素13透過 接觸窗19與薄膜電晶體18的汲極lib電性連接。其中， 圖案化金屬氧化物層171a形成方法包括薄膜沈積製程、微 影製程以及蝕刻製程等製程。 5 M443929 > 如圖2c所示，在基板14上形成閘極絕緣層15。閘極 絕緣層15的材質例如：二氧化矽、氮化矽或是氮氧化矽等 介電材料。其形成方法可為化學氣相沈積法。 在閘極絕緣層15上形成另一圖案化金屬氧化物層 171b。圖案化金屬氧化物層171b的材料包括銦鋅氧化物 (InZnO’簡稱IZO)或銦鎵鋅氧化物(InGaZn0,簡稱IGZ〇)。 在本創作之實施例中，是以銦鎵鋅氧化物作為圖案化金屬 φ 氧化物層nit)的材料。圖案金屬氧化物層171b與薄膜電 晶體18的圖案化金屬氧化物層171a可藉由同一製程和材 料而形成。 _在圖案化金屬氧化物層171b的中央位置的上方形成 貝料線11，使圖案化金屬氧化物層171b的左右兩端不被 為料線11覆蓋。資料線11、源極lla和汲極llb可藉由同 一製程和材料而形成。資料線u的材料例如：鋁、鉻、钽 或其他金屬材料。其形成方法包括薄膜沈積製程 、微影製 籲程以及姓刻製程等製程。姓刻製裎又分為是使用電聚的乾 式蝕刻製程或是使用蝕刻液的濕式蝕刻製程。 保濩層16形成在資料線丨丨上，並覆蓋資料線丨丨與圖 ’案化金屬氧化物層171b。在本創作之實施例中，保護層16 的材料是氧化石夕，其形成的方法是使用電聚化學氣相沈積 法該方法在沉積保護層16時會產生還原性氣體172，例 如氫氣，還原性氣體172與銦鎵鋅氧化物產生化學反應， 使銅鎵鋅氧化物由半導體變成導體17〇，使該導體電 性連接該資料線U，藉以降低資料線11的阻抗。 6 M443929 f ' 如圖3a所示，為本創作之第二實施例之薄膜電晶體部 份平面基板示意圖。圖3a中的AB線段之剖面在圖3b中 顯示。 如圖3a所示，薄膜電晶體基板2包括複數個薄膜電晶 體28、複數條資料線21、複數條掃描線22以及複數段導 體270。複數條資料線21與該掃描線22相互垂直。每相 鄰兩條的資料線21和每相鄰兩條的掃描線22所圍成之區 域為一畫素23，每一畫素23都有一薄膜電晶體28，其中 該薄膜電晶體28位在該掃描線22上與每相鄰兩條該資料 線21之間。該導體270位在該資料線21與該基板24之間， 且該資料線21覆蓋該導體270，使該資料線21電性連接 該導體270。但為了方便說明，圖3a僅顯示一資料線21、 一掃描線22、一薄膜電晶體28、一導體270及一畫素23。 薄膜電晶體28的結構如第一實施例所示，在此不於贅述。 如圖3b所示，於基板24上形成閘極絕緣層25。形成 方式以及材料如第一實施例所示，在此不於贅述。 圖案化金屬氧化物層271形成在閘極絕緣層25上，並 加入一摻雜製程，該摻雜製程為將該圖案化金屬氧化物層 271摻雜一還原性氣體272，使該圖案化金屬氧化物層271 由半導體變成一導體270。該圖案金屬氧化物層271可為 铟鋅氧化物或銦鎵鋅氧化物，該還原性氣體272可為氫 氣，但不以此為限。 資料線21形成在閘極絕緣層25上，並覆蓋該導體 270。保護層26形成在閘極絕緣層25上，並覆蓋資料線 7 M443929 … 21。上述的形成方式以及材料如第一實施所示，在此不於 贅述。 如圖4a所示，為本創作之第三實施例之薄膜電晶體基 板部份平面示意圖。圖4a中的AB線段之剖面在圖4b中 顯示。 薄膜電晶體基板3包括複數個薄膜電晶體39、複數條 資料線31、複數條掃描線32以及複數段導體370。該些資 料線31與該些掃描線32相互垂直。每相鄰兩條的資料線 ® 31和每相鄰兩條的掃描線32所圍成之區域為一晝素33, 每一晝素33都有一薄膜電晶體39。該導體370藉由一貫 穿孔38電性連接該掃描線32。但為了方便說明圖4a僅顯 示一資料線31、一掃描線32、一導體370、一薄膜電晶體 39、一貫穿孔38及一晝素33。薄膜電晶體39的結構如第 一實施例所示，在此不於贅述。 如圖4b所示，在基板34上形成掃描線32。該基板34 可以是玻璃基板、石英基板或是其他的基板。該掃描線32 ® 的材料例如：铭、鉻、组或其他金屬材料。其形成方法包 括薄膜沈積製程、微影製程以及蝕刻製程。 閘極絕緣層35形成在基板34上，並覆蓋掃描線32。 該閘極絕緣層35藉由一蝕刻製程而形成有一貫穿孔38， 使該貫穿孔38位在該掃描線32之中央位置上方。閘極絕 緣層35的材質例如：二氧化矽、氮化矽或是氮氧化矽等介 電材料。其形成方法可為化學氣相沈積法。圖案化金屬氧 化物層371形成在閘極絕緣層35上，該圖案化金屬氧化物 8 M443929 , 層371藉由該貫穿孔38電性連接該掃描線32。 保護層36形成在閘極絕緣層35上，並覆蓋圖案化金 屬氧化物層371。在本創作之實施例中，保護層36的材料 是氧化矽，其形成的方法是使用電漿化學氣相沈積法。該 方法在沉積保護層36時會產生還原性氣體372,例如氫 氣，還原性氣體372與圖案化金屬氧化物層371產生化學 反應，使圖案化金屬氧化物層371由半導體變成一導體 370，藉以降低資料線32的阻抗。 如圖5所示，為本創作之第四實施例之薄膜電晶體基 板部份平面示意圖。薄膜電晶體基板4包括複數個薄膜電 晶體（圖未示）、複數條資料線41、複數條掃描線42以及複 數段導體44。複數條資料線41與複數條掃描線42相互垂 直。每相鄰兩條的資料線41和每相鄰兩條的掃描線42所 圍成之區域為一畫素43，每一晝素43都有一薄膜電晶體 (圖未示）。該導體44位在該資料線41下方，且電性連接 該資料線41。該導體44位在該掃描線42上方，並藉由一 貫穿孔45電性連接該掃描線42。但是該導體44不位在掃 描線42與資料線41的交越處。薄膜電晶體（圖未示）的結 構如第一實施例所示，在此不於贅述。 資料線41與導體44的結構和形成方法請參考本發明 第一實施例；掃描線42與導體44的結構和形成方法請參 考本發明第三實施例，在此不於贅述。 如圖6所示，為本創作之第五實施例之薄膜電晶體基 板部份平面示意圖。薄膜電晶體基板5包括複數個薄膜電 9 M443929 f 晶體（圖未示）、複數條資料線51、複數條掃描線52以及複 數段導體54。複數條資料線51與該掃描線52相互垂直。 每相鄰兩條的資料線51和每相鄰兩條的掃描線52所圍成 之區域為一畫素53,每一晝素53都有一薄膜電晶體（圖未 示）。該資料線51覆蓋該導體54,該導體54電性連接該資 料線51。該導體54位在該掃描線52上方，並藉由一貫穿 孔55電性連接該掃描線52。但是該導體54不位在掃描線 52與資料線51的交越處。薄膜電晶體（圖未示）的結構如第 ® -實施例所示，在此不於贅述。 資料線51與導體54的結構和形成方法請參考本發明 第二實施例；掃描線52與導體54的結構和形成方法請參 考本發明第三實施例，在此不於贅述。 因此，本創作的特點在於最主要是利用製程的過程 中，在沉積保護層時所產生的還原性氣體（例如氫氣）會和 金屬氧化物（例如銦鎵鋅氧化物）產生化學反應，使銦鎵鋅 氧化物因為氫氣的摻雜由原本的半導體變成導體的特性， ® 將它運用在晝素電路上的掃描線和資料線，使得金屬導線 與導體化的銦鎵鋅氧化物相互電性連接，達到降低晝素電 路的阻抗，使整個畫素電路的充放電時間變短，晝素電路 的反應速度上升，尤其在大尺寸的液晶顯示器上，其晝面 的均句度提升。 綜上所述，乃僅記載本創作為呈現解決問題所採用的 技術手段之實施方式或實施例而已，並非用來限定本創作 專利實施之範圍。即凡與本創作專利申請範圍文義相符， 10 M443929 , ‘· 或依本創作專利範圍所做的均等變化與修飾，皆為本創作 ' 專利範圍所涵蓋。 【圖式簡單說明】 圖1&為習知薄膜電晶體基板部份平面示意圖； 圖lb為習知資料線之剖面圖； 圖1C為習知掃描線之剖面圖； 圖2a為本創作之第一實施例之薄膜電晶體基板部份平面 示意圖； 圖2b為本創作之第一實施例薄膜電晶體之剖面圖； φ 圖2c為本創作之第一實施例資料線之剖面圖； 圖3a為本創作之第二實施例之薄膜電晶體基板部份平面 示意圖； 圖3b為本創作之第二實施例資料線之剖面圖； 圖4a_為本創作之第三實施例之薄臈電晶體基板部份平面 示意圖； 圖4b為本創作之第三實施例掃描線之剖面圖； 圖5為本創作之第四實施例之薄膜電晶體基板部份平面示 意圖；以及 _圖6為本創作之第五實施例之薄膜電晶體基板部份平面示 意圖。 12 M443929M443929 t . • V. New description: !. [New technology field] < This is a thin film transistor substrate, especially a thin film transistor substrate with low line impedance. [Prior Art] - In recent years, with the advancement of semiconductor process technology, the manufacture of thin film transistor substrates has become easier and faster. φ Figure 1 a is a schematic plan view of a portion of a conventional thin film transistor substrate. The section of line AB in Figure 1a is shown in Figure 1b. The four sides of the CD line segment in Figure 1a are shown in Figure lc. As shown in Fig. ia, the thin germanium transistor substrate 9 includes a plurality of data lines 91 and a plurality of scanning lines 92. The area surrounded by each adjacent two data lines 91 and each adjacent two scanning lines 92 is a picture 93'. Each pixel 93 has a thin film transistor.凊 See also Figure lb and Figure lc. A scan line 92 is formed on the substrate 94. Then, the gate insulating layer ((4) is formed on the substrate φ 94 by the surface (4) of the surface (4), and covers the scanning line 92. Then, a gate line 91 is formed on the gate insulating layer 95. Finally, the protective layer ( A passivation layer 96 is formed on the gate insulating layer 95 and covers the data line 91. However, as the size of the liquid crystal display becomes larger, the resolution thereof is higher, and the data lines and scan lines on the thin film transistor substrate The significant increase in the number leads to an increase in the total impedance of the line, which makes the charging and discharging time of the entire halogen circuit longer, and the reaction speed of the halogen circuit becomes slower. Therefore, there is a need to provide a thin film transistor substrate having a low line resistance. In order to solve the aforementioned problems, M443929. [New Content] The present invention provides a thin film transistor substrate, comprising: a substrate; a plurality of scanning lines formed on the substrate; and a plurality of data lines perpendicular to the scanning lines a plurality of thin film transistors positioned on the scan lines and between adjacent two data lines; and a plurality of segments of conductors electrically connected to corresponding scan lines and/or a data line in which the conductors are formed by doping a reducing gas with a patterned metal oxide layer. Therefore, the present invention is characterized in that the most important is the use of a reducing gas generated during deposition of the protective layer during the process of the process ( For example, hydrogen) will chemically react with metal oxides (such as indium gallium zinc oxide), so that the indium gallium zinc oxide is converted from the original semiconductor to the conductor due to the doping of argon, and it is applied to the scanning of the halogen circuit. The wire and the data line electrically connect the metal wire and the conductive indium gallium zinc oxide to reduce the impedance of the halogen circuit, shorten the charging and discharging time of the entire pixel circuit, and increase the reaction speed of the halogen circuit. In particular, in the case of a large-sized liquid crystal display, the uniformity of the screen is improved. In order to make the above and other objects, features, and advantages of the present invention more apparent, the following description will be made in conjunction with the accompanying drawings. 2a is a schematic plan view of a portion of a thin film transistor substrate according to a first embodiment of the present invention. FIG. 2a is a section of the AB line segment. This is shown in Figure 2b; the cross-section of the CD line segment in Figure 2a is shown in Figure 2c. The thin film transistor substrate 1 comprises a plurality of thin film transistors 18, a plurality of data lines 11, a plurality of scan lines 12, and a plurality of segments of conductors 170. The material line 11 and the scanning lines 12 are perpendicular to each other. The area surrounded by each adjacent two data lines 11 and each adjacent two scanning lines 12 is a pixel 13, each element 13 has a thin film transistor 18, wherein the thin film transistor 18 is located between the scan line 12 and each adjacent two of the data lines 11. The conductor 170 is located below the data line 11, and the conductor 170 is electrically The data line 11 is connected. However, for convenience of description, FIG. 2a shows only a thin film transistor 18, a contact window 19, a data line 11, a scan line 12, a conductor 170 and a halogen 13, and the pixel 13 is in contact. The window 19 is electrically connected to the drain lib of the thin film transistor 18. As shown in Fig. 2b, it is a cross-sectional view of the thin film transistor 18. A gate 12a is formed on the substrate 14. Scan line 12 and gate 12a can be formed by the same process and materials. Then, a gate insulating layer 15 is formed on the substrate 14 and covers the gate 12a. Next, a patterned metal oxide layer 171a is formed on the gate insulating layer 15, and an etch stop layer 173 is formed over the intermediate position of the patterned metal oxide layer 171a, that is, the patterned metal oxide layer 171a is insulated at the gate. Between the layer 15 and the etch stop layer 173. Then, a source electrode 11a and a drain lib are formed on the gate insulating layer 15, and both sides of the patterned metal oxide layer 171a and the etch stop layer 173 are covered. Finally, a passivation layer is formed on the source 11a and the drain lib, and the stop layer 173 is covered. The pixel 13 is electrically connected to the drain lib of the thin film transistor 18 through the contact window 19. The method for forming the patterned metal oxide layer 171a includes a thin film deposition process, a photolithography process, and an etching process. 5 M443929 > As shown in FIG. 2c, a gate insulating layer 15 is formed on the substrate 14. The material of the gate insulating layer 15 is, for example, a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride. The formation method may be a chemical vapor deposition method. Another patterned metal oxide layer 171b is formed on the gate insulating layer 15. The material of the patterned metal oxide layer 171b includes indium zinc oxide (InZnO' for short) or indium gallium zinc oxide (InGaZn0, IGZ for short). In the embodiment of the present invention, indium gallium zinc oxide is used as the material of the patterned metal φ oxide layer nit). The patterned metal oxide layer 171b and the patterned metal oxide layer 171a of the thin film transistor 18 can be formed by the same process and materials. The bead line 11 is formed above the center position of the patterned metal oxide layer 171b so that the left and right ends of the patterned metal oxide layer 171b are not covered by the material line 11. The data line 11, the source 11a, and the drain 11b can be formed by the same process and materials. The material of the data line u is, for example, aluminum, chromium, ruthenium or other metal materials. The formation method includes a thin film deposition process, a micro-shadowing process, and a process of surname engraving. The surname is also divided into a dry etching process using electropolymerization or a wet etching process using an etching solution. The protective layer 16 is formed on the data line and covers the data line 丨丨 and the patterned metal oxide layer 171b. In the embodiment of the present invention, the material of the protective layer 16 is oxidized stone, which is formed by electropolymerization chemical vapor deposition. This method generates a reducing gas 172, such as hydrogen, when the protective layer 16 is deposited. The gas 172 chemically reacts with the indium gallium zinc oxide to change the copper gallium zinc oxide from the semiconductor to the conductor 17 , and electrically connects the conductor to the data line U, thereby reducing the impedance of the data line 11. 6 M443929 f ' is a schematic view of a planar substrate of a thin film transistor according to a second embodiment of the present invention, as shown in FIG. 3a. The section of line AB in Figure 3a is shown in Figure 3b. As shown in Fig. 3a, the thin film transistor substrate 2 includes a plurality of thin film electromorphs 28, a plurality of data lines 21, a plurality of scanning lines 22, and a plurality of segments 270. The plurality of data lines 21 and the scanning lines 22 are perpendicular to each other. The area enclosed by each adjacent two data lines 21 and each adjacent two scanning lines 22 is a single pixel 23, and each pixel 23 has a thin film transistor 28, wherein the thin film transistor 28 is located at The scan line 22 is between each adjacent two of the data lines 21. The conductor 270 is located between the data line 21 and the substrate 24, and the data line 21 covers the conductor 270, so that the data line 21 is electrically connected to the conductor 270. For convenience of explanation, FIG. 3a shows only a data line 21, a scan line 22, a thin film transistor 28, a conductor 270, and a pixel 23. The structure of the thin film transistor 28 is as shown in the first embodiment, and will not be described herein. As shown in FIG. 3b, a gate insulating layer 25 is formed on the substrate 24. The formation manner and materials are as shown in the first embodiment, and are not described herein. The patterned metal oxide layer 271 is formed on the gate insulating layer 25, and a doping process is performed. The doping process is performed by doping the patterned metal oxide layer 271 with a reducing gas 272 to make the patterned metal. The oxide layer 271 is changed from a semiconductor to a conductor 270. The patterned metal oxide layer 271 may be indium zinc oxide or indium gallium zinc oxide. The reducing gas 272 may be hydrogen gas, but is not limited thereto. A data line 21 is formed on the gate insulating layer 25 and covers the conductor 270. The protective layer 26 is formed on the gate insulating layer 25 and covers the data lines 7 M443929 ... 21 . The above-described formation manner and materials are as shown in the first embodiment, and will not be described herein. Fig. 4a is a schematic plan view showing a portion of a thin film transistor substrate of a third embodiment of the present invention. The section of line AB in Figure 4a is shown in Figure 4b. The thin film transistor substrate 3 includes a plurality of thin film transistors 39, a plurality of data lines 31, a plurality of scanning lines 32, and a plurality of segments of conductors 370. The data lines 31 and the scan lines 32 are perpendicular to each other. The area enclosed by each adjacent two data lines ® 31 and each adjacent two scanning lines 32 is a halogen 33, and each of the halogens 33 has a thin film transistor 39. The conductor 370 is electrically connected to the scan line 32 by a conventional via 38. For convenience of explanation, only a data line 31, a scan line 32, a conductor 370, a thin film transistor 39, a uniform via 38, and a halogen 33 are shown in Fig. 4a. The structure of the thin film transistor 39 is as shown in the first embodiment, and will not be described herein. As shown in FIG. 4b, a scan line 32 is formed on the substrate 34. The substrate 34 may be a glass substrate, a quartz substrate, or another substrate. The material of this scan line 32 ® is for example: ingot, chrome, group or other metallic material. The formation methods include a thin film deposition process, a lithography process, and an etching process. A gate insulating layer 35 is formed on the substrate 34 and covers the scan line 32. The gate insulating layer 35 is formed with a uniform via 38 by an etching process such that the through hole 38 is positioned above the center of the scanning line 32. The material of the gate insulating layer 35 is, for example, a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride. The formation method may be a chemical vapor deposition method. The patterned metal oxide layer 371 is formed on the gate insulating layer 35, and the patterned metal oxide 8 M443929 is electrically connected to the scan line 32 through the through hole 38. A protective layer 36 is formed on the gate insulating layer 35 and covers the patterned metal oxide layer 371. In the present embodiment, the material of the protective layer 36 is yttrium oxide, which is formed by using a plasma chemical vapor deposition method. The method generates a reducing gas 372, such as hydrogen, when the protective layer 36 is deposited, and the reducing gas 372 chemically reacts with the patterned metal oxide layer 371 to change the patterned metal oxide layer 371 from a semiconductor to a conductor 370. The impedance of the data line 32 is reduced. Fig. 5 is a schematic plan view showing a portion of a thin film transistor substrate of a fourth embodiment of the present invention. The thin film transistor substrate 4 includes a plurality of thin film transistors (not shown), a plurality of data lines 41, a plurality of scanning lines 42, and a plurality of segment conductors 44. The plurality of data lines 41 and the plurality of scanning lines 42 are perpendicular to each other. Each of the adjacent two data lines 41 and each adjacent two scanning lines 42 is surrounded by a pixel 43, and each of the elements 43 has a thin film transistor (not shown). The conductor 44 is located below the data line 41 and is electrically connected to the data line 41. The conductor 44 is positioned above the scan line 42 and electrically connected to the scan line 42 via a through hole 45. However, the conductor 44 is not located at the intersection of the scanning line 42 and the data line 41. The structure of the thin film transistor (not shown) is as shown in the first embodiment, and will not be described herein. For the structure and formation method of the data line 41 and the conductor 44, please refer to the first embodiment of the present invention; the structure and formation method of the scanning line 42 and the conductor 44 are referred to the third embodiment of the present invention, and will not be described herein. Fig. 6 is a schematic plan view showing a portion of a thin film transistor substrate of a fifth embodiment of the present invention. The thin film transistor substrate 5 includes a plurality of thin film electrodes 9 M443929 f crystals (not shown), a plurality of data lines 51, a plurality of scanning lines 52, and a plurality of segment conductors 54. The plurality of data lines 51 and the scanning lines 52 are perpendicular to each other. Each of the adjacent two data lines 51 and each adjacent two scanning lines 52 is surrounded by a pixel 53, and each of the elements 53 has a thin film transistor (not shown). The data line 51 covers the conductor 54, which is electrically connected to the data line 51. The conductor 54 is positioned above the scan line 52 and electrically connected to the scan line 52 via a through hole 55. However, the conductor 54 is not located at the intersection of the scanning line 52 and the data line 51. The structure of the thin film transistor (not shown) is as shown in the first embodiment, and will not be described here. For the structure and formation method of the data line 51 and the conductor 54, please refer to the second embodiment of the present invention; the structure and formation method of the scanning line 52 and the conductor 54 are referred to the third embodiment of the present invention, and will not be described herein. Therefore, the feature of this creation is that in the process of using the process, the reducing gas (such as hydrogen) generated during the deposition of the protective layer will chemically react with the metal oxide (such as indium gallium zinc oxide) to make indium. Gallium-Zinc Oxide Because the hydrogen doping is changed from the original semiconductor to the conductor, ® is applied to the scan lines and data lines on the halogen circuit, so that the metal wires and the conductive indium gallium zinc oxide are electrically connected to each other. The impedance of the halogen circuit is lowered, the charging and discharging time of the entire pixel circuit is shortened, and the reaction speed of the pixel circuit is increased, especially on a large-sized liquid crystal display, and the uniformity of the surface of the pixel is improved. In summary, only the embodiments or examples of the technical means used to solve the problem are described, and are not intended to limit the scope of implementation of the patent. That is, in accordance with the scope of the scope of this patent application, 10 M443929, ‘· or the equivalent changes and modifications made in accordance with the scope of this patent creation are covered by the scope of the patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 & is a schematic plan view of a conventional thin film transistor substrate; FIG. 1b is a cross-sectional view of a conventional data line; FIG. 1C is a cross-sectional view of a conventional scanning line; FIG. 2b is a cross-sectional view of the thin film transistor of the first embodiment of the present invention; FIG. 2c is a cross-sectional view of the data line of the first embodiment of the present invention; FIG. 3a is a cross-sectional view of the thin film transistor of the first embodiment; A schematic plan view of a portion of a thin film transistor substrate of a second embodiment of the present invention; FIG. 3b is a cross-sectional view of a data line of a second embodiment of the present invention; FIG. 4a is a thin germanium transistor substrate according to a third embodiment of the present invention. FIG. 4b is a cross-sectional view of a scan line of a third embodiment of the present invention; FIG. 5 is a partial plan view of a thin film transistor substrate according to a fourth embodiment of the present invention; and FIG. A schematic plan view of a portion of a thin film transistor substrate of the fifth embodiment. 12 M443929
【主要元件符號說明】 1 薄膜電晶體基板 11 資料線 11a 源極 lib 汲極 12 掃描線 12a 閘極 13 畫素 14 基板 15 閘極絕緣層 16 保護層 170 導體 171a 圖案化金屬氧化物層 171b 圖案化金屬氧化物層 172 還原性氣體 173 钱刻停止層 18 薄膜電晶體 19 接觸窗 2 薄膜電晶體基板 21 資料線 22 掃描線 23 晝素 24 基板 25 閘極絕緣層 26 保護層 270 導體 271 圖案化金屬氧化物層 272 還原性氣體 28 薄膜電晶體 3 薄膜電晶體基板 31 資料線 32 掃描線 33 畫素 34 基板 35 閘極絕緣層 36 保護層 370 導體 371 圖案化金屬氧化物層372 還原性氣體 38 貫穿孔 39 薄膜電晶體 4 薄膜電晶體基板 41 資料線 42 掃描線 43 晝素 44 導體 45 貫穿孔 13 M443929 5 薄膜電晶體基板 51 52 掃描線 53 54 導體 55 9 \薄膜電晶體基板 91 92 掃描線 93 94 基板 95 96 保護層 資料線 晝素 貫穿孔 資料線 畫素 閘極絕緣層[Major component symbol description] 1 Thin film transistor substrate 11 Data line 11a Source lib Bungee 12 Scan line 12a Gate 13 Pixel 14 Substrate 15 Gate insulating layer 16 Protective layer 170 Conductor 171a Patterned metal oxide layer 171b Pattern Metal oxide layer 172 Reducing gas 173 Money stop layer 18 Thin film transistor 19 Contact window 2 Thin film transistor substrate 21 Data line 22 Scan line 23 Alizarin 24 Substrate 25 Gate insulating layer 26 Protective layer 270 Conductor 271 Patterning Metal oxide layer 272 Reducing gas 28 Thin film transistor 3 Thin film transistor substrate 31 Data line 32 Scan line 33 Pixel 34 Substrate 35 Gate insulating layer 36 Protective layer 370 Conductor 371 Patterned metal oxide layer 372 Reducing gas 38 Through hole 39 Thin film transistor 4 Thin film transistor substrate 41 Data line 42 Scan line 43 Alizarin 44 Conductor 45 Through hole 13 M443929 5 Thin film transistor substrate 51 52 Scan line 53 54 Conductor 55 9 \ Thin film transistor substrate 91 92 Scan line 93 94 Substrate 95 96 Protective layer data line Alizarin through-hole data line Floor
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