CN112951924B - TFT device and preparation method thereof - Google Patents
TFT device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 99
- 239000002245 particle Substances 0.000 claims abstract description 48
- 230000004888 barrier function Effects 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 192
- 239000000758 substrate Substances 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 25
- 239000004793 Polystyrene Substances 0.000 claims description 16
- 229920002223 polystyrene Polymers 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000009832 plasma treatment Methods 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention provides a TFT device and a preparation method thereof, the preparation method of the TFT device comprises the steps of firstly dispersing barrier particles on a semiconductor layer, forming gaps between adjacent barrier particles, then carrying out plasma treatment on the semiconductor layer, leading the region of the semiconductor layer corresponding to the gaps to be conducted with a conductor, reserving the semiconductor characteristics of the region of the semiconductor layer corresponding to the barrier particles, forming the semiconductor layer with a dispersed conductor region, then removing the barrier particles, and carrying out patterning treatment on the semiconductor layer to form a required active layer pattern, wherein the active layer pattern has the structure of the semiconductor layer with the dispersed conductor region, thereby improving the on-state current and the electron mobility of an active layer, improving the charging and switching frequency of the TFT device, meeting the requirements of the charging and refreshing frequency of a large-size display panel, in addition, the process of forming a local conductor region does not need a photoetching technology, and has lower cost, meanwhile, the phenomenon that the whole channel region becomes a conductor and loses the switching characteristic is avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to a TFT (thin film transistor) device and a preparation method thereof.
Background
Thin Film Transistors (TFTs) are important components of flat panel Display devices, and can be formed on a glass substrate or a plastic substrate, and are commonly used as switching devices and driving devices in, for example, LCD (Liquid Crystal Display) Display devices and OLED (Organic Light Emitting Display) Display devices.
With the increasing size of liquid crystal displays, the driving frequency is also increased, the electron mobility of the conventional amorphous silicon thin film transistor is difficult to meet the requirement, the conductive capability is poor, and the uniformity is poor. The mobility of the IGZO of the semiconductor layer is generally 10cm2V-1s-1The content of oxygen in the semiconductor layer is reduced, and the mobility of the semiconductor layer can be improved. The conventional means for improving oxygen vacancy is mainly conducting treatment by using methods such as plasma treatment or reaction of metal and a semiconductor layer, but the two ends of the semiconductor layer are treated in a whole surface or partially conducting to improve the electron mobility of the amorphous silicon thin film transistor, so that the situation that the semiconductor layer is conducted or the stability is reduced easily occurs, and the surface flatness is poor.
In summary, the electron mobility of the semiconductor layer in the amorphous silicon thin film transistor in the prior art is low, and the driving frequency and the refresh frequency of the large-sized display panel cannot be satisfied, and improvement is needed.
Disclosure of Invention
The invention provides a TFT (thin film transistor) device and a preparation method thereof, which can solve the technical problems that the electron mobility of a semiconductor layer in an amorphous silicon thin film transistor in the prior art is low and the driving frequency and the refreshing frequency of a large-size display panel cannot be met.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides a TFT device preparation method, which comprises the following steps:
step S10, a substrate is provided, and a semiconductor layer is formed on the substrate.
Step S20 is to dispersedly dispose barrier particles on the semiconductor layer, with gaps between adjacent barrier particles.
Step S30 is to perform plasma processing on the semiconductor layer, the semiconductor layer being made conductive in a region corresponding to the gap, the semiconductor layer retaining semiconductor characteristics in a region corresponding to the barrier particles, and constituting a semiconductor layer having a dispersed conductive region.
Step S40, removing the barrier particles, and performing a patterning process on the semiconductor layer to form a desired active layer pattern.
According to a preferred embodiment of the present invention, step S20 specifically includes: preparing a barrier particle solution, preparing the barrier particle solution on the semiconductor layer, and uniformly dispersing the barrier particles on the semiconductor layer after drying the barrier particles.
According to a preferred embodiment of the present invention, the barrier particles are polystyrene spheres, the diameter of the polystyrene spheres is 10nm to 50nm, and the solvent of the barrier particle solution is ethanol or acetone.
According to a preferred embodiment of the present invention, the plasma in step S30 is one or more of helium, argon, hydrogen, and oxygen.
According to a preferred embodiment of the present invention, the step S20 further includes: before barrier particles are dispersedly arranged on the semiconductor layer, annealing treatment is carried out on the semiconductor layer, and the temperature of the annealing treatment is 200-350 ℃.
According to a preferred embodiment of the present invention, step S40 further includes: preparing a gate insulating layer on the active layer, preparing a gate electrode on the gate insulating layer, preparing an interlayer insulating layer on the substrate, and preparing a source electrode and a drain electrode on the interlayer insulating layer, wherein the interlayer insulating layer covers the active layer and the gate electrode, the source electrode is electrically connected with one end of the active layer through a source electrode contact hole, and the drain electrode is electrically connected with the other end of the active layer through a drain electrode contact hole.
According to a preferred embodiment of the present invention, the gate insulating layer and the interlayer insulating layer are made of silicon oxide, silicon nitride, or a combination thereof, and the gate electrode is made of one or more metal materials selected from aluminum, copper, and molybdenum.
According to the above TFT device manufacturing method, the present invention further provides a TFT device manufactured by the TFT device manufacturing method according to the above embodiment, where the TFT device includes a substrate, an active layer on the substrate, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the substrate and covering the active layer and the gate electrode, and a source electrode and a drain electrode on the interlayer insulating layer, where the active layer forms a semiconductor layer having a dispersed conductor region in a channel region by using a plasma process.
According to a preferred embodiment of the present invention, the semiconductor layer is any one of indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO, and indium gallium zinc tin oxide IGZTO.
According to a preferred embodiment of the present invention, the interlayer insulating layer is provided with a source contact hole and a drain contact hole at two ends corresponding to the active layer, the source electrode is electrically connected to one end of the active layer through the source contact hole and the surface thereof, the drain electrode is electrically connected to the other end of the active layer through the drain contact hole and the surface thereof, and the source electrode and the drain electrode are both in contact with the conductor region at a contact surface with the active layer.
The invention has the beneficial effects that: the embodiment of the invention provides a TFT device and a preparation method thereof, the preparation method of the TFT device comprises the steps of firstly dispersedly arranging barrier particles on a semiconductor layer, forming gaps between adjacent barrier particles, then carrying out plasma treatment on the semiconductor layer, enabling the region of the semiconductor layer corresponding to the gaps to be conductive, reserving the semiconductor characteristics of the region of the semiconductor layer corresponding to the barrier particles to form the semiconductor layer with a dispersed conductor region, then removing the barrier particles, and carrying out patterning treatment on the semiconductor layer to form a required active layer pattern, wherein the active layer pattern has the structure of the semiconductor layer with the dispersed conductor region, so that the on-state current and the electron mobility of an active layer are improved, the charging and switching frequency of the TFT device is improved, the requirements of the charging and refreshing frequency of a large-size display panel are met, in addition, a photoetching technology is not needed in the process of forming a local conductor region, the cost is low, and the phenomenon that the whole channel region becomes a conductor and loses the switching characteristic is avoided.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic view of a process flow for manufacturing a TFT device according to the present invention.
Fig. 2 to fig. 6 are schematic views of the TFT device manufacturing process structure provided in the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals, and broken lines in the drawings indicate that the elements do not exist in the structures, and only the shapes and positions of the structures are explained.
The present invention can solve the technical problem that the driving frequency and the refresh frequency of a large-sized display panel cannot be satisfied due to the low electron mobility of the semiconductor layer in the amorphous silicon thin film transistor in the prior art.
The invention provides a TFT device preparation method, as shown in FIG. 1, the method comprises the following steps:
step S10, a substrate is provided, and a semiconductor layer is formed on the substrate.
Step S20 is to dispersedly dispose barrier particles on the semiconductor layer, with gaps between adjacent barrier particles.
Step S30 is to perform plasma processing on the semiconductor layer, the semiconductor layer being made conductive in a region corresponding to the gap, the semiconductor layer retaining semiconductor characteristics in a region corresponding to the barrier particles, and constituting a semiconductor layer having a dispersed conductive region.
Step S40, removing the barrier particles, and performing a patterning process on the semiconductor layer to form a desired active layer pattern.
Preferably, the step S20 further includes: before barrier particles are dispersedly arranged on the semiconductor layer, annealing treatment is carried out on the semiconductor layer, and the temperature of the annealing treatment is 200-350 ℃.
Preferably, step S20 specifically includes: preparing a barrier particle solution, preparing the barrier particle solution on the semiconductor layer, and uniformly dispersing the barrier particles on the semiconductor layer after drying the barrier particles. The barrier particles are polystyrene spheres, the diameter of each polystyrene sphere is 10nm-50nm, and the solvent of the barrier particle solution is ethanol or acetone.
Preferably, the plasma in step S30 is one or more of helium, argon, hydrogen, and oxygen.
Preferably, step S40 further includes: preparing a gate insulating layer on the active layer, preparing a gate electrode on the gate insulating layer, preparing an interlayer insulating layer on the substrate, and preparing a source electrode and a drain electrode on the interlayer insulating layer, wherein the interlayer insulating layer covers the active layer and the gate electrode, the source electrode is electrically connected with one end of the active layer through a source electrode contact hole, and the drain electrode is electrically connected with the other end of the active layer through a drain electrode contact hole. The gate insulating layer and the interlayer insulating layer are made of silicon oxide, silicon nitride or a combination material of the silicon oxide and the silicon nitride, the gate is made of one or more metal materials of aluminum, copper and molybdenum, and the thickness of the gate insulating layer is 50nm to 100 nm.
Preferably, any two adjacent barrier particles in step S20 are in point contact or no contact, and have no overlapping structure.
Preferably, the mobility of the partially-conductive semiconductor layer in step S30 is 30cm2V-1s-1To 150cm2V- 1s-1Within the range.
Specifically, fig. 2 to fig. 6 are schematic structural diagrams of a TFT device manufacturing process provided in the present invention. As shown in fig. 2, a substrate 101 is provided, the substrate 101 includes a glass substrate and a buffer layer on the glass substrate, the glass substrate can be replaced by a plastic substrate, after being cleaned and dried by clean water, a buffer layer is deposited on the glass substrate, the buffer layer is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film in which silicon oxide films and silicon nitride films are alternately stacked, the thickness of the buffer layer is preferably in a range of 20 to 50 nanometers, the buffer layer plays a role in buffering stress on one hand, and plays a role in shading light on the other hand. A semiconductor layer 102 is deposited on the base substrate 101, and the semiconductor layer 102 is preferably any one of indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO, and indium gallium zinc tin oxide IGZTO. The semiconductor layer 102 preferably has a thickness in the range of 20 to 200 nm and is annealed at 200 to 400 c for about 0.5 hours. After the annealing treatment is completed, a blocking particle solution is coated, the blocking particle solution in this embodiment is a polystyrene sphere solution, after drying, polystyrene spheres are uniformly dispersed on the surface of the semiconductor layer 102, the diameter of the polystyrene spheres is preferably in the range of 10 to 50 nanometers, any two adjacent polystyrene spheres are in point contact or non-contact, and there is no superimposed structure, that is, only one layer of polystyrene spheres is coated on the surface of the semiconductor layer 102, and a gap is formed between two adjacent spheres, so that the subsequent plasma gas can invade the surface of the semiconductor layer 102 from the gap, the oxygen content of the local semiconductor layer 102 is reduced, and the oxygen vacancy is increased to change the local semiconductor layer into a conductor layer.
As shown in fig. 3, a plasma 104 is disposed above the polystyrene spheres, the semiconductor layer 102 is subjected to a plasma 104 treatment, the plasma 104 is used to sputter on the semiconductor layer 102 covered with the polystyrene spheres, due to the blocking of the polystyrene spheres, the semiconductor layer 102 located right below the polystyrene spheres is still a semiconductor layer, the oxygen content of the semiconductor layer 102 located at two sides of the polystyrene spheres is reduced by the plasma 104, the semiconductor layer 1021 is changed, the original semiconductor layer 102 is changed into a structure in which the semiconductor layer 102 and the conductor layer 1021 are doped, the on-state current and the electron mobility of the semiconductor layer 102 doped with a conductor region are improved, that is, the charging and switching frequency of the TFT device is improved, and the requirements of the charging and refreshing frequency of a large-size display panel can be met. In addition, a photoetching technology is not needed in the process of forming the local conductor region, the cost is low, and the phenomenon that the whole channel region becomes a conductor and loses the switching characteristic is avoided.
As shown in fig. 4, the semiconductor layer 102 and the semiconductor layer 1021 are patterned by a photolithography process, or after a wet etching process or a dry etching process using oxalic acid as an etching solution, the semiconductor layer 102 and the semiconductor layer 1021 are patterned to form an island-shaped metal oxide semiconductor layer, so as to form the desired active layer 105. A gate insulating layer 106 and a gate electrode 107 are sequentially deposited on the active layer 105. As shown in fig. 5, the gate insulating layer 106 and the gate electrode 107 are etched by a photolithography process to form the gate insulating layer 106 and the gate electrode 107, where the gate insulating layer 106 is typically made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a sandwich structure of the three. The gate electrode 107 is made of a metal material, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), or chromium (Cr). The gate electrode 107 is formed on the gate insulating layer 106 by a physical vapor deposition method, and a gate pattern is formed by a photolithography process.
As shown in fig. 6, an interlayer insulating layer 108 is formed on the substrate 101, and a source electrode 1091 and a drain electrode 1092 are formed on the interlayer insulating layer 108, wherein the interlayer insulating layer 108 covers the active layer 105, the gate insulating layer 106 and the gate electrode 107, the source electrode 1091 and the drain electrode 1092 are electrically connected to two ends and a surface of the active layer 105 through a source contact hole and a drain contact hole, respectively, and the interlayer insulating layer 108 is also made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a sandwich structure of the three. The source 1091 and the drain 1092 are preferably aluminum or molybdenum. The contact surfaces of the source and drain electrodes 1091 and 1092 with the active layer 105 are in contact with the conductor regions.
According to the above TFT device manufacturing method, the present invention further provides a TFT device, which is manufactured by the TFT device manufacturing method in the above embodiment, and the specific structure refers to fig. 6. Specifically, as shown in fig. 6, the TFT device includes a base substrate 101, an active layer 105 on the base substrate 101, a gate insulating layer 106 on the active layer 105, a gate electrode 107 on the gate insulating layer 106, an interlayer insulating layer 108 on the base substrate 101 and covering the active layer 105 and the gate electrode 107, and a source electrode 1091 and a drain electrode 1092 on the interlayer insulating layer 108. In the active layer 105, a semiconductor layer 102 having a distributed conductor region 1021 is formed in a channel region by a plasma process.
The semiconductor layer 102 is made of any one of indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO, and indium gallium zinc tin oxide IGZTO, and the conductor layer 1021 is a local region in which the semiconductor layer 102 is made conductive. The interlayer insulating layer 108 has a source contact hole and a drain contact hole respectively formed at both ends of the active layer 105, the source 1091 is electrically connected to one end of the active layer 105 through the source contact hole, the drain 1092 is electrically connected to the other end of the active layer 102 through the drain contact hole, and the source and drain are in contact with the conductor region at the contact surface with the active layer.
According to the TFT device, the present invention further provides an array substrate, which includes the TFT device in the above embodiment.
According to the array substrate, the invention further provides a display device, which comprises the array substrate in the embodiment.
The embodiment of the invention provides a TFT device and a preparation method thereof, the preparation method of the TFT device comprises the steps of firstly dispersedly arranging barrier particles on a semiconductor layer, forming gaps between adjacent barrier particles, then carrying out plasma treatment on the semiconductor layer, enabling the region of the semiconductor layer corresponding to the gaps to be conductive, reserving the semiconductor characteristics of the region of the semiconductor layer corresponding to the barrier particles to form the semiconductor layer with a dispersed conductor region, then removing the barrier particles, and carrying out patterning treatment on the semiconductor layer to form a required active layer pattern, wherein the active layer pattern has the structure of the semiconductor layer with the dispersed conductor region, so that the on-state current and the electron mobility of an active layer are improved, the charging and switching frequency of the TFT device is improved, the requirements of the charging and refreshing frequency of a large-size display panel are met, in addition, a photoetching technology is not needed in the process of forming a local conductor region, the cost is low, and the phenomenon that the whole channel region becomes a conductor and loses the switching characteristic is avoided.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (8)
1. A method for manufacturing a TFT device includes:
step S10, providing a substrate, and forming a semiconductor layer on the substrate;
step S20, disposing barrier particles on the semiconductor layer in a dispersed manner, wherein gaps exist between adjacent barrier particles, and the step S20 specifically includes: preparing a barrier particle solution, preparing the barrier particle solution on the semiconductor layer, and uniformly dispersing the barrier particles on the semiconductor layer after drying the barrier particles; the barrier particles are polystyrene spheres, the diameter of each polystyrene sphere is 10nm-50nm, and the solvent of the barrier particle solution is ethanol or acetone;
a step S30 of performing plasma processing on the semiconductor layer, the semiconductor layer being made conductive in a region corresponding to the gap, the semiconductor layer retaining semiconductor characteristics in a region corresponding to the barrier particles, and constituting a semiconductor layer having a dispersed conductive region;
step S40, removing the barrier particles, and performing a patterning process on the semiconductor layer to form a desired active layer pattern.
2. The method of manufacturing a TFT device as claimed in claim 1, wherein the plasma in step S30 is one or more of helium, argon, hydrogen, and oxygen.
3. The method for manufacturing a TFT device according to claim 1, wherein the step S20 further includes: before barrier particles are dispersedly arranged on the semiconductor layer, annealing treatment is carried out on the semiconductor layer, and the temperature of the annealing treatment is 200-350 ℃.
4. The method for manufacturing a TFT device according to claim 1, wherein the step S40 further includes: preparing a gate insulating layer on the active layer, preparing a gate electrode on the gate insulating layer, preparing an interlayer insulating layer on the substrate, and preparing a source electrode and a drain electrode on the interlayer insulating layer, wherein the interlayer insulating layer covers the active layer and the gate electrode, the source electrode is electrically connected with one end of the active layer through a source electrode contact hole, and the drain electrode is electrically connected with the other end of the active layer through a drain electrode contact hole.
5. The method for manufacturing a TFT device according to claim 4, wherein the gate insulating layer and the interlayer insulating layer are made of silicon oxide, silicon nitride or a combination of the silicon oxide and the silicon nitride, and the gate electrode is made of one or more metal materials selected from copper, aluminum, titanium, tantalum, tungsten, molybdenum and chromium.
6. A TFT device manufactured by the method of manufacturing a TFT device according to any one of claims 1 to 5, the TFT device comprising a substrate, an active layer on the substrate, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the substrate and covering the active layer and the gate electrode, and a source electrode and a drain electrode on the interlayer insulating layer, wherein the active layer forms a semiconductor layer having discrete conductor regions in a channel region by a plasma process.
7. The TFT device of claim 6, wherein the semiconductor layer is any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), and Indium Gallium Zinc Tin Oxide (IGZTO).
8. The TFT device as claimed in claim 6, wherein the interlayer insulating layer is provided with a source contact hole and a drain contact hole corresponding to the two ends of the active layer, the source electrode is electrically connected to one end of the active layer through the source contact hole and has a surface, the drain electrode is electrically connected to the other end of the active layer through the drain contact hole and has a surface, and the source electrode and the drain electrode are both in contact with the conductor region at a contact surface with the active layer.
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