KR101771251B1 - Indirect Thermal Crystalization Thin Film Transistor Substrate And Method For Manufacturing The Same - Google Patents

Abstract

The present invention relates to an indirect thermal crystallization thin film transistor substrate using a double metal layer including a metal material having excellent heat resistance for a gate electrode and a metal material having a low surface resistance for a gate wiring, and a manufacturing method thereof. A method of manufacturing an indirect thermal crystallization thin film transistor substrate according to the present invention includes depositing and patterning a gate material in a bilayer structure in which a first metal layer having a high heat resistance and a second metal layer having a low surface resistance are sequentially stacked, And the gate wiring is formed so that the second metal layer remains on the top. Therefore, the gate electrode and the gate wiring can be formed in the same layer, and the effect of reducing the number of mask processes can be obtained. Since the gate electrode includes only the first metal layer having excellent heat resistance, thermal deformation does not occur in the thermal crystallization process, and the gate wiring includes the second metal layer having a low surface resistance. Therefore, Resistance condition is satisfied.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an indirect thermal crystallization thin film transistor substrate,

The present invention relates to a thin film transistor (TFT) substrate using an Indirect Thermal Crystalization (ITC) method and a manufacturing method thereof. In particular, the present invention relates to an indirect thermal crystallization thin film transistor substrate using a double metal layer including a metal material having excellent heat resistance for a gate electrode and a metal material having a low surface resistance for a gate wiring, and a manufacturing method thereof.

Flat panel display devices such as a liquid crystal display device (LCD) or an organic light emitting diode (OLED) display device include a thin film transistor substrate having a plurality of thin film transistors for use as an active display device do. The active layer constituting the channel of the thin film transistor used in such flat panel display devices is usually formed on a substrate by a chemical vapor deposition (CVD) method. The active layer formed by this method has a low electron mobility of ~ 1 cm 2 / Vs or less as amorphous silicon. As the flat panel display devices, particularly the organic foot and display devices, are required to be larger and larger in aperture ratio and luminance, it is desirable that the electron mobility of the polycrystalline thin film transistor (hereinafter, referred to as " Is increasing. For this purpose, a technique of crystallizing amorphous silicon into a polycrystalline silicon layer by heat treatment is used.

Indirect thermal crystallization technology uses a stable infrared diode laser compared to conventional UV excimer laser to convert laser light to heat transfer layer (HTL) and convert it into heat. Thereby forming amorphous silicon into crystallized silicon. There is an advantage that uniform device characteristics can be obtained by crystallizing the silicon layer indirectly through the heat transfer layer by using a diode laser. The thin film transistor substrate and the manufacturing method thereof using the indirect thermal crystallization technique will be described with reference to FIGS. 1 and 2A to 2I. 1 is a plan view showing a structure of a polycrystalline thin film transistor substrate using an indirect thermal crystallization technology included in a conventional liquid crystal display device. 2A to 2I are cross-sectional views illustrating a process for manufacturing the polycrystalline thin film transistor substrate of FIG.

 1, a thin film transistor substrate of a liquid crystal display comprises a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a glass substrate SUB, And a transistor (TFT). A pixel region is defined by an intersection structure of a gate wiring GL and a data wiring DL. A pixel electrode PXL is formed in this pixel region.

A gate pad GP and a data pad DP are formed at one end of the gate line GL and the data line DL, respectively. The gate pad GP and the data pad DP are connected to the gate pad terminal GPT and the data pad terminal GPT via the gate pad contact hole GPH and the data pad contact hole DPH, respectively.

2A to 2I, a process of manufacturing a conventional polycrystalline thin film transistor substrate will be described.

A gate metal material is deposited on the substrate SUB, and the gate electrode G is formed by patterning with a first mask. At this time, only the gate electrode G may be formed, or if necessary, a storage capacitor electrode (not shown) may be additionally formed. However, the gate wiring GL or the gate pad GP connecting the gate electrode G is not formed. This is to prevent damage to the gate wiring having a low melting point but a low resistance due to heat at a high temperature generated in a crystallization process performed later. That is, the gate electrode G is formed using a molybdenum-titanium (Mo-Ti) alloy, which is a metal material having a high resistivity but a good heat resistance. (Fig. 2A)

An insulating material such as SiNx or SiOx is entirely deposited on the entire surface of the substrate SUB on which the gate electrode G is formed to form the gate insulating film GI. A semiconductor material such as amorphous silicon is deposited in a continuous process to form the semiconductor layer (A). On top of that, an etch stopper layer (ESL) is formed by continuously depositing an insulating material such as SiNx or SiOx on a continuous process. Then, a metal material having good thermal conductivity is deposited again by a continuous process to form a heat transfer layer. Then, the thermal transfer layer is patterned with the second mask to form a thermal transfer pattern (HTL). Since the heat transfer pattern HTL is for transferring heat to crystallize the amorphous semiconductor material underlying the gate electrode G, a part of the semiconductor layer A, particularly, the portion overlapping with the gate electrode G, It is preferable that the pattern is formed so as to have a shape of " An infrared diode laser (IR) is irradiated onto the thermal transfer pattern (HTL) by a scanning method to apply heat energy to a portion of the semiconductor layer (A), particularly to a portion overlapping the gate electrode (G) Then, the amorphous semiconductor material of the semiconductor layer (A) is crystallized and converted into a polycrystalline semiconductor material. (Figure 2b)

The purpose of indirectly transferring heat is to crystallize the amorphous semiconductor material of the semiconductor layer (A) forming the channel layer, so that it is preferable to pattern the heat transfer film so that heat can be applied only to the necessary portion. In some cases, an infrared diode laser may be irradiated to the entire thermal transfer film without patterning the thermal transfer film. In this case, the mask process number may be advantageously reduced by one. However, when the heat transfer film is not patterned, since heat is absorbed in the entire area of the substrate SUB during the crystallization process, the substrate may warp. Particularly, such a problem becomes more serious in the case of a large-area substrate such as a flat panel display. Therefore, in the case of a large-area thin film transistor substrate such as a liquid crystal display, a thermal transfer film must be patterned.

After crystallizing the semiconductor layer (A), the thermal transfer pattern (HTL) is removed by a wet etching process. Then, the etch stopper layer (ESL) exposed in the third mask process is patterned to form an etch stopper ES. It is preferable that the etch stopper ES is formed so as to overlap with a part of the semiconductor layer A superimposed on the gate electrode G. [ The etch stopper ES is formed in the process of removing the ohmic layer n between the source and drain electrodes SD when patterning the source-drain electrode SD and the ohmic layer n to be formed later. A) from being etched. In the case of a thin film transistor substrate using an amorphous semiconductor layer, since the amorphous semiconductor layer is formed in units of several thousands of angstroms, the semiconductor layer is etched to some extent (several hundred angstroms) while removing the ohmic contact layer without using an etch stopper The semiconductor layer could have a sufficient thickness. However, when the polycrystalline semiconductor layer is used, the thickness of the semiconductor layer A is formed in units of several hundreds of angstroms. Therefore, if the etch stopper is not used, the semiconductor layer A ' All of which may be etched away. Therefore, when a polycrystalline semiconductor layer is used, it is preferable to include an etch stopper. (Fig. 2C)

An impurity semiconductor material such as n + silicon doped with n + impurity at high concentration is deposited on the substrate SUB on which the etch stopper ES is formed to coat the ohmic layer n. The ohmic layer n is an interface layer for allowing the source-drain electrodes S-D, which are spaced apart from each other by a predetermined distance above the etch stopper ES, to be formed in ohmic contact with the semiconductor layer A, (Figure 2d)

A metal material is applied to the entire surface of the substrate SUB to which the ohmic layer n is applied and patterned in the fourth mask process to form the data line DL and the data pad DP formed at one end of the data line DL, A source electrode S that branches from the line DL and overlaps with one side of the gate electrode G and a drain electrode D that faces the source electrode S and faces the source electrode S with a certain distance are formed. The ohmic contact layer n 'and the semiconductor channel layer A' are completed by continuously patterning the ohmic layer n and the semiconductor layer A using the shape of the source-drain electrode S-D as a mask. This forms a thin film transistor (TFT) as a switching element together with the source electrode S, the drain electrode D, the crystallization semiconductor channel layer A ', and the gate electrode G. At this time, the ohmic layer (n) and the semiconductor layer (A) remain in the lower part of the data pad (DP) and the data line (DL). (Figure 2E)

An insulating material such as SiNx or SiOx is entirely deposited on the entire surface of the substrate SUB on which the source-drain electrode S-D is formed to form the first protective film PAS1. The first passivation film PAS1 is patterned by the fifth mask process so that the other side except the one side where the source-drain electrode SD is formed with a part of the gate electrode G, in particular, the semiconductor channel layer A ' Thereby forming a gate contact hole GH to be exposed. Here, if a storage capacitor electrode (not shown) is formed in the process of forming the gate electrode G, an auxiliary capacity contact hole (not shown) may be formed to expose a part of the storage capacitor electrode. (Figure 2f)

A metal material having a low resistivity such as a copper alloy is deposited on the entire surface of the substrate SUB on which the gate contact hole GH is formed and the data line DL is electrically connected to the gate electrode G by patterning in the sixth mask process. And a gate wiring line GL intersecting with the gate line GL. A gate pad GP is formed at one end of the gate line GL. Here, although not shown, if the auxiliary capacitance electrode is formed in the process of forming the gate electrode G, the gate wiring GL may be in electrical contact with the auxiliary capacitance electrode through the auxiliary capacitance contact hole . (Figure 2g)

An insulating material such as SiNx or SiOx is entirely deposited on the entire surface of the substrate SUB on which the gate wiring GL and the gate pad GP are formed to form the second protective film PAS2. A drain contact hole DH exposing a part of the drain electrode D and a gate pad contact hole GPH exposing a part of the gate pad GP are formed by patterning the second protective film PAS2 by a seventh mask process, And a data pad contact hole (DPH) exposing a part of the data pad (DP). (Fig. 2H)

A transparent conductive material such as ITO or IZO is deposited on the second protective film PAS2. The pixel electrode PXL which contacts the drain electrode D by patterning the transparent conductive material with the eighth mask, the gate pad terminal GPT which contacts the gate pad GP, Thereby forming a data pad terminal (DPT). (Figure 2i)

After the amorphous semiconductor is deposited on the thin film transistor substrate by the indirect thermal crystallization technique, the thin film transistor substrate including the polycrystalline semiconductor layer can be obtained by thermal crystallization with an infrared diode laser. That is, in the amorphous silicon manufacturing process, which has obtained stable technical results in the large-area display device manufacturing method, a polycrystalline or crystallized semiconductor thin film transistor substrate having better electron mobility and ON-current than the amorphous semiconductor thin film transistor substrate can be obtained through a simple heating process have.

However, as described above, the indirect thermal crystallization technique requires a metal layer capable of absorbing an infrared (IR) wavelength since crystallization is performed using a laser having an infrared wavelength. The infrared energy absorbed in this heat transfer metal layer (HTL) is converted into heat and transferred to the amorphous semiconductor layer. At this time, considerable heat energy is also transferred to the material layer under the amorphous semiconductor layer. In particular, the gate material directly under the semiconductor layer is directly exposed to the high temperature of the crystallization process. Therefore, the gate material should be made of a metal that can withstand high temperatures. For example, molybdenum (Mo), titanium (Ti), or tungsten (W) can be considered. However, although these metal materials can be used for the gate electrode, since the surface resistance is large, a problem of signal delay occurs in the gate wiring traversing the large area display device, which is unsuitable. On the other hand, metal materials such as aluminum (Al), aluminum-neodymium (AlNd), or copper (Cu) are suitable for gate wiring with low surface resistance, Not good.

Due to such a problem, the gate electrode is first formed of a molybdenum-titanium alloy having a high melting point in order to prevent the gate metal material from being denatured due to the heat at high temperature generated in the thermal crystallization process. Then, after the thermal crystallization process is performed, a gate interconnection including low-resistance copper (which has a low melting point and can be damaged in the thermal crystallization process) is formed and connected to the gate electrode. That is, metals having high melting point characteristics are not suitable for use as wiring in a large-area panel because of their large specific resistances, and metals having low resistance are likely to be denatured at high temperatures, so that they are preferably not exposed to the crystallization process. For this reason, the mask process requires a minimum of 7 to 8 steps since the gate electrode and the gate wiring, which are gate materials, must be formed in different layers in different processes.

An object of the present invention is to provide an indirect thermal crystallization thin film transistor substrate for a large area flat panel display using a gate material of a double layer structure including a metal material having excellent heat resistance against high temperature and a metal material having a low surface resistance And a manufacturing method thereof.

According to another aspect of the present invention, there is provided a method of manufacturing an indirect thermal crystallization thin film transistor substrate, comprising the steps of: laminating and patterning a first metal layer and a second metal layer on a substrate, And patterning gate elements including a gate electrode that branches off from the gate wiring; Continuously depositing an insulating layer, an amorphous semiconductor layer, an etch stopper layer, and a heat transfer metal layer on the substrate on which the gate elements are formed, and patterning the heat transfer metal layer to form a thermal transfer pattern; Irradiating a surface of the heat transfer pattern with an infrared laser to form the amorphous semiconductor layer into a polycrystalline semiconductor layer; Removing all of the thermal transfer patterns and patterning the etch stopper layer to form an etch stopper; Drain metal on the etch stopper; patterning the source-drain metal to form a source-drain element; forming the source-drain metal layer on the etch stopper using the source- And patterning the amorphous impurity semiconductor layer to complete the polycrystalline semiconductor channel layer and the ohmic contact layer, respectively, to form the thin film transistor.

Wherein patterning the gate elements comprises patterning the first metal layer and the second metal layer stacked with a halftone mask, wherein the gate electrode comprises only the first metal layer, And the second metal layer is patterned so as to have a laminated structure.

Wherein the first metal layer comprises at least one of molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (Mo-Ti), and tungsten (W) The second metal layer may include at least one of aluminum (Al), aluminum-neodymium (AlNd) alloy, copper (Cu), and copper alloy (Cu alloy).

And the heat transfer pattern is formed to be at least 10 mu m apart from the neighboring thermal transfer pattern.

A source electrode which is branched from the data line and overlaps with one side of the gate electrode, and a source electrode which is connected to the source electrode and the source electrode, And a drain electrode spaced apart from the gate electrode and overlapping the other side of the gate electrode.

Forming a drain contact hole exposing a part of the drain and a data pad contact hole exposing the data pad, and further patterning the gate insulator to form the gate pad, Forming an exposed gate pad contact hole; A pixel electrode that contacts the drain electrode through the drain contact hole, a gate pad electrode that contacts the gate pad through the gate pad contact hole, And forming a data pad electrode in contact with the data pad through the pad contact hole.

Also, an indirect thermal crystallization thin film transistor substrate according to the present invention includes: a substrate; A gate pad including a first metal layer and a second metal layer sequentially stacked on the substrate, a gate pad connected to one end of the gate wiring, and a gate electrode including only the first metal layer and branched from the gate wiring, Element; A gate insulating film formed on the gate element; A polycrystalline semiconductor channel layer overlapping the gate electrode with the gate insulating film interposed therebetween; A source electrode in contact with one side of the polycrystalline semiconductor channel layer and overlapping the gate electrode; And a drain electrode which is spaced apart from the source electrode by a predetermined distance and overlaps the gate electrode and contacts the other side of the polycrystalline semiconductor channel layer.

A method of manufacturing an indirect thermal crystallization thin film transistor substrate according to the present invention comprises forming a gate material in a bilayer structure in which a first metal layer having high heat resistance and a second metal layer having low surface resistance are sequentially stacked. Then, the gate electrode of the double layer structure is patterned so that only the first metal layer is present, and the gate wiring is formed so that the second metal layer remains on the top. Therefore, the gate electrode and the gate wiring can be formed in the same layer, and the effect of reducing the number of mask processes can be obtained. In addition, since the gate electrode includes only the first metal layer having excellent heat resistance, thermal deformation does not occur in the thermal crystallization process. Since the gate wiring includes the second metal layer having a low surface resistance, it satisfies a low resistance condition in which no signal delay occurs in the large area display device.

1 is a plan view showing a structure of a polycrystalline thin film transistor substrate using an indirect thermal crystallization technique included in a conventional liquid crystal display device.
2A to 2I are cross-sectional views illustrating a process for manufacturing the polycrystalline thin film transistor substrate of FIG.
3 is a plan view showing a structure of a polycrystalline thin film transistor substrate using an indirect thermal crystallization technology included in a flat panel display device according to the present invention.
4A to 4G are process drawings for manufacturing the polycrystalline thin film transistor substrate of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will become more apparent from the following description of the embodiments with reference to the accompanying drawings. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to FIGS. 3 and 4A to 4G attached hereto. 3 is a plan view showing a structure of a polycrystalline thin film transistor substrate using an indirect thermal crystallization technique included in a flat panel display device according to the present invention.

Referring to FIG. 3, a thin film transistor substrate for a flat panel display (liquid crystal display or organic light emitting display) according to the present invention includes a gate line GL intersecting a gate insulating layer GI on a glass substrate SUB ), A data line DL, and a thin film transistor (TFT) formed at each of the intersections. A pixel region is defined by an intersection structure of a gate wiring GL and a data wiring DL. A pixel electrode PXL is formed in this pixel region. The thin film transistor TFT includes a gate electrode G branched from the gate wiring GL and a source electrode S branched from the data line DL and overlapped with one side of the gate electrode G and a gate electrode G And a drain electrode D overlapping the other side of the source electrode S and spaced apart from the source electrode S by a predetermined distance.

A gate pad GP and a data pad DP are formed at one end of the gate line GL and the data line DL, respectively. The gate pad GP and the data pad DP are connected to the gate pad terminal GPT and the data pad terminal GPT via the gate pad contact hole GPH and the data pad contact hole DPH, respectively.

4A to 4H, a process for fabricating the polycrystalline thin film transistor substrate according to the present invention will be described. Figs. 4A to 4G are manufacturing process drawings in cross section taken along the perforated line II-II 'in Fig. 3.

A gate metal material is deposited on the substrate (SUB). Particularly, a first metal layer G1 including molybdenum (Mo), titanium (Ti), or molybdenum-titanium (Mo-Ti) alloy is first deposited to a thickness of about 300 Å. A second metal layer G2 including aluminum (Al), aluminum-neodymium (AlNd), copper (Cu), or copper alloy (Cu Alloy) is laminated to a thickness of about 2000 Å in a continuous process. Then, gate patterns including the gate wiring GL, the gate pad GP connected to one end of the gate wiring, and the gate electrode G branched to the pixel region in the gate wiring are formed by patterning with the first mask. At this time, the gate line GL and the gate pad GP include the second metal layer G2 as the upper layer, but the gate electrode G is formed in the upper second metal layer G2 so that only the first metal layer G1, ) Is selectively removed using a halftone mask. (Fig. 4A)

An insulating material such as SiNx or SiOx is deposited on the substrate SUB on which the gate elements are formed to a thickness of 1000 A to form a gate insulating film GI. In a continuous process, a semiconductor material such as amorphous silicon is entirely deposited to a thickness of 300 占 to apply the semiconductor layer (A). In addition, an etch stopper layer (ESL) is applied by continuously depositing an insulating material such as SiNx or SiOx to a thickness of 2000 A in a continuous process. Then, in a continuous process, a metal material such as molybdenum having good thermal conductivity is deposited on the etch stopper layer (ESL) to a thickness of 1000 Å to form a thermal transfer layer. The thermal transfer layer is patterned by a second mask process to form a thermal transfer pattern (HTL). Since the heat transfer pattern HTL is for transferring heat to crystallize the amorphous semiconductor material underlying the gate electrode G, a part of the semiconductor layer A, particularly, the portion overlapping with the gate electrode G, And the like. Further, when a plurality of thin film transistors are formed, a plurality of thermal transition patterns (HTL) exist adjacent to each other in accordance with the arrangement of the thin film transistors. At this time, when the gate line GL exists between the neighboring thermal transition patterns HTL, a high temperature may be applied to the gate line GL. In order to prevent this, it is desirable that the adjacent thermal transfer pattern (HTL) is designed to be at least 10 mu m or more apart. An infrared diode laser (IR) is irradiated onto the thermal transfer pattern (HTL) by a scanning method to apply heat energy to a portion of the semiconductor layer (A), particularly to a portion overlapping the gate electrode (G) Then, the amorphous semiconductor material of the semiconductor layer (A) is crystallized and converted into a polycrystalline semiconductor material. (Figure 4b)

The purpose of indirectly transferring heat is to crystallize the amorphous semiconductor material of the semiconductor layer (A) forming the channel layer, so that it is preferable to pattern the heat transfer film so that heat can be applied only to the necessary portion. In some cases, an infrared diode laser may be irradiated to the entire thermal transfer film without patterning the thermal transfer film. In this case, the mask process number may be advantageously reduced by one. However, when the heat transfer film is not patterned, since heat is absorbed in the entire area of the substrate SUB during the crystallization process, the substrate may warp. Particularly, such a problem becomes more serious in the case of a large-area substrate such as a flat panel display. Therefore, in the case of a large-area thin film transistor substrate such as a liquid crystal display, a thermal transfer film must be patterned.

After crystallizing the semiconductor layer (A), the thermal transfer pattern (HTL) is removed by a wet etching process. Then, the etch stopper layer (ESL) exposed in the third mask process is patterned to form an etch stopper ES. It is preferable that the etch stopper ES is formed so as to overlap with a part of the semiconductor layer A superimposed on the gate electrode G. [ The etch stopper ES is formed in the process of removing the ohmic layer n between the source and drain electrodes SD when patterning the source-drain electrode SD and the ohmic layer n to be formed later. A) from being etched. In the case of a thin film transistor substrate using an amorphous semiconductor layer, since the amorphous semiconductor layer is formed in units of several thousands of angstroms, the semiconductor layer is etched to some extent (several hundred angstroms) while removing the ohmic contact layer without using an etch stopper The semiconductor layer could have a sufficient thickness. However, when the polycrystalline semiconductor layer is used, the thickness of the semiconductor layer A is formed in units of several hundreds of angstroms. Therefore, if the etch stopper is not used, the semiconductor channel layer A ' ) May all be etched away. Therefore, when a polycrystalline semiconductor layer is used, it is preferable to include an etch stopper. (Figure 4c)

An impurity semiconductor material such as n + silicon doped with n + impurity at high concentration is deposited on the substrate SUB on which the etch stopper ES is formed to coat the ohmic layer n. The ohmic layer n is an interface layer for allowing the source-drain electrodes S-D, which are spaced apart from each other by a predetermined distance above the etch stopper ES, to be formed in ohmic contact with the semiconductor layer A, (Figure 4d)

A metal material is applied to the entire surface of the substrate SUB to which the ohmic layer n is applied and patterned in the fourth mask process to form the data line DL and the data pad DP formed at one end of the data line DL, A source electrode S that branches from the line DL and overlaps with one side of the gate electrode G and a drain electrode D that faces the source electrode S and faces the source electrode S with a certain distance are formed. The ohmic contact layer n 'and the semiconductor channel layer A' are completed by continuously patterning the ohmic layer n and the semiconductor layer A using the shape of the source-drain electrode S-D as a mask. This forms a thin film transistor (TFT) as a switching element together with the source electrode S, the drain electrode D, the crystallization semiconductor channel layer A ', and the gate electrode G. At this time, the ohmic layer (n) and the semiconductor layer (A) remain in the lower part of the data pad (DP) and the data line (DL). Energy is concentrated on the channel layer A ', which is a portion where a thermal transition pattern HTL is mainly formed in the thermal crystallization process. Therefore, the data pad DP and the data line DL, which are not formed with the thermal transition pattern HTL, The underlying ohmic layer (n) and the semiconductor layer (A) may remain in the amorphous semiconductor state without being changed into the polycrystalline semiconductor. (Fig. 4E)

An insulating material such as SiNx or SiOx is entirely deposited on the entire surface of the substrate SUB on which the source-drain elements (the source electrode S, the drain electrode D, the data line DL and the data pad DP) (PAS). A passivation film PAS is patterned by a fifth mask process to form a drain contact hole DH exposing a part of the drain electrode D and a data pad contact hole DPH exposing a part of the data pad DP . At the same time, the protective film PAS and the gate insulating film GI are continuously patterned to form a gate pad contact hole GPH exposing a part of the gate pad GP. (Figure 4f)

A transparent conductive material such as ITO or IZO is deposited on the protective film (PAS). The transparent conductive material is patterned by a sixth mask process to form a pixel electrode PXL in contact with the drain electrode D, a gate pad terminal GPT in contact with the gate pad GP, To form a data pad terminal (DPT). (Figure 4g)

The indirect thermal crystallization thin film transistor substrate according to the present invention has a bilayer structure in which a gate material is formed by sequentially stacking a first metal layer having high heat resistance and a second metal layer having low surface resistance. Then, the gate electrode of the double layer structure is patterned so that only the first metal layer having excellent heat resistance is present, and the gate wiring is formed so that the second metal layer having a low surface resistance remains on the top. In addition, in order to minimize thermal energy transfer to the gate wiring in the thermal crystallization process, a thermal transfer layer is formed only in a portion corresponding to the semiconductor channel layer which needs to be crystallized. Thus, since the gate wiring and the gate electrode can be formed on the same layer, the crystallized thin film transistor substrate can be obtained by a simple process in which two mask processes are reduced as compared with the conventional technique.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TFT: thin film transistor G: gate electrode
S: source electrode D: drain electrode
A: semiconductor layer n: ohmic layer
A ': semiconductor channel layer n': ohmic contact layer
ESL: etch stopper layer ES: etch stopper
GL: gate line GP: gate pad
GPH: Gate pad contact hole GPT: Gate pad terminal
GH: gate contact hole GI: gate insulating film
DH: drain contact hole PXL: pixel electrode
DL: Data line DP: Data pad
DPH: Data pad contact hole DPT: Data pad terminal
SUB: Substrate IR: Infrared

Claims (9)

A gate wiring having a structure in which a first metal layer and a second metal layer are laminated on a substrate and patterned with a halftone mask and the first metal layer and the second metal layer are stacked; a gate pad connected to one end of the gate wiring; Comprising the steps of: patterning gate elements in a gate wiring, the gate elements including a gate electrode comprising only the first metal layer;
Continuously depositing an insulating layer, an amorphous semiconductor layer, an etch stopper layer, and a heat transfer metal layer on the substrate on which the gate elements are formed, and patterning the heat transfer metal layer to form a thermal transfer pattern;
Irradiating a surface of the heat transfer pattern with an infrared laser to form the amorphous semiconductor layer into a polycrystalline semiconductor layer;
Removing all of the thermal transfer patterns and patterning the etch stopper layer to form an etch stopper;
Drain metal on the etch stopper; patterning the source-drain metal to form a source-drain element; forming the source-drain metal layer on the etch stopper using the source- And patterning the amorphous impurity semiconductor layer to complete a polycrystalline semiconductor channel layer and an ohmic contact layer, respectively, to form a thin film transistor.
delete The method according to claim 1,
Wherein the first metal layer comprises at least one of molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (Mo-Ti), and tungsten (W)
Wherein the second metal layer comprises at least one of aluminum (Al), an aluminum-neodymium (AlNd) alloy, copper (Cu), and a copper alloy (Cu Alloy) .
The method according to claim 1,
Wherein the thermal transfer pattern is formed to be at least 10 mu m apart from the adjacent thermal transition pattern.
The method according to claim 1,
A source electrode which is branched from the data line and overlaps with one side of the gate electrode, and a source electrode which is connected to the source electrode and the source electrode, And a drain electrode spaced apart from the gate electrode and overlapping with the other side of the gate electrode.
6. The method of claim 5,
Forming a drain contact hole exposing a portion of the drain and a data pad contact hole exposing the data pad; patterning the insulating layer to expose the gate pad; Forming a gate pad contact hole to form a gate pad contact hole; And,
A gate electrode pad contacting the gate pad through the gate pad contact hole, and a gate pad electrode contacting the drain pad through the drain contact hole, Forming a data pad electrode in contact with the data pad through the hole. ≪ RTI ID = 0.0 > 21. < / RTI >
Board;
A gate pad including a first metal layer and a second metal layer sequentially stacked on the substrate and a gate pad connected to one end of the gate wiring and a gate electrode including only the first metal layer and branched at the gate wiring, Element;
A gate insulating film formed on the gate element;
A polycrystalline semiconductor channel layer overlapping the gate electrode with the gate insulating film interposed therebetween;
A source electrode in contact with one side of the polycrystalline semiconductor channel layer and overlapping the gate electrode; And
And a drain electrode which is spaced apart from the source electrode by a predetermined distance and which overlaps with the gate electrode and contacts the other side of the polycrystalline semiconductor channel layer.
8. The method of claim 7,
A data line which connects the source electrode and is orthogonal to the gate line with the gate insulating film therebetween;
A data pad connected to one end of the data line;
A protective layer covering the data line, the data pad, the source electrode, and the drain electrode;
A gate pad contact hole exposing the gate pad, a data pad contact hole exposing the data pad, and a drain contact hole exposing the drain electrode; And
Further comprising: a gate pad terminal formed on the protective film, the gate pad terminal contacting the gate pad, the data pad terminal contacting the data pad, and the pixel electrode contacting the drain electrode.
8. The method of claim 7,
Wherein the first metal layer comprises at least one of molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (Mo-Ti), and tungsten (W)
Wherein the second metal layer comprises at least one of aluminum (Al), an aluminum-neodymium (AlNd) alloy, copper (Cu), and a copper alloy (Cu Alloy).

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