M439893 五、新型說明： 【新型所屬之技術領域】 本創作係與靜電放電防護電路的保持電壓調整技術有 關，旨在提供-種能夠在互補金氧半製程中，具備高於操作 電廢之保持電1的整合㈣整流器之雙極電晶體電路。 【先前技術】 近年來，先進半導體技術隨著相演進，使得靜電放電 防護更加困難處理。在積體電路上橫向雜整流器（他加 silicon-controlled rectifier » lateral SCR) 最有效的靜電放電防護元件’因為比較其他防護元件有著較 優越的靜電放電輯臨界值。然而，它的簡電壓（h〇iding voltage ’Vh)較内部電路提供的操作電壓更低，因此在ic ==，1/〇區域周圍的外部雜訊容易觸發石夕控整流 _事件’這時栓鎖事件會導致積體電路 。而應用在高電壓製程技術的靜電 化=險較高的操作電壓’將進-步更嚴重地惡 放電===專為基礎的靜電 鎖免疫力兩者為目標。 健王μ放電缝和改善栓 改善栓鎖免疫的基本準則是盡 且超過電源電壓以達到免除減】保持電麼位準並 加陽極到陰極㈣距，直接 ^最簡單改善方法是增 直接地增加電崎電壓落在這橫越間 3 M439893 距上；或者減少寄生雙極性接面電晶體（Bipolar Juncti〇n Transistor，BJT)射極面積或在射極串聯二極體以調整射極 接面左入效果，另一方法疋調整Wei 1/substrate旁路電阻， 此外SCR結構底下增加埋藏N層亦可實現較高保持電壓。 另一概念方法是增加保持點電流（holding current)超 過最低栓鎖觸發電流而不是調整保持電壓。調整外部分流電 阻和應用有效well/substrate連結佈局技術，基極_射極電 阻可顯者減少，因此SCR要求更多we 11/substrate電流才會 達到栓鎖狀態。 < 到目前為止這些新的發展在標準技術下仍然只能讓保持 電壓維持在5V左右，文獻仍然缺乏讓保持電壓比5V更高的 合適方法，現今大多的研究成果只有傳輸線脈衝 (Transmission Line Pulse / TLP)模式而不是直流（DC)的 數據結果。 性 目前已知在不同時間測試波形可能得到不同的電氣特 ’而對於栓鎖免疫力評價因為其屬於DC特性’應做適當的 ^等級量測，因此對於1C在一般操作期間的栓鎖免疫和在( 靜電敖電打擊期間有著健全靜電防護，理想上是非常需要同 時有較高的DC保持電壓和較低TLP保持電壓。 【新型内容】 有鑑於此，本創作即在提供一種能夠在互補金氧半3.3V ，壓製程中，具備高於操作電壓之保持電壓的整合石夕控整流 器之雙極電晶體電路，為其主要目的者。 為達上述目的，本創作之整合矽控整流器之雙極電晶體 M439893 電路’基本上係由含浮接P+擴散區域或浮接N+擴散區域的雙極 電晶體結構’與作為關的金氧半電晶體雜覆蓋前述浮 區域所構成’另外閘極進—步與電阻電容電職合丨整合 控整流器雙極電晶體其設計參數為陽極/陰極和浮接 擴散區域間距L，以及浮接P+/N+擴散區域的寬度W，依據靜電 .==:決定導通金氧半開關與否調整增加減 如此可藉由調整在此電路帽s的通道長度和 _範圍^寸’得到足夠的靜電強健度和免除栓鎖的保持電壓原 曰二Ϊ上ί主要技術特徵，所述整合矽控整流器之雙極電 ^ ^ pm ==電晶體閘極覆蓋=浮== >作情況I切斷開關調整減短P+浮接擴散區域又長^正常直流操 N-well中的r為基極端；以 件的射極端；以 後p型基板裡面添加二個浮接N+擴;^的p =極為集極；然 的N型金氧半電晶體閘極 勹 ，/、-人再以作為開關 成，另外閘極進一步與二 下以導通開_整增加N+浮 $二在靜電玫電狀態 作情況下切斷開關調整減短^接擴散\長域度長度在正常直流操 5 M439893 具體而言，本創作之整合矽控整流器之雙極電晶 係可以產生下列功效： 電格 1. 可藉以控制電路的佈局最佳化。 2. 能夠得到較:高的DC保持電壓和較低TLP保持電壓， DC操作期間運作接近整合矽控整流器之雙極電晶體具有 免疫力。 、鎖 3. 在靜電放電期間運作接近矽控整流器以獲得 从你业能eM439893 V. New Description: [New Technology Field] This creation is related to the voltage-maintaining technology of the ESD protection circuit. It is intended to provide a kind of retention in the complementary gold-oxygen process. The integration of the electric 1 (four) rectifier bipolar transistor circuit. [Prior Art] In recent years, advanced semiconductor technology has evolved to make electrostatic discharge protection more difficult. The most effective ESD protection component on the integrated circuit is the silicon relay. The most effective ESD protection component is because it has a superior ESD threshold compared to other protection components. However, its simple voltage (h〇iding voltage 'Vh) is lower than the operating voltage provided by the internal circuit, so the external noise around the ic ==, 1/〇 area is easy to trigger the Shi Xi control rectification _ event 'At this time A lock event can result in an integrated circuit. The application of high-voltage process technology to electrostatics = higher operating voltages will be more serious, and the most important electrostatic discharge === specifically based on electrostatic lock immunity. Jianwang μ discharge slit and improved plugs to improve the immune standard of latch-up immunity is to exceed the power supply voltage to achieve the elimination of the reduction] to maintain the level of electricity and add the anode to the cathode (four) distance, the direct ^ the simplest improvement method is to increase directly The electric wave voltage falls on this traverse distance of 3 M439893; or the Bipolar Juncti〇n Transistor (BJT) emitter area is reduced or the emitter series diode is adjusted to adjust the emitter junction left In addition, the other method 疋 adjusts the Wei 1/substrate shunt resistor, and the addition of the buried N layer under the SCR structure can also achieve a higher holding voltage. Another conceptual approach is to increase the holding current beyond the minimum latch trigger current instead of adjusting the hold voltage. By adjusting the external shunt resistance and applying an effective well/substrate connection layout technique, the base-emitter resistance can be significantly reduced, so the SCR requires more we 11/substrate current to reach the latched state. < So far these new developments still only maintain the holding voltage at around 5V under standard technology. The literature still lacks a suitable method to keep the holding voltage higher than 5V. Most of the research results today only have transmission line pulses (Transmission Line Pulse). / TLP) mode instead of DC (DC) data results. It is currently known that testing waveforms at different times may result in different electrical characteristics' and for the evaluation of the latch immunity because it belongs to the DC characteristics 'should be properly leveled, so the 1C is immune to the lock during normal operation and There is a strong electrostatic protection during the electrostatic discharge. Ideally, it is very necessary to have a high DC holding voltage and a low TLP holding voltage. [New content] In view of this, this creation is providing a kind of complementary gold. Oxygen half 3.3V, in the pressurization process, a bipolar transistor circuit with an integrated Shi Xi-controlled rectifier with a holding voltage higher than the operating voltage is the main purpose. For the above purpose, the integrated dual-controlled rectifier of the present invention The polar transistor M439893 circuit 'is basically composed of a bipolar transistor structure containing a floating P+ diffusion region or a floating N+ diffusion region and a gold-oxide semi-transistor as a gate to cover the floating region. - Step and resistor-capacitor electric 丨 丨 integrated control rectifier bipolar transistor design parameters for the anode / cathode and floating diffusion area spacing L, and floating P + / N + expansion The width W of the scattered region is determined according to the static electricity. ==: The conduction of the gold oxide half switch is adjusted or decreased. This can be achieved by adjusting the channel length and _ range of the circuit cap s to obtain sufficient electrostatic robustness and exemption. The main technical feature of the latching voltage is the bipolar voltage of the integrated rectifier rectifier ^ ^ pm == transistor gate coverage = float == > The P+ floating diffusion region is long. ^The normal DC operation is the base extreme of r in the N-well; the emitter extreme of the piece; after the p-type substrate, two floating N+ extensions are added; ^ p = extremely collector; The N-type gold-oxygen semi-transistor gate is extremely 勹, /, - people are used as a switch, and the gate is further turned on and off with two turns to increase the N+ float $2 in the case of the electrostatic discharge state. Short-term diffusion/long-length length in normal DC operation 5 M439893 Specifically, the bipolar electro-system of the integrated controlled-controlled rectifier of the present invention can produce the following effects: Cell 1. The layout of the control circuit can be optimized 2. Can get higher: high DC hold voltage and lower TLP hold voltage, The bipolar transistor operating close to the integrated step-controlled rectifier during DC operation is immune. Lock 3. Operate close to the controlled rectifier during electrostatic discharge to get from your business
【實施方式】 而 獲得=Γ可參閱本案圖式及實施例之詳細說明 本創作係揭露-種針對靜電放電防護電路的保持電壓 整技術，其發展f點是控制電路㈣騎佳化方法，得 高的DC保持電壓和較低TLP保持電壓，以使_作期間運作接 近整合雜整流器之雙極電晶體具有拾鎖免疫力，另外在靜 電放電顧運作接近雜整流器以獲得較好防護性能狀態。# 本創作之整合⑦控整流器之雙極電晶體電路一 incorwated ΒΠ電路），基本上係由含浮接p+擴散區域或 子接N擴散區域的雙極電晶體結構，與作為開_金氧半電 晶體閘極覆蓋前述浮接區域所構成，另外閘極進—步與電阻 電容電路搞合；整合雜整流器雙極電晶體其基本設計參數 為陽極/陰極和浮接P+/N+擴散區域間距L，以及浮接以^ 擴散區_寬度W’依據靜電打擊或正f操作情況以決定導通 金氧半開關與否調整增加減短浮接擴散區域寬戶w。' M439893 在第-圖所示之實施例中，所述整合梦控整流器之 電晶體電路，該雙極電晶體結構設有P型基板1〇、N井區 mN-we⑴位於該p型基板1〇中，該p型基板1〇上並設有兩個 相連接之PNP元件2〇和_元件3〇，其中係以p型基板裡的作 極11為NPN元件的射極端；p型基板裡的p+陰極12為基極端； 以N井區70中的r陽極13為集極；然後N井區7〇中裡面添加二 個浮接P+擴散區域41，其次再以作為開關的p型金氧半電晶體 閘極51覆蓋前述二個浮接p+擴散區域41中央所構成，另外閘 馨極50進一步與電阻電容電路60(其設有相互串連之電阻及電 容）輕合’在靜電放電狀態下以導通開關調整增加p+浮接擴散 區域長度；在正常直流操作情況下切斷開關調整減短p+浮接 擴散區域長度。 在第二圖所示之實施例中，所述整合矽控整流器之雙極 電晶體電路’該雙極電晶體結構設有P型基板10、N井區 70(N—wel1)位於該P型基板10中，該P型基板10上並設有 兩個相連接之pNP元件2〇和npn元件30 ’其中係以N井區 _70中的P+陽極14為PNP元件的射極端；以N井區70中的N+ 陽極13為基極端；以p型基板裡的p+陰極12為集極；然後 P型基板1〇裡面添加二個浮接矿擴散區域42,其次再以作為 開關的N型金氧半電晶體閘極52覆蓋前述二個浮接N+擴散區 域42中央所構成，另外閘極50進一步與電阻電容電路60耦 D ’在靜電放電狀態下以導通開關調整增加N+浮接擴散區域 長度，在正常直流操作情況下切斷開關調整減短N+浮接擴散 區域長度。[Embodiment] Obtaining = Γ can refer to the drawings and detailed description of the embodiments. The present invention discloses a holding voltage integration technology for an electrostatic discharge protection circuit, and the development point f is a control circuit (four) riding optimization method, The high DC hold voltage and the lower TLP hold voltage allow the bipolar transistor operating close to the integrated hybrid to have pickup immunity, and the electrostatic discharge operates close to the hybrid rectifier for better protection performance. #本本本发明的七极整流的双极电晶体电路-incorwated ΒΠ circuit), basically consists of a bipolar transistor structure containing a floating p+ diffusion region or a sub-N diffusion region, and as an open-gold oxide half The gate of the transistor is covered by the floating region, and the gate is stepped in with the resistor-capacitor circuit; the basic design parameters of the integrated rectifier bipolar transistor are anode/cathode and floating P+/N+ diffusion region spacing L And floating to ^ diffusion zone _ width W' according to the electrostatic strike or positive f operation to determine the conduction of gold and oxygen half switch or not to increase and decrease the floating diffusion area wide household w. ' M439893 In the embodiment shown in the first embodiment, the transistor circuit of the integrated dream rectifier is provided, the bipolar transistor structure is provided with a P-type substrate, and the N well region mN-we(1) is located on the p-type substrate 1 In the p, the p-type substrate 1 is provided with two connected PNP elements 2 _ and _ elements 3 〇, wherein the pole 11 in the p-type substrate is the emitter end of the NPN element; in the p-type substrate The p+ cathode 12 is the base end; the r anode 13 in the N well region 70 is the collector; then the two floating P+ diffusion regions 41 are added to the inside of the N well region, and then the p-type gold oxide is used as the switch. The semi-transistor gate 51 is formed to cover the center of the two floating p+ diffusion regions 41, and the gate slab 50 is further combined with the resistor-capacitor circuit 60 (which is provided with resistors and capacitors connected in series) to be in an electrostatic discharge state. The conduction switch is adjusted to increase the length of the p+ floating diffusion region; in the case of normal DC operation, the switch is adjusted to shorten the length of the p+ floating diffusion region. In the embodiment shown in the second figure, the bipolar transistor circuit of the integrated step-controlled rectifier is provided with a P-type substrate 10 and an N-well region 70 (N-wel1) at the P-type. In the substrate 10, the P-type substrate 10 is provided with two connected pNP elements 2 and npn elements 30', wherein the P+ anode 14 in the N-well region_70 is the emitter end of the PNP element; The N+ anode 13 in the region 70 is the base end; the p+ cathode 12 in the p-type substrate is the collector; then two floating ore diffusion regions 42 are added to the P-type substrate 1 ,, and then the N-type gold is used as the switch. The oxygen half-gate gate 52 is formed to cover the center of the two floating N+ diffusion regions 42. In addition, the gate 50 is further coupled to the resistor-capacitor circuit 60. D' is adjusted by the conduction switch in the electrostatic discharge state to increase the length of the N+ floating diffusion region. Cut off the switch to adjust the length of the N+ floating diffusion area under normal DC operation.
原則上’上揭各實施例之電路係具有1個P/N-MOSFET 7 M439893 開關埋藏在寄生NPN/PNP BJT的N/P型基座内，同時也有 外部RC電路與P / N-MOSFET的閘極連結。p / n-MOSFET的源 極和汲極是浮接的，因此電路中這些源極和沒極是相當於先 前習用SCR- incorporated BJT的浮接P+擴散區域/N+擴散 區域，N+陽極/ P+陰極與這兩種浮接P+ / N+擴散區域會像是逆 偏二極體埋藏在N型井/P型基座，並且在第一圖及第二圖之 等效電路中連結到PNP/NPN電晶體射極。 再者，第一圖及第二圖所揭露之電路，具有浮接擴散區 域的ΒΠ關於ESD特性的主要元件設計參數是介於陽極和浮接· P+ / N+擴散區域的間距L，和浮接P+ / N+擴散區域的寬度w， 具有L=0和Ψ=4μπι的SCR- incorporated BJT原型是發展SCR- incorporated BJT電路的基礎，這種電路是製作在〇18(1111高 電壓3. 3 V CMOS製程中’如第一圖及第二圖所示，標準橫向scr 和具有P/NM0S開關SCR- incorporated BJT電路兩者有著總 元件寬度50μιη ’浮接P/N-M0SFET的源極和汲極的寬度是 4μπι’閘極通道長度Lg是0.4〜3μπι。 如前所述，標準橫向SCR擁有優秀ESD防護性能，但事實· 上是運用它所擁有的栓鎖特性才達到傑出的ESD防護性能，當 在晶片一般操作下，這特性會容易使標準SCR觸發進入栓鎖^ 況，因為前述原因，本創作主要在非ESD狀態下特別考慮它: 检鎖免疫力，如果SCR想要達到完全免除检鎖，那麼需要^比操 作電壓較高的保持電壓，在電源供應丨訐下，操作電壓幾乎 與SCR保持電壓相等，所以不易觸發進入栓鎖，在電源供應 3. 3V下使SCR達到完全免除栓鎖更加困難，亦即本創作主要考 慮電源供應3. 3V下的電路結構佈局設計為目標。 M439893 在先前習用之SCR- incorporated ΒΠ案例中，浮接擴散 區域的目的是使内部的整合SCR陽極/陰極斷路，因此整合 SCR幾乎不會觸發或啟動，使得保持電壓提升和確定增強检鎖 免疫力。本創作進一步在類似元件上安裝P / N_M〇SFET開關並 且在其閘極耦合如電阻電容電路，RC電路可扮演濾波器角 色’它有低通或是高通濾波的能力’以辨識ESD脈衝、检鎖戍 是其它不同的雜訊。因此RC電路會根據ESD狀態或是—般IC ^作情況控制esd元件觸發與否，達到最終的目的權衡ESD防 等護能力和栓鎖免疫力，所以電路ESD防護能力可能部分減弱， 但是一般操作情況會容易免除栓鎖狀態。 本創作具有PM0S/NM0S開關的整合矽控整流器之雙極 電晶體電路SCR- incorporated BJT電路，其DC保持電壓可 達到高於最大操作電壓3.6V的目標，這改善了橫向SCR在一 般操作情況容易進入栓鎖的主要缺陷，並可以獲得較 電愿3. 6V- 10.5V的完全栓鎖免疫力，況且此電路仍有非^ 好的ESD / HM性能且最佳化條件甚至超過8Kv，這表示 馨有足夠強健ESD防護臨界值。 本創作所揭露之整合石夕控整流器之雙極電晶體電路 實具備可藉以㈣電路的佈局最佳化、 持電塵和較慨，叹轉作㈣運賴2 控整流器之雙極電晶體具有㈣免疫力，以及在靜電放電= 間運作接近抑整流器以獲得較好防護性能狀態等優點。 雔，本創作提供—較佳可行之整合㈣整流器之 雙極電晶體料，爰依法提呈新型專利之申請；本創作 術内谷及技術特點巳揭示如上，然而熟悉本項技術之人士仍 9 M439893 可能基於本創作之揭示而作各種不背離本案創作精神之替換 及修飾。因此，本創作之保護範圍應不限於實施例所揭示者， 而應包括各種不背離本創作之替換及修飾，並為以下之申請 專利範圍所涵蓋。 【圖式簡單說明】 第一圖係為本創作第一實施例具有PMOS開關之整合矽控 整流器之雙極電晶體電路（SCR- incorporated BJT電路）橫切 面圖和等效電路圖。 丨 第二圖係為本創作第二實施例具有NM0S開關之整合；g夕控 整流器之雙極電晶體電路（SCR- incorporated BJT電路）椹 切面圖和等效電路圖。 【主要元件符號說明】 電阻電容電路60 N井區70 P型基板10 N+陰極11 P+陰極12 N+陽極13 P+陽極14 PNP元件20 NPN元件3〇 浮接P+擴散區域41 浮接N+擴散區域42 P型金氧半電晶體閘極51 N型金氧半電晶體閘極52In principle, the circuit of the various embodiments has one P/N-MOSFET. The M439893 switch is buried in the parasitic NPN/PNP BJT N/P type pedestal, and also has an external RC circuit and a P/N-MOSFET. The gate is connected. The source and drain of the p / n-MOSFET are floating, so these sources and immersions in the circuit are equivalent to the floating P+ diffusion region / N + diffusion region of the conventional SCR- incorporated BJT, N + anode / P + cathode With these two floating P+ / N+ diffusion regions, the reverse bias diodes are buried in the N-well/P-type pedestal, and are connected to the PNP/NPN electricity in the equivalent circuits of the first and second figures. Crystal emitter. Furthermore, the circuits disclosed in the first and second figures, the main component design parameters with respect to the ESD characteristics of the floating diffusion region are the spacing L between the anode and the floating P+ /N+ diffusion region, and the floating connection. The width of the P+ / N+ diffusion region w, the SCR- incorporated BJT prototype with L=0 and Ψ=4μπι is the basis for the development of the SCR- incorporated BJT circuit, which is fabricated in 〇18 (1111 high voltage 3. 3 V CMOS) In the process, as shown in the first and second figures, the standard lateral scr and the P/NM0S switch SCR- incorporated BJT circuit have a total component width of 50μηη 'floating P/N-M0SFET source and drain The width is 4μπι' The gate channel length Lg is 0.4~3μπι. As mentioned above, the standard lateral SCR has excellent ESD protection performance, but in fact, it uses its latching characteristics to achieve outstanding ESD protection performance. Under normal operation of the wafer, this feature can easily cause the standard SCR to trigger into the latch. For the foregoing reasons, this creation is mainly considered in the non-ESD state: Check the immunity, if the SCR wants to achieve complete exemption Then To be higher than the holding voltage of the operating voltage, under the power supply, the operating voltage is almost equal to the SCR holding voltage, so it is not easy to trigger the entry latch. It is more difficult to make the SCR completely free of latching at the power supply 3. 3V. That is, the creation mainly considers the circuit structure layout design of the power supply 3. 3V. M439893 In the previously used SCR-incorporated case, the purpose of the floating diffusion region is to make the internal integrated SCR anode/cathode open circuit. Therefore, the integrated SCR hardly triggers or starts, so that the voltage is boosted and the immunity of the lock is determined. This creation further installs a P / N_M〇SFET switch on a similar component and is coupled at its gate such as a resistor-capacitor circuit, and the RC circuit can Play the role of the filter 'it has the ability of low-pass or high-pass filtering' to identify the ESD pulse, check the lock is other different noise. Therefore, the RC circuit will control the esd component trigger according to the ESD state or the general IC ^ situation. Or not, to achieve the ultimate goal to weigh ESD protection and lock immunity, so the circuit ESD protection ability may be partially weakened, but In general operation, it is easy to avoid the latching state. This is a bipolar transistor circuit SCR- incorporated BJT circuit with integrated PM5S/NM0S switch. The DC hold voltage can reach the target of 3.6V above the maximum operating voltage. This improves the main defect that the lateral SCR can easily enter the latch in normal operation, and can obtain the full latching immunity of the electric 3.6C- 10.5V, and this circuit still has a good ESD / HM performance and The optimal conditions are even more than 8Kv, which means that Xin has a strong enough ESD protection threshold. The bipolar transistor circuit of the integrated Shi Xi-controlled rectifier disclosed in this creation has the advantages of (4) optimizing the layout of the circuit, holding the electric dust and the more versatile, and the bipolar transistor having the 2-controlled rectifier is provided. (4) Immunity, and the advantages of operating near the static discharge = rectifier to obtain better protection performance.雔, this creation provides a better and feasible integration (4) rectifier bipolar transistor material, and submits a new patent application according to law; the inner valley and technical characteristics of this creation are disclosed above, but those familiar with the technology are still 9 M439893 may be based on the disclosure of this creation and may be replaced and modified without departing from the spirit of the creation of the case. Therefore, the scope of protection of the present invention is not limited to the embodiments disclosed, but includes various alternatives and modifications that do not depart from the present invention and is covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a cross-sectional view and an equivalent circuit diagram of a bipolar transistor circuit (SCR-incorporated BJT circuit) having an integrated 矽-switched rectifier of a PMOS switch according to a first embodiment of the present invention.丨 The second figure is the integration of the NM0S switch in the second embodiment of the present invention; the bipolar transistor circuit (SCR- incorporated BJT circuit) of the g-controlled rectifier is cutaway and equivalent circuit diagram. [Main component symbol description] Resistor-capacitor circuit 60 N well region 70 P-type substrate 10 N+ cathode 11 P+ cathode 12 N+ anode 13 P+ anode 14 PNP element 20 NPN element 3 〇 floating P+ diffusion region 41 Floating N+ diffusion region 42 P Type MOS semi-transistor gate 51 N-type MOS semi-transistor gate 52