M434375 _ 101年.05月17日接正替換頁 五、新型說明： --- 【新型所屬之技術領域】 [0001] 本創作係為-種鎖相迴路，特別是指—種在壓控振 盈器中利用CMOS為主動負载之差動玫大器之鎖相迴路。 [先前技術] [0002] 目前習知之鎖相迴路（Phase L〇cked L〇〇p，pLL) 由1930年代發展至今’隨著科技的進步以及生活上的應 用中，相輔相成，使得鎖相迴路在近年來的發展快速及 普遍。並在講求電路積體化、整合性研發的電子電路研 究中’扮演了不可或缺的要角之一 ’而目前基本的鎖相 迴路（Phase Locked Loop’ PLL)由五大項電路所組成 ，其分別為一相位頻率摘測器（Phase Frequency Detector)、充電泵（Charge Pump)、迴路濾波器 (Loop Filter)、壓控振盈器（Voltage Controlled Oscillator，VCO)及除頻器（Frequency Divider)。 [0003] 然而，目前鎖相迴路（Phase Locked Loop ’ PLL) 的電路應用除了頻率合成器（Frequency Synthesizer) 與時脈資料回復接收器（Clock and Data Recovery) 外’還有追縱式濾波器 '調頻器與解調頻器、調相器與 解調相器等，而在實際生活上的應用有光碟機讀取的定 位、遙控器的發射頻率、電腦主機板匯流排傳輸速度的 同步等，皆會使用到該鎖相迴路（phase Locked Loop ，PLL) 0 [0004] 又，如中華民國發明專利公告號第504904號之「電 壓控制振盪器及使用該電壓控制振盪器之PLL電路J ’其 10022351# 單編號 A0101 第 3 頁 / 共 22 頁 1013186489-0 M434375 丨101 年; 係一種於複數段之延遲元件中，由做為電沪 晶體ϋ以輪入電壓決定之電流r.該電流被供备〜至三鏟 之換々IL器，俾輸出以反轉之極性動作之輸出，於此，一 "丨崦 組之換流器尹，相較於電晶體被供給電流對輸出端子進 行充電之期間，電晶體進行放電之期間設為較短，據此 ，則可減少容易受到溫度變化影響的電晶體之電限對頻 率產生影響，抑制溫度引起之頻率變動。 , _5] 然而，在目前習知鎖相迴路（Phase LoCked L〇〇 ，PLL)中之壓控振盪器並無利用CM〇s為主動負载之〇〇P 放大器。 、差動 [0006] 【新型内容】 爰此，為改善上述習知鎖相迴路（phase d Loop，PLL)並無利用CMOS為主動負載之差動玫C fd 控振盪器之缺失，因此本創作人致力於办 。壓 ' π九，而發風山 -種具有⑽S主動負載差動放大器之鎖相趣路免展出 含有 其係包 [0007] 一相位頻率偵測電路， 器及一去除突波修正電路， 串聯該去除突波修正電路； 包含有 且該動 —動態相一率债測 態相位頻率偵測器係 [0008] [0009] [0010] 1002235#^^ -充電泵，係、電性連接該相位頻率偵測電路； 一迴路濾波器，係電性連接該充電泵； -壓控震盘1§ ’包含有_CM〇s差動放大器一 反相器、一第二反相器、一绦椒突 、一第一 缦衝器、—可變電 固定電壓源，且該壓控震盪器係電性連接該迴路=及一 A0101 第4頁/共22頁 M434375 101年.05月17日修正替換頁 ， [0011] 一除頻器，係電性連接該壓控震盪器； [0012] 該相位頻率偵測電路會針對一訊號參考頻率與一比 較頻率作頻率與相位超前或落後的偵測，並輸出一高頻 與一低頻的訊號給該充電泵作充放電的依據，再經由該 迴路濾波器給予該壓控震盪器一個持續且平穩的電壓訊 號，使該壓控震盪器輸出一可用頻率，再經由該除頻器 除頻，而當該訊號參考頻率與比較頻率之頻率與相位達 一致時，該相位頻率偵測電路偵測無訊號輸出給該充電 泵，使該充t泵不再進行充放電，而該迴路濾波器固定 給予該壓控震盪器穩定電壓使得輸出頻率也固定，進而 讓整個迴路達到穩定且鎖定之狀態。 [0013] 進一步，該CMOS差動放大器係包含一PMOS電晶體、 一NM0S電晶體、一第一電晶體及一第二電晶體，該第一 電晶體包含有一高電位輸入端，該第二電晶體包含有一 低電位輸入端，該PM0S電晶體與第二電晶體共同包含有 一電位輸出端，而該第一反相器之一輸入端及一輸出端 分別電性連接差動放大器之電位輸出端及高電位輸入端 ，該第二反相器之一輸入端分別電性連接差動放大器之 第一電晶體之高電位輸入端及第一反相器之輸出端，而 該第二反相器另以一輸出端電性連接差動放大器之第二 電晶體之低電位輸入端，而該緩衝器分別電性連接該第 二電晶體之低電位輸入及第二反相器之輸出端，該可變 電壓源係與該差動放大器、第一反相器及第二反相器電 性連接，該固定電壓源係與緩衝器電性連接。 22351产單編號A〇101 第5頁/共22頁 1013186489-0 M434375M434375 _ 101 years. May 17th, the replacement page is 5, the new description: --- [New technology field] [0001] This creation is a kind of phase-locked loop, especially the pressure-controlled vibration The CMOS is the phase-locked loop of the differential rose of the active load. [Prior Art] [0002] The current phase-locked loop (Phase L〇cked L〇〇p, pLL) has been developed since the 1930s. With the advancement of technology and the application of life, they complement each other, making the phase-locked loop The development in recent years has been rapid and widespread. And in the research of electronic circuits that integrates circuit integration and integrated research, 'plays one of the indispensable corners' and the current basic phase-locked loop (PLL) consists of five major circuits. They are a Phase Frequency Detector, a Charge Pump, a Loop Filter, a Voltage Controlled Oscillator (VCO), and a Frequency Divider. [0003] However, the current phase-locked loop (PLL) circuit application has a frequency filter (Frequency Synthesizer) and a clock data recovery receiver (Clock and Data Recovery). Frequency modulator and demodulator, phase modulator and demodulation phase, etc., and the actual life applications include the positioning of the optical disk drive, the transmission frequency of the remote control, and the synchronization of the transmission speed of the computer motherboard. The phase locked loop (PLL) will be used. [0004] Also, as in the Republic of China Invention Patent Publication No. 504904, "Voltage Control Oscillator and PLL Circuit J' Using the Voltage Controlled Oscillator's 10022351 #单编号A0101 Page 3 of 22 1013186489-0 M434375 丨101年; is a kind of delay component in a plurality of segments, which is used as the current of the electric crystal, which is determined by the wheel-in voltage. ~ to the three shovel to change the 器IL device, 俾 output the output of the reverse polarity action, here, a " 丨崦 group of converter Yin, compared to the transistor is supplied with current to charge the output terminal During this period, the period during which the transistor is discharged is set to be short, whereby the electric potential of the transistor which is easily affected by the temperature change can be reduced to affect the frequency, and the frequency fluctuation caused by the temperature can be suppressed. _5] However, at present The voltage-controlled oscillator in the conventional phase-locked loop (Phase LoCked L〇〇, PLL) does not use the 〇P amplifier with CM〇s as the active load. Differential [0006] [New content] In order to improve the above-mentioned conventional locks Phase d Loop (PLL) does not use CMOS as the active load of the differential Rose C fd controlled oscillator, so this creator is committed to. Press 'π九, and the wind-mountain has (10)S initiative The load differential amplifier is locked out of the game with its package [0007] a phase frequency detection circuit, a de-emphasis correction circuit, and the de-emphasis correction circuit in series; Phase-to-one debt measurement phase frequency detector system [0008] [0009] [0010] 1002235#^^ - a charge pump that is electrically connected to the phase frequency detection circuit; a primary loop filter that is electrically connected The charge pump; - pressure control Disk 1 § 'contains _CM〇s differential amplifier-inverter, a second inverter, a pepper, a first buffer, a variable electrical fixed voltage source, and the voltage control oscillation The circuit is electrically connected to the circuit = and an A0101 page 4 / a total of 22 pages M434375 101. May 17 revised replacement page, [0011] a frequency divider, is electrically connected to the voltage controlled oscillator; [0012 The phase frequency detecting circuit detects the frequency and phase lead or backward for a signal reference frequency and a comparison frequency, and outputs a high frequency and a low frequency signal to charge and discharge the charging pump, and then The loop filter gives the voltage controlled oscillator a continuous and stable voltage signal, so that the voltage controlled oscillator outputs an available frequency, and then divides the frequency by the frequency divider, and when the frequency of the reference frequency and the comparison frequency of the signal is When the phase is consistent, the phase frequency detecting circuit detects that no signal is output to the charging pump, so that the charging pump is no longer charged and discharged, and the loop filter is fixed to give the voltage controlled oscillator a stable voltage so that the output frequency is also Fixed, and then let the whole loop A stable and locked state is achieved. [0013] Further, the CMOS differential amplifier includes a PMOS transistor, an NMOS transistor, a first transistor, and a second transistor. The first transistor includes a high potential input terminal, and the second transistor The crystal includes a low-potential input terminal, and the PMOS transistor and the second transistor jointly include a potential output end, and one input end and one output end of the first inverter are electrically connected to the potential output end of the differential amplifier And a high-potential input terminal, wherein one input end of the second inverter is electrically connected to the high-potential input end of the first transistor of the differential amplifier and the output end of the first inverter, and the second inverter The output terminal is electrically connected to the low potential input end of the second transistor of the differential amplifier, and the buffer is electrically connected to the low potential input of the second transistor and the output end of the second inverter respectively. The variable voltage source is electrically connected to the differential amplifier, the first inverter and the second inverter, and the fixed voltage source is electrically connected to the buffer. 22351 Production Order No. A〇101 Page 5 of 22 1013186489-0 M434375
I 皿年 DMI dish year DM
[0014] 進一步，該動態相位頻率偵測電路包含有二半穿^ 暫存器且電性連接一NAND邏輯閘。 [0015] 進一步’該充電泵包含有十二個MOS電晶體相互電性 連接’各該MOS電晶體分別為第一m〇S電晶體、第二MOS 電晶體、第三MOS電晶體、第四MOS電晶體、第五MOS電 晶體、第六MOS電晶體、第七m〇S電晶體、第八MOS電晶 體、第九MOS電晶鱧、第十m〇S電晶體、第十一MOS電晶 體及第十二MOS電晶體。 [0016] 進一步’該迴路濾波器係為一二階低通濾波器》 [0017] 進一步，該除頻器係為除2電路。 [0018] 本創作具有下列之優點： [0019] 1·本創作在鎖相迴路（PLL)中之壓控振盪器利用 CMOS差動放大器有較穩定之鎖定頻率。 [0020] 2.本創作在鎖相迴路（PLL)中之壓控振盪器利用 CMOS差動放大器有較高之輸出功率。 [0021] 3.本創作利用差動式的高輸入阻抗、高輸出阻抗和 高電壓增益來實現壓控振盪器電路並將運用在鎖相迴路 (Phase Locked Loop > PLL)t [0022] 4.本創作除了功能上的提昇之外，還同時兼具實用 之設計效果。 【實施.方式】 [0023] 有關本創作之技術特徵及增進功效，配合下列圖式 之較佳實施例即可清楚呈現，首先，請參閱第一圖及第 1013186489-0 1002235#單编號A〇101 第6頁/共22頁 M434375 修正 1101年.05月17日 一圖所示，一鎖相迴路（Phase Locked Loop，PLL)其 係包含有' : [0024] 一相位頻率偵測電路（1)，且該相位頻率偵測電路 (1)包含有一動態相位頻率偵測器（11)及一去除突波修正 電路（12)，且該動態相位頻率偵測器（1丨）係串聯該去除 突波修正電路（12); —充電泵（2)，且該充電泵（2)係電 性連接該相位頻率偵測電路（1); 一迴路濾波器（3)，且 該迴路濾波器（3)係電性連接該充電泵（2); —壓控震盪 器（4) ’且該壓控震盪器（4)係電性連接該迴路濾波器 (3); —除頻器（5)，係電性連接該壓控震盪器（4);其 中該相位頻率偵測電路（1)會針對一訊號參考頻率與一比 較頻率[如第一圖所示]作頻率與相位超前或落後的偵測 ，並輸出一高頻與一低頻的訊號[如第一圖所示]給該充 電泵（2)作充放電的依據’再經由該迴路濾波器（3)給予 s亥壓控震盪器（4) 一個持續且平穩的電壓訊號，使該壓控 震盥器（4)輸出一可用頻率，並且再經由該除頻器（5)除 頻’然而’當該訊號參考頻率與比較頻率之頻率與相位 達一致時’即該相位頻率偵測電路（1)偵測無訊號輸出給 該充電泵（2)，使該充電泵（2)不再進行充放電，而該迴 路濾波器（3)固定給予該壓控震盪器（4) 一穩定電壓使得 輸出頻率也固定，進而讓整個迴路達到穩定且鎖定之狀 態。 [0025] 再者’進一步說明該相位頻率偵測電路（1)請參閱第 一圖及第一圖所示，該相位頻率偵測電路（1)包含有一動 態相位頻率偵測器（⑴及_去除突波修正電路（⑵其 10022351#單編號 A〇101 第7頁/共22頁 1013186489-0 M434375 101:年05月17日梭正替換頁 中該動態相位頻率偵測器（1 1 )係合併有二個半穿透暫存 器[Hatf-Transpareiit Register，HT Register](lll)及一個NAND邏輯閘（112)，而該動態相 位頻率偵測器（11)係利用該NAND邏輯閘（11 2)去延遲 RST訊號’因此在鎖相迴路（phase Locked Loop， PLL)鎖定時’該相位頻率偵測電路（丨）將會產生出相同脈 波寬度的UP與DN訊號，所以利用該相位頻率偵測電路（i) 可以偵測出相位與頻率的差值》 [0026] 再者’進一步說明該充電泵（2)請參閱第一圖及第三 圖所示’在該充電泵（2)電路中係包含有十二個M0S電晶 體相互電性連接，且分別為第一M0S電晶體（21) [Ml]、 第二M0S電晶體（22)[M2]、第三M0S電晶體（23)[M3]、 第四仙3電晶體（24)[M4]、第五M0S電晶體（25)[M5]、 第六M0S電晶體（26)[M6]、第七M0S電晶體（27)[M7]、 第八M0S電晶體（28)[M8]、第九M0S電晶體（29)[M9]、 第十M0S電晶體（210)[M10]、第十一M0S電晶體 (211)[M11]及第十二M0S電晶體（212)[M12]，其中第五 M0S電晶體（25)[M5]、第六M0S電晶體（26)[M6]、第七 M0S電晶體（27)[M7]、第八M0S電晶體（28)[M8]、第九 M0S電晶體（29)[M9]係為電流鏡，而第一M0S電晶體 (21)[M1]、第二M0S電晶體（22)[M2]、第四M0S電晶體 (24)[M4]、第十一M0S電晶體（211)[M11]係產生參考電 流’而第三M0S電晶體（23)[M3]及第十二M0S電晶體 (212)[M12]係為依照接收的訊號端：一 UPB端（213)與 一 DN端（215)，進而判斷該充電泵（2)的充電或者放電， 最後再由一Cout端（214)輸出，並且可以有效降低電荷 10022351^·^^^ A0101 第8頁/共22頁 1013186489-0 M434375 分子的效應。 [0027] 再者’進一步說明該迴路濾波器（3)請參閱第一圖及 第四圖所示，該迴路濾波器（3)係為一二階低通濾波器， 其係包含有前述Cout端（214)、一電阻Rl(31)、一電容 Cl(32)、一電容C2(33)與一可變電壓源[Vctrl] (34) ’在該鎖相迴路（Phase Locked Loop，PLL)中若不提 供該低通濾波器，則系統中會具有兩極點，若再有一零 點將會造成系統一開始不穩定的狀況，而利用該低通濾 波器在該鎖相迴路（Phase Locked Loop，PLL)中能提 供一個零點補償，因此能使整個系統趨於穩定。 [0028] 101年.05月17日[0014] Further, the dynamic phase frequency detecting circuit includes a second half of the register and is electrically connected to a NAND logic gate. [0015] Further, the charging pump includes twelve MOS transistors electrically connected to each other. Each of the MOS transistors is a first m〇S transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, fifth MOS transistor, sixth MOS transistor, seventh m〇S transistor, eighth MOS transistor, ninth MOS transistor, tenth m〇S transistor, eleventh MOS Crystal and twelfth MOS transistor. [0016] Further, the loop filter is a second-order low-pass filter. [0017] Further, the frequency divider is a divide-by-2 circuit. [0018] This creation has the following advantages: [0019] 1. The voltage controlled oscillator of the present invention in a phase locked loop (PLL) utilizes a CMOS differential amplifier with a relatively stable locking frequency. [0020] 2. The voltage controlled oscillator of the present invention in a phase locked loop (PLL) utilizes a CMOS differential amplifier with a higher output power. [0021] 3. This creation uses a differential high input impedance, high output impedance and high voltage gain to implement a voltage controlled oscillator circuit and will be used in a phase locked loop (Phase Locked Loop > PLL) t [0022] 4 In addition to the functional enhancement, this creation also has a practical design effect. [Implementation. Modes] [0023] The technical features and enhancements of the present invention can be clearly presented in conjunction with the preferred embodiments of the following figures. First, please refer to the first figure and the 1013186489-0 1002235# single number A 〇101 Page 6 of 22 M434375 Correction 1101. May 17th, as shown in the figure, a Phase Locked Loop (PLL) system contains ' : [0024] a phase frequency detection circuit ( 1), and the phase frequency detecting circuit (1) comprises a dynamic phase frequency detector (11) and a removal surge correction circuit (12), and the dynamic phase frequency detector (1丨) is connected in series Removing the surge correction circuit (12); - a charge pump (2), and the charge pump (2) is electrically connected to the phase frequency detecting circuit (1); a loop filter (3), and the loop filter (3) electrically connected to the charge pump (2); - voltage controlled oscillator (4) ' and the voltage controlled oscillator (4) is electrically connected to the loop filter (3); - frequency divider (5 ), electrically connecting the voltage controlled oscillator (4); wherein the phase frequency detecting circuit (1) is for a signal reference frequency and a comparison frequency [ As shown in the first figure, the frequency and phase are detected in advance or backward, and a high frequency and a low frequency signal are output [as shown in the first figure] to charge and discharge the charge pump (2). A continuous and smooth voltage signal is given to the voltage controlled oscillator (4) via the loop filter (3), so that the voltage controlled oscillator (4) outputs an available frequency, and then via the frequency divider (5) The frequency division 'however' when the frequency and phase of the reference frequency of the signal and the comparison frequency are the same, that is, the phase frequency detecting circuit (1) detects no signal output to the charging pump (2), so that the charging pump ( 2) The charging and discharging are no longer performed, and the loop filter (3) is fixedly given to the voltage controlled oscillator (4). A stable voltage is applied so that the output frequency is also fixed, thereby allowing the entire loop to reach a stable and locked state. [0025] Furthermore, the phase frequency detecting circuit (1) is further described. Referring to the first figure and the first figure, the phase frequency detecting circuit (1) includes a dynamic phase frequency detector ((1) and _ Remove the glitch correction circuit ((2) its 10022351# single number A 〇 101 page 7 / total 22 page 1013186489-0 M434375 101: May 17th, the shuttle is replacing the dynamic phase frequency detector (1 1) The two half-transmissive registers [Hatf-Transpareiit Register, HT Register] (lll) and a NAND logic gate (112) are combined, and the dynamic phase frequency detector (11) utilizes the NAND logic gate (11). 2) De-delay RST signal 'When the phase locked loop (PLL) is locked, the phase frequency detection circuit (丨) will generate UP and DN signals with the same pulse width, so use the phase frequency The detection circuit (i) can detect the difference between phase and frequency. [0026] Furthermore, the further explanation of the charge pump (2) can be seen in the first and third figures 'in the charge pump (2) The circuit includes twelve MOS transistors electrically connected to each other, and is respectively the first MOS Transistor (21) [Ml], second MOS transistor (22) [M2], third MOS transistor (23) [M3], fourth fairy 3 transistor (24) [M4], fifth MOS Crystal (25) [M5], sixth MOS transistor (26) [M6], seventh MOS transistor (27) [M7], eighth MOS transistor (28) [M8], ninth MOS transistor ( 29) [M9], a tenth MOS transistor (210) [M10], an eleventh MOS transistor (211) [M11], and a twelfth MOS transistor (212) [M12], wherein the fifth MOS transistor (25) [M5], sixth MOS transistor (26) [M6], seventh MOS transistor (27) [M7], eighth MOS transistor (28) [M8], ninth MOS transistor (29) [M9] is a current mirror, and the first MOS transistor (21) [M1], the second MOS transistor (22) [M2], the fourth MOS transistor (24) [M4], the eleventh MOS The transistor (211) [M11] generates a reference current ' while the third MOS transistor (23) [M3] and the twelfth MOS transistor (212) [M12] are in accordance with the received signal terminal: a UPB terminal ( 213) and a DN end (215), thereby determining the charging or discharging of the charging pump (2), and finally outputting by a Cout terminal (214), and can effectively reduce the charge 10022351^·^^^ A0101 8th / 1013186489-0 M434375 effector molecules of 22. [0027] Furthermore, the circuit filter (3) is further described as shown in the first and fourth figures. The loop filter (3) is a second-order low-pass filter, which includes the aforementioned Cout. The terminal (214), a resistor R1 (31), a capacitor Cl (32), a capacitor C2 (33) and a variable voltage source [Vctrl] (34) 'in the phase locked loop (PLL) If the low-pass filter is not provided, the system will have two poles. If there is another zero point, the system will be unstable at first, and the low-pass filter is used in the phase-locked loop (Phase Locked Loop, A zero offset can be provided in the PLL), thus making the entire system stable. [0028] 101 years. May 17th
再者’進一步說明請參閱第一圖及第五圖所示，係 本創作之特徵所在，係為前述壓控震盪器（4)之詳細電路 圖，其係包含有一CMOS差動放大器（41)、一第一反相器 (42)、一第二反相器（43)、一緩衝器（44)，且該CMOS 差動放大器（41)連接有一可變電壓源[Vctrl](34)，而 該緩衝器（44)包含有一輸入端（441)及一輸出端（442)， 且該緩衝器（44)連接有一固定電壓源[Vdd](443)，其中 該CMOS差動放大器（41)包含有一 PM0S電晶體（411)、一 NM0S電晶體（412)、一第一電晶體（413)、一第二電晶體 (414) ，以及該第一電晶體（413)包含有一高電位輸入端 (415) ’而該第二電晶體（414)包含有一低電位輸入端 (416) ，而該PM0S電晶體（411)與該第二電晶體（414)共 同包含有一電位輸出端（417);而該第一反相器（42)之 輸入端（421)係電性連接該電位輸出端（417)，而該第一 反相器（42)之輸出端（422)則係電性連接該高電位輸入 10022351 产單编號 A0101 第9頁/共22頁 1013186489-0 M434375 101年.05月17日接正替換頁 端（415);而該第二反相器（43)之輸入端（431)係電性連 接該高電位輪入端（415)，·而該第二反相器（43)之輸出 端（432)係電性連接該低電位輸入端（416);而該緩衝器 (44)包含有一輸入端（441)及一輸出端（442)，其中該緩 衝器（44)之輸入端（441)係電性連接該第二反相器（43) 之輸出端（432)與該低電位輸入端（416)，而該緩衝器 (44)係電性連接有一固定電壓源[Vdd](443)，而最後由 該緩衝器（44)之輸出端（442)輸出。 [0029] 再者，請參閱第五圖及第六圖所示，第六圖係為前 述壓控震盪器（4)之簡化邏輯圖，該壓控震盪器（4)包含 有該CMOS差動放大器（41)串聯該第一反相器（42)，該第 一反相器（42)再串聯該第二反相器（43)，而該第二反相 器（43)再串聯該緩衝器（44)。 [0030] 再者，請參閱第一圖、第七圖及第八圖所示，第七 圖及第八圖係為一除2電路示意圖以及一除2詳細電路圖 ，當CLK端之輸入為in時，則Q端之輸出則為in/2，該除 頻器（5)係利用真單相時脈（True Single-Phase Clock ’ TSPC)，因此只需要單一時脈訊號而不需要反相 的時脈訊號，因此可相對的減少延遲時間、簡化電路的 複雜度以及具備有良好的整波功能，並且可依照使用者 之設計串接N級，以達到除頻之效果。 [0031] 再者，請參閱第九圖所示，係為一鎖定頻率與輸出 功率圖，係由模擬軟體模擬出之波型圖，其中例如：m3 之頻率為2. 880GHz，而dBm為8. 483。 [0032] 10022351^^^^ A0101 惟以上所述僅係為本創作之較佳實施例，當不能以 第10頁/共22頁 1013186489-0 M434375 [0033] [0034] [0035] [0036] [0037] [0038] [0039] [0040] [0041] [0042] 1002235#^'^ ΙΟί年.05月17日修正替_頁 此限定本創作實施之範圍，即依本創作申請專利範圍及 新型說明内容所作簡單的等效變化與修飾，皆屬本創作 專利涵蓋之範圍内。 【圖式簡單說明】 第一圖係為本創作之結構方塊圖。 第二圖係為本創作之相位頻率偵測電路之電路圖， 說明包含有一動態相位頻率偵測器及一去除突波修正電 路。 第三圖係為本創作之充電泵之電路圖。 第四圖係為本創作之迴路濾波器之電路圖。 第五圖係為本創作之壓控振盪器之電路圖。 第六圖係為本創作之壓控振盪器之簡化邏輯圖。 第七圖係為本創作之除頻器電路示意圖，說明除2電 路。 第八圖係為本創作之除頻器詳細電路示意圖，說明 除2電路。 第九圖係為本創作之鎖定頻率與輸出功率圖。 【主要元件符號說明】 (I) 相位頻率偵測電路 (II) 動態相位頻率偵測器 (III) 半穿透暫存器 (1 1 2 ) NAND邏輯閘 (12) 去除突波修正電路 A0101 第11頁/共22頁 1013186489-0 M434375 101年.05月17日梭正替換頁 (2 ) (21) 充電泵 第一 Μ 0 S電晶體 (22) 第二Μ0 S電晶體 (23) 第二MO S電晶體 (24) 第四Μ0 S電晶體 (25) 第五MO S電晶體 (26) 第六Μ〇 S電晶體 (27) 第七Μ 0 S電晶體 (28) 第八Μ0 S電晶體 (29) 第九MO S電晶體 (210) 第十MO S電晶體 (211) 第十一MO S電晶體 (212) 第十二Μ 0 S電晶體 (2 1 3 ) u P B端 (214) Cout端 (2 1 5 ) D N端 (3) 迴路濾波器 (31) R1 (32) C1 (33) C 2 (34) 可變電壓源 (4) 壓控振盪器 (41) CMO S差動放大器 (411) PM0S電晶體 (412) NMOS電晶體 (4 1 3)第一電晶體 1002235#單编號 A0101 第12頁/共22頁 1013186489-0 M434375 •101年.05月17日修正替換頁 (414) 第二電晶體 (415) 向電位輸入端 (416) 低電位輸入端 (417) 電位輸出端 (42) 第一反相器 (4 21 )輸入端 (4 2 2 )輸出端 (43) 第二反相器 (4 31 )輸入端 (4 3 2)輸出端 (44) 緩衝器 (4 41 )輸入端 (4 4 2 )輸出端 (4 4 3 )固定電壓源 (5 ) 除頻器 （5 1)除2電路 10022351#單編號 A〇101 第13頁/共22頁 1013186489-0Furthermore, please refer to the first and fifth figures. The feature of this creation is the detailed circuit diagram of the above-mentioned voltage controlled oscillator (4), which includes a CMOS differential amplifier (41). a first inverter (42), a second inverter (43), a buffer (44), and the CMOS differential amplifier (41) is connected to a variable voltage source [Vctrl] (34), and The buffer (44) includes an input terminal (441) and an output terminal (442), and the buffer (44) is connected to a fixed voltage source [Vdd] (443), wherein the CMOS differential amplifier (41) comprises There is a PM0S transistor (411), an NM0S transistor (412), a first transistor (413), a second transistor (414), and the first transistor (413) includes a high potential input terminal ( 415) 'and the second transistor (414) includes a low potential input terminal (416), and the PMOS transistor (411) and the second transistor (414) together comprise a potential output terminal (417); An input end (421) of the first inverter (42) is electrically connected to the potential output end (417), and an output end of the first inverter (42) ( 422) is electrically connected to the high potential input 10022351 production order number A0101 page 9 / total 22 pages 1013186489-0 M434375 101 years. May 17th replace the replacement page end (415); and the second inversion The input end (431) of the device (43) is electrically connected to the high potential wheel end (415), and the output end (432) of the second inverter (43) is electrically connected to the low potential input end. (416); the buffer (44) includes an input terminal (441) and an output terminal (442), wherein the input terminal (441) of the buffer (44) is electrically connected to the second inverter ( 43) an output terminal (432) and the low potential input terminal (416), and the buffer (44) is electrically connected to a fixed voltage source [Vdd] (443), and finally by the buffer (44) Output (442) output. [0029] Furthermore, please refer to the fifth and sixth figures, the sixth figure is a simplified logic diagram of the aforementioned voltage controlled oscillator (4), the voltage controlled oscillator (4) includes the CMOS differential An amplifier (41) is connected in series with the first inverter (42), the first inverter (42) is connected in series with the second inverter (43), and the second inverter (43) is connected in series with the buffer (44). [0030] Furthermore, please refer to the first, seventh and eighth figures. The seventh and eighth diagrams are a schematic diagram of the divide-by-2 circuit and a detailed circuit diagram of the divide-by-2, when the input of the CLK terminal is in The output of the Q terminal is in/2, and the frequency divider (5) utilizes a True Single-Phase Clock 'TSPC, so only a single clock signal is needed and no inversion is required. The clock signal can reduce the delay time, simplify the circuit complexity, and have good wave shaping function. It can be connected to the N level according to the user's design to achieve the effect of frequency division. [0031] Furthermore, please refer to the figure ninth, which is a lock frequency and output power diagram, which is a waveform diagram simulated by a simulation software, wherein, for example, the frequency of m3 is 2.880 GHz, and the dBm is 8. 483. [0032] 10022351^^^^ A0101 However, the above description is only a preferred embodiment of the present invention, when it is not possible to use page 10 / total 22 pages 1013186489-0 M434375 [0033] [0035] [0036] [0040] [0040] [0042] [0042] [0042] 1002235 #^'^ ΙΟί年. May 17th revised for the _ page this limit the scope of the implementation of this creation, that is, according to the scope of the patent application and The simple equivalent changes and modifications made to the new description are within the scope of this creation patent. [Simple description of the diagram] The first diagram is a block diagram of the structure of the creation. The second figure is a circuit diagram of the phase frequency detecting circuit of the present invention, and the description includes a dynamic phase frequency detector and a removing surge correction circuit. The third picture is the circuit diagram of the created charge pump. The fourth picture is the circuit diagram of the loop filter of this creation. The fifth picture is the circuit diagram of the voltage controlled oscillator of this creation. The sixth picture is a simplified logic diagram of the voltage controlled oscillator of this creation. The seventh figure is a schematic diagram of the circuit of the frequency divider of this creation, illustrating the elimination of 2 circuits. The eighth figure is a detailed circuit diagram of the frequency divider of this creation, illustrating the addition of 2 circuits. The ninth figure is the lock frequency and output power diagram of the creation. [Main component symbol description] (I) Phase frequency detection circuit (II) Dynamic phase frequency detector (III) Semi-transmissive register (1 1 2) NAND logic gate (12) Removal surge correction circuit A0101 11 pages/total 22 pages 1013186489-0 M434375 101 years. May 17th Shuttle replacement page (2) (21) Charge pump first Μ 0 S transistor (22) Second Μ 0 S transistor (23) Second MO S transistor (24) fourth Μ 0 S transistor (25) fifth MO S transistor (26) sixth Μ〇 S transistor (27) seventh Μ 0 S transistor (28) eighth Μ 0 S Crystal (29) Ninth MO S transistor (210) Tenth MO S transistor (211) Eleventh MO S transistor (212) Twelfth Μ 0 S transistor (2 1 3 ) u PB terminal (214 Cout end (2 1 5 ) DN end (3) Loop filter (31) R1 (32) C1 (33) C 2 (34) Variable voltage source (4) Voltage controlled oscillator (41) CMO S differential Amplifier (411) PM0S transistor (412) NMOS transistor (4 1 3) first transistor 1002235# single number A0101 page 12 / total 22 pages 1013186489-0 M434375 • 101 years. May 17 revision replacement page (414) Second transistor (415) to potential input (416) low potential input (417) potential input Out terminal (42) first inverter (4 21 ) input (4 2 2 ) output (43) second inverter (4 31 ) input (4 3 2) output (44) buffer ( 4 41 ) Input (4 4 2 ) Output (4 4 3 ) Fixed voltage source (5) Frequency divider (5 1) Divide 2 circuit 10022351#Single number A〇101 Page 13/Total 22 Page 1013186489-0