M422758 五、新型說明： 【新型所屬之技術領域】 本創作係關於一種太陽能電池及其背面電極結構。 【先前技術】 由於目前全球的石油化燃料逐漸括蝎，因此人們積極 尋找及開發替代的能源’如太陽能發電、風力發電及水力 發電…等，而其中係以太陽能的利用為最主要的技術發展 # 方向’其因在於太陽光可照射在全球各個地區，且太陽能 在進行轉換的過程係不會對環境造成汙染，舉例來說，在 太陽光能轉換為電能的過程中’無須藉由消耗其他能源而 導致溫室效應的問題。但是，太陽能轉換為電能的轉換效 率卻容易受限於整個太陽能電池系統的機構設計。 基本的太爿b電池系構可分為ρ·Ν二極體（PN Diode )、抗反射層（Antireflection )、和正面金屬電極（Fr〇nt contact metal)、及背面金屬電極（Back c〇ntact咖㈤）等 .·四個部份。 其中，背面電極的製程方式為將鋁膠以網版印刷 (Scireen Printing )或蒸錄之方法’於晶圓半成品的表面上 製作出導電電極’高溫燒結後做為背面電場（BSF)，以辦 加載子收集效率。然而，文獻中指出背面電場仍無法有效 的降低表面再結合速率（SRV)，因此為了降低載子電流的 複合效應’有效方法可於基板及背面電極之間設置一 層。由於鈍化層之設置，使得基板與背面電極無法直 3 M422758 性連接，因此必須藉由物理或化學的方式於純化層上產生 開孔，再以燒結之方式使基板與背面電極共溶而達到相互 電性連接。 於習知技術中，係設置一整層的铭膠於鈍化層，於燒 結的同時，铭分子與妙分子會達到—共炫（邮灿。）组成 的溫度’此時兩種物質會於互_素下相互流動，也就是 石夕基板㈣分子會流⑽膠，同時_巾馳分子會流向 石夕基板。而物質本身流動性還有相平衡的因素，在低於共 融溫度時兩者物質會回至原本的組成，但由於石夕分子在銘 膠中流動速度彳Mf ’使得在降溫軸流賴分子I法快速 流回原本區域，導致部分於固化後㈣基板與_連接處 會產生複數空洞，此不僅降低基板與背面電極的電性連接 度’更使得太陽能電池整體的效率降低。 因此，如何提供一種太陽能電池及其背面電極結構， 其在增加基板與背面電極電性連接程度的同時，更可避免 於基板及身面電極之間形成空洞，進而提升太陽能電池的 光電轉換效率，已成為太陽能製造產業的焦點課題。 【新型内容】 有鑑於上述課題，本創作之目的為提供一種太陽能電 池背面電極結構，能夠增加基板與背面電極電性連接程 度’更可避免形成空洞於基板及導電材料之間，以提升背 面電極的導電率。 為達上述目的，依據本創作之一種太陽能電池背面電 M422758 極結構包括一基板、一鈍化層及複數導電材料。純化層設 置於基板，且鈍化層具有複數開孔。該些導電材料間隔設 置於鈍化層，該些導電材料經由該些開孔連接基板° 於本創作之一實施例中，基板為N型半導體基板或P 型半導體基板。 於本創作之一實施例中，該些導電材料係與鈍化層的 該些開孔對應設置。 於本創作之一實施例中，當該些開孔可為非連續設 φ 置。 於本創作之一實施例中，鈍化層的該些開孔具有一第 一寬度，第一寬度係大於50μιη小於300μιη。 於本創作之一實施例中，該些導電材料具有一第二寬 度，第二寬度係大於50μηι小於500μιη，第二寬度大於或 等於第一寬度。 於本創作之一實施例中，該些導電材料具有一高度， 高度係大於5μιη小於40μιη。 ® 為達上述目的，依據本創作之一種太陽能電池包括一 基板、二鈍化層及複數導電材料。基板具有一第一表面及 一第二表面’該些鈍化層分別設置於基板的第一表面及第 二表面’其中一鈍化層具有複數開孔《該些導電材料間隔 設置於具有該些開孔的鈍化層，該些導電材料經由該些開 孔連接基板。 於本創作之一實施例中，基板為Ν型半導體基板或ρ 型半導體基板。 5 M422758 於本創作之一實施例中，鈍化層的該些開孔具有一第 一寬度，第一寬度係大於50μιη小於300μιη。 於本創作之一實施例中，該些導電材料具有一第二寬 度’第二寬度係大於50μιη小於500μιη，第二寬度大於或 等於第一寬度。 於本創作之一實施例中，該些導電材料具有一高度， 高度係大於5μιη小於40μηι。 承上所述’本創作之太陽能電池背面電極結構，係藉 由具有開孔的鈍化層及導電材料的設置，使得設置於背光 表面的導電材料經高溫燒結後，能與基板相連接，以達到 形成背面電場的目的。值得注意的是，於背光表面的鈍化 層形成複數開孔，接續將導電材料設置於該鈍化層，使得 基板與導電材料於燒結時，可相互融合，達到較佳的電性 連接；且於基板與導電材料固化後，更可避免於基板及導 電材料之間形成空洞，進而提升背面電極的導電率。 【實施方式】 同的參照符號加以說明。 以下將參照相關式，說明依本創作較佳實施例之一 種太陽能電池及其背面電極結構，其中相同以件將以相 凊參照圖1及圖2所示，圖1為本貪 一種太陽—— 為本創作較佳實施例之M422758 V. New description: [New technical field] This creation is about a solar cell and its back electrode structure. [Prior Art] As the world's petrochemical fuels are gradually being scrutinized, people are actively searching for and developing alternative energy sources such as solar power, wind power and hydropower... among which the use of solar energy is the most important technological development. The reason for #direction is that sunlight can be irradiated in various parts of the world, and the process of solar energy conversion does not pollute the environment. For example, in the process of converting solar energy into electricity, it is not necessary to consume other Energy causes a greenhouse effect. However, the conversion efficiency of solar energy into electrical energy is easily limited by the mechanical design of the entire solar cell system. The basic solar cell structure can be divided into ρ·Diode (PN Diode), antireflective layer (Antireflection), and front metal electrode (Fr〇nt contact metal), and back metal electrode (Back c〇ntact). Coffee (5)) and so on. Four parts. The back electrode is processed by a method of screen printing (Scireen Printing or steaming) to form a conductive electrode on the surface of the semi-finished product of the wafer to be sintered at a high temperature and then used as a back surface electric field (BSF). Load collection efficiency. However, it is pointed out in the literature that the back surface electric field still cannot effectively reduce the surface recombination rate (SRV), so in order to reduce the composite effect of the carrier current, an effective method can provide a layer between the substrate and the back electrode. Due to the setting of the passivation layer, the substrate and the back electrode cannot be directly connected to each other. Therefore, it is necessary to form an opening in the purification layer by physical or chemical means, and then the substrate and the back electrode are co-dissolved by sintering to achieve mutual Electrical connection. In the prior art, a whole layer of gelatin is placed on the passivation layer. At the same time of sintering, the molecular and the molecular molecules will reach the temperature of the composition (the postal temperature). At this time, the two substances will interact with each other. _ under the mutual flow, that is, the Shixi substrate (four) molecules will flow (10) glue, while the _ toweling molecules will flow to the Shixi substrate. The fluidity of the material itself is also a factor of phase balance. When the temperature is lower than the temperature of the co-melting, the two materials will return to the original composition, but because the flow velocity of the Shixi molecule in the gelatin 彳Mf ' makes the molecule flow in the cooling axis The I method quickly flows back to the original region, causing a plurality of voids to be generated in the substrate and the _ junction after curing (4), which not only reduces the electrical connection degree between the substrate and the back electrode, but also reduces the overall efficiency of the solar cell. Therefore, how to provide a solar cell and a back electrode structure thereof, while increasing the degree of electrical connection between the substrate and the back electrode, avoiding the formation of voids between the substrate and the body electrode, thereby improving the photoelectric conversion efficiency of the solar cell. Has become the focus of the solar manufacturing industry. [New content] In view of the above problems, the purpose of the present invention is to provide a solar cell back electrode structure, which can increase the degree of electrical connection between the substrate and the back electrode, and avoid void formation between the substrate and the conductive material to enhance the back electrode. Conductivity. In order to achieve the above object, a solar cell backside M422758 pole structure according to the present invention comprises a substrate, a passivation layer and a plurality of conductive materials. The purification layer is disposed on the substrate, and the passivation layer has a plurality of openings. The conductive materials are spaced apart from the passivation layer, and the conductive materials are connected to the substrate via the openings. In one embodiment of the present invention, the substrate is an N-type semiconductor substrate or a P-type semiconductor substrate. In an embodiment of the present invention, the conductive materials are disposed corresponding to the openings of the passivation layer. In an embodiment of the present invention, the openings may be non-continuously set. In one embodiment of the present invention, the openings of the passivation layer have a first width, the first width being greater than 50 μm and less than 300 μm. In one embodiment of the present invention, the conductive materials have a second width, the second width is greater than 50 μm and less than 500 μm, and the second width is greater than or equal to the first width. In an embodiment of the present invention, the conductive materials have a height, and the height is greater than 5 μm and less than 40 μm. ® For the above purposes, a solar cell according to the present invention comprises a substrate, a second passivation layer and a plurality of conductive materials. The substrate has a first surface and a second surface. The passivation layers are respectively disposed on the first surface and the second surface of the substrate. One of the passivation layers has a plurality of openings. The conductive materials are spaced apart from the openings. The passivation layer, the conductive materials are connected to the substrate via the openings. In one embodiment of the present invention, the substrate is a Ν-type semiconductor substrate or a p-type semiconductor substrate. 5 M422758 In one embodiment of the present invention, the openings of the passivation layer have a first width, the first width being greater than 50 μm and less than 300 μm. In one embodiment of the present invention, the conductive materials have a second width ' the second width is greater than 50 μηη less than 500 μηη, and the second width is greater than or equal to the first width. In an embodiment of the present invention, the conductive materials have a height, and the height is greater than 5 μm and less than 40 μm. The solar cell back electrode structure of the present invention is provided by a passivation layer having an opening and a conductive material, so that the conductive material disposed on the backlight surface is sintered at a high temperature and can be connected to the substrate to achieve The purpose of forming a back electric field. It is noted that a plurality of openings are formed in the passivation layer of the backlight surface, and the conductive material is successively disposed on the passivation layer, so that the substrate and the conductive material can be fused to each other during sintering to achieve a better electrical connection; After curing with the conductive material, voids are formed between the substrate and the conductive material, thereby improving the conductivity of the back electrode. [Embodiment] The same reference numerals will be described. Hereinafter, a solar cell and a back electrode structure thereof according to a preferred embodiment of the present invention will be described with reference to the related art, wherein the same components will be referred to as shown in FIGS. 1 and 2, and FIG. For the preferred embodiment of the present invention
作太陽能 別說明的 M422758 員示及說明’故可能於實際結構的比例不符，於此僅作為 參考而非為限制性者。太陽能電池背面電極結構丨包括一 基板11、一鈍化層12以及複數導電材料13。 基板11為半導體基板或光電轉換基板，其中基板更 可為單晶矽基板、多晶矽基板、微晶矽基板、非晶矽基板 或砷化鎵基板等。基板u為N型半導體基板或p型半導 體基板，在本實施例中之基板u係以p型半導體基板為 例。本實施例之基板n具有一第一表面1U及一第二表面 • U2，分別於基板11之正反面設置，第一表面111可為光 入射表面’而第二表面112為背光表面。 鈍化層12設置於基板11。詳而言之，將鈍化層12設 ! 置於基板11的第二表面1丨2。其中，鈍化層12設置的方 式可例如但不限於為化學氣相沉積（CVD)或物理氣相沉 積（PVD)等方式。鈍化層12可降低電池表面載子的複合 速度，達到提高光電流的作用，同時還具有保護太陽能電 池，防刮傷、防濕氣等功效。本實施例之鈍化層12通常 ® 由介電質材料構成’其材質係例如但不限於氧化矽、氮化 石夕、氧化紹、非晶石夕或碳化石夕。 鈍化層12具有複數開孔121。本實施例係以雷射 (laser)或蝕刻（etching)的方式於鈍化層12上設置該 些開孔121。其中，蝕刻通常使用含有磷酸、氫氟酸或者 是硝酸的膠狀物，利用網印的方式局部開孔。該些開孔121 之態樣可例如但不限於線條狀、虛線狀、斜線條紋狀、圓 點狀或孔狀等。該些開孔121可為等距間隔設置，亦可為 7 M422758 不等距間隔設置。惟要說明的是，設置於同一直線的該些 開孔121係可為連續或不連續，亦即’該些開孔121可以 分段區隔且直線排列設置於鈍化層I2,或以連續線條狀或 長條狀設置於鈍化層12，其中，分段區隔的間距可因設計 或需求不同，而設計為不同長度或態樣，亦可將不同態樣 的純化層12設置於同一排或相連接。本實施例中，該些 開孔121係以等距間隔設置，且該些開孔12丨為條狀。其 中，該些開孔121皆穿透鈍化層12與基板11相連。另外， 本實施例的該些開孔121具有一第一寬度dl，第一寬度 dl的範圍為50μιη小於300μιη。 複數導電材料13間隔設置於鈍化層12。利用例如但 不限於網版印刷（Screen printing )、塗佈等方式將該些導 電材料13設置於鈍化層12。值得注意的是，本實施例的 該些導電材料13係對應鈍化層12的該些開孔121設置， 導電材料13之態樣可例如但不限於線條狀、虛線狀、斜 線條紋狀、圓點狀或孔狀等，由於本實施例之該些開孔121 係以條狀為例，因此該些導電材料13亦以條狀的態樣形 成於鈍化層12,且為間隔設置於鈍化層12，以形成局部 網印。值得注意的是，設置於同一直線的複數導電材料13 係可為連續或不連續，亦即，該些導電材料13可以分段 區隔且直線排列設置於鈍化層12,或以連續線條狀設置於 鈍化層12，其中，分段區隔的間距可因設計或需求不同’ 而設計為不同長度或態樣，亦可將不同態樣的導電材料13 設置於同一排或相連接。另外，本實施例之導電材料13 M422758 係為糊狀物或膠狀物，且其材質係以鋁膠為例，更可為氧 化銦錫、鎳、銅、鈦、鋁或錫。再者，本實施例之該些導 電材料13具有一第二寬度d2及一高度h，其中，第二寬 度d2係大於或等於第一寬度d1’第二寬度d2的範圍為大 於80μιη小於500μιη。而高度h的範圍為大於5μιη小於 30μιη 〇 由於，設置於鈍化層12的該些導電材料π係與基板 非連接設置，為使該些導電材料13可經由該些開孔121 • 與基板11電性連接，因此’設置複數導電材料13於鈍化 層12之後，將基板11及該些導電材料13進行燒結，用 以燒結膠狀或糊狀的導電材料13。燒結之動作係去除該些 導電材料13中可揮發的溶劑，於例如57〇〜84〇它的溫度 下烘烤燒結，以使該些導電材料13金屬化。更詳細來說， 燒結之動作係燒結基板11及該些導電材料，當燒結達 -定的溫度（例如577。〇時，即會產生共熔的：象’:則 #基板11及該些導電材料13的分子結構將改變，俾使得於 基板11與該些導電材料13穿透鈍化層12的該些開孔121 相互融合及連接。值得注意的是，本實施例該些導電材料 13的高度h係與基板U的石夕原子擴散進該些導電材料η 之數量有關。 接著，固化基板11及導電材料13。如圖i所示， =陽能電池背面電極於固化後的示意 透純化層12的該些開孔_板 相連接，進而達成能形成局部背面電場之結構。此外， 9 M422758 於本實施例係以局部網印的方式將該些導電材料13形成 於鈍化層12，使得基板11與該些導電材料13於燒結時， 可相互融合；而於固化後，可避免形成空洞於基板11及 該些導電材料13之間，進而提升背面電極的導電率。其 中，於基板11及該些導電材料13的連接處形成鋁矽合 金，以大幅提高導電性。 請參照圖3所示，其為本創作之一種太陽能電池的示 意圖。須特別說明的是，圖3中各結構的比例關係，為了 方便顯示及說明，故可能於實際結構的比例不符，於此僅 作為參考而非為限制性者。太陽能電池2包括一基板21、 至少一半導體層22、二鈍化層23、24以及複數導電材料 25 ' 26 ° 基板21係為一矽基板，其矽基板又分為單晶矽基板、 多晶矽基板、非晶矽基板或微晶矽基板《基板21為N型 半導體基板或P型半導體基板，在本實施例中之基板21 係以P型半導體基板為例。基板21具有一第一表面211 及一第二表面212,第一表面211可為光入射表面，而第 二表面212為背光表面。 半導體層22設置於基板21的第一表面211，半導體 層22亦具有一第一表面221及一第二表面222，第一表面 221為光入射表面，半導體層22的第二表面222係與基板 21的第一表面211相連接。在本實施例中之半導體層22 係以一 N型半導體層為例，實際上半導體層22可依基板 21為N型或P型半導體基板，而為P型半導體層或N型 M422758 半導體層。當基板21為N型半導體基板時，則將P型半 導體材料擴散至N型半導體基板上，以形成一 P型半導體 層於N型半導體基板上；當基板21為P型半導體基板時， 則將N型半導體材料擴散至P型半導體基板上，以形成一 N型半導體層於P型半導體基板上。當P型及N型半導體 層互相接觸時，N型半導體層内的電子會湧入P型半導體 層中，以填補其内的電洞。在P-N接面附近，因電子一電 洞的再結合形成一個載子空乏區，而P型及N型半導體層 φ 中也因分別帶有負、正電荷，因此形成一個内建電場。當 太陽光照射到P-N結構時，P型和N型半導體層因吸收太 陽光而產生電子一電洞對。由空乏區所提供的内建電場， | 可以讓半導體層22内產生的電子在電池内流動。 半導體層22的第一表面221進行結構化處理。以單 晶石夕基板為例係以KOH溶液等向性餘刻（anisotropic etching)，而粗化半導體層22的第一表面221，於第一表 面221殘留大小不均如金字塔般的結構，使其入射光至少 ® 要經過半導體層22的第一表面221第二次反射，因此降 低入射光第一次反射就折回的機率。 二鈍化層23、24分別設置於半導體層22的第一表面 221及基板21的第二表面212。由於空氣與矽的折射係數 差異甚大，光線通過空氣與矽的介面時會有明顯光線反射 情形，因此以氮化矽（SiN)材質之鈍化層23、24塗佈於 基板21及半導體層22,以減少入射光的反射，而且可降 低復合中心（recombination center)’進而提升光電轉換效 M422758 率。由於半導體層22的第一表面221因結構化處理形成 如金字塔般狀的結構’俾使得鈍化層23亦形成金字塔般 狀的結構於半導體層22’以降低入射光第一次反射就折回 的機率® 設置於基板21的第二表面212的鈍化層24具有複數 開孔241。本實施例係以雷射（iaser )或姓刻（etching ) 的方式於鈍化層24上設置該些開孔241。其中，蝕刻通常 使用含有構酸、氫氟酸或者是硝酸的膠狀物，利用網印的 方式局部開孔。該些開孔241之態樣可例如但不限於線條 狀、虛線狀、斜線條紋狀、圓點狀或孔狀等。該些開孔241 可為等距間隔設置，亦可為不等距間隔設置。惟要說明的 是，設置於同一直線的該些開孔241係可為連續或不連 續，亦即，該些開孔241可以分段區隔且直線排列設置於 鈍化層24，或以連續線條狀或長條狀設置於純化層24， 其中，分段區隔的間距可因設計或需求不同，而設計為不 同長度或形狀，亦可將不同態樣或形狀的鈍化層24設置 於同一排或相連接。本實施例中，該些開孔241係以等距 間隔設置’且該些開孔241為條狀。其中，該些開孔241 皆穿透鈍化層24與基板21相連。另外，本實施例的該些 開孔241具有一第一寬度d3’第一寬度d3的範圍為50μπι 小於 300μιη。 於半導體層22的第一表面221及基板21的第二表面 212分別設置複數導電材料25、26。其中，本實施例設置 於半導體層22之第一表面221的該些導電材料25之材質 12 M422758 係例如銀膠；而設置於基板21之第二表面212的該些導 電材料26之材質係例如鋁膠，更可為氧化銦錫、鎳、銅、 鈦、鋁或錫。值得注意的是，本實施例的該些導電材料26 • 係對應鈍化層24的該些開孔241設置，導電材料26之態 樣可例如但不限於線條狀、虛線狀、斜線條紋狀、圓點狀 或孔狀等’由於本實施例之該些開孔241係以條狀為例， 因此該些導電材料26亦以條狀的態樣形成於純化層24， 且為間隔設置於鈍化層24 ’以形成局部網印。值得注意的 • 是，設置於同一直線的複數導電材料26係可為連續或不 連續，亦即，該些導電材料26可以分段區隔且直線排列 設置於鈍化層24，或以連續線條狀設置於鈍化層24，其 1 中’分段區隔的間距可因設計或需求不同，而設計為不同 、 長度或態樣，亦可將不同態樣的導電材料26設置於同一 排或相連接。另外’本實施例之該些導電材料26具有一 第二寬度d4及一高度hi’其中，第二寬度d4係大於或等 於第一寬度d3，第二寬度d4的範圍為大於5〇μιη小於 500μιη。而高度hi的範圍為大於5μιη小於40μπι。 設置於鈍化層23、24的該些導電材料25、26係與基 板21及半導體層22非連接設置，為使該些導電材料25、 26可與基板21及半導體層22電性連接，因此，設置複數 導電材料25、26設於鈍化層23、24之後，將基板21、半 導體層22及導電材料25、26進行燒結。利用共同燒結 (co-firing)製程得以製作正面電極及背面電極，俾使得 導電材料25、26與基板21及半導體層22電性連接。當 13 M422758 基板21及半導體層22將吸收到的光線轉變為電子時，基 板21及半導體層22將所產生之電子匯集至導電材料25、 ° 藉由導電材料25、26與外部負載的連結，以 將經過光、電轉換反應所產生的電子傳遞至外界。 接著’固化基板21、半導體層22及該些導電材料25、 26、。將基板21、半導體層22及導電材料25、26進行降溫 或、’卞直到降至室溫之溫度，以固化基板21、半導體層 22及導電材料25、26。 / * ^上所述’本創作之太陽能電池及其背面電極結構 係藉由具有開孔的鈍化層及導電材料的設置，使得設置^ 方光表面的導電材料經高溫燒結後’能與基板相連接，」 達到开y成者面電場的目的。值得注意的是，設置於背光: 面的純化層經由雷射或姓刻的方式形成複數開孔，接續」 局部網印的方式將導電材料設置於該鈍化層，使得基板; =電材料於燒結時’可相互融合’達到較佳的電性連接 ^基板與導電材料固化後，可避免於基板及導電材料 成空洞’進而提升背面電極的導電率。 與習知相較，本創作之太陽能電池及其背面電極 及導咸少導電材料的設置’降低成本，避免於基: 提升:之間形成空洞’提高背面電極的導電率，進 升整體太陽能電池的光電轉換效率及性能。 :上所述僅為舉例性’而非為限制性二任何未脫 應包含=:::專=r等效修改或變更， M422758 【圖式簡單說明】 圖1為依據本創作較佳實施例之一種太陽能電池背面 電極結構的不意圖， 圖2為依據本創作之太陽能電池背面電極結構製作的 流程剖面示意圖；以及 圖3為依據本創作較佳實施例之一種太陽能電池的示 意圖。 φ 【主要元件符號說明】 〔習知〕 無 | 〔本創作〕 . 1 :太陽能電池背面電極結構 II、 21 :基板 III、 211、221 :第一表面 112、212、222 :第二表面 ·· 12、23、24 :鈍化層 121、241 :開孔 13、25、26 :導電材料 2 :太陽能電池 22 :半導體層 dl、d3 :第一寬度 d2、d4 :第二寬度 h、hi :高度 15M422758 is not to be construed as a reference to the actual structure. The solar cell back electrode structure 丨 includes a substrate 11, a passivation layer 12, and a plurality of conductive materials 13. The substrate 11 is a semiconductor substrate or a photoelectric conversion substrate, and the substrate may be a single crystal germanium substrate, a polycrystalline germanium substrate, a microcrystalline germanium substrate, an amorphous germanium substrate or a gallium arsenide substrate. The substrate u is an N-type semiconductor substrate or a p-type semiconductor substrate, and the substrate u in the present embodiment is exemplified by a p-type semiconductor substrate. The substrate n of the present embodiment has a first surface 1U and a second surface U2 disposed on the front and back surfaces of the substrate 11, respectively, the first surface 111 being a light incident surface and the second surface 112 being a backlight surface. The passivation layer 12 is disposed on the substrate 11. In detail, the passivation layer 12 is placed on the second surface 1丨2 of the substrate 11. The passivation layer 12 may be disposed in a manner such as, but not limited to, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The passivation layer 12 can reduce the recombination speed of the carrier on the surface of the battery, thereby improving the photocurrent, and also protecting the solar battery, preventing scratches and moisture. The passivation layer 12 of the present embodiment is generally made of a dielectric material. The material of the passivation layer 12 is, for example, but not limited to, cerium oxide, cerium oxide, oxidized, amorphous or carbonized. The passivation layer 12 has a plurality of openings 121. In this embodiment, the openings 121 are provided on the passivation layer 12 by laser or etching. Among them, etching is usually carried out by using a gel containing phosphoric acid, hydrofluoric acid or nitric acid, and partially opening by means of screen printing. The aspects of the openings 121 may be, for example but not limited to, a line shape, a dotted line shape, a diagonal line shape, a dot shape, or a hole shape. The openings 121 may be equally spaced, or may be set at 7 M422758 unequal spacing. It should be noted that the openings 121 disposed on the same line may be continuous or discontinuous, that is, the openings 121 may be segmented and arranged in a line in the passivation layer I2, or in a continuous line. The shape or the strip shape is disposed on the passivation layer 12, wherein the spacing of the segmentation segments may be designed to different lengths or aspects depending on design or requirements, and the different layers of the purification layer 12 may be disposed in the same row or Connected. In this embodiment, the openings 121 are disposed at equal intervals, and the openings 12 are strip-shaped. The openings 121 are connected to the substrate 11 through the passivation layer 12. In addition, the openings 121 of the embodiment have a first width d1, and the first width dl ranges from 50 μm to less than 300 μm. A plurality of conductive materials 13 are spaced apart from the passivation layer 12. The conductive materials 13 are disposed on the passivation layer 12 by, for example, but not limited to, screen printing, coating, or the like. It should be noted that the conductive materials 13 of the present embodiment are disposed corresponding to the openings 121 of the passivation layer 12, and the conductive material 13 may be, for example but not limited to, a line shape, a dotted line shape, a diagonal line shape, and a dot. The conductive material 13 is also formed in the stripe pattern in the stripe layer 12 and is spaced apart from the passivation layer 12. To form a partial screen printing. It should be noted that the plurality of conductive materials 13 disposed on the same line may be continuous or discontinuous, that is, the conductive materials 13 may be segmented and arranged in a line in the passivation layer 12, or may be arranged in a continuous line. In the passivation layer 12, the spacing of the segmentation segments may be designed to different lengths or aspects due to different designs or requirements, and different conductive materials 13 may be disposed in the same row or connected. In addition, the conductive material 13 M422758 of the present embodiment is a paste or a gel, and the material thereof is exemplified by an aluminum paste, and more preferably indium tin oxide, nickel, copper, titanium, aluminum or tin. Furthermore, the conductive materials 13 of the present embodiment have a second width d2 and a height h, wherein the second width d2 is greater than or equal to the first width d1' and the second width d2 is greater than 80 μm and less than 500 μm. The height h ranges from more than 5 μm to less than 30 μm, because the conductive materials π disposed on the passivation layer 12 are not connected to the substrate, so that the conductive materials 13 can pass through the openings 121 and the substrate 11 The connection is made, so that after the plurality of conductive materials 13 are disposed on the passivation layer 12, the substrate 11 and the conductive materials 13 are sintered to sinter the gel-like or paste-like conductive material 13. The sintering action removes the volatile solvent in the conductive material 13 and bakes it at a temperature of, for example, 57 Torr to 84 Torr to metallize the conductive materials 13. In more detail, the sintering action is to sinter the substrate 11 and the conductive materials, and when sintering reaches a predetermined temperature (for example, 577 Å, eutectic is generated: like ': then # substrate 11 and the conductive materials The molecular structure of the material 13 will be changed, so that the substrate 11 and the conductive materials 13 penetrate the vias 121 of the passivation layer 12 to fuse and connect with each other. It is worth noting that the height of the conductive materials 13 in this embodiment The h-system is related to the amount of the conductive atoms of the substrate U being diffused into the conductive material η. Next, the substrate 11 and the conductive material 13 are cured. As shown in Fig. i, the back surface electrode of the solar cell is cured after being cured. The openings _ the plates of 12 are connected to form a structure capable of forming a partial back surface electric field. Further, 9 M422758 is formed in the passivation layer 12 by local screen printing in the embodiment, so that the substrate When the conductive materials 13 are sintered, they can be fused to each other; after curing, voids are formed between the substrate 11 and the conductive materials 13, thereby improving the conductivity of the back electrodes. Some of these The aluminum alloy is formed at the junction of the conductive material 13 to greatly improve the electrical conductivity. Please refer to FIG. 3, which is a schematic diagram of a solar cell of the present invention. It should be particularly noted that the proportional relationship of each structure in FIG. In order to facilitate the display and description, the actual structure may be inconsistent, and this is for reference only and not limitation. The solar cell 2 includes a substrate 21, at least one semiconductor layer 22, two passivation layers 23, 24, and a plurality of conductive layers. The material 25 ' 26 ° substrate 21 is a germanium substrate, and the germanium substrate is further divided into a single crystal germanium substrate, a polycrystalline germanium substrate, an amorphous germanium substrate or a microcrystalline germanium substrate. The substrate 21 is an N-type semiconductor substrate or a P-type semiconductor substrate. The substrate 21 in this embodiment is exemplified by a P-type semiconductor substrate. The substrate 21 has a first surface 211 and a second surface 212. The first surface 211 can be a light incident surface, and the second surface 212 is a backlight surface. The semiconductor layer 22 is disposed on the first surface 211 of the substrate 21. The semiconductor layer 22 also has a first surface 221 and a second surface 222. The first surface 221 is a light incident surface, and the semiconductor layer 22 is The surface 222 is connected to the first surface 211 of the substrate 21. In the embodiment, the semiconductor layer 22 is exemplified by an N-type semiconductor layer, and the semiconductor layer 22 can be an N-type or P-type semiconductor substrate according to the substrate 21. a P-type semiconductor layer or an N-type M422758 semiconductor layer. When the substrate 21 is an N-type semiconductor substrate, the P-type semiconductor material is diffused onto the N-type semiconductor substrate to form a P-type semiconductor layer on the N-type semiconductor substrate. When the substrate 21 is a P-type semiconductor substrate, the N-type semiconductor material is diffused onto the P-type semiconductor substrate to form an N-type semiconductor layer on the P-type semiconductor substrate. When the P-type and N-type semiconductor layers are in contact with each other At this time, electrons in the N-type semiconductor layer are poured into the P-type semiconductor layer to fill the holes therein. In the vicinity of the P-N junction, a carrier-depletion region is formed by recombination of electron-holes, and the P-type and N-type semiconductor layers φ also have negative and positive charges, respectively, thereby forming a built-in electric field. When sunlight is applied to the P-N structure, the P-type and N-type semiconductor layers generate electron-hole pairs by absorbing sunlight. The built-in electric field provided by the depletion region allows the electrons generated in the semiconductor layer 22 to flow in the battery. The first surface 221 of the semiconductor layer 22 is structured. Taking the single crystal substrate as an example, an anisotropic etching of a KOH solution is used to roughen the first surface 221 of the semiconductor layer 22, and a structure having a size unevenness like a pyramid remains on the first surface 221. The incident light is at least 2 to be reflected a second time through the first surface 221 of the semiconductor layer 22, thereby reducing the probability of the incident light being folded back for the first time. The two passivation layers 23, 24 are respectively disposed on the first surface 221 of the semiconductor layer 22 and the second surface 212 of the substrate 21. Since the refractive index difference between the air and the crucible is very large, when the light passes through the interface between the air and the crucible, there is a significant light reflection. Therefore, the passivation layers 23 and 24 made of tantalum nitride (SiN) are applied to the substrate 21 and the semiconductor layer 22, In order to reduce the reflection of incident light, and reduce the recombination center' and thus increase the photoelectric conversion efficiency M422758 rate. Since the first surface 221 of the semiconductor layer 22 is formed into a pyramid-like structure due to the structuring process, the passivation layer 23 also forms a pyramid-like structure on the semiconductor layer 22' to reduce the probability of the incident light being folded back for the first time. The passivation layer 24 disposed on the second surface 212 of the substrate 21 has a plurality of openings 241. In this embodiment, the openings 241 are provided on the passivation layer 24 by means of an iaser or an etching method. Among them, etching is usually carried out by using a gel containing amic acid, hydrofluoric acid or nitric acid, and partially opening by means of screen printing. The aspects of the openings 241 may be, for example but not limited to, a line shape, a dotted line shape, a diagonal line shape, a dot shape, or a hole shape. The openings 241 may be arranged at equal intervals or may be arranged at unequal intervals. It should be noted that the openings 241 disposed on the same line may be continuous or discontinuous, that is, the openings 241 may be segmented and arranged in a line on the passivation layer 24, or in a continuous line. The shape or the strip shape is disposed on the purification layer 24, wherein the spacing of the segmentation segments may be designed to have different lengths or shapes depending on design or requirements, and the passivation layers 24 of different patterns or shapes may be disposed in the same row. Or connected. In this embodiment, the openings 241 are disposed at equal intervals and the openings 241 are strip-shaped. The openings 241 are connected to the substrate 21 through the passivation layer 24 . In addition, the openings 241 of the embodiment have a first width d3' and the first width d3 ranges from 50 μm to less than 300 μm. A plurality of conductive materials 25, 26 are respectively disposed on the first surface 221 of the semiconductor layer 22 and the second surface 212 of the substrate 21. The material of the conductive material 25 disposed on the first surface 221 of the semiconductor layer 12 is M422758, for example, silver paste; and the materials of the conductive materials 26 disposed on the second surface 212 of the substrate 21 are, for example, Aluminum glue, more preferably indium tin oxide, nickel, copper, titanium, aluminum or tin. It should be noted that the conductive materials 26 of the present embodiment are disposed corresponding to the openings 241 of the passivation layer 24, and the conductive material 26 may be, for example but not limited to, a line shape, a dotted line shape, a diagonal line shape, and a circle. Since the openings 241 of the embodiment are in the form of strips, the conductive materials 26 are also formed in the strip layer in the strip layer 24 and are spaced apart from the passivation layer. 24 ' to form a partial screen printing. It is noted that the plurality of conductive materials 26 disposed on the same line may be continuous or discontinuous, that is, the conductive materials 26 may be segmented and arranged in a line in the passivation layer 24, or in a continuous line shape. Provided in the passivation layer 24, the spacing of the 'segment divisions in 1 may be different according to design or requirement, and may be different, length or aspect, and different conductive materials 26 may be arranged in the same row or connected. . In addition, the conductive materials 26 of the embodiment have a second width d4 and a height hi', wherein the second width d4 is greater than or equal to the first width d3, and the second width d4 is greater than 5 〇μιη less than 500 μm. . The height hi ranges from more than 5 μm to less than 40 μm. The conductive materials 25 and 26 disposed on the passivation layers 23 and 24 are not connected to the substrate 21 and the semiconductor layer 22, so that the conductive materials 25 and 26 can be electrically connected to the substrate 21 and the semiconductor layer 22. After the plurality of conductive materials 25 and 26 are provided on the passivation layers 23 and 24, the substrate 21, the semiconductor layer 22, and the conductive materials 25 and 26 are sintered. The front electrode and the back electrode are formed by a co-firing process, and the conductive materials 25, 26 are electrically connected to the substrate 21 and the semiconductor layer 22. When the 13 M422758 substrate 21 and the semiconductor layer 22 convert the absorbed light into electrons, the substrate 21 and the semiconductor layer 22 collect the generated electrons to the conductive material 25, and the conductive material 25, 26 is connected to the external load. The electrons generated by the light and electric conversion reaction are transmitted to the outside. Next, the substrate 21, the semiconductor layer 22, and the conductive materials 25, 26 are cured. The substrate 21, the semiconductor layer 22, and the conductive materials 25, 26 are cooled or cooled to a temperature lower than room temperature to cure the substrate 21, the semiconductor layer 22, and the conductive materials 25, 26. / * ^ The above-mentioned solar cell and its back electrode structure are provided by a passivation layer having an opening and a conductive material, so that the conductive material provided on the surface of the square is sintered at a high temperature Connection," achieves the purpose of turning on the electric field. It is worth noting that the backlight layer is disposed on the surface of the purification layer by means of laser or surname, and a plurality of openings are formed in a manner of partial screen printing to place a conductive material on the passivation layer, so that the substrate; When the 'integrable' can achieve a better electrical connection, after the substrate and the conductive material are cured, the substrate and the conductive material can be prevented from becoming hollow, thereby improving the conductivity of the back electrode. Compared with the conventional one, the solar cell of the present invention and the back electrode and the conductive material of the conductive salt are less 'cost reduction, avoiding the base: lifting: forming a void between the holes', improving the conductivity of the back electrode, and advancing the overall solar cell Photoelectric conversion efficiency and performance. The above description is only exemplary, and is not intended to be limiting. Any unresolved inclusions include::::specific =r equivalent modification or modification, M422758 [Simplified description of the drawings] FIG. 1 is a preferred embodiment according to the present invention. FIG. 2 is a schematic cross-sectional view showing a process of fabricating a back electrode structure of a solar cell according to the present invention; and FIG. 3 is a schematic view of a solar cell according to a preferred embodiment of the present invention. Φ [Explanation of main component symbols] [Practical] No | [This creation] . 1 : Solar cell back electrode structure II, 21: Substrate III, 211, 221: First surface 112, 212, 222: Second surface·· 12, 23, 24: passivation layers 121, 241: openings 13, 25, 26: conductive material 2: solar cell 22: semiconductor layers d1, d3: first width d2, d4: second width h, hi: height 15