M422754 五、新型說明： 【新型所屬之技術領域】 本創作是有關於一種晶片結構’且特別是有關於一種 增強凸塊與接合墊之間之結合強度的晶片結構。 【先前技術】 傳統上，半導體晶片係以接合塾上的凸塊作為電性連 接之接點。然而，當凸塊與接合墊之間的接合強度不足而 Φ 無法承受剪力測试（Shear Test)或掉落測試（Dr〇p Test) 所施加的外力時，凸塊的底部將會發生斷層或裂縫，而使 凸塊之結構受到破壞，無法作為電性連接之接點。因此， 習知半導體晶片的凸塊常無法承受太大的外力而造成永 久性的破壞，故可靠度不佳。 【新型内容】 本創作係有關於-種晶片結構，增強凸塊與接合塾之 間的接合強度，以提高可靠度。 、…根據本創作之-方面，提出一種晶片結構，包括：一 半導體基材、—接合塾、多數個凸起結構、-凸塊以及- 2屬層。半導體基材具有—晶片表面。接合塾配置於晶 。接合墊具有—凸塊接合面。此些㈣結構配置 合面。凸塊配置於凸塊接合面上。凸塊與此些凸 互谈合。介金屬層形成於凸塊之底部，且介金屬 長物，此些生長物多方向性地突出於此些 凸起結構之周圍表面。 3 M422754 根據本案之另一方面，提出一種晶片結構，包括：一 半導體基材、一接合墊、一凸塊以及一介金屬層。半導體 基材具有一晶片表面。接合墊配置於晶片表面。接合墊具 有一凸塊接合面。接合墊包括多數個位於凸塊接合面的凹 陷結構。凸塊配置於凸塊接合面上。凸塊與此些凹陷結構 相互嵌合。介金屬層形成於凸塊之底部，且介金屬層包括 多數個生長物，此些生長物多向性地突出於此些凹陷結構 之周圍表面。 為了對本創作之上述及其他方面有更佳的瞭解，下文 特舉較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 在本創作之晶片結構的實施例中，其可應用於各種包 含主動元件或被動元件（active or passive elements)、 數位電路或類比電路（digital or analog circuits)等積 體電路的電子元件（electronic components)，例如是有 關於光電元件（opto electronic devices)、微機電系統 (Micro Electro Mechanical System; MEMS)、微流體系 統（micro fluidic systems)、或利用熱、光線及壓力等 物理量變化來測量的物理感測器（Phys i ca 1 Sensor)。特 別是可選擇使用晶圓級封裝（wafer scale package; WSP) 製程對影像感測元件、發光二極體（light-emitting diodes; LEDs)、太陽能電池（solar cells)、射頻元件（RF circuits)、加速計（accelerators)、陀螺儀 (gyroscopes)、微制動器（micro actuators)、表面聲波 M422754 元件（surf ace acoustic wave devices)、壓力感測器 (process sensors)或喷墨頭（ink printer heads)等半導 體晶片進行封裝之晶片結構。 其中上述晶圓級封裝製程主要係指在晶圓階段完成 封裝步驟後，再予以切割成獨立的封裝體，然而，在一特 定實施例中，例如將已分離之半導體晶片重新分布在—承 載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製 程。另外，上述晶圓級封裝製程亦適用於藉堆疊（stael〇 • 方式安排具有積體電路之多片晶圓’以形成多層積體電路 (multi-layer integrated circuit devices)之晶片封裂 體。 本實施例之晶片結構，係於接合墊之凸塊接合面上設 置多數個凸起結構，以使凸塊與凸起結構相互嵌合而増加 介金屬層生長之面積及抗拉強度；或於凸塊接合面設置多 數個凹陷結構，以使凸塊與凹陷、结構相互散合而增加介金 屬層生長之面積及抗拉強度。此外’介金屬層形成於凸塊 鲁 的底部，且多數個生長物多方向性地沿著凸起結構（或凹 陷結構）之周圍表面生長，以使凸塊之底部與凸起結構（或 凹陷結構）之間的接合強度變得更強，故本實施例之晶片 結構於進行剪力測試或掉落測試時，凸塊可承受較大的外 力而不易受外力破壞，以提高晶片結構之可靠度。 以下所舉之二實施例分別就不同態樣的晶片結構進 行說明，並具體化晶片結構之製造方法’以對本實施例之 晶片結構有更深入之瞭解。 5 M422754 第一實施例 凊參照第1A及1B圖，其中第1A圖繪示依照第一實 施例之晶片結構的剖面示意圖及局部放大圖，第1β圖繪 示依照第-實施狀接合墊及凸起結構的俯視圖。晶片二 構100包括-半導體基材11〇、一接合墊12〇、多數個凸 U冓122、-凸塊13〇以及一介金屬層mo。半導體基 材110例如為摻雜P型雜質◎型雜質之石夕基材，以形成 所需的P型導電區或1\1型導電區。半導體基材11〇具有一 晶片表面112,例如是主動表面或與主動表面相對之一背 面。接合墊120配置於晶片表面112上。接合墊12〇具有 一凸塊接合面121。凸起結構122位於凸塊接合面121上。 此外，凸塊130配置於凸塊接合面121上，以使凸塊13〇 與此些凸起結構m相互嵌合。另外，介金屬们4〇 (僅 不意性地繪示一部分）形成於凸塊130之底部，且包圍此 些凸起結構122。 在第1A圖中’晶片結構1〇〇更包括一保護層114，覆 蓋於晶片表面112上。保護層114具有一開口 U4a，顯露 出接合墊120以及此些凸起結構12卜保護層114可覆蓋 凸塊接合面121之-部分（即外圍部分），而開口心顯 露凸塊接合面121之其餘部分（即中央部分），以定義接 合墊120於開口 114a中所顯露的凸塊接合面積。 此外，晶片結構1〇〇更可包括一阻障層124。阻障層 124覆蓋於凸塊接合面121與此些凸起結構122上。阻障 層124之材質可為鎳-金（Ni—Au)合金或其他合金。 接。墊120與凸起結構m之材質可為銅或其他金 M422754 屬，而凸塊130可為錫球，其材質包括錫_銀_銅合金或其 他無鉛銲錫合金。阻障層124 (例如Ni-Au合金）覆蓋於 接合墊120及各個凸起結構122上，可增加凸塊13〇及接 合墊120之間的附著力與凸塊13〇及各個凸起結構122之 間的附著力，並減緩接合墊丨2〇及凸起結構122中的銅原 子擴散至凸塊130中。 以錫-銀-銅合金之凸塊丨3〇來說，當凸塊13〇以植球 方式配置於銅質接合墊120及銅質凸起結構122上，並經 過咼溫迴焊之後，銅原子會穿過阻障層124並擴散到於凸 塊130之底部，而使介金屬層14〇於凸塊13〇的底部形成 多數個生長物142及144。 這些生長物142及144例如為（Ni，Cu)3Sn4、 (Cu, Ni)6Sn5及NhSm中至少一化合物或由上述多個化合物 所組成。其中，（Ni，CiOaSm為鬚晶狀介金屬化合物， (Cu，Ni)6Sns為角錐狀介金屬化合物，Ni3sn4為細針狀介金 屬化合物。 明參考弟1A圖之局部放大圖，生長物142及144突 出於凸起結構122之周圍表面，包括橫向地突出於凸起結 構122之周圍的生長物144及縱向地突出於凸起結構122 之上方的生長物142。由於這些生長物142及144係多向 性地向外生長，並非是單向性向上生長而已’故可藉由增 加這些生長物142及144的數量及分佈的範圍’以使晶片 結構100於承受較大的外力衝擊時，可避免晶片結構1〇〇 X到永久性的破壞。舉例來說，當上述之晶片結構進 行労力測試或掉落測試時，橫向生長的生長物144將可增 7 M422754 強凸塊130抵抗水平方向的剪應力，以避免凸塊130的底 部發生斷層或裂縫。 請參照第2A〜2G圖，其分別繪示依照第一實施例之 晶片結構之製造方法的流程示意圖。首先，請參考第2A 圖，形成一種子層220a於半導體基材210之晶片表面212 上。接著，請參考第2B圖，形成一圖案化光阻層PR1於 種子層220a上，圖案化光阻層PR1覆蓋一部分種子層 220a，並顯露一部分種子層220a於光阻開口 OP1 (僅繪示 其一）中，以定義後續欲電鍍的區域。之後，進行電鍍製 程，以形成一第一金屬層220b於光阻開口 OP1中的種子 層220a上。 接著，請參考第2C及2D圖，移除圖案化光阻層PR1， 並形成第二圖案化光阻層PR2於種子層220a與第一金屬 層220b上。第二圖案化光阻層PR2覆蓋一部分第一金屬 層220b，並顯露一部分第一金屬層220b於多個第二光阻 開口 OP2中，以定義後續欲電鍍的區域。之後，進行電鍍 製程，以形成一第二金屬層222於此些第二光阻開口 OP2 中的第一金屬層220b上。 接著，請參考第2E圖，移除第二圖案化光阻層PR2， 並蝕刻部分種子層220a。未被蝕刻之第一金屬層220b及 其下方之種子層220a組成一接合墊220,即為第1圖之接 合墊120，而位於接合墊220上方的第二金屬層222包括 多數個凸起結構，即為第1圖之多數個凸起結構122。接 著，請參考第2F圖，覆蓋一保護層214於半導體基材210 之晶片表面212上。保護層214具有一開口 214a，顯露出 M422754 接合墊220及第二金屬層222 (即凸起結構）。 接著’請參考第2G圖，以植球方式形成一凸塊230 於接合墊220上，並高溫迴焊凸塊230,以形成一球狀體。 凸塊230底部與凸起結構222相互嵌合，以增加介金屬層 240生長之面積。此外，受到Cu、Ni等金屬擴散效應的作 用與凸塊230内的Sn相互接合，使得介金屬層240於凸 塊230的底部向上地或沿著凸起結構222之周圍橫向地生 長出多個生長物（參見第1A圖），以使凸塊230之底部與 凸起結構222之間的接合強度變得更強，故於晶片結構進 行剪力測試或掉落測試時，凸塊230可承受較大的外力而 不易受外力破壞’以提高晶片結構之可靠度。 第二實施例 請參照第3圖，其繪示依照第二實施例之晶片結構的 剖面示意圖及局部放大圖。晶片結構3 〇 〇包括一半導體基 材310、一接合墊320、一凸塊330以及一介金屬層34ι 本貫施例與第一實施例類似，相同的構件不再贅述。本實 施例與第一實施例不同之處在於：接合墊320包括多數個 凹陷結構322，位於凸塊接合面321。凸塊330與此些凹 陷結構322相互嵌合。在本實施例中，凹陷結構322例如 為一凹槽或一貫孔。 請參考第3圖之局部放大圖，介金屬層34〇具有多數 個生長物 342 及 344，其例如為（Ni，Cu)3Sn4、（Cu Ni)6Sn5 及NisSm中至少一化合物或由上述多個化合物所組成。這 些生長物342及344突出於凹陷結構322之周圍表面，包 9 M422754 括橫向地突出於凹陷結構322之周圍之生長物344及縱向 地突出於凹陷結構322之上方的生長物342。由於這些生 長物342及344係多向性地向外生長，並非是單向性生 長，故藉由增加這些生長物342及344的數量及分佈的範 圍，以使晶片結構300承受較大的外力衝擊時，可避免晶 片結構300受到永久性的破壞。舉例來說，當上述之晶片 結構300進行剪力測試或掉落測試時，橫向生長的生長物 344將可增強凸塊330抵抗水平方向的剪應力，以避免凸 塊330的底部發生斷層或裂縫。 請參照第4A〜4G圖，其分別繪示依照第二實施例之 晶片結構之製作方法的流程示意圖。首先，請參考第4A 圖，形成一種子層420a於半導體基材410之晶片表面412 上。接著，請參考第4B圖，形成一圖案化光阻層PR1於 種子層420a上，圖案化光阻層PR1覆蓋一部分種子層 420a，並顯露一部分種子層420a於光阻開口 OP1 (僅繪示 其一）中，以定義欲電鍍之區域。之後，進行電鍍製程， 以形成一第一金屬層420b於光阻開口 OP1中的種子層 420a上。接著，請參考第4C及4D圖，移除圖案化光阻層 PR1，並形成第二圖案化光阻層PR2於種子層420a與第一 金屬層420b上。第二圖案化光阻層PR2覆蓋一部分第一 金屬層220b，並顯露一部分第一金屬層220b於多個第二 光阻開口 OP2中，以定義欲蝕刻之區域。之後，進行蝕刻 製程，以形成多數個凹陷結構422於此些第二光阻開口 OP2 中的第一金屬層420b内。接著，請參考第4E圖，移除第 二圖案化光阻層PR2，並蝕刻部分種子層420a。未被蝕刻 M422754 之第一金屬層420b及其下方之種子層420a組成一接合墊 420 ’即為第3圖之接合墊320，而位於第一金屬層220b 内的多數個凹陷結構422即為第3圖之凹陷結構322。接 著，請參考第4F圖，覆蓋一保護層414於半導體基材41〇 之晶片表面412上。保護層414具有一開口 414a，顯露出 接合墊420及凹陷結構422。M422754 V. New Description: [New Technical Field] The present invention relates to a wafer structure and, in particular, to a wafer structure for enhancing the bonding strength between a bump and a bonding pad. [Prior Art] Conventionally, a semiconductor wafer has a bump on a bonding pad as a contact for electrical connection. However, when the joint strength between the bump and the bonding pad is insufficient and Φ cannot withstand the external force applied by the Shear Test or the Dr〇p Test, the bottom of the bump will be faulted. Or a crack, so that the structure of the bump is damaged, and cannot be used as a contact for electrical connection. Therefore, the bumps of conventional semiconductor wafers are often unable to withstand excessive external forces and cause permanent damage, so reliability is poor. [New content] This creation is about a kind of wafer structure, which enhances the joint strength between the bump and the joint to improve the reliability. According to the aspect of the present invention, a wafer structure is proposed comprising: a semiconductor substrate, a bonding pad, a plurality of bump structures, a bump, and a - 2 genera layer. The semiconductor substrate has a wafer surface. The joint 塾 is disposed on the crystal. The bond pads have a bump-bonding surface. These (4) structural configurations are combined. The bumps are disposed on the bump joint faces. The bumps talk to each other. The intermetallic layer is formed at the bottom of the bump and is intermetallic elongated, and the growth directionally protrudes from the peripheral surface of the raised structure. 3 M422754 According to another aspect of the present invention, a wafer structure is provided comprising: a semiconductor substrate, a bond pad, a bump, and a via metal layer. The semiconductor substrate has a wafer surface. The bond pads are disposed on the surface of the wafer. The bond pad has a bump interface. The bond pad includes a plurality of recessed structures on the bump joint faces. The bumps are disposed on the bump joint faces. The bumps and the recessed structures are fitted to each other. A via layer is formed on the bottom of the bump, and the intermetallic layer includes a plurality of growths that multiply protrude from the peripheral surface of the recessed structure. In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below in detail with reference to the accompanying drawings, in which: FIG. It can be applied to various electronic components including integrated circuits such as active or passive elements, digital circuits or analog circuits, such as opto electronic devices. ), Micro Electro Mechanical System (MEMS), micro fluidic systems, or physical sensors (Phys i ca 1 Sensor) that measure changes in physical quantities such as heat, light, and pressure. In particular, wafer scale package (WSP) processes can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Semiconductors such as accelerators, gyroscopes, micro actuators, surface acoustic wave M422754 components, pressure sensors or ink printer heads The wafer structure in which the wafer is packaged. The wafer level packaging process described above mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in the carrier crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above-described wafer level packaging process is also applicable to a wafer cracker formed by stacking (multiple wafers having integrated circuits in a stael® manner to form multi-layer integrated circuit devices). The wafer structure of the embodiment is provided with a plurality of convex structures on the bump bonding surface of the bonding pad, so that the convex and convex structures are mutually fitted to increase the area and tensile strength of the metal layer growth; or A plurality of recessed structures are arranged on the block joint surface, so that the bumps and the recesses and the structures are interspersed to each other to increase the area of the metal layer growth and the tensile strength. Further, the 'metal layer is formed at the bottom of the bumps, and most of the growth is performed. The material is multidirectionally grown along the peripheral surface of the convex structure (or the recessed structure) so that the joint strength between the bottom of the bump and the convex structure (or the recessed structure) becomes stronger, so the embodiment When the wafer structure is subjected to the shear test or the drop test, the bump can withstand a large external force and is not easily damaged by the external force, so as to improve the reliability of the wafer structure. The following two embodiments respectively The wafer structure of different aspects will be described, and the manufacturing method of the wafer structure will be described in order to have a better understanding of the wafer structure of the present embodiment. 5 M422754 First embodiment 凊 Refer to Figures 1A and 1B, wherein Figure 1A A cross-sectional view and a partial enlarged view of the wafer structure according to the first embodiment are shown. The first β-graph shows a top view of the bonding pad and the bump structure according to the first embodiment. The wafer structure 100 includes a semiconductor substrate 11 . The bonding pad 12A, the plurality of convex U冓122, the bump 13〇, and a dielectric metal layer mo. The semiconductor substrate 110 is, for example, a stone substrate doped with a P-type impurity ◎ type impurity to form a desired P-type. a conductive region or a conductive region of type 1. The semiconductor substrate 11 has a wafer surface 112, such as an active surface or a back surface opposite the active surface. The bonding pad 120 is disposed on the wafer surface 112. The bonding pad 12 has a The bump joint surface 121. The bump structure 122 is located on the bump joint surface 121. Further, the bump 130 is disposed on the bump joint surface 121 such that the bump 13 is fitted to the bump structures m. , the metal is 4 〇 (only The portion is schematically formed at the bottom of the bump 130 and surrounds the raised structures 122. In FIG. 1A, the 'wafer structure 1' further includes a protective layer 114 overlying the wafer surface 112. The layer 114 has an opening U4a exposing the bonding pad 120 and the raised structures 12, the protective layer 114 can cover a portion of the bump bonding surface 121 (ie, the peripheral portion), and the opening core reveals the rest of the bump bonding surface 121 a portion (ie, a central portion) to define a bump bonding area exposed by the bonding pad 120 in the opening 114a. Further, the wafer structure 1 may further include a barrier layer 124. The barrier layer 124 covers the bump bonding surface 121 and the raised structures 122. The material of the barrier layer 124 may be a nickel-gold (Ni-Au) alloy or other alloy. Pick up. The material of the pad 120 and the raised structure m may be copper or other gold M422754 genus, and the bump 130 may be a solder ball, and the material thereof includes tin-silver_copper alloy or other lead-free solder alloy. The barrier layer 124 (for example, Ni-Au alloy) covers the bonding pad 120 and each of the protruding structures 122, and can increase the adhesion between the bumps 13 and the bonding pads 120 and the bumps 13 and the respective protruding structures 122. The adhesion between them and the diffusion of copper atoms in the bonding pads 2 and the raised structures 122 into the bumps 130 are alleviated. In the case of a tin-silver-copper alloy bump 〇3〇, when the bump 13〇 is placed on the copper bond pad 120 and the copper bump structure 122 by ball implantation, after the temperature reflow, copper The atoms pass through the barrier layer 124 and diffuse to the bottom of the bumps 130, causing the intermetallic layer 14 to form a plurality of growths 142 and 144 at the bottom of the bumps 13A. These growth products 142 and 144 are, for example, at least one of (Ni, Cu) 3Sn4, (Cu, Ni) 6Sn5 and NhSm or consist of the above plurality of compounds. Among them, (Ni, CiOaSm is a whisker-like intermetallic compound, (Cu, Ni) 6Sns is a pyramidal intermetallic compound, Ni3sn4 is a fine needle-like intermetallic compound. Partial enlarged view of the reference 1A, growth 142 and 144 protrudes from the peripheral surface of the raised structure 122, including a growth 144 that projects laterally around the raised structure 122 and a growth 142 that projects longitudinally above the raised structure 122. Because of these growths 142 and 144 Multi-directional outward growth, not unidirectional upward growth, can be achieved by increasing the range and distribution of these growths 142 and 144 to allow the wafer structure 100 to withstand large external impacts. Avoid wafer structure 1〇〇X to permanent damage. For example, when the above wafer structure is subjected to the force test or drop test, the laterally grown growth 144 can be increased by 7 M422754 strong bumps 130 against the horizontal direction. The stress is sheared to avoid the occurrence of a fault or crack in the bottom of the bump 130. Please refer to FIGS. 2A-2G, which respectively illustrate the flow chart of the manufacturing method of the wafer structure according to the first embodiment. Referring to FIG. 2A, a sub-layer 220a is formed on the wafer surface 212 of the semiconductor substrate 210. Next, referring to FIG. 2B, a patterned photoresist layer PR1 is formed on the seed layer 220a to pattern the photoresist layer PR1. Covering a portion of the seed layer 220a, and exposing a portion of the seed layer 220a in the photoresist opening OP1 (only one of which is shown) to define a region to be subsequently plated. Thereafter, an electroplating process is performed to form a first metal layer 220b to the light. The seed layer 220a in the opening OP1 is blocked. Next, referring to the 2C and 2D drawings, the patterned photoresist layer PR1 is removed, and the second patterned photoresist layer PR2 is formed on the seed layer 220a and the first metal layer 220b. The second patterned photoresist layer PR2 covers a portion of the first metal layer 220b and exposes a portion of the first metal layer 220b in the plurality of second photoresist openings OP2 to define a region to be subsequently plated. Thereafter, an electroplating process is performed, Forming a second metal layer 222 on the first metal layer 220b of the second photoresist openings OP2. Next, referring to FIG. 2E, removing the second patterned photoresist layer PR2, and etching part of the seed layer 220a. Not etched The first metal layer 220b and the seed layer 220a underneath thereof constitute a bonding pad 220, which is the bonding pad 120 of FIG. 1, and the second metal layer 222 located above the bonding pad 220 includes a plurality of convex structures, that is, A plurality of raised structures 122 of Figure 1. Next, please refer to Figure 2F, overlying a protective layer 214 on the wafer surface 212 of the semiconductor substrate 210. The protective layer 214 has an opening 214a that exposes the M422754 bond pad 220. And a second metal layer 222 (ie, a raised structure). Then, please refer to FIG. 2G, a bump 230 is formed on the bonding pad 220 by balling, and the bump 230 is reflowed at a high temperature to form a spherical body. The bottom of the bump 230 and the protruding structure 222 are fitted to each other to increase the area in which the metal layer 240 is grown. In addition, the effect of the diffusion effect of the metal such as Cu or Ni and the Sn in the bump 230 are mutually joined, so that the intermetallic layer 240 laterally grows at the bottom of the bump 230 or along the periphery of the convex structure 222. The growth material (see FIG. 1A) is such that the bonding strength between the bottom of the bump 230 and the convex structure 222 becomes stronger, so that the bump 230 can withstand when the wafer structure is subjected to a shear test or a drop test. Large external forces are not easily damaged by external forces' to improve the reliability of the wafer structure. Second Embodiment Referring to Figure 3, there is shown a cross-sectional view and a partial enlarged view of a wafer structure in accordance with a second embodiment. The wafer structure 3 〇 〇 includes a semiconductor substrate 310, a bonding pad 320, a bump 330, and a via metal layer 34. The present embodiment is similar to the first embodiment, and the same components will not be described again. This embodiment differs from the first embodiment in that the bonding pad 320 includes a plurality of recessed structures 322 located at the bump engaging faces 321 . The bumps 330 and the recessed structures 322 are fitted to each other. In the present embodiment, the recessed structure 322 is, for example, a groove or a uniform hole. Referring to a partial enlarged view of FIG. 3, the intermetallic layer 34 has a plurality of growth bodies 342 and 344, which are, for example, at least one of (Ni, Cu) 3Sn4, (Cu Ni)6Sn5 and NisSm or Composition of compounds. The growths 342 and 344 protrude from the peripheral surface of the recessed structure 322, and the package M422754 includes a growth 344 that projects laterally around the recessed structure 322 and a growth 342 that projects longitudinally above the recessed structure 322. Since these growths 342 and 344 are multi-directionally outwardly grown, not unidirectionally grown, the wafer structure 300 is subjected to a large external force by increasing the range and distribution of these growths 342 and 344. The wafer structure 300 can be protected from permanent damage during impact. For example, when the wafer structure 300 described above is subjected to a shear test or a drop test, the laterally grown growth 344 will enhance the shear stress of the bump 330 against the horizontal direction to avoid a fault or crack in the bottom of the bump 330. . Referring to FIGS. 4A to 4G, there are shown schematic flow diagrams of a method of fabricating a wafer structure in accordance with a second embodiment. First, referring to FIG. 4A, a sub-layer 420a is formed on the wafer surface 412 of the semiconductor substrate 410. Next, referring to FIG. 4B, a patterned photoresist layer PR1 is formed on the seed layer 420a, the patterned photoresist layer PR1 covers a portion of the seed layer 420a, and a portion of the seed layer 420a is exposed on the photoresist opening OP1 (only the a) to define the area to be electroplated. Thereafter, an electroplating process is performed to form a first metal layer 420b on the seed layer 420a in the photoresist opening OP1. Next, referring to FIGS. 4C and 4D, the patterned photoresist layer PR1 is removed, and a second patterned photoresist layer PR2 is formed on the seed layer 420a and the first metal layer 420b. The second patterned photoresist layer PR2 covers a portion of the first metal layer 220b and exposes a portion of the first metal layer 220b in the plurality of second photoresist openings OP2 to define a region to be etched. Thereafter, an etching process is performed to form a plurality of recess structures 422 in the first metal layer 420b of the second photoresist openings OP2. Next, referring to FIG. 4E, the second patterned photoresist layer PR2 is removed, and a portion of the seed layer 420a is etched. The first metal layer 420b not etched M422754 and the seed layer 420a underneath thereof constitute a bonding pad 420' which is the bonding pad 320 of FIG. 3, and the plurality of recess structures 422 located in the first metal layer 220b are 3 recessed structure 322. Next, please refer to FIG. 4F to cover a protective layer 414 on the wafer surface 412 of the semiconductor substrate 41. The protective layer 414 has an opening 414a that exposes the bond pad 420 and the recess structure 422.
接著，請參考第4G圖，以植球方式形成一凸塊43〇 於接合墊420上，並高溫迴焊凸塊430,以形成一球狀體。 凸塊430底部與凹陷結構422相互嵌合，以增加接觸面積 及接合強度。此外，受到Cu、Ni等金屬擴散效應的作用 與凸塊430内之Sn相互接合，介金屬層44〇於凸塊43〇 的底部向上地或沿著凹陷結構422之周圍横向地生長出多 個生長物（參見第3圖），以使凸塊43〇之底部與凹陷結 構422之間的接合強度變得更強’故於晶片結構進行剪力 測試或掉落測試時’凸塊43〇可承受較大的外力而不易受 外力破壞’以提高可靠度。 上述二實施例所揭露之晶片結構，係於接合墊之凸塊 接δ面上⑶置多數個凸起結構或多數個凹陷結構，以使凸 塊與凸起結構（或凹陷結構）相互嵌合而增加介金屬層生 長之面積。此外，介金屬層之生長物係多向性地向外生 長’並非是早向性向上生長，故可增加橫向及縱向的接合 2。因而，當本實_之晶片結構崎剪力職 =時，橫向生長的生長物將可增強凸塊抵抗水平方向的 ^應力’㈣免凸㈣底部發生斷層或裂縫，進而提高可 罪度。 M422754 綜上所述，雖然本創作已以較佳實施例揭露如上，然 其並非用以限定本創作。本創作所屬技術領域中具有通常 知識者，在不脫離本創作之精神和範圍内，當可作各種之 更動與潤飾。因此，本創作之保護範圍當視後附之申請專 利範圍所界定者為準。 【圖式簡單說明】 第1A圖繪示依照第一實施例之晶片結構的剖面示意 圖及局部放大圖。 第1B圖繪示依照第一實施例之接合墊及凸起結構的 俯視圖。 第2A〜2G圖別繪示依照第一實施例之晶片結構之製 作方法的流程示意圖。 第3圖繪示依照第二實施例之晶片結構的剖面示意 圖及局部放大圖。 第4A〜4G圖分別繪示依照第二實施例之晶片結構之 製作方法的流程示意圖。 【主要元件符號說明】 100、300 :晶片結構 110、210、310、410 :半導體基材 112、212、312、412 :晶片表面 114、214、414 :保護層 114a、214a、414a :開口 120、220、320、420 :接合墊 12 M422754 121、321 :凸塊接合面 122 :凸起結構 124 :阻障層 130、230、330、430 :凸塊 140、240、340、440 :介金屬層 220a、420a :種子層 220b、420b :第一金屬層 222 :第二金屬層 • 322、422 :凹陷結構 PR1、PR2 :圖案化光阻層 OP1、OP2 :光阻開口 13Next, referring to FIG. 4G, a bump 43 is formed on the bonding pad 420 by balling, and the bump 430 is soldered at a high temperature to form a spherical body. The bottom of the bump 430 and the recessed structure 422 are fitted to each other to increase the contact area and the joint strength. In addition, due to the effect of the diffusion effect of metal such as Cu or Ni, the Sn in the bump 430 is bonded to each other, and the intermetallic layer 44 is laterally grown on the bottom of the bump 43 or upwards along the periphery of the recess 422. The growth material (see Fig. 3) is such that the bonding strength between the bottom of the bump 43 and the recessed structure 422 becomes stronger. Therefore, when the wafer structure is subjected to a shear test or a drop test, the bump 43 can be used. Withstand large external forces and is not vulnerable to external forces' to improve reliability. The wafer structure disclosed in the above two embodiments is characterized in that a plurality of convex structures or a plurality of concave structures are disposed on the bump δ plane (3) of the bonding pad, so that the bump and the convex structure (or the recessed structure) are fitted to each other. And increase the area of the metal layer growth. In addition, the growth of the intermetallic layer grows multi-directionally outwardly. It is not an early-direction upward growth, so that the lateral and longitudinal joints 2 can be increased. Therefore, when the solid structure of the wafer structure is =, the growth of the lateral growth will enhance the convexity against the horizontal stress of the stress (4) and the fault or crack at the bottom of the convex (four), thereby increasing the suspicion. M422754 In summary, although the present invention has been disclosed above in the preferred embodiment, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present creation. Therefore, the scope of protection of this creation is subject to the definition of the scope of the application patent. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a cross-sectional view and a partial enlarged view of a wafer structure in accordance with a first embodiment. Fig. 1B is a plan view showing the bonding pad and the projection structure according to the first embodiment. 2A to 2G are views showing a flow chart of a method of fabricating a wafer structure according to the first embodiment. Fig. 3 is a cross-sectional view and a partially enlarged view showing the structure of the wafer in accordance with the second embodiment. 4A to 4G are flow diagrams respectively showing a method of fabricating a wafer structure according to a second embodiment. [Main component symbol description] 100, 300: wafer structure 110, 210, 310, 410: semiconductor substrate 112, 212, 312, 412: wafer surface 114, 214, 414: protective layer 114a, 214a, 414a: opening 120, 220, 320, 420: bonding pad 12 M422754 121, 321 : bump bonding surface 122 : convex structure 124 : barrier layer 130 , 230 , 330 , 430 : bump 140 , 240 , 340 , 440 : metal layer 220 a 420a: seed layer 220b, 420b: first metal layer 222: second metal layer • 322, 422: recessed structure PR1, PR2: patterned photoresist layer OP1, OP2: photoresist opening 13