五、新型說明： 【新型所屬之技術領域】 本新型是有關於一種記憶體裝置，且特別是有關於— 種具有高可靠度的記憶體裝置。 【先前技術】 隨著記憶體裝置於電腦及周邊的應用越來越普及，且 k著對於資料存取完整性的高度需求，有些記憶體褒置具 有僧錯與更正功能，以提高記憶體裝置的功效。 目前’快閃記憶體廣泛地被使用。快閃記憶體於資料 讀寫的過程中，必需藉由特定的讀寫裝置或電路來進行， 且此過程必需對讀寫資料内容進行偵錯與更正的動作，以 確保快閃記憶體資料讀寫的正確性。 由於快閃記憶體的製程趨於將其尺寸縮得更小，而此 種縮小的結構會導致位元錯誤率（biterrorrate)的增加。 現有技術的快閃記憶體的倾與更正機制僅採用博斯-喬 赫里（B〇se，Chaudhuri & H〇CqUenghem，簡稱為 B ^ 編碼與解碼方式。然:而，BCH演算法對於較多的位元 :的資料需要較多的同位檢查位元（parityeheekbi〇二吏 編碼速率u〇derate)降低’導致_體的利用率不佳。 以提开貝料正確性，有必要接Φ 置，這是-财待歧的^^—衫完善的記憶體裝 M417635 【新型内容】 得以供-種具有高可靠度的記憶 鮮成无刚技術所述及的問題。 體裝 置，其 在依據本創作的例示性實施例中，提供一種 :又的C憶體裝置’其包括-快閃記憶體以及一錯★吳= 2。所述㈣記憶體用以儲存至少碼字^斤述許 次所述快閃記憶體，所述錯誤更正裝置以多曰 =嗔取重试方式從所述快閃記憶體讀取所述第— 二取=軟資訊，接著使用所述組軟#訊對所述第一碼字 進仃-第—錯誤更正碼處理，以產生—第二碼字 ==行一第二錯誤更正碼處理’據以回“述 在依據本創作的例示性實施例中，所述錯誤更正 將用於讀取重試的位準區分為多個電壓級別。、 在依據本創作的例示性實施例中，所述組軟資訊 聯於所述第一碼字中的每一位元資料為1的機率值。 在依據本創作的例示性實施例中，所述第—錯誤更正 碼處理為低密度同位檢查碼處理。 在依據本創作的例示性實施例♦，所述第二錯誤更正 碼處理為博斯·喬赫里處理。 ' 在依據本創作的例示性實施例中，所述快閃記憔體的 型態為反及快閃記憶體。 ~ 在依據本創作的例示性實施例中，所述錯誤更正裝置 包括一第一編解碼器以及一第二編解喝器。所述第一編解 編解碼器輕接所述第_^丁弟一錯誤更正碼處理。所述第二 述第-碼字進行第—扭編解竭器’使用所述組軟資訊對所 字。 錯誤更正碼處理，以產生所述第二碼 舉實下文特 【實施方式】 使用才目同標號的元俗構件‘二或類貫施方式中 圖。請===:;體裝置的電路方塊 正歩蓄nm ~的°己憶體褒置1〇〇包括一錯誤更 f ^ 决閃"己憶體130。此快閃記憶體130耦 •曰、^正裝置110。此記憶體裝置1〇〇可以對一用戶資 枓面一data進行儲存前的編碼（enc〇de) 記 =:!:取資料以進行回復。此記憶體裳請的二 作原理疋措由兩種的編碼/解碼方式對用戶資料順她 進行編碼與儲存，或者進行解碼（反編媽）愈回復。如此 -來’可以提高資料内容的正確與完整。詳細的工作肩理 如下。 錯5吳更正裝置110藉由第一種編碼方式對用戶資料 而一data進行第-次編碼，以產生第一偵錯同位資訊（_ —ectingparityinformatl〇n);接著藉由第二種編碼 M417635 方式對用戶資料user_data進行第二次編碼’以產生第二價 錯门位寅況（sec〇nd error-correcting parity information ) 〇 上述用戶資料、第一偵錯同位資訊與第二偵錯同位資訊形 成—個碼字（codeword)。然後，錯誤更正裝置11()將表 不用戶資料user_data的碼字儲存在快閃記憶體13〇。 圖2是依據本創作實施例說明碼字201 (即編碼後之 用戶資料）的結構圖。請合併參照圖丨和圖2。快閃記憶 肢13〇可以將編碼後的用戶資料user一data以相關的三個區 t做為記錄，例如圖2所示的碼字201中，相關的三個區 丰又f別記錄著：用戶資料user_data、第一偵錯同位資訊2〇3 與，二偵錯同位資訊205。上述第一偵錯同位資訊2〇3例 疋博斯円赫里（B〇se，Chaudhuri & Hocquenghem，簡稱 為=CH_)偵錯同位資訊，而第二偵錯同位資訊2〇5例如是 低岔度同位檢查碼（Low density parity check⑶扣，簡稱為 ^DPC)偵錯同位資訊。關於碼字2〇1結構的紀錄順序與 態樣可以做類似的變化，但不以此為限。 承上述，當反過來從快閃記憶體13〇讀取用戶資料 時，錯誤更正裝置110可以針對碼字2〇1以多次讀取重試 (read retry )方式來獲取一組軟資訊（soft information )， 其中這組軟資訊為關聯於碼字2〇1中的每一位元資料為1 的機率值。關於這組軟資訊，將於後文詳細說明。接著 由對碼字201進行第-錯誤更正碼處理，而在第—錯誤^ 正碼處理過程中可以參考第二偵錯同位資訊應來^行 並且對資料數值進行錯誤更正，以產生第二碼字（未繪 不）。再對這第二碼字進行第二錯誤 二錯誤更JE碼處理過程巾可轉考第#理L而在第 來推弁<=» μ 气务偵錯同位資訊203 二=㈣復此用戶資料，-，並做輸出。 能的型能、ft:中已經對本創作的記憶體裝置描述可 此的n但所屬技術領域巾具有通常 各廠商對於記憶體襞置100的設計 Π1^ * 的雍田Α 〜又°卞都不一樣，因此本創作 的應用當不_於上述可能的型態。換言之， 正裝置從快閃記憶體讀取資料的解、2 ' 來姦— 4 — + 寸町解馬動作中可以根據碼字 綠_㈣k，就已經是符合了本創作的精神所 幾個實施方式以便本領域具有財知識者能 ^ 乂的了解本創作的精神，並實施本創作。 請再合併參關丨和圖2。錯誤更正裝置ug可以包 ，編解碼器m以及第二編解碼器114。第一編解碼 =2可以物第—種方式的編碼與解碼，而第二編解碼 态114可以進行第二種方式的編碼與解碼。 值得一提的疋’第一編解碼器112可以為博斯_喬赫里 (B〇se，Chaudhuri&Hocquenghem，簡稱為 BCH)的編碼 與解碼。第二編解碼H 1M可以為低密度㈣檢查碼（L〇w density yarity check code，簡稱為 LDPC)的編碼與解碼。 因此，第一偵錯同位資訊203與第二偵錯同位資訊2〇5可 以分別為BCH的同位資訊與LDPC的同位資訊。關於BCH 以及LDPC的編碼與解碼規則屬本創作相關領域具有通常 知識者所熟識的技藝，因而在此並不再加以贅述之。 另外，快閃記憶體130的型態可以為反及（NAND) M417635 快閃記憶體，但不以此為限。 圖3是依據本創作實施例之記憶體裝置的解碼流程 圖。接下來明參知圖3 ’將說明解碼流程的細節。步驟S31， 開始解碼。接著進入步驟S32A，判斷BCH錯誤更正碼 (error-correcting code，簡稱為Ecc )是否可以完成碼字 的錯誤更正碼處理而回復用戶資料，如果可以完成則結束 解碼而進人步驟S33A4 BCHECC失敗時進人步驟 ^驟S34 ’識別目前在快閃記憶體的讀取位準，並暫存所 ，取到的各位it資料’織進入步驟阳。步驟奶，設 疋-個新物取位準’同樣也暫存以此新的讀取位準所讀 取到的各位7^資料。接著，步驟S32B，判斷BCHECC是 字的錯誤更正碼處理，若可以則進入步驟 步驟S33B，結束解碼。 平…、後進入V. New description: [New technical field] The present invention relates to a memory device, and in particular to a memory device with high reliability. [Prior Art] With the increasing popularity of memory devices in computers and peripheral applications, and the high demand for data access integrity, some memory devices have error and correction functions to improve memory devices. The effect. Currently, flash memory is widely used. In the process of data reading and writing, the flash memory must be performed by a specific read/write device or circuit, and the process must perform debugging and correcting operations on the read and write data content to ensure flash memory data reading. The correctness of writing. Since the flash memory process tends to shrink its size smaller, this reduced structure results in an increase in the bit error rate. The prior art flash memory tilting and correction mechanism only uses Boss-Johri (B〇se, Chaudhuri & H〇CqUenghem, abbreviated as B ^ encoding and decoding. However: BCH algorithm for More bits: The data requires more parity check bits (parityeheekbi〇2 encoding rate u〇derate) to reduce 'cause _ body utilization is not good. To improve the correctness of the shell material, it is necessary to connect Φ This is the -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ In an exemplary embodiment of the creation, a C memory device is provided which includes a flash memory and a fault ★ Wu = 2. The (four) memory is used to store at least a code word. Depicting the flash memory, the error correction device reads the second-pass=soft information from the flash memory in a multi-曰=retry retry mode, and then using the group soft The first code word enters the first-error error correction code processing to generate - the second code word == line A second error correction code processing is referred to as "returned" in the exemplary embodiment according to the present invention, the error correction is to distinguish the level for reading the retry into a plurality of voltage levels. In an exemplary embodiment, the set of soft information is associated with a probability value of each bit data in the first codeword being 1. In an exemplary embodiment in accordance with the present creation, the first error correction The code processing is low density parity check code processing. In an exemplary embodiment ♦ according to the present creation, the second error correction code processing is Bosch Johri processing. In an exemplary embodiment in accordance with the present creation, The type of the flash memory is inverse flash memory. ~ In an exemplary embodiment in accordance with the present invention, the error correction device includes a first codec and a second codec. The first codec is lightly connected to the first error correction code processing. The second first code-word is subjected to a first-to-be-compiler to use the set of soft information pairs. Error correction code processing to generate the second code Venter [Embodiment] The use of the same vulgar component is the same as the standard component of the second or the class. Please ===:; The circuit block of the body device is storing the nm ~ ° 己 褒 褒 〇 〇 〇 〇 包括 包括 包括 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The code (enc〇de) ==!: Take the data to reply. The second principle of this memory is to encode and store the user data by two encoding/decoding methods, or to decode it. (Reverse mother) more and more. So - to 'can improve the correctness and completeness of the data content. The detailed work shoulders are as follows. The error correction device 110 performs the first encoding of the user data by the first encoding method to generate the first debugging parity information (__ectingparityinformatl〇n); then the second encoding M417635 mode Performing a second encoding of the user data user_data to generate a second sec 〇 error-correcting parity information 〇 forming the user data, the first debugging parity information, and the second debugging parity information— Codewords. Then, the error correction means 11() stores the code words indicating the user data user_data in the flash memory 13'. Figure 2 is a block diagram showing the codeword 201 (i.e., encoded user data) in accordance with the present embodiment. Please combine reference figure 图 and Figure 2. The flash memory limb 13 can record the encoded user data user-data in the relevant three regions t. For example, in the code word 201 shown in FIG. 2, the relevant three regions are recorded: The user data user_data, the first debug parity information 2〇3, and the second debug parity information 205. The first debug information is 2, 3 cases, B〇se, Chaudhuri & Hocquenghem (referred to as =CH_), the same information, and the second debug information 2〇5 is low, for example. Low density parity check (3), referred to as ^DPC) is the same information. Similar changes can be made to the order and pattern of the code word 2〇1 structure, but not limited to this. In the above, when the user data is read from the flash memory 13〇 in turn, the error correction device 110 can acquire a set of soft information in a read retry manner for the code word 2〇1. Information ), wherein the set of soft information is a probability value associated with each bit data in the code word 2〇1 being 1. This group of soft information will be explained in detail later. Then, the first error correction code processing is performed on the codeword 201, and the second debug parity information should be referred to in the first error correction code processing and error correction is performed on the data value to generate the second code. Word (not drawn). Then the second error is made to the second codeword. The JE code processing process can be transferred to the first #理理L and in the first push 弁<=» μ gas troubleshooting information 203 2=(4) repeat this user Information, -, and output. The energy type of the energy, ft: has been described for the memory device of this creation. However, the technical field of the technical field has the design of the memory device 100, which is usually designed by various manufacturers. The same, so the application of this creation does not _ the above possible types. In other words, the positive device reads the solution from the flash memory, 2 ' 来 — 4 4 4 4 4 4 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作 动作In this way, those who have financial knowledge in this field can understand the spirit of this creation and implement this creation. Please merge the reference and Figure 2. The error correction device ug can include a codec m and a second codec 114. The first codec = 2 can encode and decode in the first mode, and the second codec 114 can perform the encoding and decoding in the second mode. It is worth mentioning that the first codec 112 can be the encoding and decoding of Boss, Chaudhuri & Hocquenghem (BCH). The second codec H 1M may be a code and decoding of a low density (y) check code (LDPC). Therefore, the first debug parity information 203 and the second debug parity information 2〇5 may be the parity information of the BCH and the parity information of the LDPC, respectively. The coding and decoding rules for BCH and LDPC are well-known in the field of creation and are familiar to those skilled in the art and will not be described here. In addition, the type of the flash memory 130 may be reversed (NAND) M417635 flash memory, but not limited thereto. Fig. 3 is a flow chart showing the decoding of the memory device in accordance with the present embodiment. Next, the details of the decoding process will be explained. In step S31, decoding is started. Then, proceeding to step S32A, it is determined whether the BCH error correction code (referred to as Ecc) can complete the error correction code processing of the codeword and reply to the user data, and if it can be completed, the decoding is terminated and the step S33A4 fails. The human step S34 'recognizes the current reading level in the flash memory, and temporarily stores the obtained information. Step milk, set 疋-a new object to take the level ‘also temporarily stores the 7^ data read by this new reading level. Next, in step S32B, it is judged that BCHECC is the error correction code processing of the word, and if so, the flow proceeds to step S33B to end the decoding. Ping..., then enter
S36，承^斷%當S32B的BCH ECC失敗日夺進入步驟 H 1 、里到第N次讀取位準的調整，其中第N 一人為取後—次調整，若未到達N次，則回到牛驟^ Γ 之進入步驟S38。在❹到步驟S35，反 調整時所暫存的各位^次 ，將先刖在進行讀取位準 訊’藉由碼字與此進行分析，而㈣—組軟資 更正碼處理後可以細LDPC解碼，咖C錯誤 關於對各位元資料如_〜第—碼字’然後進入步驟S32C。 細的說明。在步驟細過程，將於後文有更詳 咖同位料掏版= 8 M417635 利地完成碼字的校正而回復用戶資料時，進入步驟S33C， 結束解碼。若BCHECC失敗時則進入步驟S39,表示元件 才貝毀。 圖4是依據本創作實施例之藉由讀取重試操作來獲得 組軟資訊的示意圖。請參照圖4 «>記憶體裝置可以藉由 項取重試的機制來產生一組軟資訊。在原先預設的讀取位 準Vread中’可以讀取（量測）到一筆為12位元的資料， 由表咼有效位元（most significant bit，簡稱為MSB )至最 低有效位元（least significant bit，簡稱為LSB)依序為“0011 1001 0000”。在讀取重試操作時，新的讀取位準可以為多 個遞增及/或多個遞減的讀取電壓級別，並且在每一次 言買取位準設定時暫存一筆所讀取（量測）到的12個位元。 請注意，本創作雖然以丨2位元的資料為例，但位元的數目 不以此為限。 本實施例共進行15次的可靠度量測，可以得到15筆 暫存資料，然而量測的次數不以此為限。以每一筆資料的 LSB為例，1出現為3次，因此出現1的機率“3/15” ； 再以每一筆資料的MSB為例，“1”出現為〇:欠，'因此出現 1的機率為“〇”。如果碼字為12位元資料，則這組軟資訊 由MSB至LSB ’關於每—位元資料為丨的機率值依序分 別為 0、2/15、8/15、U/15、卜 4/15、7/15、丄、1/15、6/15、 〇以及3/15。 值得-提的是，本創作可以根據實際量測來做分析， 進而可以獲取-_MLDPC錯誤更正碼處理的軟資訊。 9 以提Ϊΐίΐ，本創作的記憶體裝置中，錯誤更正I晋τ _錯同方式，並且快閃記憶體可以記錄碼;與: 以從快閃妙；^於回復使用者資料時，錯誤更正裝置可 制來心_讀取資料的解碼動作中藉由讀取重試 2產生-組軟資訊，將此組軟資訊 4的機 ==復資料。此外，本創作的記憶體 可度的需=僅:;=置：點’還可，高 應用性亦更為叙/ 可更為提高， 創作已以實施例揭露如上，然其並_以限定 太碰ί何所屬技術領域中具有通常知識者，在不脫離 之^神和範圍内，當可作些許之更動與潤飾，故太 •Η乍之保護範圍當賊附之巾請專纖圍所界定者為準。 【圖式簡單說明】 哥圖1疋依據本創作實施例之記憶體裝置的電路方塊 圖2是依據本創作實施例之碼字結構圖。 ι圖3是依據本創作實施例之記憶體裝置的解碼流程 獲得 圖4是依據本創作實施例之藉由讀取重試操作來 一組軟資訊的示意圖。S36, the % of the failure of the BCH ECC of the S32B enters the adjustment of the reading level H 1 and the Nth reading step, wherein the Nth person takes the post-adjustment adjustment, if it does not reach N times, then The process proceeds to step S38. In step S35, the temporary storage of each bit will be performed before the reading of the bit information 'by the code word and the analysis, and (4) - the group of soft money correction code processing can be fine LDPC Decoding, coffee C error about the metadata of each element such as _~first-codeword' then proceeds to step S32C. Detailed instructions. In the detailed process of the step, the user will reply to the user data after the correction of the code word is completed in the following paragraph, and the process proceeds to step S33C to end the decoding. If the BCHECC fails, the process proceeds to step S39, indicating that the component is destroyed. 4 is a schematic diagram of obtaining group soft information by a read retry operation in accordance with the present creative embodiment. Referring to Figure 4, the <memory device can generate a set of soft information by means of a retry. In the original preset read level Vread, 'can read (measure) to a 12-bit data, from the most significant bit (MSB) to the least significant bit (least) The significant bit, referred to as LSB, is "0011 1001 0000". During a read retry operation, the new read level can be a plurality of incremental and/or multiple decremented read voltage levels, and a read is temporarily stored each time the level is set. ) to 12 bits. Please note that although this creation is based on the data of 丨2 bits, the number of bits is not limited to this. In this embodiment, a total of 15 reliable measurements are performed, and 15 temporary data can be obtained. However, the number of measurements is not limited thereto. Taking the LSB of each data as an example, 1 appears as 3 times, so the probability of occurrence of 1 is “3/15”. Taking the MSB of each data as an example, “1” appears as 〇: owe, 'so 1 appears The probability is "〇". If the codeword is 12-bit data, the probability of the set of soft information from MSB to LSB 'About per-bit data is 0, 2/15, 8/15, U/15, and Bu 4 respectively. /15, 7/15, 丄, 1/15, 6/15, 〇 and 3/15. It is worth mentioning that this creation can be analyzed according to the actual measurement, and then the soft information of the -_MLDPC error correction code processing can be obtained. 9 In the memory device of this creation, the error correction I τ _ wrong way, and the flash memory can record the code; and: to flash from the wonderful; ^ in response to user data, error correction The device can generate the heart_read data decoding operation by reading retry 2 to generate the group soft information, and the set of soft information 4 machine == complex data. In addition, the memory of this creation needs to be = only:; = set: point 'can also, high applicability is more narration / can be more improved, the creation has been exposed as above in the embodiment, but it is limited If you have a general knowledge in the technical field, you can make some changes and refinements without departing from the scope of the gods and the scope. Therefore, the scope of protection of the Η乍 Η乍 当 贼 请 请 请 请 请 请 请 请The definition is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a block diagram of a code word according to an embodiment of the present invention. FIG. 3 is a decoding flow of the memory device according to the present embodiment. FIG. 4 is a schematic diagram of a set of soft information by a read retry operation according to the present embodiment.