1335502 ' . 99 年10 月 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種快閃記憶體，尤指一種快閃記憶體 *系統及其控制方法。 产 【先前技術】 在過去的數十年間，錯誤修正和錯誤彳貞測的問題有實 鲁際可行的重要性。錯誤偵測和修正可在傳送方傳輸到接受 方的過程中偵測因塗改或其他損傷造成的錯誤，並同時定 位和修正錯誤。為了解決上述問題而產生了錯誤修正碼 (Error Correcting Code, ECC)。ECC使用於如快閃記憶體 和動態隨機存取記憶體的電腦資料儲存設備和資料傳輸 中。例子包含漢明碼（Hamming code)、里德所羅門碼 (Reed-Solomon code) 、 BCH 碼 ® (Bose-Chaudhuri-Hocquenham, BCH)、里德米勒碼 (Reed-Muller code)、二次元格雷碼（Binary Golay code)、迴旋碼（convolutional code)、及滿輪碼（turbo code)。最簡單的錯誤修正碼可修正單一位元錯誤並偵測雙 位元錯誤。其他碼則可偵測或修正多位元錯誤。ECC藉由對 抗電腦記憶體中可能的錯誤來提高資料準確性和系統正常 運行時間。 5 1335502 99年10月12日修正贊換頁 圖1依據先别技術說明快閃檔案系統中虛擬對實體位 址的轉換。實體空間13是由實際上是抹除區的實體單元U1 所組成，意即.可被抹除的最小區塊。每一個實體單元 含有一或多個實體頁113’而一頁是可被寫入的最小區塊。 虛擬空間11疋由有等同實體單元大小的虛擬單元121所組 成。每一虛擬單元含有一或多個虛擬頁123，其大小等同實 體頁113。當一應用為了讀取或寫入提供一虛擬位址時，虛 擬位址所屬的虛擬單元數字將從虛擬位址中摘錄。同上所毫 述’-實體頁是用以程式設計資料讀取的最小單元。換言 之，先别技術無法處理小於一頁大小的儲存資料像是傳 統决閃。己憶體的512位元組或細D快閃記憶體的2〇48位元 組，並相對地影響快閃記憶體的整體可靠度和表現。 另外，錯誤修正所需時間與錯誤修正位元的長度和錯 誤修正循環中處理的資料位元長度有關。一般而言，可藉 由在錯誤位置中處理更長位元長度的ECC來達成高效率， 所謂錯誤位置意即錯誤最常發生處，反之亦然。然而，先 前記憶體管理電路，像是美國專利申請號n〇 5,937,425的 快閃記憶體系統’因為ECC位元長度和頁數大小受工業標 準:限制’使錯誤修正的經常性消耗相對較高。為了克服 先月J技術的限制’就需要提供一種更有效利用一頁的容量 並有效配置ECC的快閃記憶體系統及其控制方法。 6 1335502 - 、 99年10月12日修正替換頁 ' * 【發明内容】 本發明發現了習知裝置的某些問題。本發明所揭示效 率倍增和其他好處的方法克服了習知錯誤修正電路系統所 .無法達成的缺點。本發明的目標是提供一種更有效利用一 -頁的容量並有效配置ECC的快閃記憶體系統。 依照本發明之一觀點，快閃記憶體系統包括每頁由不 同容量的複數個記憶體區域所組成的一組頁數、用以控制 •其中一頁的資料讀取或寫入的讀取/寫入控制器、包含至 少兩個ECC引擎且每個引擎可編碼或解碼資料用以執行錯 誤偵測和錯誤修正的錯誤修正單元、及用以在預設條件基 礎上選取一適當ECC引擎的ECC判斷單元。 根據本案構想，預設條件包括考量所使用記憶體區域 和所放置的資料特性。 根據本案構想，ECC有不同的位元長度。 # 根據本案構想，ECC有不同的編碼演算法。 根據本案構想，編碼演算法包括漢明碼、里德所羅門 碼、BCH碼、里德米勒碼、二次元格雷碼、迴旋碼、及渦輪 碼。 根據本案構想，每頁包含2048位元組。 根據本案構想，每頁包含512位元組。 根據本案構想，錯誤頻繁的記憶體區域搭配更長位元 長度的ECC。 7 99年10月I2日修正管換頁 本根據本案構想，快閃記憶體系統能成為USB隨身碟、SD 卡、MMC卡、及快閃隨身碟。 本發明的另一個目標是提供一種用以控制有一組頁數 的快閃s己憶體系統的方法。 依照本發明的另一觀點，一種用以控制有一組頁數的 快閃記憶體系統的方法’包括以下步驟··將每頁分割成有 不同容量的複數個記憶體區域；取得資料；在預設條件基 礎上由複數個ECC引擎中選取一個適當的咖；及儲存資料 和ECC輸出（通稱冗位或同位檢查數字）。 根據本案構想，預設條件包括考量所使用記憶體區域 和所放置的資料特性。 根據本案構想，ECC有不同的位元長度。 根據本案構想，ECC有不同的編碼演算法。 根據本案構想，編碼演算法包括漢明碼、里德所羅門 碼、BCH碼、里德米勒碼、二次元格雷碼、迴旋碼、及渴 輪編碼。 根據本案構想，每頁包含2048位元組。 根據本案構想’每頁包含512位元組。 根據本案構想，錯誤頻繁的記憶體區域搭配更長位元 長度的ECC。 根據本案構想，快閃記憶體系統能成為USB隨身碟、幼 卡、MMC卡、及快閃隨身碟。 1335502 99年10月12日修正替換頁 依照本發明的另一觀點，一種用以控制有一組頁數的 快閃記憶體系統的方法，包括以下步驟：要求存取儲存於 記憶體區域的資料；透過快閃記憶體系統存取資料；在預 設條件基礎上由複數個ECC引擎中選取一個適當的ECC ;用 選取的ECC修正資料；及輸出資料。 根據本案構想，預設條件包括考量所使用記憶體區域 和所放置的資料特性。 根據本案構想，ECC有不同的位元長度。 根據本案構想5 ECC有不同的編碼演鼻法。 根據本案構想，編碼演算法包括漢明碼、里德所羅門 碼、BCH碼、里德米勒碼、二次元格雷碼、迴旋碼、及渦 輪編碼。 根據本案構想，每頁包含2048位元組。 根據本案構想，每頁包含512位元組。 根據本案構想，錯誤頻繁的記憶體區域搭配更長位元 長度的ECC。 根據本案構想，快閃記憶體系統能成為USB隨身碟、SD 卡、MMC卡、及快閃隨身碟。 依照本發明的另一觀點，一種快閃記憶體系統包括每 頁由相同容量的複數個記憶體區域所組成的一組頁數、用 以控制其中一頁的資料讀取或寫入的讀取/寫入控制器、 包含至少兩個ECC引擎且每個引擎可編碼或解碼資料用以 91335502 '. October 1999 IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory, and more particularly to a flash memory system and a control method thereof. Production [Prior Art] In the past few decades, the problems of error correction and error speculation have been of practical importance. Error detection and correction can detect errors caused by alterations or other damage during transmission to the recipient, and simultaneously locate and correct errors. In order to solve the above problem, an Error Correcting Code (ECC) has been generated. ECC is used in computer data storage devices and data transmission such as flash memory and dynamic random access memory. Examples include Hamming code, Reed-Solomon code, BCH code (Bose-Chaudhuri-Hocquenham, BCH), Reed-Muller code, and second-order Gray code ( Binary Golay code), convolutional code, and turbo code. The simplest error correction code corrects a single bit error and detects double bit errors. Other codes can detect or correct multi-bit errors. ECC improves data accuracy and system uptime by countering possible errors in computer memory. 5 1335502 October 12, 1999 Revised Likes Page 1 Figure 1 illustrates the conversion of virtual to physical addresses in a flash file system based on prior art. The physical space 13 is composed of a physical unit U1 which is actually an erased area, that is, the smallest block that can be erased. Each physical unit contains one or more physical pages 113' and one page is the smallest block that can be written. The virtual space 11 is composed of virtual units 121 having an equivalent physical unit size. Each virtual unit contains one or more virtual pages 123 that are equal in size to the physical page 113. When an application provides a virtual address for reading or writing, the virtual unit number to which the virtual address belongs will be extracted from the virtual address. As stated above, the '-physical page is the smallest unit used to read the programming data. In other words, the prior art cannot handle stored data smaller than one page in size like a traditional flash. The 512-bit tuple of the memory or the 2〇48-bit of the fine-D flash memory, and relatively affect the overall reliability and performance of the flash memory. In addition, the time required for error correction is related to the length of the error correction bit and the length of the data bit processed in the error correction loop. In general, high efficiency can be achieved by processing ECCs of longer bit lengths in the wrong location, meaning that the wrong location means that the error occurs most often, and vice versa. However, prior memory management circuits, such as the flash memory system of U.S. Patent Application Serial No. 5,937,425, are subject to industry standards because of the ECC bit length and the number of pages. In order to overcome the limitations of the prior art J technology, it is necessary to provide a flash memory system and a control method thereof that efficiently utilize the capacity of one page and effectively configure the ECC. 6 1335502 - , October 12, 1999 Amendment Replacement Page '* [Invention] The present invention finds certain problems with conventional devices. The method of multiplying efficiency and other benefits disclosed by the present invention overcomes the shortcomings that conventional error correction circuitry cannot achieve. It is an object of the present invention to provide a flash memory system that utilizes one-page capacity more efficiently and efficiently configures ECC. According to one aspect of the present invention, a flash memory system includes a set of pages consisting of a plurality of memory regions of different capacities per page, for controlling the reading of a page of data reading or writing/ Writing to the controller, an error correction unit including at least two ECC engines, each of which can encode or decode data for performing error detection and error correction, and an ECC for selecting an appropriate ECC engine based on preset conditions Judging unit. According to the concept of the present case, the preset conditions include consideration of the memory area used and the characteristics of the data placed. According to the concept of the case, ECC has different bit lengths. # According to the concept of this case, ECC has different coding algorithms. According to the present concept, the encoding algorithm includes Hamming code, Reed Solomon code, BCH code, Reed Miller code, quadratic Gray code, convolutional code, and turbo code. According to the concept of the case, each page contains 2048 bytes. According to the concept of the case, each page contains 512 bytes. According to the concept of the case, the frequently erroneous memory area is matched with the ECC of a longer bit length. 7 October 1999 I2 revision tube change page According to the concept of this case, the flash memory system can become a USB flash drive, SD card, MMC card, and flash flash drive. Another object of the present invention is to provide a method for controlling a flash suffix system having a set of pages. According to another aspect of the present invention, a method for controlling a flash memory system having a set of pages includes the following steps: dividing each page into a plurality of memory regions having different capacities; acquiring data; Based on the conditions, select an appropriate coffee from a plurality of ECC engines; and store data and ECC output (known as redundant or parity check numbers). According to the concept of the present case, the preset conditions include consideration of the memory area used and the characteristics of the data placed. According to the concept of the case, ECC has different bit lengths. According to the concept of this case, ECC has different coding algorithms. According to the present concept, the coding algorithm includes Hamming code, Reed Solomon code, BCH code, Reed Miller code, quadratic Gray code, convolutional code, and thirsty wheel coding. According to the concept of the case, each page contains 2048 bytes. According to the concept of the case, each page contains 512 bytes. According to the concept of the case, the frequently erroneous memory area is matched with the ECC of a longer bit length. According to the concept of this case, the flash memory system can be a USB flash drive, a baby card, an MMC card, and a flash flash drive. 1335502 Modified on October 12, 1999, in accordance with another aspect of the present invention, a method for controlling a flash memory system having a set of pages, comprising the steps of: requiring access to data stored in a memory region; Accessing data through the flash memory system; selecting an appropriate ECC from a plurality of ECC engines based on preset conditions; correcting the data with the selected ECC; and outputting the data. According to the concept of the present case, the preset conditions include consideration of the memory area used and the characteristics of the data placed. According to the concept of the case, ECC has different bit lengths. According to the concept of this case, 5 ECC has different coded nasal algorithms. According to the present concept, the encoding algorithm includes Hamming code, Reed Solomon code, BCH code, Reed Miller code, quadratic Gray code, convolutional code, and turbo coding. According to the concept of the case, each page contains 2048 bytes. According to the concept of the case, each page contains 512 bytes. According to the concept of the case, the frequently erroneous memory area is matched with the ECC of a longer bit length. According to the concept of the case, the flash memory system can be a USB flash drive, an SD card, an MMC card, and a flash drive. According to another aspect of the present invention, a flash memory system includes a set of pages each composed of a plurality of memory regions of the same capacity, and a reading for reading or writing data of one of the pages. / write controller, contains at least two ECC engines and each engine can encode or decode data for 9
JJUZ 99年10月l2日修正管換頁 執行錯誤仙!和錯祕正的錯誤修正單元^用以 條件基礎上選取-適當ECC引擎的ECC判斷單元。 根據本案構想’預設條件包括考量所使用記憶體區 域和所放置的資料特性。 根據本案構想，ECC有不同的位元長度。 根據本案構想，Ecc有不同的編碼演算法。 根據本案構想，編碼演算法包括漢明碼、里德所羅 ’ I BCH碼、里德米勒碼、二次元格雷碼、迴旋碼、及 渴輪碼。 根據本案構想，每頁包含2048位元組。 根據本案構想，每頁包含512位元組。 根據本案構想，複數個記憶體區域各有n x 512位 元組的容量，而η是一個自然數。 根據本案構想，錯誤頻繁的記憶體區域搭配更長位元 長度的ECC。 根據本案構想，快閃記憶體系統包含USB隨身碟、 SD卡、MMC卡、及快閃隨身碟。 依照本發明的另一觀點，一種用以控制有一組頁數 的快閃記憶體系統的方法，包括以下步驟：將每頁分割成 有相同容量的複數個記憶體區域；取得資料在預設條件基 礎上由複數個ECC引擎t選取一個適當的ECC;及儲存資 料和ECC輸出（通稱冗位或同位檢查數字）。 1335502 - 、 99年10月12日修正替換頁 - « ♦ / 【實施方式】 本發明揭露一種快閃記憶體系統及其控制方法。熟悉 此技藝者將在閱讀接下來實施方式和附帶圖式後，更了解 .本發明的上述目標和優點。本發明不需被接下來的實施例 • 所限制。 請參考圖2，其根據本發明說明快閃記憶體系統的較 佳内部結構。如圖2所示，快閃記憶體系統含有一組頁數（為 • 了示範用途，所以在圖式中只以頁20來呈現）、用以控制其 中一頁資料讀取或寫入的一讀取/寫入控制器21、一ECC 判斷單元22、及一錯誤修正單元23。錯誤修正單元23進一 步包括ECC引擎231、232、及233。 每頁之容量為21 12(2048資料攔位+64備用欄位）位元 組，及進一步組成不同容量的複數個記憶體區域用以儲存 資料。儲存的資料分割成數段以符合分別的記憶體區域。 _替代實施例亦可在快閃記憶體系統使用不同容量大小的一 頁。如圖2的頁20所示，為了清楚說明，記憶體區域被分別 給予區號。如圖3所示，每一記憶體區域可儲存帶有ECC的 資料段，意即，描述在資料段中位元序列的冗餘資訊。另 外，分別資料段的ECC亦可一併放在每頁頁尾的冗餘部份。 根據在預設條件基礎上ECC判斷單元22的選取，例如考量所 使用的記憶體區域和所放置的資料特性，錯誤修正單元23 的ECC引擎23卜232或233將編碼輸入的資料及產生冗位。 11 1335502 _ 99年10月I2日修正管換頁 搭配的ECC可以有不同的位元長度，如果有偵測到錯誤的 -話，可用增加額外資訊到資料段的方式允許資料段的修 正。此外，ECC引擎231、232及233可採納一些不同的編碼 演算法，例如漢明碼、里德所羅門碼、BCH碼、里德米勒碼、 二次元格雷碼、迴旋碼、及渦輪碼等等之類。錯誤修正單 -元23是專用以ECC判斷單元22方式選取的ECC來編碼或解碼 資料。 請參考圖4和圖5,其根據本發明說明一種用以控制資 _ 料輸入方法的步驟。步驟S 31是在寫入資料到錯誤修正循環 期間的頁數之前實施。2112位元組容量的頁20是被分割成 有不同容量的複數個記憶體區域。在此實施例中，共有8 個記憶體區域，區1、區2、區3..... 及區8,且替代實 施例亦可分割額外的記憶體區域以進行操作。分割過的每 頁容量分別是522位元組、8位元組、522位元組、4位元組、 522位元組、4位元組、522位元組、及8位元組。輸入的資 φ 料也是依照每個記憶體區域的大小去分割。在圖4步驟 S32，輸入的資料是傳送到ECC判斷單元22以從錯誤修正單 元23的ECC引擎23卜232、及233中選取適當的ECC引擎。基 於考量所使用的記憶體區域和所放置的資料特性，此實施 例中，里德所羅門碼和BCH碼是被選取做為編碼資料。在步 驟S33中，錯誤修正單元23中ECC引擎23卜232及233的其中 一個被指示產生有分別冗位的8個不同編碼資料段。 12 1335502 - 99年10月12日修正替換頁 v • ' 每個ECC引擎利用一個特殊的編碼演算法把資料段重 組及編碼成冗餘格式。更具體而言，編碼演算法可以依據 錯誤位置在位元或符號層作業。因此，藉由里德所羅門碼、 .BCH碼、里德所羅門碼、BCH碼、里德所羅門碼、BCH碼、里 .德所羅門碼、及BCH碼將資料編碼，並分割成8段後落在對 應的記憶體區域，而它們對應的ECC分別如下：4個符號、4 個位元、4個符號、5個位元、4個符號、5個位元、4個符號、 參及4個位元。在步驟S34，演算法基礎冗餘資訊是透過讀取 /寫入控制器21與資料段一起記錄，並同時增加到預先定 義記憶體區域的冗餘部分，在此部份中，ECC含有可被解碼 以偵測及修正可能因資料傳輸造成的錯誤有效冗餘資訊。 請參考圖6及圖7，其根據本發明說明一種用以控制資 料輸出方法的步驟。如圖7的步驟S41，當要求讀取儲存的 資料時，連同ECC的資料段由頁20的記憶體區域取得並透過 鲁讀取/寫入控制器21傳送到ECC判斷單元22，如圖6所示。 同樣地，在圖7的步驟S42，ECC判斷單元22根據冗餘資訊決 定哪個ECC引擎有使用過。基於ECC判斷單元22的選取，產 生的ECC藉由原本所使用的演算法再次計算和解碼儲存的 資料及資料段，意即，如圖7步驟S43所示的里德所羅門碼 和BCH碼。接著是步驟S44，在偵測出錯誤，且可被錯誤修 正的情況下，錯誤修正單元23偵測錯誤存在與否並對頁20 的儲存資料段進行適當修正，如果藉由解碼ECC的方式沒偵 13 1335502 _ 99年10月I2日修正管換頁 測出錯誤的話，代表資料沒錯誤且將被讀出，如圖7的步驟-· S45所示。否則，遺漏或錯誤的位元會透過解碼的ECC決定， 並藉由步驟S46所設定之演算法方式提供或修正單一位元 或數個位元，並在圖7最後一個步驟S47輸出修正的資料。 本發明的特性特別適合應用於USB隨身碟、SD卡、MMC 卡、及快閃隨身碟。另外，每頁亦可被分割成數個相同容 量的記憶體區域，每區有η X 512位元組的容量，而η是一 個自然數。無疑地，替代實施例可能採納多樣性的編碼演 鲁 算法或更長位元長度的ECC以進行一頁的錯誤修正操作。換 言之，為了達到ECC的有效利用和配置，更長位元長度或較 佳修正能力的ECC可配合來使用及分配其預設條件，例如錯 誤頻繁的記憶體區域，或儲存容許零位元錯誤的重要資料。 總而言之，本發明提供一種快閃記憶體系統及其控制 方法。快閃記憶體系統含有分割成不同容量記憶區的複數 頁，且此方法在一頁中使用多個ECC來控制快閃記憶體系 _ 統，如在錯誤位置應用更長位元長度的ECC，意即，錯誤最 常發生處，反之亦然。不同於傳統快閃記憶體管理系統， 本發明提供一ECC判斷單元，依據所使用記憶體區域和所放 置的資料特性，選取適當的ECC。本快閃記憶體系統為有效 利用ECC進一步納入至少兩個ECC引擎。鑑於ECC位元長度和 頁數大小受工業標準的限制，本發明藉由提供一種更有效 利用一頁的容量、有效配置ECC的快閃記憶體系統及其控制 1335502 - 、 99年10月12日修正替換頁 . , « ••方法，並整合完整的快閃記憶體系統來成功克服先前技術 的限制。 縱使本發明已由上述之實施例詳細敘述而可由熟悉 本技藝之人士任施匠思而為諸般修飾，然皆不脫如附申請 - 專利範圍所欲保護者。JJUZ October, October, l2, correction tube change page execution error! And the wrong error correction unit ^ used to select the ECC judgment unit of the appropriate ECC engine. According to the concept of the case, the pre-set conditions include consideration of the memory area used and the characteristics of the data placed. According to the concept of the case, ECC has different bit lengths. According to the concept of this case, Ecc has different coding algorithms. According to the present concept, the coding algorithm includes Hamming code, Reed's IBS code, Reed Miller code, quadratic Gray code, convolutional code, and thirsty wheel code. According to the concept of the case, each page contains 2048 bytes. According to the concept of the case, each page contains 512 bytes. According to the present concept, a plurality of memory regions each have a capacity of n x 512 bytes, and η is a natural number. According to the concept of the case, the frequently erroneous memory area is matched with the ECC of a longer bit length. According to the concept of the case, the flash memory system includes a USB flash drive, an SD card, an MMC card, and a flash drive. According to another aspect of the present invention, a method for controlling a flash memory system having a set of pages includes the steps of: dividing each page into a plurality of memory regions having the same capacity; obtaining data in a preset condition Based on a plurality of ECC engines t select an appropriate ECC; and store data and ECC output (known as redundancy or parity check numbers). 1335502 - , October 12, 1999 Amendment Replacement Page - « ♦ / [Embodiment] The present invention discloses a flash memory system and a control method thereof. Those skilled in the art will appreciate the above objects and advantages of the present invention after reading the following embodiments and accompanying drawings. The invention is not limited by the following embodiments. Referring to Figure 2, a preferred internal structure of a flash memory system is illustrated in accordance with the present invention. As shown in Figure 2, the flash memory system contains a set of pages (for demonstration purposes, so only the page 20 is presented in the drawing), one for controlling the reading or writing of one page of data. The read/write controller 21, an ECC judging unit 22, and an error correcting unit 23 are provided. The error correcting unit 23 further includes ECC engines 231, 232, and 233. Each page has a capacity of 21 12 (2048 data block + 64 spare fields) and further forms a plurality of memory areas of different capacities for storing data. The stored data is divided into segments to match the respective memory regions. Alternative embodiments may also use one page of different size in the flash memory system. As shown on page 20 of Fig. 2, the memory regions are given area codes, respectively, for clarity of explanation. As shown in Figure 3, each memory region can store data segments with ECC, meaning redundant information describing the sequence of bits in the data segment. In addition, the ECC of the data segment can also be placed in the redundant part of the page at the end of each page. According to the selection of the ECC judging unit 22 based on the preset condition, for example, considering the memory area used and the placed data characteristics, the ECC engine 23 232 or 233 of the error correcting unit 23 will encode the input data and generate redundancy. . 11 1335502 _ October 1999 I2 correction tube change page The ECC can be used with different bit lengths. If there is an error detected, the data segment can be corrected by adding additional information to the data segment. In addition, ECC engines 231, 232, and 233 can employ a number of different encoding algorithms, such as Hamming code, Reed Solomon code, BCH code, Reed Miller code, Quadratic Gray code, gyro code, and turbo code. class. Error Correction Unit - Element 23 is an ECC specifically selected by the ECC judgment unit 22 to encode or decode data. Referring to Figures 4 and 5, a method for controlling the input method of the material is illustrated in accordance with the present invention. Step S31 is performed before the number of pages during which the data is written to the error correction loop. Page 20 of the 2112-byte capacity is divided into a plurality of memory regions having different capacities. In this embodiment, there are a total of 8 memory areas, area 1, area 2, area 3, ... and area 8, and alternative memory areas may be split for operation in place of the embodiment. The divided page capacity is 522 bytes, octets, 522 bytes, 4 bytes, 522 bytes, 4 bytes, 522 bytes, and 8 bytes. The input information is also divided according to the size of each memory area. At step S32 of Fig. 4, the input data is transmitted to the ECC judging unit 22 to select an appropriate ECC engine from the ECC engines 23, 232, and 233 of the error correcting unit 23. Based on the memory area used and the characteristics of the data placed, in this embodiment, the Reed Solomon code and the BCH code are selected as the encoded data. In step S33, one of the ECC engines 23 232 and 233 in the error correcting unit 23 is instructed to generate 8 different coded data segments having respective redundancy. 12 1335502 - October 12, 1999 Revised Replacement Page v • 'EEC's ECC engine uses a special encoding algorithm to reassemble and encode data segments into a redundant format. More specifically, the encoding algorithm can operate at the bit or symbol level depending on the location of the error. Therefore, the data is encoded by Reed Solomon code, .BCH code, Reed Solomon code, BCH code, Reed Solomon code, BCH code, Riede Solomon code, and BCH code, and is divided into 8 segments and then falls on Corresponding memory regions, and their corresponding ECC are as follows: 4 symbols, 4 bits, 4 symbols, 5 bits, 4 symbols, 5 bits, 4 symbols, and 4 bits. yuan. In step S34, the algorithm basic redundancy information is recorded together with the data segment by the read/write controller 21, and simultaneously added to the redundant portion of the predefined memory region, in which the ECC contains Decoding to detect and correct invalid and redundant information that may be caused by data transmission. Referring to Figures 6 and 7, a method for controlling a data output method is illustrated in accordance with the present invention. As step S41 of FIG. 7, when the stored data is requested to be read, the data segment along with the ECC is taken from the memory area of page 20 and transmitted to the ECC judging unit 22 through the Lu/Read controller 21, as shown in FIG. Shown. Similarly, in step S42 of Fig. 7, the ECC judging unit 22 decides which ECC engine has been used based on the redundant information. Based on the selection of the ECC judging unit 22, the generated ECC recalculates and decodes the stored data and data segments by the algorithm originally used, i.e., the Reed Solomon code and the BCH code as shown in step S43 of FIG. Next, in step S44, in the case where an error is detected and can be corrected by mistake, the error correcting unit 23 detects the presence or absence of the error and appropriately corrects the stored data segment of the page 20, if the method of decoding the ECC is not Detective 13 1335502 _ In October, I2, when the correction tube was changed, the data was found to be error-free and will be read, as shown in step-S45 of Figure 7. Otherwise, the missing or erroneous bit is determined by the decoded ECC, and a single bit or a plurality of bits are provided or corrected by the algorithm set in step S46, and the corrected data is output in the last step S47 of FIG. . The features of the present invention are particularly well suited for use with USB flash drives, SD cards, MMC cards, and flash flash drives. In addition, each page can be divided into a plurality of memory areas of the same capacity, each area having a capacity of η X 512 bytes, and η is a natural number. Undoubtedly, alternative embodiments may employ a diverse coded algorithm or a longer bit length ECC to perform a one page error correction operation. In other words, in order to achieve efficient use and configuration of ECC, ECCs with longer bit lengths or better correction capabilities can be used in conjunction with and assigning their preset conditions, such as frequently erroneous memory regions, or storing permissible zero bit errors. Important information. In summary, the present invention provides a flash memory system and a control method therefor. The flash memory system contains a plurality of pages divided into different capacity memory areas, and this method uses multiple ECCs in one page to control the flash memory system, such as applying a longer bit length ECC at the wrong location, That is, the most common occurrence of the error, and vice versa. Unlike the conventional flash memory management system, the present invention provides an ECC judging unit that selects an appropriate ECC depending on the memory area used and the data characteristics placed. This flash memory system is further integrated into at least two ECC engines for efficient use of ECC. In view of the limitation of ECC bit length and page size by industry standards, the present invention provides a flash memory system and its control for effectively configuring ECC with more efficient use of one page capacity. 1335502 - October 12, 1999 Fixed replacement page. , « •• method, and integrated complete flash memory system to successfully overcome the limitations of the prior art. Even though the invention has been described in detail by the above-described embodiments, it can be modified by those skilled in the art, and the invention is intended to be protected by the appended claims.
15 1335502 . 99年10月I2日修正弩換頁 【圖式簡單說明】 熟悉此技藝者將在閱讀接下來實施方式和附帶圖式 後，更了解本發明的上述目標和優點： 圖1根據習知說明在快閃檔案系中實體位址的示意圖； 圖2根據本發明說明快閃記憶體系統的内部結構· 圖3是一頁的示意圖； 圖4是根據本發明之資料輸入路徑的示意圖； 圖5根據本發明說明資料輸入方法的步驟流程； 《 圖6是根據本發明之資料輸出路徑的示意圖；及 圖7根據本發明說明資料輸出方法的步驟流程。 【主要元件符號說明】 11 虛擬空間 111 XiO — 早兀 113 頁 121 單元 123 頁 13 實體空間 20 頁 21 讀取/寫入控制器 22 ECC判斷單元 23 錯誤修正單元 16 1335502 231 232 233 ECC引擎 ECC引擎 ECC引擎 99年10月12日修正替換頁15 1335502. October 1999 I2 弩 弩 弩 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 阅读 阅读 阅读 阅读 阅读 阅读 阅读 阅读 阅读 阅读 阅读BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic diagram showing the internal structure of a flash memory system according to the present invention. FIG. 3 is a schematic diagram of a page; FIG. 4 is a schematic diagram of a data input path according to the present invention; 5 is a flow chart showing the steps of the data input method according to the present invention; and Fig. 6 is a schematic diagram showing the data output path according to the present invention; and Fig. 7 is a flow chart showing the steps of the data output method according to the present invention. [Main component symbol description] 11 Virtual space 111 XiO — Early 113 pages 121 Unit 123 Page 13 Physical space 20 Page 21 Read/write controller 22 ECC judgment unit 23 Error correction unit 16 1335502 231 232 233 ECC engine ECC engine ECC engine revised replacement page on October 12, 1999
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