TWM400092U - Power converter integrated circuit floor plan and package - Google Patents

Power converter integrated circuit floor plan and package Download PDF

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Publication number
TWM400092U
TWM400092U TW099212539U TW99212539U TWM400092U TW M400092 U TWM400092 U TW M400092U TW 099212539 U TW099212539 U TW 099212539U TW 99212539 U TW99212539 U TW 99212539U TW M400092 U TWM400092 U TW M400092U
Authority
TW
Taiwan
Prior art keywords
pad
corner
μπι
die
μιη
Prior art date
Application number
TW099212539U
Other languages
Chinese (zh)
Inventor
H Nguyen James
Original Assignee
Monolithic Power Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Monolithic Power Systems Inc filed Critical Monolithic Power Systems Inc
Publication of TWM400092U publication Critical patent/TWM400092U/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

For a DC to DC converter circuit integrated on a packaged die, the relative positions of various die pads and power MOSFETs on the die for a small outline integrated circuit package are described.

Description

M400092 五、新型說明: 【新型所屬之技術領域】 [0001] 【先前技術】 [0002 ] 第1圖所示的電路可以表示多種類型的直流直流功率轉換 積體電路。如第1圖所示,負載102通過從電源VI N獲取能 量,使負載電壓穩定在一個低於VIN的數值。節點103提 供回饋信號給控制器1 04。控制器1 04通過控制高端開關 φ 1〇6和低端開關1〇8的占空比調節負載電壓。電感11〇和 電容112耦接於開關節點114和輸出負載1〇2之間,組成 低通濾波器,用以獲取平滑的負載電壓》 對於本領域技術人員來說,第1圖所示電路的工作原理已 是眾所周知,因此無須在此重述。在此,第1圖所示的電 路疋作為一個不例’用以付論電路設計人員所面臨的一 些技術要點。要點之一是開關106和108導通時的電阻, 即導通電阻(on-resistance)。現代微處理器和其他 • 低功耗電路的電源電壓均較低,因此低端開關1 〇 8的占空 比大於尚端開關1 0 6的占空比。隨著負載電壓的降低,減 小低端開關10 8的導通電阻成為減小功率損失的重要方法 。開關106和108的連接導線(bond wire)電阻和導通電 阻是功率熱損耗的主要因素。 實踐中’開關106和108通常由功率M0SFET (金屬-氧化 物_半導體場效應電晶體)實現,並且每個開關均由大量 的M0SFET並聯而成。眾所周知,功率mosfet可能會產生 寄生NPN電晶體,導致有害電流產生。如第2圖所示,功 表單編號A0101 第3頁/共30頁 M400092 率MOSFET 202和204對應高端開關和低端開關,NPN電 晶體206是功率M0SFET 204的寄生電晶體。為說明方便 ,在第2圖中未示出回饋環路和控制器,功率M0SFET 202和204的驅動電路也被簡化為邏輯門208和210。來自 埠212的開關信號經過邏輯門208和21 0後產生死區時間 (dead-time),使功率M0SFET 202和204不能在同一 時間導通。 在死區時間内,功率M0SFET 202和204同時關閉。此時 ,若電流通過電感110流向負載102,如箭頭214所示, 開關節點114的電位小於零,為-VBE ,從而導致電晶體 206產生發射極電流,其中VBE為NPN電晶體206的導通 電壓。這會導致產生有害的襯底注入電流(substrate injection current),進而影響到控制器104中部分 電路的性能。例如,對於提供參考電壓的帶隙電路以及 其他電路,空間分隔的電路元件往往需要良好的性能匹 配。然而,由於流過這些電路元件的注入電流不相同, 導致其出現性能不匹配,這可能會嚴重降低直流直流功 率轉換積體電路的整體性能。 為了減少流入至敏感電路元器件的襯底注入電流,功率 M0SFET周圍需形成特殊結構,用以收集襯底注入電流並 將之傳導至地電位,使襯底注入電流無法到達敏感電路 ,這些特殊結構通常被稱為壕溝(moat)。 另一個設計要點是從積體電路到引腳之間連接導線的電 阻,這點對高性能積體電路的設計尤為突出。連接導線 的長度取決於直流直流功率轉換積體電路各個組成部分 的位置、大小以及封裝類型。晶片的成本已經下降到最 表單編號A0101 第4頁/共30頁 M400092 終產品的成本取決於封裝而不是晶粒。因此,往往是電 路設計人員必須為特定封裝定做電路。不能自由選擇引 腳的數目和相對位置,這給設計人員在設計電路尤其是 設計高性能電路時帶來巨大挑戰。對於一個特定的封裝 ,沒有明顯的方法能優化功率MOSFET、壕溝和開關端點 的尺寸和位置,使得一個或者兩個功率MOSFET的導通電 阻和連接導線電阻之和最小或者接近最小。 【新型内容】 [0003] 為解決上述技術問題,本案提供了一能最小化功率 MOSFET的導通電阻和連接導線電阻的晶粒及包含該晶粒 的功率轉換積體電路。 為瞭解決上述技術問題,本案提供了 一晶粒,有一晶粒 拐角,所述晶粒包括:一高端功率MOSFET,所述高端功 率MOSFET具有一漏極和一源極;以及第一焊盤和第二焊 盤,所述第一焊盤和第二焊盤耦接至所述高端功率 MOSFET的漏極,所述第一焊盤相對於晶粒拐角的的座標 為(158. 3 μιη ± d,2945. 8 μπι ± d),所述第二焊 盤相對於晶粒拐角的的座標為(398. 8 μπι 土 d, 2959.4 μιη 土 d),其申 d 不超過 320 μπι。 根據本案的實施例,所述晶粒還包括:一低端功率MOS-FET,所述低端功率MOSFET具有一漏極和一源極;以及 第三焊盤、第四焊盤、第五焊盤和第六焊盤,所述第三 至第六焊盤耦接至高端功率MOSFET的源極和低端功率 MOSFET的漏極,所述第三至第六焊盤相對於晶粒拐角的 座標分別為( 599. 2 μιη ± d,2810. 2 μπι 土 d)、( 表單編號Α0ΚΠ 第5頁/共30頁 M400092 599.2 μπι ± d,2465.1 μιη ± d) 、 (599.2 μιη ± d ’2133.8 μιη ± d)和(599·2 μιη ± d,1791.5 um ± d) ° 根據本案的實施例,所述晶粒還包括:第七焊盤、第八 焊盤、第九焊盤和第十焊盤,所述第七至第十焊盤耦接 至所述高端功率MOSFET的源極和所述低端功率MOSFET的 漏極,所述第七至第十焊盤對於晶粒拐角的座標分別為 (379.5 μιη ± d,1716.2 μιη ± d) 、 (179.8 μιη土 d’1716.2 μιη ± d)、(417.2 μπι± d,1 439. 3 μπι ± d)和(417.2 μιη± d ,1 083.2 μηι ± d)。 根據本案的實施例,所述晶粒還包括:第十四焊盤、第 十五焊盤、第十六焊盤、第十七焊盤、第十八焊盤和第 十九焊盤,所述第十四至第十九焊盤耦接至所述低端功 率MOSFET的源極,所述第十四至第十九焊盤相對於晶粒 拐角的座標分別為(1466.3 _ ± d,2815.1 μπι ± d )、( 1466.3 μπι ± d,2469 μιη ± d) 、 (1466.3 μηι± d,2121.9 μιη 土 d) 、 (1466.3 μπι ± d, 1 774.8 um ± d) 、 ( 1466.4 μιη ± d , 1427.7 μιη ± d)和(1466.4 μπι ± d,l〇8〇.6 μιη ± d)。 根據本案的實施例,所述高端功率M〇SFET具有第一拐角 、第二拐角、第三拐角和第四拐角,所述第一至第四拐 角相對於晶粒拐角的座標分別為(33.0 μιη ± d, 2894.3 ± d) 、( 525,3 pm± d,2894.3 μπι ± d )、( 525. 3 μηι ± d,1767. 1 μιη ± d)和(33 〇 μ ra ± d ’ 1767· 1 μιη ± d)。 根據本案的實施例,所述低端功率恥”以具有第一拐角 表單煸號A0101 第6頁/共30頁 、第二拐角、第三拐角、第四拐角、第五拐角和第六拐 角’所述第-至第六拐角相對於晶粒拐角的座標分別為 (. 6 μιη 土 d,3040. 士 μιη ± d) 、( 1407. 9 ’ 3040. 9 μηι ± d )、( 1407. um ± d , 97fi ⑽ ± d) 、 ( 479.5 μιη ± d ,976 3 μπ] ± d)、( 479.5 ⑽ ± d,1 545‘3 _ ± d)和(66i 6 叫 ± d ’1545.3 μιη ± d)。 根據本案的實施例,所述低端功輸sfet包括第一區域 MOSFET、第二區域MOSFET和第三區域mosfET » 根據本案的實施例,所述第一區域MOSFET的拐角相對於 晶粒拐角的座標分別為(479 5 μιη ± d,1545 3叩± d)、( 1407. 9 μηι± d,1545. 3 μηι ± d)、( l4〇7. 9 μιη ± d,976. 3 ± d)和( 479. 5 ± mm, 6.3 "m ± d),所述第二區域m〇sfET的拐角相對於 晶粒拐角的座標為(661· 6 ± d,2297. i㈣± d )、(1407. 9 pm ± d ,2297. 1 _ ± d)、( 〇7’9 μιη ± d’1557.1 μιη ± d)和(661.6 μπι 土 d ’ 1557. 1 μιη 土 d);所述第三區域M0SFET的拐角相 對於晶粒拐角的座標為(6616 μ[Π ± d,3040.9 μιη土 d) 、 ( 1407.9 um ± d,3040,9 μιη ± d) ' ( 407.9 μιη 土 d’2308.9 μηι ± d)和(661.6 μιη± d ’ 2308. 9 μπι ± d )。 根據本案的實施例’所述d不超過“Ο μιη。 根據本案的實施例’所述d不超過8〇 μιη。 本案還提供了 一功率轉換積體電路,包括:一晶粒,所 述晶粒有一晶粒拐角,所述晶粒包括:一高端功率M0S- 第7頁/共30頁 表單編號Α0101 FET,所述高端功率MOSFET具有一漏極和一源極;第一 焊盤和第二焊盤,所述第一焊盤和第二焊盤耦接至所述 咼端功率MOSFET的漏極,所述第一焊盤相對晶粒拐角的 的座標為(158.3 μπι 土 d’2945.8 μιη ± d),所述 第二焊盤相對於晶粒拐角的的座標為(398 8 um ± d, 29 59. 4 μιη 土 d),其中d不超過320 um ;以及一引線 框,所述引線框包括第一引腳,所述第一引腳耦接至第 一焊盤和第二焊盤。 根據本案的實施例,所述功率轉換積體電路還包括:所 述晶粒還包括:一低端功率M0SFET,所述低端功率 MOSFET具有一漏極和一源極;第三焊盤、第四焊盤、第 五烊盤和第六焊盤,所述第三至第六焊盤耦接至高端功 率MOSFET的源極和低端功率m〇SFET的漏極,所述第三至 第六焊盤相對於晶粒拐角的座標分別為(599 2 pm ± d ’2810.2 μιη ± d)、( 599.2 μηι土 d,2465.1 ± d) 、 ( 599.2 μπι 土 d,2133.8 μιπ 土 d)和( 599.2 ⑽士 d,1791. 5 ± d);所述引線框還包括第二引 腳,所述第二引腳耦接至第三焊盤、第四焊盤、第五焊 盤和第六焊盤。 根據本案的實施例,所述功率轉換積體電路還包括·所 述晶粒還包括:第七焊盤、第八焊盤、第九焊盤和第十 焊盤所述第七至第十焊盤搞接至所述高端功率 源極和所述低端功率M0SFET的漏極,所述第七至第十焊 盤相對於晶粒拐角的座標分別為( 379·5 μ{π ± d. U16.2 um ± d) 、(179.8 ⑽土 d ’ 1716 2 ⑽土( 表單煸號A0I01 )、(417. 2 μιη土 d ’ 1439. 3 土 d)和(417. 2 u 第8頁/共30頁 ra ~ d ,l〇83.2 ± d);所述引線框還包括第三 引腳,所述第三弓丨腳搞接至第七焊盤、第八焊盤、第九 焊盤和第十焊盤。 根據本案的實施例,所述功率轉換積體電路還包括:所 述b曰粒包括:第十三焊盤、第十四焊盤、第十五焊盤、 第十六焊盤、第十七焊盤、第十八焊盤和第十九焊盤, 所述第十四至第十九焊盤耦接至所述低端功率MOSFET的 源極,所述第十三至第十九焊盤相對於晶粒拐角的座標 分別為(1 493. 4 μπι 土 d,2984. 2 μιη ± d)、( H66.3 土 d ,2815. i μιη ± d) 、 ( 1466 3 _ ± d’24 69 ⑽ ± d)、(1466.3 μιη ± d,2121.9 ± d) 、 ( 1466. 3 μιπ ± d,1774. 8 μιη 土 d)、( !466.4 μιη ± d . 1427.7 ± d) ^ ( 1466.4 μπ, ± d ’刚0.6⑽± d);所述引線框還包括:第四引腳, 所述第四引腳耦接至第十三焊盤;以及一晶粒貼裝盤, 所述日日粒貼裝盤搞接至第十四焊盤、第十五焊盤、第十 六焊盤、第十七焊盤、第十八焊盤和第十九焊盤。 根據本案的實施例,所述高端功率MOSFET具有第一拐角 '第二拐角、第三拐角和第四拐角,所述第一至第四拐 角相對於晶粒拐角的座標分別為(33. 0 nm ± d, 2894.3 ± d) ^ ( 525.3 pm ± d > 2894.3 μπΐ ± d) 、(525.3 pm 土 d,1767.1 μιη ± d)和(33.0 μιη ± d,1 767. 1 μπι ± d)。M400092 V. New description: [New technical field] [0001] [Prior Art] [0002] The circuit shown in Fig. 1 can represent various types of DC-DC power conversion integrated circuits. As shown in Figure 1, the load 102 stabilizes the load voltage at a value below VIN by taking energy from the power supply VI N . Node 103 provides a feedback signal to controller 104. The controller 104 adjusts the load voltage by controlling the duty ratios of the high side switch φ 1〇6 and the low side switch 1〇8. The inductor 11 〇 and the capacitor 112 are coupled between the switch node 114 and the output load 1 〇 2 to form a low pass filter for obtaining a smooth load voltage. For those skilled in the art, the circuit shown in FIG. 1 The working principle is well known and therefore need not be repeated here. Here, the circuit shown in Fig. 1 serves as a technical point for some of the circuit designers. One of the main points is the resistance when the switches 106 and 108 are turned on, that is, on-resistance. Modern microprocessors and others • Low-power circuits have low supply voltages, so the duty cycle of the low-side switch 1 〇 8 is greater than the duty cycle of the low-side switch 1 0 6 . As the load voltage decreases, reducing the on-resistance of the low-side switch 108 becomes an important method of reducing power loss. The bond wire resistance and conduction resistance of switches 106 and 108 are the main factors for power heat loss. In practice, switches 106 and 108 are typically implemented by a power MOSFET (metal-oxide-semiconductor field effect transistor), and each switch is formed by a plurality of MOSFETs connected in parallel. It is well known that power mosfets may generate parasitic NPN transistors, resulting in unwanted current generation. As shown in Fig. 2, the work form number A0101 Page 3 of 30 M400092 The rate MOSFETs 202 and 204 correspond to the high side switch and the low side switch, and the NPN transistor 206 is the parasitic transistor of the power MOSFET 204. For ease of illustration, the feedback loop and controller are not shown in FIG. 2, and the drive circuits of power MOSFETs 202 and 204 are also simplified to logic gates 208 and 210. The switching signal from 埠 212 passes through logic gates 208 and 207 and generates a dead-time such that power MOSFETs 202 and 204 cannot be turned on at the same time. During the dead time, power MOSFETs 202 and 204 are simultaneously turned off. At this time, if current flows through the inductor 110 to the load 102, as indicated by the arrow 214, the potential of the switch node 114 is less than zero, which is -VBE, thereby causing the transistor 206 to generate an emitter current, where VBE is the turn-on voltage of the NPN transistor 206. . This can result in harmful substrate injection currents that can affect the performance of some of the circuits in controller 104. For example, for bandgap circuits that provide a reference voltage, as well as other circuits, space-separated circuit components often require good performance matching. However, since the injection current flowing through these circuit elements is not the same, resulting in a performance mismatch, which may seriously degrade the overall performance of the DC-DC power conversion integrated circuit. In order to reduce the injection current flowing into the substrate of the sensitive circuit component, a special structure is formed around the power MOSFET to collect the substrate injection current and conduct it to the ground potential, so that the substrate injection current cannot reach the sensitive circuit. These special structures Often referred to as a moat. Another design point is the resistance of the wires from the integrated circuit to the pins, which is especially true for high-performance integrated circuits. The length of the connecting wires depends on the position, size and package type of the various components of the DC-DC power conversion integrated circuit. The cost of the wafer has dropped to the maximum Form No. A0101 Page 4 of 30 M400092 The cost of the final product depends on the package and not the die. Therefore, it is often the circuit designer who must customize the circuit for a particular package. The inability to freely select the number and relative positions of the pins poses a significant challenge for designers in designing circuits, especially designing high performance circuits. For a particular package, there is no obvious way to optimize the size and position of the power MOSFETs, trenches, and switch terminals to minimize or minimize the sum of the on-resistance and connection resistance of one or two power MOSFETs. [New content] [0003] In order to solve the above technical problem, the present invention provides a die which minimizes the on-resistance of the power MOSFET and the resistance of the connecting wire, and a power conversion integrated circuit including the die. In order to solve the above technical problem, the present invention provides a die having a die corner, the die comprising: a high side power MOSFET having a drain and a source; and a first pad and a second pad, the first pad and the second pad are coupled to a drain of the high-side power MOSFET, and a coordinate of the first pad with respect to a die corner is (158. 3 μηη ± d , 2945. 8 μπι ± d), the coordinates of the second pad relative to the corner of the die are (398. 8 μπι soil d, 2959.4 μηη soil d), and the d is not more than 320 μπι. According to an embodiment of the present invention, the die further includes: a low-end power MOS-FET having a drain and a source; and a third pad, a fourth pad, and a fifth solder a third and sixth pads coupled to a source of the high side power MOSFET and a drain of the low side power MOSFET, and coordinates of the third to sixth pads with respect to the die corner (599. 2 μιη ± d, 2810. 2 μπι soil d), (Form No. ΚΠ0ΚΠ Page 5 of 30 M400092 599.2 μπι ± d, 2465.1 μηη ± d), (599.2 μιη ± d '2133.8 μιη ± d) and (599·2 μηη ± d, 1791.5 um ± d) ° According to an embodiment of the present invention, the die further includes: a seventh pad, an eighth pad, a ninth pad, and a tenth pad, The seventh to tenth pads are coupled to the source of the high side power MOSFET and the drain of the low side power MOSFET, and the coordinates of the seventh to tenth pads for the die corner are respectively (379.5 Μιη ± d, 1716.2 μηη ± d) , (179.8 μιη土 d'1716.2 μιη ± d), (417.2 μπι ± d, 1 439. 3 Μπι ± d) and (417.2 μηη± d , 1 083.2 μηι ± d). According to an embodiment of the present invention, the die further includes: a fourteenth pad, a fifteenth pad, a sixteenth pad, a seventeenth pad, an eighteenth pad, and a nineteenth pad. The fourteenth to nineteenth pads are coupled to the source of the low-side power MOSFET, and the coordinates of the fourteenth to nineteenth pads with respect to the die corner are respectively (1466.3 _ ± d, 2815.1 Μπι ± d ), ( 1466.3 μπι ± d, 2469 μιη ± d) , (1466.3 μηι ± d, 2121.9 μηη soil d), (1466.3 μπι ± d, 1 774.8 um ± d) , ( 1466.4 μηη ± d , 1427.7 μηη ± d) and (1466.4 μπι ± d, l〇8〇.6 μιη ± d). According to an embodiment of the present invention, the high-end power M〇SFET has a first corner, a second corner, a third corner, and a fourth corner, and the coordinates of the first to fourth corners relative to the die corner are respectively (33.0 μm ± d, 2894.3 ± d) , ( 525, 3 pm ± d, 2894.3 μπι ± d ), (525. 3 μηι ± d, 1767. 1 μιη ± d) and (33 〇μ ra ± d ' 1767· 1 μηη ± d). According to an embodiment of the present invention, the low end power shame "has a first corner form nickname A0101 page 6 / total 30 pages, second corner, third corner, fourth corner, fifth corner and sixth corner ' The coordinates of the first to sixth corners with respect to the corners of the crystal grains are respectively (. 6 μιη soil d, 3040. ± μηη ± d), (1407. 9 ' 3040. 9 μηι ± d ), (1407. um ± d , 97fi (10) ± d) , ( 479.5 μηη ± d , 976 3 μπ) ± d), ( 479.5 (10) ± d, 1 545'3 _ ± d) and (66i 6 is called ± d '1545.3 μηη ± d). According to an embodiment of the present invention, the low-side power sfet includes a first region MOSFET, a second region MOSFET, and a third region mosfET. According to an embodiment of the present invention, a corner of the first region MOSFET is opposite to a corner of the die corner They are (479 5 μιη ± d, 1545 3叩 ± d), (1407. 9 μηι ± d, 1545. 3 μηι ± d), ( l4 〇 7. 9 μιη ± d, 976. 3 ± d) and 479. 5 ± mm, 6.3 "m ± d), the coordinates of the corner of the second region m〇sfET relative to the grain corner are (661· 6 ± d, 2297. i (four) ± d ), (1407. 9 pm ± d , 2297. 1 _ ± d), (〇7'9 μιη ± d'1557.1 μιη ± d) and (661.6 μπι soil d '1557. 1 μιη soil d); The coordinates of the corner of the third-area MOSFET are relative to the corner of the die (6616 μ [Π ± d, 3040.9 μηη soil d), (1407.9 um ± d, 3040, 9 μηη ± d) ' ( 407.9 μιη土 d'2308.9 μηι ± d) and (661.6 μηη ± d ' 2308. 9 μπι ± d ). According to the embodiment of the present invention, d does not exceed "Ο μιη. According to the embodiment of the present invention, the d does not exceed 8 〇 μιη. The present invention also provides a power conversion integrated circuit, comprising: a die having a die corner, the die comprising: a high-end power M0S-page 7/total 30 page form number Α0101 FET, The high-side power MOSFET has a drain and a source; a first pad and a second pad, the first pad and the second pad being coupled to a drain of the terminal power MOSFET, the The coordinates of a pad relative to the corner of the die are (158.3 μπι soil d'2945.8 μηη ± d), and the coordinates of the second pad relative to the corner of the die are (398 8 um ± d, 29 59. 4 μιη Earth d), wherein d does not exceed 320 um; and a lead frame, the lead frame including a first pin, the first pin being coupled to the first pad and the second pad. According to an embodiment of the present invention, the power conversion integrated circuit further includes: the die further comprising: a low-end power MOSFET having a drain and a source; a third pad, a fourth pad, a fifth pad and a sixth pad, the third to sixth pads being coupled to a source of the high side power MOSFET and a drain of the low side power m〇SFET, the third to sixth The coordinates of the pad relative to the corner of the die are (599 2 pm ± d '2810.2 μηη ± d), ( 599.2 μηι soil d, 2465.1 ± d), ( 599.2 μπι soil d, 2133.8 μιπ soil d) and ( 599.2 (10) d, 1791. 5 ± d); the lead frame further includes a second pin, the second pin being coupled to the third pad, the fourth pad, the fifth pad, and the sixth pad. According to an embodiment of the present invention, the power conversion integrated circuit further includes: the die further includes: a seventh pad, an eighth pad, a ninth pad, and a tenth pad. The disk is connected to the high-end power source and the drain of the low-side power MOSFET, and the coordinates of the seventh to tenth pads with respect to the die corner are respectively (379·5 μ{π±d. U16) .2 um ± d) , (179.8 (10) soil d ' 1716 2 (10) soil (form nickname A0I01 ), (417. 2 μιη土 d ' 1439. 3 soil d) and (417. 2 u Page 8 of 30 Pages ra ~ d , l 〇 83.2 ± d); the lead frame further includes a third pin, and the third bow is connected to the seventh pad, the eighth pad, the ninth pad, and the tenth According to an embodiment of the present disclosure, the power conversion integrated circuit further includes: the b thorium pad, the thirteenth pad, the fifteenth pad, the sixteenth pad, a seventeenth to nineteenth pad and a nineteenth pad, the fourteenth to nineteenth pads being coupled to a source of the low side power MOSFET, the thirteenth to tenth Nine pads relative to the grain turn The coordinates are (1 493. 4 μπι soil d, 2984. 2 μιη ± d), (H66.3 soil d, 2815. i μιη ± d), (1466 3 _ ± d'24 69 (10) ± d), (1466.3 μιη ± d, 2121.9 ± d) , ( 1466. 3 μιπ ± d, 1774. 8 μιη soil d), ( !466.4 μιη ± d . 1427.7 ± d) ^ ( 1466.4 μπ, ± d 'just 0.6 (10) ± The lead frame further includes: a fourth pin, the fourth pin is coupled to the thirteenth pad; and a die attaching disk, wherein the day-to-day grain mounting disk is connected to the first Fourteen pads, fifteenth pads, sixteenth pads, seventeenth pads, eighteenth pads, and nineteenth pads. According to an embodiment of the present invention, the high side power MOSFET has a first corner 'The second corner, the third corner and the fourth corner, the coordinates of the first to fourth corners relative to the grain corner are (33. 0 nm ± d, 2894.3 ± d) ^ (525.3 pm ± d > 2894.3 μπΐ ± d) , (525.3 pm soil d, 1767.1 μηη ± d) and (33.0 μηη ± d, 1 767. 1 μπι ± d).

表單編號A010I 根據本案的實施例,所述低端功率MOSFET具有第一拐角 、第一拐角、第三拐角、第四拐角、第五拐角和第六拐 角所述第一至第六拐角相對於晶粒拐角的座標分別為 第9頁/共30頁 ^ Α0Ι0Ι « „ ....... ‘ (66i.6 um 土 d,3040.9 um ± d) ' ( 1407.9 μιη 士 d’ 3040.9 μιη 士 d) 、 (1407.9 pm ± d,976,3 um ± d) 、 ( 479. 5 um ± d ,976. 3 μιη ± d)、( 479. 5 um ± d,1 545. 3 um ± d)和(661· 6 _ ± d ’ 15 4 5. 3 μ m ± d )。 根據本案的實施例,所述低端MOSFET的包括第一區域 M0SFET、第二區域M0SFET和第三區域M0SFET。 根據本案的實施例,所述第一區域MOSFET的拐角相對於 晶粒拐角的座標為( 479· 5 μιη ± d,1 545. 3 μιη ± d )、(1 407. 9 μπι 土 d , 1 545. 3 μιη ± d)、( 14〇7, 9 μιη ± d,976. 3 μιη ± d)和( 479. 5 土 μιη, 976.3 um ± d);所述第二區域MOSFET的拐角相對於 晶粒拐角的座標為(661. 6 μιη ± d,2297. 1 μιη ± d )、(U07. 9 μιη ± d ,2297. 1 μιη ± d)、( 9 土 d ’ 1 557- 1 μιη ± d)和(661, 6 _ i d ’ 1 557. 1 μιη ± d);所述第三區域MOSFET的拐角相 對於晶粒拐角的座標為(661, 6 μπι ± d,3040.9 μιη 土 d) 、 ( 1407.9 μιη ± d,3040,9 μιη 土 d)、( ^07. 9 μπι ± d ’ 2308. 9 μιη ± d)和(661. 6 μιη 土 d ’ 2308. 9 μιη ± d)。 根據本案的實施例,所述d不超過160 μπι» 根據本案的實施例,所述d不超過8 0 μ m。 本案通過優化功率MOSFET、壕溝和開關端點的尺寸和位 置’使得功率MOSFET的導通電阻和連接導線電阻之和最 小或者接近最小。 表單編號A0101 第10頁/共30頁 M400092 【實施方式】 [0004]在文獻中所述的特定實施例代表本案的示例性實施例, 並且本質上僅為演示而非限制。說明書中&quot;一個實施例&quot; 或者實施例&quot;的引用意味著結合該實施例所描述的特定 特徵,結構或者特性包括在本案的至少一個實施例中。 短語&quot;在一個實施例中”在說明書中各個位置出現並不全 部涉及相同的實施例,也不是相互排除其他實施例或者 可變實施例。 本案的實施例描述了適用於特定封裝類型的直流直流功 率轉換積體電路的布圖,包括功率M〇SFET、壕溝和開關 節點的布圖,並為其他如控制功率MOSFET占空比的電路 留下足夠的空間。針對所考慮的的具體封裝形式,本案 實施例所示的布圖至少接近最佳方案。對於其他輔助性 電路,例如帶隙電路,由於不影響連接導線電阻和 MOSFET的導通電阻,不必詳細描述。 第3圖是根據本案一個實施例的功率轉換積體電路的俯視 圖。第3圖中標號卜23是焊盤。在第3圖所示實施例中, 焊盤22提供了一個信號,用以表明電源是否足夠。在一 些實施例中,可以不使用這個焊盤。在其他的一些實施 例中,焊盤可以有一個或者幾個不使用,無需耦接至其 他引腳。第3圖中標號302、304、306、308、310、312 、314、316和318是引腳。位於底部的引腳318比較大( 它的面積佔據了封裝尺寸非常大的一部分),通常用作 功率地(power ground),可以作為晶粒貼裝盤(a die attach pad )使用,並可以幫助晶粒320散熱。第 3圖未不出覆蓋晶粒320和一部分引腳的頂層封裝。第3圖 表單编號A0101 第1丨頁/共30頁 M400092 所示的實施例可以使用個8引腳小外形積體電路封裝( small outline integrated circuit package, SOIC),該封裝通常被稱為帶裸露焊盤(exposed pad )的S0IC8或S0IC8E 。 對於第3圖’使用晶粒320的左下腳,即標記300的位置, 作為X-Y坐標系統301的原點。功率M0SFET 322是高端 開關,功率M0SFET 324是低端開關。眾所周知,功率 M0SFET 322和324包含了大量並聯的M0SFET。功率M0S-FET 324的周圍是壕溝328。功率M0SFET的周邊,以及 壕溝’ 一般是平行於X軸或Y軸的直線。 第5圖示出一個示例性壕溝的剖面圖,該剖面圖垂直於壕 溝的走向。假如壕溝走向平行於X袖,第5圖所示剖面平 行於Y軸並垂直於X-Y面,其中第5圖所示壕溝的左邊靠近 M0SFET 324。矽襯底402包括p摻雜隔離區403、η摻雜 掩埋層404、η摻雜阱406、高摻雜η區408和高摻雜Ρ區 410 ’其中高摻雜η區408和高摻雜Ρ區410耦接至地412用 以去除(或大幅去除)襯底注入電流。 焊盤1和2分別通過連接導線lb和2b耦接至引腳302,引 腳302耦接至電源電壓VIN。焊盤1的座標為(158.3 μιη ’ 2945· 8 μπι),焊盤2 的座標為( 398. 8 μιη,2959. 4 ura)。開關節點焊盤3、4、5和6 (例如,開關節點114 )’通過連接導線3b ' 4b、5b和6b分別搞接至引腳304 。上述焊盤的座標分別為(599.2 μιη,2810. 2μηι)、 ( 599·2 μιη,2465. l&quot;m) ' ( 599.2 μηι,2133.8μιη )和( 599·2 μιη ’ 1791.5μιη) » 開關節點焊盤7、8、9 和10 ’分別通過連接導線7b、8b、9b和10b耦接至引腳 A0101 第 12 頁/共 30 頁 M400092 306。上述焊盤的座標分別為(379 5㈣,l7i6 2 _ )、(179. 8 μπι ’ 1716. 2 um)、(417. 2 μπι, 1439.3 μιη)和(417·2 μιη,1083.2 μπι) » 焊盤11通過連接導線lib耦接至引腳3〇8,引腳3〇8作為 一個自舉引腳使用。例如,對於一些實施例,可能有一 個電容耦接於開關節點和自舉引腳之間,形成浮動電源 ,用以驅動高端MOSFET 322。焊盤11的座標為(353 8 Μΐη,883.4 μιη)。焊盤12通過連接導線12b耦接至引 腳316 ,引腳316可作為一個雙功能引腳使用,用以使能 (enbale)或者同步(synchronize)直流直流功率轉 換積體電路。舉例來說,有些實施例中,引腳31 6通過一 個100K的電阻耦接至電源VIN,用以自動啟動直流直流功 率轉換積體電路。另外一些實施例中,外部時鐘可通過 引腳31 6改變直流直流功率轉換積體電路的開關頻率。 焊盤 12 的座標為(96.5 μιη,229. 8μπι )。 焊盤13通過連接導線13b耦接至引腳310。引腳310耦接 至模擬地(analog ground)。焊盤 14、15 ' 16、17、 18和19分別通過連接導線14b、15b、16b、17b、18b和 19b耦接至引腳318。焊盤13~ 19的座標分別是(1493. 4 μηι ’ 2984.2μιη)、( 1466.3 μιη,2815.Ιμιη)、( 1466.3 μιη’2469μιη)、( 1 466.3 jjm,2121.9pm) 、(1466.3 μπι,1774·8μπι)、(1466.4 μπι, 1427.7μπι)和(1466.4 μιη,1080.6 μπι)。 焊盤20和21分別通過連接導線20b和2 lb耦接至引腳312 。引腳312耦接至偏置電壓VCC。焊盤20和21的座標分別 為(1456·7μπι,757.6μπι)和(1477·8 μπι,595.7μπι 表單編號Α0101 第丨3頁/共30頁 焊盤23耦接至引腳314,引腳314用作回饋電壓(例如’ 節點103的電壓)引腳。焊盤23的座標為(1473.5 μιη, 95. 3 Mm)。對於一些實施例,回饋電壓可能由耦接於輸 出電壓和地之間的外部電阻網路產生,並提供給引腳314 〇 為了說明方便,未示出以下耦接關係:焊盤丨和2耦接至 高端MOSFET 322的漏極,開關節點焊盤34 〇柄接至高端 MOSFET 322的源極和低端MOSFET 324的漏極,功率地 焊盤14~19耦接至低端MOSFET 324的源極。 高端MOSFET 322的四個拐角的座標分別為(33.〇 μΙΠ, 2894.3μπι) &gt; ( 525.3 pm * 2894. 3μπι) ' ( 525.3 μ m,1767. lMm)和(33. 0 μιη,1767. Ιμηι)。低端M0S-FET 324的拐角的座標分別為(661.6 μιη,3040.9 μπι )、( 1407.9 μπι’3040.9μιη)、( 1407.9 μιη, 976. 3μπι)、( 479.5 μπι,976.3&quot;m)、( 479.5 μπι, 1 545. 3μιη)和(661. 6 μιη,1 545· 3μπ〇。 對於一些實施例,焊盤的高度和寬度為11〇. 〇 μιπ,壕溝 的寬度為24 μιη。對於一些實施例,一個不包括劃片槽( scribeline)的晶粒的寬度為1 570 μπι,高度為3070 μ ra。對於一些實施例,拐角300和332之間的偏移可能有土 20密爾(mils,1 mil等於25.4 μπι)。對於一些實施 例,連接導線的直徑大約為1, 5密爾。 對於第3圖所示的實施例,功率MOSFET 324可以分為三 個區域,每個區域均由大量的MOSFET並聯組成,如第4圖 所示。這三個區域MOSFET的源端和漏端並聯,柵極由不 表箪碥號A0101 第丨4頁/共30頁 M400092 同的驅動電路驅動。比如,第一區域的拐角的座標分別 為(479.5 μιη,1545.3 μιη)、(1407.9 μιη, 1545.3 jjm)、(1407.9 μπι’ 976.3 μιη)和( 479.5 μιη’976.3 μιη);第二區域MOSFET的拐角的座 標分別為(661.6 μπι,2297.1 μπι)、(1407.9 μηι, 2297. 1 μιη) ' (1407.9 μιη,1557. 1 μπι)和( 661. 6 μιη,1 557. 1 μπι);第三區域M0SFET的拐角的座 標分別為(661.6 μπι,3040.9 μιη)、(1407.9 μιη, 3040.9 μιη)、(1407·9 μπι,2308.9 μπι)和( 661. 6 pm,2308. 9 μιη) » 在實踐中,並非所有實施例的焊盤和拐角的座標均與第3 圖中指述的實施例相同《焊盤或拐角座標的X值或者γ值 可在上述值的320 μιη以内變動。顯然,焊盤不能太接近 M0SFET ’也不能太接近晶粒的邊緣。晶粒32〇的晶粒拐 角(die corner) 300 和封裝拐角(package corner)332之間的偏移也可以在上述值之間變動。在一 些實施例中,焊盤或拐角座標的X值或者γ值可在上述值 的160 μιη或80pm以内變動。例如,假定將座標(479.5 μπι, 1545.3 μιη)變動 160 μπι,可以將χ座標在(479. 5 μπι ± 160 μπι ’1545. 3 μπι)範圍内變動,也可以將γ座 標在( 479.5 um,1545.3 μιη ± 160 μιη)範圍内變動 ’還可以同時將X座標和γ座標在(479 5 μπ] 土 16〇㈣ ,1545.3 μιη ± 160 μιη)範圍内變動。 上述各實施例的焊盤和拐角的座標在上述說明的各個偏 移量範圍内,本領域的技術人員可以根據本案的說明, 選取本說明書中未寫明的具體數值,同樣可以達到本案 表單編號Α0101 第頁/共30頁 M400092 的技術效果。 各座標的偏移量中,取偏移範圍最大為32〇υπι時,座標的 偏移量可以是0-320μπι之間以ΙΟμπι或5μπι遞增的偏移量, 如可以取偏移值為320μπι、310μιη、300μπι等等,也可以 取320μπι、315μπι、310μιη、305μιη等等。同樣,取偏移 範圍最大為160μηι或80μιη時,也可以以ΙΟμιη或5_遞增 獲取具體的座標值。 逋過選取不同的偏移 得到其他不同的實施例。選取偏移量時,所獲得的具體 座標值顯然不能為負值,如第丨圖中焊盤丨的原座標為為 G58· 3 μιη,2945- 8 um),則在通過選取負值偏移量 得到另一實施例時,偏移量的絕對值不應該大於158 3 ^ m而使新實施例的焊盤丨的座標出現負值。 需要聲明的是’上述發明内容及具體實施方式意在證明 本發明所提供技術方_實際應用,不聽釋為對本發 月保。蔓把圍的限^。本領域技術人員在本發明的精神和 原理内,當可作各種修改 '㈣祕、或改^本發明 的保護範圍以所附申請專利範圍書為準。 說月曰中公開的所有特徵,或公開的所有方法或過程 的步驟’除了互相排斥的特徵和/或步驟以外,均可以 以任何方式組合。 本說明書(包含任何 中公開的任-翻,圍、摘要和附圖) 星有 · ! ’除非特別敘述,均可被其他等效或 已 表單編號A0101 ,每個特徵。是^換°即’除非特別敛述 已。疋—系列等效或類似特徵中的一個例子而 第丨6頁/共30頁 M400092 本發明並不局限於前述的具體實施方式。本發明擴展到 任何在本說明書中披露的新特徵或任何新的組合,以及 披露的任一新的方法或過程的步驟或任何新的組合。 【圖式簡單說明】 [0005] 第1圖示出一個使用現有技術的直流直流功率轉換積體電 路。 第2圖示出一個使用現有技術的直流直流功率轉換積體電 路,同時示出了低端功率MOSFET的寄生NPN。 第3圖是根據本案一個實施例的功率轉換積體電路的俯視 圖。 第4圖是根據本案另一個實施例的功率轉換積體電路的俯 視圖。 第5圖示出一個使用現有技術的壕溝的剖面圖。 【主要元件符號說明】 [0006] 1 〜23 :焊盤 lb〜23b :連接導線 102 :負載 103 :輸出節點 104 :控制器 106 :高端開關 108 :低端開關 110 :電感 114 :開關節點Form No. A010I According to an embodiment of the present invention, the low-end power MOSFET has a first corner, a first corner, a third corner, a fourth corner, a fifth corner, and a sixth corner. The first to sixth corners are opposite to the crystal The coordinates of the grain corners are page 9/total 30 pages ^ Α0Ι0Ι « „ ....... ' (66i.6 um soil d, 3040.9 um ± d) ' ( 1407.9 μιη士d' 3040.9 μιη士d) , (1407.9 pm ± d, 976, 3 um ± d), (479. 5 um ± d , 976. 3 μιη ± d), (479. 5 um ± d, 1 545. 3 um ± d) and (661 6 _ ± d ' 15 4 5. 3 μ m ± d ) According to an embodiment of the present invention, the low-side MOSFET includes a first region MOSFET, a second region MOSFET, and a third region MOSFET. According to an embodiment of the present invention The coordinates of the corner of the first region MOSFET with respect to the corner of the die are (479. 5 μιη ± d, 1 545. 3 μιη ± d ), (1 407. 9 μπι soil d, 1 545. 3 μιη ± d ), (14〇7, 9 μιη ± d, 976. 3 μιη ± d) and (479. 5 soil μηη, 976.3 um ± d); the corner of the second region MOSFET is relative to the grain corner The coordinates are (661. 6 μιη ± d, 2297. 1 μιη ± d ), (U07. 9 μιη ± d , 2297. 1 μιη ± d), (9 soil d ' 1 557- 1 μιη ± d) and (661 , 6 _ id ' 1 557. 1 μιη ± d); the coordinates of the corner of the third region MOSFET with respect to the corner of the die are (661, 6 μπι ± d, 3040.9 μηη soil d), (1407.9 μηη ± d, 3040, 9 μιη soil d), ( ^07. 9 μπι ± d ' 2308. 9 μιη ± d) and (661. 6 μιη soil d ' 2308. 9 μιη ± d). According to an embodiment of the present invention, the d Not more than 160 μπι» According to the embodiment of the present invention, the d does not exceed 80 μm. This case minimizes the sum of the on-resistance of the power MOSFET and the resistance of the connecting wire by optimizing the size and position of the power MOSFET, trench and switch terminals. Or, it is close to the minimum. Form No. A0101 Page 10 of 30 M400092 [Embodiment] The specific embodiments described in the literature represent exemplary embodiments of the present invention and are merely illustrative and not limiting. A reference to &quot;an embodiment&quot; or an embodiment&quot; in the specification means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrases &quot;in one embodiment&quot; are in the <RTI ID=0.0> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Layout of DC-DC power conversion integrated circuits, including layout of power M〇SFETs, trenches, and switching nodes, and leaving enough space for other circuits such as controlling the duty cycle of the power MOSFET. For the specific package under consideration Form, the layout shown in the embodiment of the present case is at least close to the optimal solution. For other auxiliary circuits, such as the bandgap circuit, since it does not affect the connection wire resistance and the on-resistance of the MOSFET, it is not necessary to describe in detail. Figure 3 is a case according to the present case. A top view of the power conversion integrated circuit of the embodiment. Reference numeral 23 in Fig. 3 is a pad. In the embodiment shown in Fig. 3, the pad 22 provides a signal indicating whether the power supply is sufficient. In some implementations In this case, the pad may not be used. In other embodiments, the pad may have one or several unused, no coupling To other pins, the numbers 302, 304, 306, 308, 310, 312, 314, 316, and 318 in Figure 3 are pins. The pin 318 at the bottom is relatively large (its area occupies a very large package size) Part of it, usually used as a power ground, can be used as a die attach pad and can help the die 320 to dissipate heat. Figure 3 shows the coverage of the die 320 and a portion of the pins. The top-level package. Figure 3, Form No. A0101, Page 1 of 30, M400092 The embodiment shown can use an 8-lead small outline integrated circuit package (SOIC), which is usually It is called S0IC8 or S0IC8E with an exposed pad. For the third figure 'use the left lower leg of the die 320, that is, the position of the mark 300, as the origin of the XY coordinate system 301. The power MOSFET 322 is a high-side switch The power MOSFET 324 is a low side switch. As is well known, the power MOSFETs 322 and 324 comprise a large number of MOSFETs connected in parallel. The power MOSFET 324 is surrounded by a trench 328. The periphery of the power MOSFET and the trench 'are generally parallel to the X axis A straight line of the Y-axis. Figure 5 shows a cross-sectional view of an exemplary sulcus perpendicular to the sulcus. If the sulcus is parallel to the X-sleeve, the section shown in Figure 5 is parallel to the Y-axis and perpendicular to the XY plane. The left side of the trench shown in Fig. 5 is adjacent to the MOSFET 324. The germanium substrate 402 includes a p-doped isolation region 403, an n-doped buried layer 404, an n-doped well 406, a highly doped n region 408, and a highly doped germanium. Region 410' wherein high doped n region 408 and highly doped germanium region 410 are coupled to ground 412 for removing (or substantially removing) substrate implant current. Pads 1 and 2 are coupled to pin 302 via connection leads lb and 2b, respectively, and pin 302 is coupled to supply voltage VIN. The coordinates of pad 1 are (158.3 μηη ' 2945· 8 μπι), and the coordinates of pad 2 are (398. 8 μιη, 2959. 4 ura). Switch node pads 3, 4, 5, and 6 (e.g., switch node 114)' are coupled to pin 304 by connecting wires 3b' 4b, 5b, and 6b, respectively. The coordinates of the above pads are (599.2 μιη, 2810. 2μηι), (599·2 μηη, 2465. l&quot;m) ' ( 599.2 μηι, 2133.8μιη ) and ( 599·2 μιη ' 1791.5μιη) » Switch node soldering The disks 7, 8, 9, and 10' are coupled to pins A0101, page 12, and page 30, M400092 306, respectively, via connecting wires 7b, 8b, 9b, and 10b. The coordinates of the above pads are (379 5 (four), l7i6 2 _ ), (179. 8 μπι '1716. 2 um), (417. 2 μπι, 1439.3 μιη) and (417·2 μηη, 1083.2 μπι) » pads 11 is connected to pin 3〇8 through the connection wire lib, and pin 3〇8 is used as a bootstrap pin. For example, for some embodiments, there may be a capacitor coupled between the switch node and the bootstrap pin to form a floating power supply for driving the high side MOSFET 322. The coordinates of the pad 11 are (353 8 Μΐη, 883.4 μηη). Pad 12 is coupled to pin 316 via a connection lead 12b which can be used as a dual function pin to enable or synchronize the DC/DC power conversion integrated circuit. For example, in some embodiments, pin 31 6 is coupled to power supply VIN through a 100K resistor to automatically initiate a DC-DC power conversion integrated circuit. In other embodiments, the external clock can change the switching frequency of the DC-DC power conversion integrated circuit through pin 31 6 . The coordinates of the pad 12 are (96.5 μιη, 229. 8 μπι). The pad 13 is coupled to the pin 310 through a connection wire 13b. Pin 310 is coupled to an analog ground. The pads 14, 15' 16, 17, 18, and 19 are coupled to the leads 318 by connecting wires 14b, 15b, 16b, 17b, 18b, and 19b, respectively. The coordinates of pads 13 to 19 are (1493. 4 μηι '2984.2μιη), (1466.3 μηη, 2815.Ιμιη), (1466.3 μιη '2469μιη), (1 466.3 jjm, 2121.9pm), (1466.3 μπι, 1774·). 8μπι), (1466.4 μπι, 1427.7μπι) and (1466.4 μηη, 1080.6 μπι). Pads 20 and 21 are coupled to pin 312 by connecting wires 20b and 2 lb, respectively. Pin 312 is coupled to a bias voltage VCC. The coordinates of pads 20 and 21 are (1456·7μπι, 757.6μπι) and (1477·8 μπι, 595.7μπι form number Α0101, page 3/total 30 pages of pad 23 coupled to pin 314, pin 314 Used as a feedback voltage (eg, voltage at node 103). The coordinates of pad 23 are (1473.5 μηη, 95.3 Mm). For some embodiments, the feedback voltage may be coupled between the output voltage and ground. An external resistor network is generated and provided to pin 314. For ease of illustration, the following coupling relationship is not shown: pads 丨 and 2 are coupled to the drain of high side MOSFET 322, and switch node pad 34 is connected to the high side. The source of the MOSFET 322 and the drain of the low side MOSFET 324, the power ground pads 14-19 are coupled to the source of the low side MOSFET 324. The coordinates of the four corners of the high side MOSFET 322 are respectively (33. 〇μΙΠ, 2894.3 Μπι) &gt; ( 525.3 pm * 2894. 3μπι) ' ( 525.3 μ m, 1767. lMm) and (33. 0 μιη, 1767. Ιμηι). The coordinates of the corners of the low-end M0S-FET 324 are (661.6 μιη, respectively). 3040.9 μπι ), (1407.9 μπι '3040.9μιη), (1407.9 μιη, 976. 3 Πι), (479.5 μπι, 976.3 &quot; m), (479.5 μπι, 1 545. 3 μιη) and (661. 6 μιη, 1 545·3 μπ〇. For some embodiments, the height and width of the pad are 11 〇. 〇μιπ, the width of the trench is 24 μηη. For some embodiments, a die that does not include a scribeline has a width of 1 570 μm and a height of 3070 μ ra. For some embodiments, corners 300 and 332 The offset may be 20 mils (mils, 1 mil equals 25.4 μm). For some embodiments, the diameter of the connecting wires is approximately 1,5 mils. For the embodiment shown in Figure 3, the power MOSFET 324 It can be divided into three regions, each of which is composed of a large number of MOSFETs in parallel, as shown in Fig. 4. The source and drain terminals of the three regions of the MOSFET are connected in parallel, and the gate is not represented by the nickname A0101. Page / Total 30 pages M400092 Drive with the same drive circuit. For example, the coordinates of the corners of the first area are (479.5 μηη, 1545.3 μηη), (1407.9 μηη, 1545.3 jjm), (1407.9 μπι' 976.3 μιη) and (479.5 μιη) '976.3 μιη); second zone The coordinates of the corners of the domain MOSFET are (661.6 μπι, 2297.1 μπι), (1407.9 μηι, 2297. 1 μιη) ' (1407.9 μιη, 1557. 1 μπι) and (661. 6 μιη, 1 557. 1 μπι); The coordinates of the corners of the three-region MOSFET are (661.6 μπι, 3040.9 μηη), (1407.9 μηη, 3040.9 μιη), (1407·9 μπι, 2308.9 μπι), and (661. 6 pm, 2308. 9 μιη) » In practice Not all of the pad and corner coordinates of the embodiment are the same as the embodiment described in FIG. 3. The X value or the γ value of the pad or corner coordinate may vary within 320 μm of the above value. Obviously, the pad should not be too close to the M0SFET' and should not be too close to the edge of the die. The offset between the die corners 300 of the die 32 turns and the package corner 332 can also vary between the above values. In some embodiments, the X or gamma value of the pad or corner coordinates may vary within 160 μηη or 80 pm of the above values. For example, assuming that the coordinates (479.5 μπι, 1545.3 μηη) are changed by 160 μπι, the χ coordinates can be changed within the range of (479. 5 μπι ± 160 μπι '1545. 3 μπι), or the γ coordinates can be placed at (479.5 um, 1545.3). The variation in the range of μιη ± 160 μιη) can also vary the X coordinate and the γ coordinate in the range of (479 5 μπ] soil 16〇 (4), 1545.3 μηη ± 160 μιη). The coordinates of the pads and the corners of the above embodiments are within the respective offset ranges described above, and those skilled in the art can select specific values not specified in the present specification according to the description of the present case, and can also reach the form number of the present case. Α0101 Page / Total 30 pages of technical effects of M400092. In the offset of each coordinate, when the offset range is up to 32〇υπι, the offset of the coordinates may be an offset of ΙΟμπι or 5μπι between 0-320μπι, for example, the offset value may be 320μπι, 310 μm, 300 μm, etc., may also take 320 μm, 315 μm, 310 μm, 305 μm, and the like. Similarly, when the offset range is at most 160μηι or 80μιη, the specific coordinate value can also be obtained in increments of ΙΟμιη or 5_. Other different embodiments are obtained by choosing different offsets. When the offset is selected, the specific coordinate value obtained can obviously not be negative. For example, if the original coordinate of the pad 丨 in the figure is G58·3 μιη, 2945-8 um), the negative offset is selected. When another embodiment is obtained, the absolute value of the offset should not be greater than 158 3 ^ m and the coordinates of the pad 新 of the new embodiment are negative. It is to be noted that the above-mentioned summary of the invention and the specific embodiments are intended to prove that the technical means provided by the present invention is practically applied and is not to be interpreted as a warranty. The limit of the vines is limited. Those skilled in the art will be able to make various modifications within the spirit and scope of the present invention, and the scope of protection of the present invention is subject to the scope of the appended claims. All of the features disclosed in the semester, or the steps of all methods or processes disclosed may be combined in any manner other than mutually exclusive features and/or steps. This specification (including any of the disclosures, disclosures, summaries, and drawings disclosed in the text) has a star! 'Unless specifically stated, it can be equivalent to other or has been form number A0101, each feature. Yes ^ change ° ie ' unless specifically mentioned. An example of a series-equivalent or similar feature is described. Page 6 of 30 M400092 The present invention is not limited to the specific embodiments described above. The invention extends to any new feature or any new combination disclosed in this specification, as well as any novel method or process steps or any new combination disclosed. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Fig. 1 shows a DC-DC power conversion integrated circuit using the prior art. Figure 2 shows a DC-DC power conversion integrated circuit using the prior art while showing the parasitic NPN of the low-side power MOSFET. Figure 3 is a plan view of a power conversion integrated circuit in accordance with one embodiment of the present invention. Figure 4 is a top plan view of a power conversion integrated circuit in accordance with another embodiment of the present invention. Figure 5 shows a cross-sectional view of a trench using the prior art. [Main component symbol description] [0006] 1 to 23: Pad lb~23b: Connection wire 102: Load 103: Output node 104: Controller 106: High-side switch 108: Low-side switch 110: Inductor 114: Switch node

202、204、322、324 :功率MOSFET 206 :寄生NPN 表單編號A0101 第17頁/共30頁 M400092 208 ' 210 ··邏輯門 30 0 ‘·晶粒拐角,X-Y坐標系統原點 301 : X-Υ坐標系統 302、304、30 6、308、310、312、314、316:引腳 318 :晶粒貼裝盤 320 :晶粒 328 :壕溝 332 :引線框柺角 402 :矽襯底 403 : ρ摻雜隔離區 404 : η換雜掩埋層 406 : η摻雜阱 4 0 8 .南推雜π區 410 :高摻雜Ρ區 41 2 :地 表單編號Α0101 第丨8頁/共30頁202, 204, 322, 324: Power MOSFET 206: Parasitic NPN Form No. A0101 Page 17 of 30 M400092 208 '210 · Logic Gate 30 0 '·Chip Corner, XY Coordinate System Origin 301: X-Υ Coordinate system 302, 304, 30 6, 308, 310, 312, 314, 316: Pin 318: die attach pad 320: die 328: trench 332: leadframe corner 402: germanium substrate 403: p-doped Miscellaneous isolation region 404: η-mutated buried layer 406: η-doped well 4 0 8 . South-doped π-region 410 : highly doped germanium region 41 2 : ground form number Α 0101 丨 8 pages / total 30 pages

Claims (1)

M400092 六、申請專利範圍: 1 一晶粒,有一晶粒拐角’所述晶粒包括. 一高端功率MOSFET,所述高端功率MOSFET具有一漏極和 一源極;以及 第一焊盤和第二焊盤,所述第一焊盤和第二焊盤耦接至所 述高端功率MOSFET的漏極,所述第一焊盤相對於晶粒拐 角的的座標為(158.3 μπι ± d,2945.8 μιπ 土 d) ’ 所 述第二焊盤相對於晶粒拐角的的座標為( 398.8 μπι ± d ,2959.4 μπι ± d),其中 d 小於或等於 320 μιπ。 2 .如申請專利範圍第1項所述之晶粒,其特徵在於,還包括 一低端功率MOSFET,所述低端功率MOSFET具有一漏極和 一源極;以及 第三焊盤、第四焊盤、第五焊盤和第六焊盤,所述第三至 第六焊盤耦接至高端功率MOSFET的源極和低端功率 MOSFET的漏極,所述第三至第六焊盤相對於晶粒拐角的 座標分別為(599·2 μιη ± d,2810.2 μπι 土 d)、( 5 9 9 · 2 μ m ± d ,2 4 6 5. 1 μ m ± d ) 、 ( 5 9 9 · 2 μ m 土 d ,2133.8 μπι ± d)和(599.2 μπι ± d,1791.5 μπι ± d) ο 3 .如申請專利範圍第2項所述之晶粒,其特徵在於,還包括 第七焊盤、第八焊盤、第九焊盤和第十焊盤,所述第七至 第十焊盤耦接至所述高端功率MOSFET的源極和所述低端 功率MOSFET的漏極,所述第七至第十焊盤對於晶粒拐角 099212539 表單編號A0101 第19頁/共30頁 0993388900-0 的座標分別為( 379.5 ± 179 « 16*2 Mm ± d) ^ ( 79』Mm ± d’ 1716·2 ⑽ ,14〇〇 Q (417.2 Mm ± d 1083.2 μη &quot;39.3 μ„ ± d)和(417.2 ⑽ + d ± d) 〇 如 申請專利細第3賴述H其特徵在於, 還包括 W第十五焊盤、第十六焊盤、第十七焊盤、第 =盤和第十九焊盤,所述第切至第十九焊餘接至 所述低端功率贿ΕΤ的源極,所述第十四至第十九焊盤 相對於晶粒拐角的座標分別為( 1466.3⑽± d, 2 815 · 1 μ m ± d )、( 14 ft fi q U4b6.3 ⑽ ± d,2469 叩 ± d 、(1··3 _ d,2m 9 “…)、⑴6&quot; ⑽ 土 d,1 774.8 ㈣-+ d) 、(M66.4 μπι + d, W7.hm±db( 1466 4 um±d,i〇8〇6_± d ) 〇 .如申請專利第4項所述之晶粒,其特徵在於,所述高 端功帷sm具有第-拐角、第二拐角、第三拐角和第 四招角,所述第一至第四招角相對於晶救招角的座標分別 為(33.(^m±d,2894.3 _±d)、( 525 3 叫 + d,2_.“m±d)、(525.3 Mm±d,i 767 i^ ± d)和(33. 0 ⑽ ± d,i 767 】⑽ ± ㈧。 如申請專利範園第5項所述之晶粒,其特徵在於,所述低 端功率MOSFET具有第一拐角、第二拐角第三拐 四拐角、第五拐角和第六拐角’所述第—至第六拐角相對 於晶粒拐㈣座標分別為(661 6⑽± d,30復9㈣ 0992η;539 表單編號A0101 ± d) &gt; ( 1407.9 μηι ± d, 3040.9 pm ± d),( 0993388900-0 第20頁/共30頁 !4〇7.9 μηι ± d,976.3 &quot;m ± d) 、 (479.5 μιη ± d ’ 976. 3 μιη ± d) 、 (479. 5 μΐϋ ± d,1545. 3 μιη 士 d)和(661. 6 μπι 土 d ’ 1545. 3 μπι ± d)。 7 .如申請專利範圍第6項所述之晶粒,其特徵在於,所述低 端功率MOSFET包括第一區域M0SFET、第二區域M〇SFET和 第三區域MOSFET。 8 .如申請專利範圍第7項所述之晶粒,其特徵在於,所述第 . —區域M0SFET的拐角相對於晶粒拐角的座標分別為( % 479*5 ym±d,1545.3 PDi±d)、(1407.9|Llm:!:d ,1545. 3 μιη ± d) ' ( M07. 9 um ± d ,976· 3 土 d)和(479.5 土 μιη’976.3 μπι ± d);所述第二區 域MOSFET的拐角相對於晶杻拐角的座標為(6616 ^ + d ’ 2297. 1 μιη ± d) 、 ( 140 7. 9 μιη 土 d ,2297 1 , Μ m ± d) 、 ( 1407. 9 um ± d,1557. 1 um ± d)和( 661.6 um 士 d,1557.1 _ ± d);所述第三區域 MOSFET的拐角相對於晶粒拐角的座標為(661.6 Mm + d _ ’3040.9 μπι± d) 、(1407,9 μιη ± d,3040.9 ⑽ ' 土 d) 、 ( 140 7. 9 μιη ± d,2308· 9 μιη ± d)和( 661.6 μπι土 d’2308.9 |im ± d)。 9 ‘如申請專利範圍第1項至第8項中任一項所述之晶粒,其特 徵在於,所述d不超過160 μιη。 10 ·如申請專利範圍第1項至第8項中任一項所述之晶粒,其特 徵在於,所述d不超過80 Mm。 11 . 一功率轉換積體電路,包括: 一晶粒,所述晶粒有一晶敕拐角 所述晶粒包括:一高端 099212539 功率MOSFET,所述高端功率MOSFET具有一漏極和—源極 表單編號A0101 第21頁/共30頁 0993388900-0 M400092 ;第一焊盤和第二焊盤,所述第一焊盤和第二焊盤耦接至 所述馬端功率MOSFET的漏極,所述第一焊盤相對晶粒拐 角的的座標為(158.3 μπι ± d,2945.8 μπι ± d),所 述第二焊盤相對於晶粒拐角的的座標為(398·8 ± d ,2959. 4 μιη ± d) ’ 其中d不超過320 μπι;以及 一引線框,所述引線框包括第一引腳,所述第一引腳耦接 至第一焊盤和第二焊盤。 12 . 如申請專利範圍第11項所述之功率轉換積體電路,其特徵 在於,還包括: 所述晶粒還包括:一低端功率MOSFET,所述低端功率 MOSFET具有一漏極和一源極;第三焊盤、第四焊盤、第 五焊盤和第六焊盤,所述第三至第六焊盤耦接至高端功率 MOSFET的源極和低端功率MOSFET的漏極,所述第三至第 六焊盤相對於晶粒拐角的座標分別為(599 2 μπι ± d, 2810. 2 μπι ± d)、( 599. 2 _± d,2465. 1 μιη ± d )、(599.2 μπι 土 d,2133.8 μπι ± d)和(599.2 μ m 土 d’ 1791.5 μπι ±d); 所述引線框還包括第二引聊,所述第二引腳叙接至第三焊 盤、第四焊盤、第五焊盤和第六焊盤。 13 如申請專利範圍第12項所述之功率轉換積體電路’其特徵 在於,還包括: 所述晶粒還包括:第七焊盤、第八焊盤、第九焊盤和第十 焊盤,所述第七至第十焊盤耦接至所述高端功率m〇sfet 源極和所述低端功率MOSFET的漏極,所述第七至第十焊 盤相對於晶粒拐角的座標分別為(379 5 μιη ± d, 1716, 2 μπι ± d) 、( 179. 8 μιη± d,1716. 2 _ ± d 09921^539 0993388900-0 表單編號A0101 第22頁/共30頁 M400092 )、(417.2 μπι± d,1439.3 um ± d)和(417.2 pm ± d ,1083. 2 μιη ± d); 所述引線框還包括第三引腳,所述第三引腳柄接至第七焊 盤、第八焊盤、第九焊盤和第十焊盤。 14 ·如申請專利範圍第13項所述之功率轉換積體電路,其特徵 在於,還包括: 所述晶粒包括:第十三焊盤 '第十四焊盤、第十五焊盤、 第十六焊盤、第十七焊盤、第十八焊盤和第十九焊盤,所 述第十四至第十九焊盤耦接至所述低端功率M0SFET的源 極’所述第十三至第十九焊盤相對於晶粒拐角的座標分別 為(1493.4 μιη ± d,2984.2 μιη ± d) 、 (1466·3 μ m ± d’ 2815.1 μιη ± d) 、 (1466.3 μιη ± d,2469 Mm ± d) 、 ( 1466-3 Mm 土 d,2121.9 ym ± d)、( 1 46 6. 3 pm ± d ,1774· 8 μπι ± d) 、 ( 1466. 4 &quot;m 土 d’ 1427.7 μπι ± d)和(1466.4 μπι ± d,1080.6 μ m ± d); 所述引線框還包括:第四引腳,所述第四引腳耦接至第十 三焊盤;以及一晶粒貼裝盤,所述晶粒貼裝盤耦接至第十 四焊盤、第十五焊盤、第十六焊盤、第十七焊盤、第十八 焊盤和第十九焊盤。 15 .如申請專利範圍第14項所述之功率轉換積體電路,其特徵 在於,所述高端功率M0SFET具有第一拐角、第二拐角、 第三拐角和第四拐角,所述第一至第四拐角相對於晶粒拐 角的座標分別為(33.0 μιη 土 d,2894.3 μιη 士 d)、 ( 525.3 μπι± d ,2894. 3 μπι ± d) 、 ( 525.3 μιη 土 d,1767. 1 Mm ± d )和(33. 0 μπι ± d,1767. l μπι 099212539 表單編號A0101 0993388900-0 第23頁/共30頁 财00092 ± d ) ° 16 .如申請專利範圍第1 5項所述之功率轉換積體電路,其特徵 在於’所述低端功率M0SFET具有第一拐角、第二拐角、 第二拐角、第四拐角、第五拐角和第六拐角,所述第一至 第六拐角相對於晶粒拐角的座標分別為(661.6 μ® ± d ,3040.9 μπι 士 d) 、(1407.9 μιη 土 d,3040.9 um 土 d) 、 ( 1407· 9 μιη ± d ,976. 3 nm 土 d)、( 479.5 μιη ± d’976.3 ± d) 、 ( 479.5 μιη 土 d ’ 1545. 3 μηι ± d )和(661. 6 μιη ± d,1545. 3 μιη 土 d)。 籲 17 .如申請專利範圍第16項所述之功率轉換積體電路,其特徵 在於,所述低端MOSFET的包括第一區域MOSFET、第二區 域MOSFET和第三區域MOSFET。 18 .如申請專利範圍第17項所述之功率轉換積體電路,其特徵 在於,所述第一區域MOSFET的拐角相對於晶粒拐角的座 標為(479.5 μπι ± d,1545.3 μηι ± d) 、(1407.9 Mm ± d,1545· 3 μπι ± d) ' ( 1407· 9 μιη ± d, 976. 3 μπι ± d)和( 479. 5 土 μπι,976. 3 μιη ± d);-修 所述第一區域MOSFET的拐角相對於晶粒拐角的座標為( 661. 6 μιη ± d &gt; 2297. 1 Mm + d) % (Η〇7. 9 μπι ± d’2297. 1 μπι ± d)、(1407.9 μπι ± d,1557. 1 &quot; m 土 d)和(661.6 μιη 土 d,1 557. 1 μπι ± d);所述 第三區域’ΡΈΤ的拐角相對於晶粒拐角的座標為( 661. 6 μιη ± d ’ 3040. 9 μιη;!: d)、(14〇7· 9 μπ] 土 ,3040.9 pm ± d)、( 1407 9 ㈣ ± d,23〇8 9 丨 U992iZb39 ± d)和(661. 6 pm土 d,2308. 9 μπι ± d)。 0993388900-0 表軍編號A0101 第24頁/共貞 M400092 19 .如申請專利範圍第11項至第18項中任一項所述之功率轉 換積體電路,其特徵在於,所述d不超過160 μιη。 20 .如申請專利範圍第11項至第18項中任一項所述之功率轉 換積體電路,其特徵在於,所述d不超過80 μιη。 0993388900-0 099212539 表單編號Α0101 第25頁/共30頁M400092 VI. Patent application scope: 1 a die having a die corner. The die includes: a high side power MOSFET having a drain and a source; and a first pad and a second a pad, the first pad and the second pad are coupled to a drain of the high-side power MOSFET, and a coordinate of the first pad relative to a die corner is (158.3 μπι ± d, 2945.8 μππ d) 'The coordinates of the second pad relative to the die corner are (398.8 μπι ± d, 2959.4 μπι ± d), where d is less than or equal to 320 μππ. 2. The die of claim 1, further comprising a low-side power MOSFET having a drain and a source; and a third pad, a fourth a pad, a fifth pad, and a sixth pad, the third to sixth pads being coupled to a source of the high side power MOSFET and a drain of the low side power MOSFET, the third to sixth pads being opposite The coordinates at the corners of the grains are (599·2 μηη ± d, 2810.2 μπι soil d), (5 9 9 · 2 μ m ± d , 2 4 6 5. 1 μ m ± d ), ( 5 9 9 · 2 μ m 地面 d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d An eighth pad, a ninth pad, and a tenth pad, the seventh to tenth pads being coupled to a source of the high side power MOSFET and a drain of the low side power MOSFET, the seventh To the tenth pad for the die corner 099212539 Form No. A0101 Page 19 / Total 30 page 0993388900-0 The coordinates are (379.5 ± 179 « 16*2 Mm ± d ) ^ ( 79 )Mm ± d' 1716·2 (10) , 14〇〇Q (417.2 Mm ± d 1083.2 μη &quot;39.3 μ„ ± d) and (417.2 (10) + d ± d) The H is characterized in that it further includes a fifteenth pad, a sixteenth pad, a seventeenth pad, a fifth disk, and a nineteenth pad, and the first to the nineteenth solder joints are connected to the The source of the low-end power bribe, the coordinates of the fourteenth to nineteenth pads relative to the die corner are (1466.3(10)±d, 2 815 · 1 μm ± d ), ( 14 ft fi q U4b6.3 (10) ± d,2469 叩± d , (1··3 _ d,2m 9 “...), (1)6&quot; (10) Soil d,1 774.8 (four)-+ d) , (M66.4 μπι + d, W7 ??? </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; a corner, a third corner, and a fourth angle, the coordinates of the first to fourth angles relative to the crystal rescue angle are (33.(^m±d, 2894.3 _±d), (525 3 is called + d, 2_. "m±d), (525.3 Mm ± d, i 767 i^ ± d) and (33. 0 (10) ± d, i 767 】 (10) ± (eight). The die of claim 5, wherein the low-end power MOSFET has a first corner, a second corner, a third corner, a fifth corner, and a sixth corner. The coordinates to the sixth corner relative to the grain turn (4) are (661 6(10) ± d, 30 complex 9 (four) 0992η; 539 Form No. A0101 ± d) &gt; (1407.9 μηι ± d, 3040.9 pm ± d), ( 0993388900-0 20 pages/total 30 pages! 4〇7.9 μηι ± d,976.3 &quot;m ± d) , (479.5 μηη ± d ' 976. 3 μιη ± d) , (479. 5 μΐϋ ± d, 1545. 3 μιη士d ) and (661. 6 μπι soil d ' 1545. 3 μπι ± d). 7. The die of claim 6, wherein the low side power MOSFET comprises a first region MOSFET, a second region M 〇 SFET, and a third region MOSFET. 8. The die according to claim 7, wherein the corner of the first region MOSFET is opposite to the corner of the die (% 479*5 ym ± d, 1545.3 PDi ± d ), (1407.9|Llm:!:d , 1545. 3 μιη ± d) ' ( M07. 9 um ± d , 976 · 3 soil d) and (479.5 soil μιη '976.3 μπι ± d); the second region The coordinates of the corner of the MOSFET relative to the corner of the wafer are (6616 ^ + d ' 2297. 1 μιη ± d) , ( 140 7. 9 μηη soil d , 2297 1 , Μ m ± d ) , ( 1407. 9 um ± d , 1557. 1 um ± d) and (661.6 um d, 1557.1 _ ± d); the coordinates of the corner of the third region MOSFET with respect to the die corner are (661.6 Mm + d _ '3040.9 μπι ± d), (1407, 9 μηη ± d, 3040.9 (10) 'soil d), (140 7. 9 μηη ± d, 2308·9 μηη ± d) and (661.6 μπι soil d'2308.9 | im ± d). The granule according to any one of claims 1 to 8, wherein the d does not exceed 160 μm. The crystal grain according to any one of claims 1 to 8, wherein the d does not exceed 80 Mm. 11. A power conversion integrated circuit comprising: a die having a wafer corner: the die comprising: a high side 099212539 power MOSFET having a drain and a source form number A0101 page 21 of 30 pages 0993388900-0 M400092; a first pad and a second pad, the first pad and the second pad being coupled to a drain of the horsepower MOSFET, the The coordinates of a pad relative to the corner of the die are (158.3 μπι ± d, 2945.8 μπι ± d), and the coordinates of the second pad relative to the corner of the die are (398·8 ± d , 2959. 4 μιη ± d) 'where d does not exceed 320 μm; and a lead frame, the lead frame includes a first pin, the first pin being coupled to the first pad and the second pad. 12. The power conversion integrated circuit of claim 11, further comprising: the die further comprising: a low side power MOSFET, the low side power MOSFET having a drain and a a third pad, a fourth pad, a fifth pad, and a sixth pad, the third to sixth pads being coupled to a source of the high side power MOSFET and a drain of the low side power MOSFET, The coordinates of the third to sixth pads with respect to the corners of the die are respectively (599 2 μπι ± d, 2810. 2 μπι ± d), (599. 2 _± d, 2465. 1 μιη ± d ), ( 599.2 μπι soil d, 2133.8 μπι ± d) and (599.2 μ m soil d' 1791.5 μπι ±d); the lead frame further includes a second lead, the second pin is connected to the third pad, Four pads, a fifth pad, and a sixth pad. The power conversion integrated circuit of claim 12, further comprising: the die further comprising: a seventh pad, an eighth pad, a ninth pad, and a tenth pad The seventh to tenth pads are coupled to the high side power m〇sfet source and the drain of the low side power MOSFET, and the seventh to tenth pads are respectively opposite to the coordinates of the die corner (379 5 μιη ± d, 1716, 2 μπι ± d), (179. 8 μιη ± d, 1716. 2 _ ± d 09921^539 0993388900-0 Form No. A0101 Page 22 of 30 M400092), ( 417.2 μπι ± d, 1439.3 um ± d) and (417.2 pm ± d , 1083. 2 μιη ± d); the lead frame further includes a third pin, the third pin handle is connected to the seventh pad, The eighth pad, the ninth pad, and the tenth pad. The power conversion integrated circuit of claim 13, further comprising: the die includes: a thirteenth pad 'fourteenth pad, a fifteenth pad, a a sixteenth pad, a seventeenth pad, an eighteenth pad, and a nineteenth pad, the fourteenth to nineteenth pads being coupled to a source of the low side power MOSFET The coordinates of the thirteenth to nineteenth pads relative to the grain corners are (1493.4 μηη ± d, 2984.2 μηη ± d), (1466·3 μ m ± d' 2815.1 μηη ± d), (1466.3 μηη ± d, 2469 Mm ± d) , ( 1466-3 Mm soil d, 2121.9 ym ± d), ( 1 46 6. 3 pm ± d , 1774· 8 μπι ± d) , ( 1466. 4 &quot;m soil d' 1427.7 μπι ± d) and (1466.4 μπι ± d, 1080.6 μ m ± d); the lead frame further includes: a fourth pin, the fourth pin is coupled to the thirteenth pad; and a die attach The die attach pad is coupled to the fourteenth pad, the fifteenth pad, the sixteenth pad, the seventeenth pad, the eighteenth pad, and the nineteenth pad. [15] The power conversion integrated circuit of claim 14, wherein the high side power MOSFET has a first corner, a second corner, a third corner, and a fourth corner, the first to the first The coordinates of the four corners relative to the grain corners are (33.0 μιη soil d, 2894.3 μηη士d), (525.3 μπι ± d, 2894. 3 μπι ± d), (525.3 μηη soil d, 1767. 1 Mm ± d ) And (33. 0 μπι ± d, 1767. l μπι 099212539 Form No. A0101 0993388900-0 Page 23 / Total 30 pages 00092 ± d ) ° 16 . Power conversion integrated body as described in claim 15 a circuit, characterized in that the low-end power MOSFET has a first corner, a second corner, a second corner, a fourth corner, a fifth corner, and a sixth corner, the first to sixth corners being relative to the die corner The coordinates are (661.6 μ® ± d , 3040.9 μπι d), (1407.9 μηη soil d, 3040.9 um soil d), (1407·9 μηη ± d, 976. 3 nm soil d), (479.5 μηη ± d '976.3 ± d) , ( 479.5 μιη土 d ' 154 5. 3 μηι ± d ) and (661. 6 μιη ± d, 1545. 3 μιη soil d). The power conversion integrated circuit of claim 16, wherein the low-side MOSFET comprises a first-region MOSFET, a second-region MOSFET, and a third-region MOSFET. 18. The power conversion integrated circuit of claim 17, wherein a corner of the first region MOSFET is (479.5 μπι ± d, 1545.3 μηι ± d) with respect to a corner of the die. (1407.9 Mm ± d, 1545· 3 μπι ± d) ' ( 1407· 9 μιη ± d, 976. 3 μπι ± d) and ( 479. 5 soil μπι, 976. 3 μιη ± d); The coordinates of the corner of a region MOSFET with respect to the corner of the die are (661. 6 μιη ± d &gt; 2297. 1 Mm + d) % (Η〇7.9 μπι ± d'2297. 1 μπι ± d), (1407.9 Μπι ± d,1557. 1 &quot; m soil d) and (661.6 μηη soil d, 1 557. 1 μπι ± d); the coordinates of the third region 'ΡΈΤ corner with respect to the grain corner are (661. 6) Μιη ± d ' 3040. 9 μιη;!: d), (14〇7· 9 μπ) soil, 3040.9 pm ± d), (1407 9 (four) ± d, 23〇8 9 丨 U992iZb39 ± d) and (661. 6 pm soil d, 2308. 9 μπι ± d). The power conversion integrated circuit according to any one of the items 11 to 18, wherein the d does not exceed 160. The power conversion integrated circuit according to any one of claims 11 to 18, wherein the d is not more than 160. Ιιη. The power conversion integrated circuit according to any one of claims 11 to 18, wherein the d does not exceed 80 μm. 0993388900-0 099212539 Form number Α0101 Page 25 of 30
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814480B (en) 2010-04-16 2011-08-31 杭州矽力杰半导体技术有限公司 Chip package structure and packaging method thereof
US8368192B1 (en) * 2011-09-16 2013-02-05 Powertech Technology, Inc. Multi-chip memory package with a small substrate
US20160056131A1 (en) * 2013-05-28 2016-02-25 Sharp Kabushiki Kaisha Semiconductor device
US10063149B2 (en) 2016-11-23 2018-08-28 Apple Inc. Multi-phase switching power converter module stack
US20230353050A1 (en) * 2022-05-02 2023-11-02 Nxp Usa, Inc. Isolation connections for high-voltage power stage
CN116072663B (en) * 2023-02-28 2024-02-02 海信家电集团股份有限公司 Power module and electronic equipment with same

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2439999A (en) * 1998-04-23 1999-11-08 Matsushita Electric Industrial Co., Ltd. Method of designing power supply circuit and semiconductor chip
US6465898B1 (en) * 2001-07-23 2002-10-15 Texas Instruments Incorporated Bonding alignment mark for bonds over active circuits
US6709900B2 (en) * 2002-06-11 2004-03-23 Texas Instruments Incorporated Method of fabricating integrated system on a chip protection circuit
US6770935B2 (en) * 2002-06-11 2004-08-03 Texas Instruments Incorporated Array of transistors with low voltage collector protection
US6784493B2 (en) * 2002-06-11 2004-08-31 Texas Instruments Incorporated Line self protecting multiple output power IC architecture
US6940724B2 (en) * 2003-04-24 2005-09-06 Power-One Limited DC-DC converter implemented in a land grid array package
JP4115882B2 (en) * 2003-05-14 2008-07-09 株式会社ルネサステクノロジ Semiconductor device
US7138698B2 (en) * 2003-12-18 2006-11-21 Kabushiki Kaisha Toshiba Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof
JP4565879B2 (en) * 2004-04-19 2010-10-20 ルネサスエレクトロニクス株式会社 Semiconductor device
US7495296B2 (en) * 2004-06-01 2009-02-24 Panasonic Corporation Semiconductor integrated circuit device
JP4477952B2 (en) * 2004-07-09 2010-06-09 株式会社ルネサステクノロジ Semiconductor device, DC / DC converter and power supply system
JP2006049341A (en) * 2004-07-30 2006-02-16 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP4426955B2 (en) * 2004-11-30 2010-03-03 株式会社ルネサステクノロジ Semiconductor device
US7566931B2 (en) * 2005-04-18 2009-07-28 Fairchild Semiconductor Corporation Monolithically-integrated buck converter
JP4758787B2 (en) * 2006-03-02 2011-08-31 パナソニック株式会社 Semiconductor integrated circuit
US7618896B2 (en) * 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
TW200812066A (en) * 2006-05-30 2008-03-01 Renesas Tech Corp Semiconductor device and power source unit using the same
JP5222466B2 (en) * 2006-08-09 2013-06-26 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8126928B2 (en) * 2007-06-27 2012-02-28 Sap Ag Systems and methods for merging data into documents
US20090057869A1 (en) * 2007-08-31 2009-03-05 Alpha & Omega Semiconductor, Ltd. Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion
US7882482B2 (en) * 2007-10-12 2011-02-01 Monolithic Power Systems, Inc. Layout schemes and apparatus for high performance DC-DC output stage
JP2009170747A (en) * 2008-01-18 2009-07-30 Toshiba Corp Semiconductor device and method for manufacturing the same
US8063472B2 (en) * 2008-01-28 2011-11-22 Fairchild Semiconductor Corporation Semiconductor package with stacked dice for a buck converter
US7776658B2 (en) * 2008-08-07 2010-08-17 Alpha And Omega Semiconductor, Inc. Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
US20100059795A1 (en) * 2008-09-08 2010-03-11 Firas Azrai Vertical current transport in a power converter circuit
US8148815B2 (en) * 2008-10-13 2012-04-03 Intersil Americas, Inc. Stacked field effect transistor configurations
US8168490B2 (en) * 2008-12-23 2012-05-01 Intersil Americas, Inc. Co-packaging approach for power converters based on planar devices, structure and method

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