M383816 五、新型說明： 【新型所屬之技術領域】 本新型是有關於一種發光二極體封裝結構，特別是指 一種晶片式發光二極體封裝結構。 【先前技術】 參閱圖1，一般表面黏著型的晶片式發光二極體（smd CHIP-LED)封裝結構9，大多是將發光二極體晶片9i置於 印刷電路板92 (PCB)表面，再將透光膠體93覆蓋發光二 極體晶片91並以模造（M〇lding)方式固化，而將發光二極 體晶片91密封。 現有的晶片式發光二極體封裝結構9具有以下缺點： 1-當透光膠體93含有螢光材質或為有色膠體時，無法 直接辨識封裝結構9的極性，造成安裝封裝結構9 於欲結合的電子裝置時的麻煩。 2. 發光二極體晶片91置放於印刷電路板92表面，而 透光膠體93的厚度必須大於發光二極體晶片91的 厚度’才能將發光二極體晶片91密封，使得整體封 裝結構9的厚度受到印刷電路板92及透光膠體％ 的厚度所限制’無法滿足薄型化發展的需求。 3. 印刷電路板92的中間通常為絕緣層921 ，其導熱效 果不佳，因此發光二極體晶片91所發出的熱需由印 刷電路板92表層的金屬層922傳導，如圖1中的箭 頭路徑所示，熱傳導先由印刷電路板92的上表面往 外擴散’再由側邊傳遞至印刷電路板92的下表面散 3 熱’使4熱傳遞路技較長，無法迅速散熱。而熱能 累積則會影響發光二極體晶# 91 #發光效能及使用 壽命。 此外，現有晶片式發光二極體封裝結構9大多僅適於 封裝一個發光二極體晶片91，使得應用範圍較受侷限。 由上述可知，現有晶片式發光二極體封裝結構9仍有 改進的空間。 【新型内容】 因此，本新型之一目的，即在提供一種具有雙凹槽以 供設置兩個二極體，且可以降低整體厚度並能提高散熱速 度的晶片式發光二極體封裝結構。 本新型之另一目的，即在提供一種晶片式發光二極體 封裝結構，其導電底層之最外邊界相對於絕緣層下側的最 外邊界内縮一定距離，可防止毛邊產生以避免吃錫不良。 於是’本新型晶片式發光二極體封裝結構，包含：一 基板、兩個二極體及一透光膠層。該基板包括一絕緣層、 一導電底層、一第一凹槽及一第二凹槽。該導電底層設置 於該絕緣層下，該絕緣層向下凹陷以與該導電底層共同界 定出該第一凹槽及該第二凹槽，且該導電底層的最外邊界 與該絕緣層下側的最外邊界間隔一定距離。該等二極體分 別没於該第一凹槽及該第二凹槽内的該導電底層上。該透 光膠層覆蓋於該基板上，並密封該等二極體。 本新型之功效’藉由雙凹槽結構除了可以同時設置兩 個發光二極體之外，也可以是設置一個發光二極體及一個 M383816 齊納二極體’而能提高抗靜電能力，而且，導電底層的最 外邊界與絕緣層下側的最外邊界間隔—定距離，可防止毛 邊產生以避免吃錫不良。進一步地，基板還包括一防銲層 ，具有防銲及極性辨識功能。必匕夕卜，凹槽使發光二極體可 以直接與導電底層接觸’縮短熱傳遞路徑，以加快散熱速 度，而且發光二極體位於凹槽中，可減少透光膠體在基板 表面的厚度，使整體封裝結構的厚度較薄，符合薄型化的 需求。 【實施方式】 有關本新型之前述及其他技術内容、特點與功效，在 以下配合參考圖式之二較佳實施例的詳細說明中，將可清 楚的呈現。 在本新型被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。M383816 V. New description: [New technical field] The present invention relates to a light-emitting diode package structure, in particular to a wafer type light-emitting diode package structure. [Prior Art] Referring to FIG. 1, a general surface-adhesive chip-type light-emitting diode (smd CHIP-LED) package structure 9 is generally provided with a light-emitting diode chip 9i on a surface of a printed circuit board 92 (PCB). The light-transmitting colloid 93 is covered with the light-emitting diode wafer 91 and cured by molding, and the light-emitting diode wafer 91 is sealed. The existing chip-type light-emitting diode package structure 9 has the following disadvantages: 1. When the light-transmitting colloid 93 contains a fluorescent material or a colored colloid, the polarity of the package structure 9 cannot be directly recognized, resulting in the mounting of the package structure 9 to be combined. Trouble with electronic devices. 2. The LED chip 91 is placed on the surface of the printed circuit board 92, and the thickness of the transparent colloid 93 must be greater than the thickness of the LED substrate 91 to seal the LED chip 91, so that the overall package structure 9 The thickness is limited by the thickness of the printed circuit board 92 and the transparent colloid %, which cannot meet the demand for thinning development. 3. The middle of the printed circuit board 92 is usually an insulating layer 921, and the heat conduction effect is not good. Therefore, the heat emitted by the LED chip 91 needs to be conducted by the metal layer 922 on the surface of the printed circuit board 92, as shown by the arrow in FIG. As shown by the path, the heat conduction is first diffused outward from the upper surface of the printed circuit board 92, and then transmitted from the side to the lower surface of the printed circuit board 92 to dissipate 3 heats, so that the 4 heat transfer path is long and cannot be quickly dissipated. The accumulation of thermal energy affects the luminous efficacy and lifetime of the LED. In addition, the conventional wafer-type light-emitting diode package structure 9 is mostly only suitable for packaging one light-emitting diode chip 91, so that the application range is limited. As can be seen from the above, there is still room for improvement in the conventional wafer type light emitting diode package structure 9. [New content] Therefore, it is an object of the present invention to provide a wafer type light emitting diode package structure having two recesses for providing two diodes, which can reduce the overall thickness and improve the heat dissipation speed. Another object of the present invention is to provide a wafer type light emitting diode package structure in which the outermost boundary of the conductive underlayer is recessed by a certain distance from the outermost boundary of the lower side of the insulating layer to prevent burrs from being generated to avoid eating tin. bad. Thus, the novel wafer type light emitting diode package structure comprises: a substrate, two diodes and a light transmissive layer. The substrate includes an insulating layer, a conductive underlayer, a first recess and a second recess. The conductive bottom layer is disposed under the insulating layer, the insulating layer is recessed downward to define the first recess and the second recess together with the conductive bottom layer, and an outermost boundary of the conductive bottom layer and a lower side of the insulating layer The outermost boundary is separated by a certain distance. The diodes are not on the conductive underlayer in the first recess and the second recess, respectively. The light transmissive layer covers the substrate and seals the diodes. The function of the present invention can improve the antistatic capability by providing a light emitting diode and a M383816 Zener diode by using a double groove structure in addition to two light emitting diodes. The outermost boundary of the conductive bottom layer is spaced apart from the outermost boundary of the lower side of the insulating layer, and the distance between the outermost edges of the insulating layer can be prevented to prevent the occurrence of burrs. Further, the substrate further includes a solder mask, which has solder resist and polarity recognition functions. In some cases, the recess enables the light-emitting diode to directly contact the conductive underlayer to shorten the heat transfer path to accelerate the heat dissipation speed, and the light-emitting diode is located in the recess to reduce the thickness of the transparent colloid on the surface of the substrate. The thickness of the overall package structure is thin, which meets the requirements of thinning. [Embodiment] The foregoing and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of FIG. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖2、圖3與圖4 ’為本新型晶片式發光二極體封 裝結構1之第-較佳實施例’其中圖2為剖面圖圖3為 俯視圖以及圖4為仰視圖，本新型可以利用於表面點著技 術而安裝於一電子裝置的電路板上。 晶片式發光二極體封裝結構丨包含一基板2、一齊納二 極體3、一發光二極體4及一透光膠層5。 基板2包括一絕緣層21、一導電底層22、一導電層23 、一_ 24、_第一凹槽25及一第二凹槽％。絕緣層 21具有-頂面211及一底面212，且導電底層22設置於絕 緣層2i下（即底面212處）。此外，絕緣層21之頂面2ιι 5 M383816 向下往底面212凹陷而與導電底層22共同界定出第一凹槽 25及第二凹槽26，且第一凹槽25及第二凹槽26分別用以 谷置齊納二極體3及發光二極體4。 導電底層22具有互相不導通的一第一正極區221及一 第一負極區222，第一正極區221與第一負極區222相間隔 並與絕緣層21共同界定出一第—斷開區224，且第一正極 區221 '函蓋第一凹槽25的範圍，第一負極區222涵蓋第二 凹槽26的範圍。防銲層24覆蓋導電底層22的部分第一正 極區221及部分第一負極區222的表面並覆蓋第一正極 區22i與第一負_如之間的第一斷開區224，可避免鲜 接後造成第-正極㊣221與第一負極區222導通防鲜層 24的寬度（仏跨第—正極區221與第一負極區的距離 )以不小於〇_4mm較佳，以便可有效避免銲接後易造成第 -正極區221與第—負極區222 $通的問題。而且，因為 銲錫不會附著於防銲層24,而能藉由防銲層24,在未覆蓋 防鲜層24的區域產生銲塾圖形（扣心—叫㈣。此外 防銲層24位於第_負極區222之一側邊川❾中間部分 ί外側H用以作為極識，以提昇作業人員或自動 機台的辨識率^ 另外#電底層22的最外邊界223與絕緣層21下側 (即底面212)的最外邊界213間隔一定距離ι，亦即，導 電底層22整體的最外邊只 卜透界223相對於絕緣層21的最外邊 界213為在内縮一定距雜τ , 離I’内縮距離I以介於〇〇25至 0.1mm較佳。由於莫雷在 、導電底層22若為具有較佳延展性的金屬 6 M383816 ’例如鋼。於是導電底層 , 之最外邊界223容易產生毛邊 ，導致銲接時吃錫不良， a 糟由導電底層22的最外邊界223 相對於絕緣層21底面212 M ^ ^ „ 的最外邊界213往内縮，可降低 導電底層22的最外邊界223被外&細 " 主4 ▲ 被外物觸碰的機會以避免產生 毛邊。在本實施例中，封裝結構i 免產生 〇.8_，即為絕緣層21 …咖 1的面積〜.2w(l6m二界、213尺寸，而封裝結構 絕緩幻丨》 .6mmX〇.8mm)，導電底層22相對於 絕緣層21早側内縮距離j 马.5mm，第一正極區221與第 一負極區222的間隔（即坌齡„广 ，道^ a (即第—斷開區224寬度）為〇.07mm 導電底層22的面積約* 因而導電底層22的面積 ”’勺4封裝，..吉構1面積的78 2%，曰费— · 且覆盍防銲層24後仍可露 出为佔封裝結構1面積的53 9%。 此外’根據前面描述，由於内縮距離！較佳為⑽5至 •lmm，因此若封裝結構1之尺寸為1.6mmx0.8mm時’導 電底層22可以約佔封裝結構1面積之60〜90%，即使後續 覆蓋有防銲層24,苴露出的遙雷成麻μ 4㈣導電底層22面積仍可約佔封裝 ，、-。構1面積之45〜70%。 再者’若是封裝結構！之尺寸擴大為3 2mmxi 6匪， 内縮距離！仍可保持為㈣25U.lmm，於是導電底層η 則可以約佔封裝結構！面積之80〜95%，即使後續覆蓋有防 銲層24，其露出的導電底層22面積仍可約佔封裝結構i面 積之70〜8G%，因而提供了非常大範圍的導電面績有 升散熱效率。 導電層23設於絕緣層21，並通過第一凹槽25及第二 M383816 凹槽26的側壁214、215與導電底層22電連接，且導電層 23環繞於第一凹槽25及第二凹槽26且具有互相不導通且 與導電底層22相對應之一第二正極區232及一第二負極區 233 °亦即，導電層23在第一凹槽25與第二凹槽26之間 有一第二斷開區231，以使第二正極區232與第二負極區 233互相不導通，且導電層23的第二正極區232通過第— 凹槽25之側壁214與導電底層22的第一正極區221電連 接，而導電層23的第二負極區233通過第二凹槽20之側 壁215與導電底層22的第一負極區222電連接。 導電底層22與導電層23可為單一金屬或多層金屬堆 疊所製成，單一金屬可例如銅，多層金屬可例如w/Ni/Au 或Ag’且導電底層22與導電層23可為相同材質或不同材 質。 齊納二極體3及發光二極體4分別設於第一凹槽25及 第二凹槽26内的導電底層22上，其中齊納二極體3的正 極直接與導電底層22的第一正極區221電連接，其負極則 以打線方式與導電層23的第二負極區233電連接，並藉由 導電層23與導電底層22的第一負極區222電連接。發光 二極體4以打線方式分別與導電層23的第二正極區232及 第二負極區233電連接，並藉由導電層23分別與導電底層 22的第一正極區221及第一負極區222電連接。在本實施 例中，第一凹槽25内是設置齊納二極體3，以加強抗靜電 能力，但是在其它實施中亦可以改換設置另一發光二極體 8 M383816 參閱圖2與圖5,透光膠層5覆蓋於基板。上，並密封 背納一極體3與發光二極體4。透光膠層5可配合發光二極 體4摻混有螢光粉以產生白光若發光二極體*以單色光 使用，則透光膠層5不需摻混螢光粉。 參閱圖6,為本新型晶片式發光二極體封裝結構^，之第 二較佳實施例，其與第一較佳實施例大致相同惟，在此 第二較佳實_巾，透铸層5,對應導電底層22的第一負 極區222 (第二較佳實施例之導電底層與第一較佳實施例相 同，故參閱圖4說明，不另外圖示）的一端具有一缺角51， ，用以作為極性辨識。透光膠層5,與防銲層24分別位於上 、下兩側’可達到雙重極性辨識的功能。 在前述較佳實施例中，基板2的製作方式，是將預先 製成的雙面金屬中間夾絕緣層的板體，先移除部分上層金 屬並移除絕緣層21形成第一凹槽25及第二凹槽26，再對 側壁 214、215 進行鍍通孔（Plated Through Hole，PTH 或稱 為化銅）作業以使絕緣的側壁214、215進行金屬化（ metahzation)，便於後續製程進行。接著沉積或電鑛金屬層 ’以使側壁214、215覆有金屬層而使導電層23與導電底 層22電性連接。另去除部分導電底層22，以使其最外邊界 223與絕緣層21底面212之最外邊界213間隔一定距離I， 並形成第一斷開區224及第一正極區221與第一負極區222 ’以及去除部分導電層23，以形成第二斷開區221及第二 正極區232與第二負極區233。再於導電底層22的預定區 域形成防銲層24 (綠漆），例如以油墨印刷方式塗佈，待防 9 M383816 銲層24固化後即完成基板2的製作。齊納二極體3及發光 二極體4以一般固晶方式設置，打線後再覆蓋透光膠體5、 5’，將齊納二極體3及發光二極體4密封。 综上所述，本新型晶片式發光二極體封裝結構1、1 ’， 其第一凹槽25及第二凹槽26除了可以同時設置一個發光 二極體4及一個齊納二極體3，而能提高抗靜電能力，也可 以設置兩個發光二極體。進一步地，導電底層22的最外邊 界223相對於絕緣層21往内縮一定距離，可防止毛邊產生 以避免吃錫不良’且防銲層24具有防銲及極性辨識功能， 再加上透光膠體5 ’可達到雙重極性辨識的功效。此外，發 光二極體4位於第二凹槽26中，可以直接與導電底層22 接觸，縮短熱傳遞路徑，以加快散熱速度，而且可減少透 光膠體5、5’在基板2表面的厚度，使整體封裝結構丨、 的厚度較薄，符合薄型化的需求，故確實能達成本新型之 目的。 。 惟以上所述者，僅為本新型之較佳實施例而已，當不 能以此限定本新型實施之範圍，即大凡依本新型申請專利 範圍及新型說明内容所作之簡單的等效變化與修飾，皆仍 屬本新型專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一示意圖，說明現有的一晶片式發光二極體封 裝結構； 圖2疋示思圖，說明本新型晶片式發光二極體封裝 結構之第一較佳實施例； 10 M383816 圖3是一俯視圖，說明該第一較佳實施例之一基板頂 側； 圖4是一仰視圖，說明該第一較佳實施例之該基板底 側； 圖5是一立體圖’說明該第一較佳實施例；及 圖 6 , __ 疋一立體圖’說明本新型晶片式發光二極體封裝 結構之第二較佳實施例。 M383816 【主要元件符號說明】 1 ....... …封裝結構 23.… •…導電層 Γ…… …封裝結構 231… •…第二斷開區 2 ....... …·基板 232… .第·一正極Εΐ 21…… •…絕緣層 233… 第^—負極£ 211… •…頂面 24·...· •…防銲層 212… •…底面 241… •…側邊 213… •…最外邊界 25•‘… ‘…第凹槽 214… …·侧壁 26…·· •…第二凹槽 215 ··· ....側壁 3…… •…齊納二極體 22…… …·導電底層 4…… •…發光二極體 221… ----第 正極區 5 ....... •…透光膠層 222 ··· ----第 負極區 5? ·.··· •…透光膠層 223 ·· …最外邊界 51，.··· …·缺角 224… …·第一斷開區 I....... •…距離 12Referring to FIG. 2, FIG. 3 and FIG. 4, a first preferred embodiment of a novel wafer-type light-emitting diode package structure 1 is shown in FIG. 2 in a cross-sectional view, FIG. 3 is a top view, and FIG. 4 is a bottom view. It is mounted on a circuit board of an electronic device by using a surface-on technology. The wafer type light emitting diode package structure comprises a substrate 2, a Zener diode 3, a light emitting diode 4 and a light transmissive layer 5. The substrate 2 includes an insulating layer 21, a conductive underlayer 22, a conductive layer 23, a _24, a first recess 25, and a second recess%. The insulating layer 21 has a top surface 211 and a bottom surface 212, and the conductive underlayer 22 is disposed under the insulating layer 2i (i.e., at the bottom surface 212). In addition, the top surface 2 ι 5 M383816 of the insulating layer 21 is recessed downward toward the bottom surface 212 to define the first recess 25 and the second recess 26 together with the conductive bottom layer 22, and the first recess 25 and the second recess 26 respectively It is used to store the Zener diode 3 and the light-emitting diode 4. The conductive underlayer 22 has a first positive electrode region 221 and a first negative electrode region 222 that are not electrically connected to each other. The first positive electrode region 221 is spaced apart from the first negative electrode region 222 and together with the insulating layer 21 defines a first-break region 224. And the first positive electrode region 221' covers the range of the first recess 25, and the first negative electrode region 222 covers the range of the second recess 26. The solder resist layer 24 covers a portion of the first positive electrode region 221 and a portion of the first negative electrode region 222 of the conductive underlayer 22 and covers the first disconnect region 224 between the first positive electrode region 22i and the first negative region, such as to avoid fresh After the connection, the width of the first positive electrode region 221 and the first negative electrode region 222 to conduct the anti-frying layer 24 (the distance between the first positive electrode region 221 and the first negative electrode region) is preferably not less than 〇 4 mm, so that it can be effectively avoided. After the soldering, the first positive electrode region 221 and the first negative electrode region 222 are easily connected. Moreover, since the solder does not adhere to the solder resist layer 24, the solder mask pattern can be generated by the solder resist layer 24 in the region where the anti-fresh layer 24 is not covered (the buckle is called (4). Further, the solder resist layer 24 is located at the The middle portion ί of the one side of the negative electrode region 222 is used as an extreme knowledge to enhance the recognition rate of the operator or the automatic machine. The outermost boundary 223 of the electric bottom layer 22 and the lower side of the insulating layer 21 (ie, The outermost boundary 213 of the bottom surface 212) is spaced apart by a distance ι, that is, the outermost edge of the conductive bottom layer 22 is only the outermost boundary 213 of the insulating layer 21 with respect to the outermost boundary 213 of the insulating layer 21. The retraction distance I is preferably between 〇〇25 and 0.1 mm. Since the Moore is, the conductive underlayer 22 is a metal 6 M383816' having a better ductility, such as steel. Thus, the outermost boundary 223 of the conductive underlayer is easily generated. The burrs cause poor soldering during soldering, and the outermost boundary 223 of the conductive underlayer 22 is retracted relative to the outermost boundary 213 of the bottom surface of the insulating layer 21 by 212 M ^ ^ „, which reduces the outermost boundary 223 of the conductive underlayer 22 By the outside & fine " main 4 ▲ the opportunity to be touched by foreign objects to avoid In this embodiment, the package structure i is free of 〇.8_, that is, the area of the insulating layer 21 ... coffee 1 ~ 2w (l6m two bounds, 213 size, and the package structure is slow and illusory). 6mmX〇. 8mm), the conductive bottom layer 22 is retracted from the front side of the insulating layer 21 by a distance of 5 mm, and the interval between the first positive electrode region 221 and the first negative electrode region 222 (ie, the age of the „„, ^^ a (ie, the first-disconnected The area 224 width) is 〇.07mm The area of the conductive bottom layer 22 is approximately * Thus the area of the conductive bottom layer 22"'s spoon 4 package, 78. 2% of the area of the Geji structure, the cost - and after the solder mask 24 is covered It can still be exposed as 53 9% of the area of the package structure 1. Further, 'according to the foregoing description, since the retraction distance! is preferably (10) 5 to • lmm, if the package structure 1 has a size of 1.6 mm x 0.8 mm, the conductive bottom layer 22 It can occupy about 60~90% of the area of the package structure 1. Even if the solder resist layer 24 is subsequently covered, the exposed area of the ray reveals the area of the conductive bottom layer 22, which can still occupy the package, and the area of the structure 1 is 45~ 70%. In addition, 'if the package structure! The size is expanded to 3 2mmxi 6匪, the retraction distance! Can still be maintained as (four) 25U.lmm, so conductive The layer η can occupy about 80~95% of the package structure! Even if the solder resist layer 24 is subsequently covered, the exposed conductive bottom layer 22 can still occupy about 70~8G% of the area of the package structure i, thus providing a very The conductive layer 23 is disposed on the insulating layer 21 and electrically connected to the conductive underlayer 22 through the sidewalls 214 and 215 of the first recess 25 and the second M383816 recess 26, and the conductive layer 23 Surrounding the first recess 25 and the second recess 26 and having a second positive region 232 and a second negative region 233 corresponding to the conductive underlayer 22, that is, the conductive layer 23 is in the first recess There is a second breaking region 231 between the groove 25 and the second groove 26, so that the second positive electrode region 232 and the second negative electrode region 233 are not electrically connected to each other, and the second positive electrode region 232 of the conductive layer 23 passes through the first groove. The sidewall 214 of the 25 is electrically connected to the first positive region 221 of the conductive underlayer 22, and the second negative region 233 of the conductive layer 23 is electrically connected to the first negative region 222 of the conductive underlayer 22 through the sidewall 215 of the second recess 20. The conductive underlayer 22 and the conductive layer 23 may be made of a single metal or a multilayer metal stack, the single metal may be, for example, copper, the multilayer metal may be, for example, w/Ni/Au or Ag', and the conductive underlayer 22 and the conductive layer 23 may be the same material or Different materials. The Zener diode 3 and the LED 4 are respectively disposed on the conductive underlayer 22 in the first recess 25 and the second recess 26, wherein the anode of the Zener diode 3 is directly connected to the first layer of the conductive underlayer 22 The positive electrode region 221 is electrically connected, and the negative electrode thereof is electrically connected to the second negative electrode region 233 of the conductive layer 23 by wire bonding, and is electrically connected to the first negative electrode region 222 of the conductive underlayer 22 by the conductive layer 23. The LEDs 4 are electrically connected to the second positive electrode region 232 and the second negative electrode region 233 of the conductive layer 23, respectively, and are electrically connected to the first positive electrode region 221 and the first negative electrode region of the conductive underlayer 22, respectively. 222 electrical connection. In this embodiment, the Zener diode 3 is disposed in the first recess 25 to enhance the antistatic capability, but in other implementations, another LED 8 M383816 may be replaced. Referring to FIG. 2 and FIG. 5 The light transmissive layer 5 covers the substrate. The upper body 3 and the light-emitting diode 4 are sealed and sealed. The light-transmitting adhesive layer 5 can be blended with the light-emitting diode 4 to form a white light. If the light-emitting diode is used as a single-color light, the light-transmitting adhesive layer 5 does not need to be blended with the fluorescent powder. Referring to FIG. 6, a second preferred embodiment of the novel wafer type light emitting diode package structure is substantially the same as the first preferred embodiment, but the second preferred embodiment is a through-cast layer. 5, corresponding to the first negative electrode region 222 of the conductive underlayer 22 (the conductive underlayer of the second preferred embodiment is the same as the first preferred embodiment, so the one shown in FIG. 4, not shown) has a notch 51 at one end. Used for polarity identification. The light-transmitting adhesive layer 5 and the solder resist layer 24 are located on the upper and lower sides respectively to achieve the function of dual polarity identification. In the foregoing preferred embodiment, the substrate 2 is formed by forming a pre-formed double-sided metal interlayer insulating layer, removing a portion of the upper metal and removing the insulating layer 21 to form the first recess 25 and The second recess 26 further performs a plated through hole (PTH or copper) operation on the sidewalls 214, 215 to metallize the insulated sidewalls 214, 215 for subsequent processing. Next, a layer of metal ore is deposited or electrically conductive so that the sidewalls 214, 215 are covered with a metal layer to electrically connect the conductive layer 23 to the conductive underlayer 22. The portion of the conductive underlayer 22 is further removed such that the outermost boundary 223 is spaced apart from the outermost boundary 213 of the bottom surface 212 of the insulating layer 21 by a distance I, and the first broken region 224 and the first positive region 221 and the first negative region 222 are formed. And removing a portion of the conductive layer 23 to form a second break region 221 and a second positive region 232 and a second negative region 233. Further, a solder resist layer 24 (green lacquer) is formed in a predetermined region of the conductive underlayer 22, for example, by ink printing, and the substrate 2 is completed after the 9 M383816 solder layer 24 is cured. The Zener diode 3 and the light-emitting diode 4 are disposed in a general solid crystal manner, and after covering the wire, the light-transmitting colloids 5, 5' are covered, and the Zener diode 3 and the light-emitting diode 4 are sealed. In summary, the novel chip type LED package structure 1, 1 ', the first recess 25 and the second recess 26 can be provided with one LED diode 4 and one Zener diode 3 at the same time. To improve the antistatic ability, two light emitting diodes can also be provided. Further, the outermost boundary 223 of the conductive underlayer 22 is retracted by a certain distance with respect to the insulating layer 21 to prevent the burrs from being generated to avoid tin defects, and the solder resist layer 24 has the functions of solder resist and polarity identification, and light transmission. The colloid 5' achieves dual polarity identification. In addition, the light-emitting diode 4 is located in the second recess 26, and can directly contact the conductive bottom layer 22, shorten the heat transfer path to accelerate the heat dissipation speed, and reduce the thickness of the transparent colloid 5, 5' on the surface of the substrate 2. The thickness of the overall package structure is thin, and it meets the requirements of thinning, so the purpose of the present invention can be achieved. . However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the simple equivalent change and modification made by the novel patent application scope and the novel description content, All remain within the scope of this new patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional wafer type light emitting diode package structure; FIG. 2 is a schematic view showing a first preferred embodiment of the novel chip type light emitting diode package structure. 10 M383816 FIG. 3 is a plan view showing the top side of the substrate of the first preferred embodiment; FIG. 4 is a bottom view showing the bottom side of the substrate of the first preferred embodiment; FIG. 5 is a perspective view A first preferred embodiment of the present invention; and FIG. 6, a perspective view of the second preferred embodiment of the novel wafer type light emitting diode package structure will be described. M383816 [Description of main component symbols] 1....... Package structure 23....•...Conductive layer Γ... Package structure 231... •...Second break zone 2 ............. Substrate 232.... First positive electrode Εΐ 21... •...Insulation layer 233... The first negative electrode 211... •...Top surface 24·...·......solder resist layer 212... •...bottom surface 241... •... side Side 213... •... outermost boundary 25•'...'...first groove 214... ...·side wall 26...···...second groove 215 ··· .... side wall 3... •...Zina 2 Polar body 22...... ...·conductive bottom layer 4... •...lighting diode 221... ----first positive region 5 ....... •...translucent adhesive layer 222 ··· ---- Negative electrode area 5? ····· •...translucent adhesive layer 223 ··...outer boundary 51,.·····corner angle 224...··first break zone I....... • ...distance 12