五、新型說明： 【新型所屬之技術領域】 相作有關於-種功率電晶體之封裝結構，主要將設 有後數個功率電晶體的基板_在承載板上，並對基板 行研磨及切割，以完成功率電晶體的設置。 . 【先前技術】 -立凊參閱第1圖’為f用功率電晶體之封裝結構的剖面 :思圖。如圖所示，功率電晶體之封裝結構1G0主要包括 力率電阳體1〇及—封裝膠體14，其中功率電晶體 L括有基板11，且基板11包括一 N+型基板ill及 =型蟲晶層113’_基板lu及—μ蟲晶層113以 層®的方式設置。 Ν+型基板111的表面為一沒極12，而Ν型蟲晶層⑴ 上推雜設置有至少—Ρ型井區13。Ρ型井區13内摻雜設 置有至少-源極區15，並於源極區15上設置有一源極 16。此外Ν型蟲晶層113上還設置有至少—閘極18，並以 一絕緣層17隔離Ν型磊晶層113及閘極18。 藉由上述的構件便已完成功率電晶體10的初步架 構’在使用時可透過導線19纽極12、源極16及間極 18相連接，並可進一步將導線19的另一端與導電架相連 接，而有利於進行功率電晶體1〇的使用，例如在使用時 亦可將_基板⑴餘設置在導電架上，並進行導電架 與源極16及閘極18的電性連接。此外，在完成上述的連 M378477 接後可以封裝膠體14包覆功率電晶體10，藉此在功率電 晶體10外部形成一保護構造。 對習用的功率電晶體10來說，基板11的厚度Η往往 必須大於200微米以維持功率電晶體10的結構，並避免 功率電晶體10之基板11出現碎裂的情形，然而對功率電 晶體10來說厚度Η的大小將與其串聯電阻成正比。由於 習用之功率電晶體10的厚度Η無法縮減，使其串聯電阻 無法進一步降低，並容易在使用的過程當中產生較大的熱 量0 【新型内容】 本創作之主要目的，在於提供一種功率電晶體之封裝 結構，主要將功率電晶體與一承載板相連接，並減少功率 電晶體的基板厚度，藉此以降低功率功率電晶體的串聯電 阻。 本創作之次要目的，在於提供一種功率電晶體之封裝 結構，其中在將功率電晶體與承載板連接後，可進一步對 功率電晶體的基板進行研磨，藉此有利於縮小功率電晶體 的尺寸。 本創作之又一目的，在於提供一種功率電晶體之封裝 結構，藉由功率電晶體之基板厚度的減少，將有利於降低 串聯電阻，並可減少功率電晶體在使用時所產生的熱量。 本創作之又一目的，在於提供一種功率電晶體之封裝 結構，其中功率電晶體之汲極、閘極及源極皆可透過導電 M378477 箸技 在使 層而連接至基板的同-表面’藉此將可以透過表面黏 術（SMD)進行功率電晶體的設置，並提高功率電晶體 用時的便利性。 本創作之又-目的，在於提供一種功率電晶體之 方法’其主要將功率電晶體與承載板進行連接，而後ς 晶 功率電晶體之基板進彳了研磨的製程，並達到降低功 體之基板的厚度的目的。 ％ 本創作之又-目的’在於提供一種功率電晶體之 方法’其中功率電晶體的祕、閘極及源極皆可透過導電 層而連接至基板的同-表面’並以表面黏著技術設置功率 電晶體，而有利於功率電晶體之設置步驟的減化。 本創作之又-目的，在於提供—種功率電晶體之封展 方法，主要於基板（晶圓）上形成複數個功率電晶體，並將 基板貼附在承載板上再進行研磨，之後再將基板及承載板 進订切割，以完成複數個功率電晶體的設置，藉此將有利 於降低功率電晶體的製作成本。 為達成上述目的，本創作提供一種功率電晶體之封裝 結構’包括有：一承载板；一功率電晶體，包括有：一基 板，包括有一第一表面及一第二表面，並以第一表面的方 向與承載板連接；至少一源極，設置於基板的第一表面； 及至少一閘極，設置於基板的第一表面。 此外，本創作尚提供一種功率電晶體之封裝結構，包 括有：—承載板；一功率電晶體，包括有：一基板，包括 有一弟一表面及一第二表面，並以第一表面的方向與承載 M378477 板連接；至少一源極，設置於基板的第一表面；至少一閘 極，設置於基板的第一表面；及至少一汲極，設置於基板 的第一表面。 本創作尚提供一種功率電晶體之封裝方法，其中功率 電晶體包括有一基板，且基板包括一第一表面及一第二表 面，並於第一表面上設置有至少一源極及至少一閘極，主 要包括有以下步驟：將基板之第一表面的方向貼附在一承 載板上；及對功率電晶體之基板的第二表面進行研磨。 【實施方式】 請參閱第2圖，為本創作功率電晶體之封裝結構一較 佳實施例之剖面示意圖。如圖所示，功率電晶體之封裝結 構200包括有一承載板210及一功率電晶體20,其中功率 電晶體20包括有一基板21，且該基板21包括有一第一表 面211及一第二表面212,並以第一表面211的方向連接 承載板210。 基板21的第一表面211上設置有至少一源極26及至 少一閘極28，而基板21的第二表面212則為一汲極22。 基板21包括有一第一型基板213及一第一型磊晶層215， 且第一型基板213及第一型磊晶層215以層疊的方式設 置。例如第一型基板213可為N+型基板（N+ substrate)， 而第一型磊晶層215則可為N型磊晶層（N-epi)。 基板21上可以摻雜方式設置有至少一第二型井區 23，並於第二型井區23内設有至少一第一型源極區25。 /8477 例如第二型井區23設置在第一型磊晶層215内，且第二 型井區23為P-型井區，而第一型源極區25則為N型源極 區。第一型源極區25上設置有至少一源極26，並透過源 極26與第一型源極區25及/或第二型井區23電性連接。 基板21之第一表面211上還設置有至少一絕緣層 ,7,並於絕緣層27上設置有至少一閘極別，藉此將可二 絕緣層27對閘極28進行隔離，使得閘極28 *會與基板 21、第一型磊晶層215、第二型井區23及/或第一型源極 區25接觸。並以第一型基板213的表面為汲極22。 在本創作中主要對功率電晶體2〇的厚度進行縮減， 並使得功率電晶體20的厚度H1及/或基板21的厚度H2 小於⑽微米’藉此不僅有利於縮小功率電晶體2〇 ^尺 寸，同時藉由厚度H1/H2的縮小更可進一步降低功率電晶 ，20的串聯電阻’並可減少功率電晶體2q在使用的過程 虽中日所產生的熱量。理論上來說電阻的大小與導電物的長 度（厚度）成iL比，若本創作所述之功率電晶體2 =為習用功率電晶體⑽的厚度H的—半，則功率2 屯的串聯電阻亦會是習用功率電晶體（1〇)之電阻的一 明參閱第3圖’為本創作功率電晶體之封|結構—每 意圖。如圖所示’本實施例所述之功率電: 連接方：H主要進一步揭露功率電晶體20的線路 板21〇1 ’工率電晶體之封裝結構300同樣包括有—承載 板mo及-功率電晶體2〇，並將功率電晶體2〇設置在承 7 M378477 載板210上，例如以基板21的第一表面211方向，進行 功率電晶體20與承載板210的連接。 在本創作實施例中，功率電晶體20的源極26及閘極 28分別與至少一導電層29連接，且導電層29由基板21 第一表面211延伸至第二表面212,藉由導電層29的設置 可將源極26與閘極28的接點引導至基板21的第二表面 212。例如於基板21上設置有至少一穿孔24，該穿孔24 由基板21的第一表面211延伸至第二表面212,可將導電 層29設置在穿孔24内，並使得導電層29與源極26及閘 極28連接。 由於基板21的第二表面212為功率電晶體20之汲極 22，而源極26與閘極28的接點則可透過導電層29延伸 至基板21的第二表面212,因此功率電晶體20的汲極22、 源極26及閘極28皆設置在同一表面，並可直接透過表面 黏著技術（SMD)將功率電晶體20設置在不同的裝置上，例 如透過焊球241進行功率電晶體20與電路板的連接。藉 由透過表面黏著技術進行功率電晶體之封裝結構300與電 路板之間的連接，將有利於提高功率電晶體20之設置效 率的提升及體積的縮小。 請參閱第4圖，為本創作功率電晶體之封裝結構又一 實施例之剖面示意圖。如圖所示，本創作所述之功率電晶 體之封裝結構400包括有一承載板210及一功率電晶體 40，其中功率電晶體40的基板41包括有一第一表面411 及一第二表面412,並以第一表面411的方向與承載板210 M378477 相連接。 基板41的第一表面411上設置有至少一沒極42、至 少一源極46及至少一閘極48 ’其中基板41包括有一第一 型基板413及一第一型蟲晶層415，且第一型基板413及 第一型磊晶層415以層疊的方式設置。第一型磊晶層415 内設置有一第二型井區43及一第一型汲極區451，而第二 型井區43内則設置有一第一型源極區453。 第一型沒極區451上設置有至少一没極42，而第一型 源極區453上則設置有至少一源極46。第一型蟲晶層415 的部分表面上設置有一絕緣層47，並於絕緣層47上設置 有至少一閘極48，藉此將可以絕緣層47對閘極48進行隔 離，例如絕緣層47可橫跨在第一型没極區451及第一型 源極區4 5 3之間。 功率電晶體40之汲極42、源極46及閘極48分別與 至少一導電層49相連接’並透過不同的導電層49將汲極 42、源極46及閘極48的接點引導至基板41的第二表面 412，例如導電層49可由基板41的侧邊延伸至基板41的 -第二表面412’藉此功率電晶體40將可以透過表面黏著技 術（SMD)設置在不同的裝置上。 在本創作第3圖所示之功率電晶體20為垂直雙擴散 金屬氧化物半導體場效應管（VDMOS，vertical double-diffused MOSFET) ’而第4圖所示之功率電晶體 40則是橫向雙擴散金屬氧化物半導體場效應管（LDM0S， lateral double-dif fused M0SFET)，然而在實際應用時 9 M378477 亦可將本創作應用不同形式之功率電晶體。 請參閱第5 A圖至第5 E圖，為本創作功率電晶體之 封裝方法的流程圖。如圖所示，本創作首先進行功率電晶 體20的相關製程，例如於基板21上形成一第一型基板213 及一第一型磊晶層215。之後透過摻雜方式在第一型磊晶 層215上形成至少一第二型井區23,並於第二型井區23 内設有至少一第一型源極區2 5。 在完成上述第一型基板213、第一型磊晶層215、第 二型井區23及第一型源極區25的設置後，可於第一型源 極區25上設置有至少一源極26。並於第一型磊晶層215 及/或第一型源極區25的部分表面上設置一絕緣層27,例 如可使得絕緣層27橫跨於兩個源極26或兩個源極區25 之間，而後再於絕緣層27上設置有至少一閘極28，如第 5 A圖所示。 在完成功率電晶體20的初步架構後，可將功率電晶 體20與承載板210相連接，例如以功率電晶體20之基板 21的第一表面211的方向貼附在承載板210上，如第5 B 圖所示。功率電晶體20在與承載板210連接後將可以得 到承載板210的支撐，並可以進一步對功率電晶體20之 基板21的第二表面212進行研磨。例如在實際應用時可 對基板21的第一型基板213進行研磨，並使得基板21的 厚度H2小於100微米，藉此不僅有利於縮小功率電晶體 20的尺寸，同時亦可達到降低功率電晶體20之串聯電阻 的目的，如第5C圖所示。 10 M378477 在完成研磨的步驟後，可進一步在功率電晶體20上 設置有至少一導電層29,導電層29分別與源極26及閘極 28相連接，並將源極26及閘極28的接點引導至基板21 的第二表面212。在實際應用時亦可依據功率電晶體20之 配置方式的不同，而在基板21上設置有至少一穿孔24， 使得穿孔24由基板21的第一表面211延伸至第二表面 212，而導電層29則可設置在穿孔24内部，並將源極26 及閘極28的接點引導至基板21的第二表面212,如第5 D圖所示。 在完成上述的步驟後，便已完成功率電晶體20的封 裝，並使得功率電晶體20之汲極22、源極26及閘極28 的接點皆設置在基板21的同一表面，藉此將可透過表面 黏著技術（SMD)進行功率電晶體20的設置，例如透過焊球 241將功率電晶體20設置在一電路板50上，如第5 E圖 所示。 在本創作製作方法的實施例中，主要是以垂直雙擴散 金屬氧化物半導體場效應管（VDMOS)為實施例進行說明， 然而橫向雙擴散金屬氧化物半導體場效應管（LDMOS)或其 他形式的功率電晶體亦可以類似的製作方法完成設置。例 如可以在基板21的第一表面211上設置有至少一汲極 22，再進行功率電晶體20與承載板210之間的連接，以 及後續對基板21進行研磨的步驟。此外，在實際製作時 亦可依據不同的需求調整上述各個步驟的順序，皆可完成 功率電晶體之封裝結構。 11 M378477 在實際製作時基板21可為一晶圓（wafer)，同一個基 板21上可形成複數個功率電晶體20,並將基板21貼附在 承載板210上再進行研磨，以縮小功率電晶體20的厚度。 此外，亦可同時在基板21的複數個功率電晶體20上形成 穿孔24，並於穿孔24内形成導電層29，最後再將承載板 210與基板21進行切割，例如延著虛線進行切割，以同時 完成複數個功率電晶體20的設置，藉此將有利於功率電 晶體20之設置步驟的簡化及製作成本的降低，如第6圖 所示。 以上所述者，僅為本創作之較佳實施例而已，並非用 來限定本創作實施之範圍，即凡依本創作申請專利範圍所 述之形狀、構造、特徵及精神所為之均等變化與修飾，均 應包括於本創作之申請專利範圍内。 【圖式簡單說明】 第1圖：為習用功率電晶體之封裝結構的剖面示意圖。 第2圖：為本創作功率電晶體之封裝結構一較佳實施例之 剖面示意圖。 第3圖：為本創作功率電晶體之封裝結構一實施例之剖面 示意圖。 第4圖：為本創作功率電晶體之封裝結構又一實施例之剖 面示意圖。 第5A圖至第5E圖：為本創作功率電晶體之封裝方法的 流程圖。 12 第6圖 :為本創作功率電 圖。 晶體又一實施例之封骏方法流程 【主要元件符號說明】 10 功率電晶體 100 11 基板 111 113 N型磊晶層 12 •13 p型井區 14 •15 源極區 16 18 閘極 19 20 功率電晶體 200 21 基板 210 211 第一表面 212 213 第一型基板 215 22 没極 23 24 1 穿孔 241 •25 第一型源極區 26 -27 絕緣層 28 29 300 導電層 功率電晶體之封裝結構 40 功率電晶體 400 41 基板 411 412 第二表面 413 415 第一型磊晶層 42 功率電晶體之封裝結構 N+型基板 >及極 封裝膠體 源極 導線 功率電晶體之封裝結構 承载板 第二表面 第一型磊晶層 第二型井區 焊球 源極 閘極 功率電晶體之封裝結構 第一表面 第一型基板 沒極 13 M378477 43 第二型井區 451 第一型及極區 453 第一型源極區 46 源極 47 絕緣層 48 閘極 49 導電層 50 電路板 14V. New description: [New technical field] The related structure of the power transistor is mainly composed of a substrate with a plurality of power transistors _ on the carrier plate, and the substrate is polished and cut. To complete the setting of the power transistor. [Prior Art] - Refer to Figure 1 for a section of the package structure of the power transistor for f: Think. As shown in the figure, the power transistor package structure 1G0 mainly includes a force rate electric anode 1 and an encapsulant 14 , wherein the power transistor L includes a substrate 11 , and the substrate 11 includes an N + type substrate ill and a type insect The crystal layer 113'_substrate lu and the -μ insect layer 113 are disposed in a layer® manner. The surface of the Ν+-type substrate 111 is a immersion 12, and the Ν-type worm layer (1) is provided with at least a 井-type well region 13. The doped well region 13 is doped with at least a source region 15 and a source 16 is disposed on the source region 15. Further, at least the gate electrode 18 is disposed on the germanium-type insect layer 113, and the germanium-type epitaxial layer 113 and the gate electrode 18 are separated by an insulating layer 17. The preliminary structure of the power transistor 10 has been completed by the above-mentioned components. In use, the wire 19, the source 16 and the interpole 18 can be connected through the wire 19, and the other end of the wire 19 can be further connected to the conductive frame. The connection is beneficial to the use of the power transistor 1〇. For example, the _ substrate (1) can be disposed on the conductive frame during use, and the conductive frame is electrically connected to the source 16 and the gate 18. In addition, after the completion of the above-mentioned connection of M378477, the encapsulant 14 can be coated with the power transistor 10, thereby forming a protective structure outside the power transistor 10. For the conventional power transistor 10, the thickness 基板 of the substrate 11 often must be greater than 200 μm to maintain the structure of the power transistor 10 and avoid the occurrence of chipping of the substrate 11 of the power transistor 10, whereas for the power transistor 10 The thickness Η will be proportional to its series resistance. Since the thickness of the conventional power transistor 10 cannot be reduced, the series resistance cannot be further reduced, and it is easy to generate a large amount of heat during use. [New content] The main purpose of the present invention is to provide a power transistor. The package structure mainly connects the power transistor to a carrier plate and reduces the substrate thickness of the power transistor, thereby reducing the series resistance of the power transistor. The second objective of the present invention is to provide a package structure of a power transistor, wherein after the power transistor is connected to the carrier plate, the substrate of the power transistor can be further ground, thereby facilitating the reduction of the size of the power transistor. . Another object of the present invention is to provide a power transistor package structure. By reducing the thickness of the substrate of the power transistor, it is advantageous to reduce the series resistance and reduce the heat generated by the power transistor during use. Another object of the present invention is to provide a package structure of a power transistor, wherein the drain, the gate and the source of the power transistor can be connected to the same surface of the substrate by the conductive M378477 technology. This will enable the setting of power transistors through surface cementation (SMD) and improve the convenience of power transistors. The purpose of the present invention is to provide a method for powering a transistor, which mainly connects a power transistor to a carrier plate, and then the substrate of the silicon crystal power transistor is subjected to a grinding process and reaches a substrate for reducing the work. The purpose of the thickness. % The purpose of this creation is to provide a method of power transistor in which the secret, gate and source of the power transistor are connected to the same surface of the substrate through the conductive layer and the power is set by surface adhesion technology. The transistor is beneficial to the reduction of the setting steps of the power transistor. The purpose of this creation is to provide a method for sealing a power transistor, which mainly forms a plurality of power transistors on a substrate (wafer), and attaches the substrate to the carrier plate for grinding, and then The substrate and the carrier board are stapled and cut to complete the setting of a plurality of power transistors, thereby facilitating the reduction of the manufacturing cost of the power transistor. In order to achieve the above object, the present invention provides a power transistor package structure including: a carrier plate; a power transistor comprising: a substrate including a first surface and a second surface, and the first surface The direction is connected to the carrier board; at least one source is disposed on the first surface of the substrate; and at least one gate is disposed on the first surface of the substrate. In addition, the present invention further provides a package structure of a power transistor, comprising: a carrier plate; a power transistor, comprising: a substrate comprising a body surface and a second surface, and the direction of the first surface Connecting to the carrying M378477 board; at least one source disposed on the first surface of the substrate; at least one gate disposed on the first surface of the substrate; and at least one drain disposed on the first surface of the substrate. The present invention further provides a power transistor packaging method, wherein the power transistor includes a substrate, and the substrate includes a first surface and a second surface, and the first surface is provided with at least one source and at least one gate The method further comprises the steps of: attaching the direction of the first surface of the substrate to a carrier plate; and grinding the second surface of the substrate of the power transistor. [Embodiment] Please refer to Fig. 2, which is a schematic cross-sectional view showing a preferred embodiment of a package structure of a power transistor. As shown in the figure, the package structure 200 of the power transistor includes a carrier 210 and a power transistor 20, wherein the power transistor 20 includes a substrate 21, and the substrate 21 includes a first surface 211 and a second surface 212. And the carrier board 210 is connected in the direction of the first surface 211. The first surface 211 of the substrate 21 is provided with at least one source 26 and at least one gate 28, and the second surface 212 of the substrate 21 is a drain 22. The substrate 21 includes a first type substrate 213 and a first type epitaxial layer 215, and the first type substrate 213 and the first type epitaxial layer 215 are stacked. For example, the first type substrate 213 may be an N+ type substrate (N+ substrate), and the first type epitaxial layer 215 may be an N type epitaxial layer (N-epi). At least one second type well region 23 may be disposed on the substrate 21 in a doped manner, and at least one first type source region 25 may be disposed in the second type well region 23. /8477 For example, the second type well region 23 is disposed in the first type epitaxial layer 215, and the second type well region 23 is a P-type well region, and the first type source region 25 is an N-type source region. The first type source region 25 is provided with at least one source 26 and is electrically connected to the first type source region 25 and/or the second type well region 23 through the source 26. The first surface 211 of the substrate 21 is further provided with at least one insulating layer 7, and at least one gate is disposed on the insulating layer 27, thereby isolating the gate insulating layer 27 to the gate 28, so that the gate is 28* will be in contact with the substrate 21, the first type epitaxial layer 215, the second well region 23, and/or the first type source region 25. The surface of the first type substrate 213 is the drain 22 . In the present creation, the thickness of the power transistor 2〇 is mainly reduced, and the thickness H1 of the power transistor 20 and/or the thickness H2 of the substrate 21 is less than (10) micrometers, thereby not only facilitating the reduction of the size of the power transistor 2〇^ At the same time, by reducing the thickness H1/H2, the power transistor, the series resistance of 20' can be further reduced, and the heat generated by the power transistor 2q during use can be reduced. Theoretically, the magnitude of the resistance is in iL ratio to the length (thickness) of the conductive material. If the power transistor 2 of the present invention is half the thickness H of the conventional power transistor (10), the series resistance of the power 2 亦 is also It will be a conventional power transistor (1〇) resistor. See Figure 3 for the creation of a power transistor. As shown in the figure, the power supply described in the present embodiment: the connection side: H mainly further exposes the circuit board 21 of the power transistor 20. The package structure 300 of the power transistor also includes the carrier board mo and the power. The transistor 2 is placed and the power transistor 2 is placed on the carrier 7 M378477, for example, in the direction of the first surface 211 of the substrate 21, and the power transistor 20 is connected to the carrier 210. In the present embodiment, the source 26 and the gate 28 of the power transistor 20 are respectively connected to at least one conductive layer 29, and the conductive layer 29 extends from the first surface 211 of the substrate 21 to the second surface 212 by a conductive layer. The arrangement of 29 can direct the junction of source 26 and gate 28 to second surface 212 of substrate 21. For example, at least one through hole 24 is provided on the substrate 21, and the through hole 24 extends from the first surface 211 of the substrate 21 to the second surface 212. The conductive layer 29 can be disposed in the through hole 24, and the conductive layer 29 and the source electrode 26 are disposed. And the gate 28 is connected. Since the second surface 212 of the substrate 21 is the drain 22 of the power transistor 20, the junction of the source 26 and the gate 28 can extend through the conductive layer 29 to the second surface 212 of the substrate 21, thus the power transistor 20 The drain 22, the source 26 and the gate 28 are all disposed on the same surface, and the power transistor 20 can be directly disposed on different devices through surface adhesion technology (SMD), for example, the power transistor 20 is performed through the solder ball 241. Connection to the board. The connection between the package structure 300 of the power transistor and the circuit board through the surface adhesion technology will be advantageous for improving the efficiency of setting the power transistor 20 and reducing the volume. Please refer to FIG. 4, which is a cross-sectional view showing still another embodiment of the package structure of the power transistor. As shown in the figure, the package structure 400 of the power transistor of the present invention includes a carrier plate 210 and a power transistor 40. The substrate 41 of the power transistor 40 includes a first surface 411 and a second surface 412. And connected to the carrier plate 210 M378477 in the direction of the first surface 411. The first surface 411 of the substrate 41 is provided with at least one gate 42 , at least one source 46 and at least one gate 48 ′. The substrate 41 includes a first type substrate 413 and a first type of worm layer 415 , and The first type substrate 413 and the first type epitaxial layer 415 are disposed in a stacked manner. A first type well region 43 and a first type drain region 451 are disposed in the first type epitaxial layer 415, and a first type source region 453 is disposed in the second type well region 43. At least one of the poles 42 is disposed on the first type of non-polar region 451, and at least one source 46 is disposed on the first type of source region 453. An insulating layer 47 is disposed on a portion of the surface of the first type of crystal layer 415, and at least one gate 48 is disposed on the insulating layer 47, whereby the insulating layer 47 can be used to isolate the gate 48, for example, the insulating layer 47 can be It straddles between the first type non-polar region 451 and the first type source region 4 5 3 . The drain 42 , the source 46 and the gate 48 of the power transistor 40 are respectively connected to at least one conductive layer 49 and direct the contacts of the drain 42 , the source 46 and the gate 48 through different conductive layers 49 to The second surface 412 of the substrate 41, such as the conductive layer 49, may extend from the sides of the substrate 41 to the second surface 412' of the substrate 41 whereby the power transistor 40 will be permeable to surface mount technology (SMD) on different devices. . The power transistor 20 shown in Fig. 3 of the present invention is a vertical double-diffused MOSFET (VDMOS) and the power transistor 40 shown in Fig. 4 is a lateral double-diffusion. Metal oxide semiconductor field effect transistor (LDM0S, lateral double-dif fused MOSFET), however, in practical applications, 9 M378477 can also apply different forms of power transistors to this creation. Please refer to Figure 5A to Figure 5E for a flow chart of the packaging method of the power transistor. As shown in the figure, the present invention first performs a related process of the power transistor 20, for example, forming a first type substrate 213 and a first type epitaxial layer 215 on the substrate 21. At least one second type well region 23 is formed on the first type epitaxial layer 215 by doping, and at least one first type source region 25 is disposed in the second type well region 23. After the first type substrate 213, the first type epitaxial layer 215, the second well region 23, and the first type source region 25 are disposed, at least one source may be disposed on the first type source region 25. Extreme 26. An insulating layer 27 is disposed on a portion of the surface of the first type epitaxial layer 215 and/or the first type source region 25, for example, the insulating layer 27 may be spanned across the two source 26 or the two source regions 25. At least one gate 28 is then disposed between the insulating layer 27, as shown in FIG. 5A. After completing the preliminary architecture of the power transistor 20, the power transistor 20 can be connected to the carrier 210, for example, attached to the carrier 210 in the direction of the first surface 211 of the substrate 21 of the power transistor 20. 5 B shows the picture. The power transistor 20 can be supported by the carrier 210 after being connected to the carrier 210, and the second surface 212 of the substrate 21 of the power transistor 20 can be further ground. For example, in the actual application, the first type substrate 213 of the substrate 21 can be ground, and the thickness H2 of the substrate 21 is less than 100 micrometers, thereby not only facilitating the reduction of the size of the power transistor 20, but also achieving the reduction of the power transistor. The purpose of the series resistance of 20 is shown in Figure 5C. 10 M378477 After completing the grinding step, at least one conductive layer 29 may be further disposed on the power transistor 20, and the conductive layer 29 is respectively connected to the source 26 and the gate 28, and the source 26 and the gate 28 are The contacts are directed to the second surface 212 of the substrate 21. In practical applications, depending on the configuration of the power transistor 20, at least one through hole 24 is disposed on the substrate 21 such that the through hole 24 extends from the first surface 211 of the substrate 21 to the second surface 212, and the conductive layer 29 may be disposed inside the perforation 24 and direct the contacts of the source 26 and the gate 28 to the second surface 212 of the substrate 21, as shown in FIG. 5D. After the above steps are completed, the package of the power transistor 20 is completed, and the contacts of the drain 22, the source 26 and the gate 28 of the power transistor 20 are disposed on the same surface of the substrate 21, thereby The power transistor 20 can be placed through a surface mount technology (SMD), such as by placing the power transistor 20 on a circuit board 50 via solder balls 241, as shown in FIG. In the embodiment of the present fabrication method, a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) is mainly described as an embodiment, but a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) or other form is used. Power transistors can also be set up in a similar way. For example, at least one drain 22 may be disposed on the first surface 211 of the substrate 21, and then the connection between the power transistor 20 and the carrier 210 may be performed, and the subsequent step of polishing the substrate 21. In addition, in the actual production, the order of the above steps can be adjusted according to different requirements, and the package structure of the power transistor can be completed. 11 M378477 In actual production, the substrate 21 can be a wafer, a plurality of power transistors 20 can be formed on the same substrate 21, and the substrate 21 is attached to the carrier 210 and then ground to reduce the power. The thickness of the crystal 20. In addition, the through holes 24 may be formed on the plurality of power transistors 20 of the substrate 21, and the conductive layer 29 may be formed in the through holes 24. Finally, the carrier plate 210 and the substrate 21 are cut, for example, by a dotted line. At the same time, the arrangement of the plurality of power transistors 20 is completed, thereby facilitating the simplification of the setting steps of the power transistor 20 and the reduction of the manufacturing cost, as shown in FIG. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the equivalent changes and modifications of the shapes, structures, features and spirits described in the scope of the patent application. , should be included in the scope of the patent application of this creation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a package structure of a conventional power transistor. Fig. 2 is a cross-sectional view showing a preferred embodiment of the package structure of the power transistor of the present invention. Fig. 3 is a cross-sectional view showing an embodiment of a package structure of the power transistor of the present invention. Fig. 4 is a cross-sectional view showing still another embodiment of the package structure of the power transistor of the present invention. 5A to 5E are flowcharts showing a method of packaging a power transistor according to the present invention. 12 Figure 6: This is the power picture of the creation. Sealing method flow of another embodiment of crystal [Main component symbol description] 10 Power transistor 100 11 Substrate 111 113 N-type epitaxial layer 12 • 13 p-type well region 14 • 15 source region 16 18 gate 19 20 power Transistor 200 21 substrate 210 211 first surface 212 213 first type substrate 215 22 no pole 23 24 1 perforation 241 • 25 first type source region 26 -27 insulating layer 28 29 300 conductive layer power transistor package structure 40 Power transistor 400 41 substrate 411 412 second surface 413 415 first type epitaxial layer 42 power transistor package structure N+ type substrate> and pole package colloid source wire power transistor package structure carrier board second surface Type I epitaxial layer second type well area solder ball source gate power transistor package structure first surface first type substrate immersion 13 M378477 43 second type well area 451 first type and polar area 453 first type Source region 46 source 47 insulating layer 48 gate 49 conductive layer 50 circuit board 14