TWM368188U - Stacking structure of flash memory chips - Google Patents

Stacking structure of flash memory chips Download PDF

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Publication number
TWM368188U
TWM368188U TW098206272U TW98206272U TWM368188U TW M368188 U TWM368188 U TW M368188U TW 098206272 U TW098206272 U TW 098206272U TW 98206272 U TW98206272 U TW 98206272U TW M368188 U TWM368188 U TW M368188U
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TW
Taiwan
Prior art keywords
pin
flash memory
busy
standby
control unit
Prior art date
Application number
TW098206272U
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Chinese (zh)
Inventor
yu-min Liang
gui-wu Zhu
Xuan-Yu Lu
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Mao Bang Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Mao Bang Electronic Co Ltd filed Critical Mao Bang Electronic Co Ltd
Priority to TW098206272U priority Critical patent/TWM368188U/en
Publication of TWM368188U publication Critical patent/TWM368188U/en

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    • Y02E60/521

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  • Read Only Memory (AREA)

Description

M368188 五、新型說明: 【新型所屬之技術領域】 本創作是有關於-種,_記,_ “堆疊結構,尤指一種 可使各晶粒達到易於進行線路佈局、易於生產管理、降低製作 成本及符合客制化需求之功效者。 【先前技術】M368188 V. New description: [New technology field] This creation is related to - kind, _ note, _ "Stack structure, especially one that can make each die easy to layout, easy to produce management, reduce production costs And those who meet the requirements of customized requirements. [Prior technology]

按,-般習用快閃記憶體晶粒係於一面上設有電源接腳、 接地接腳、輸入/出接腳、選擇接腳及待命/忙碌機,而當進 打各記憶晶粒於進行堆疊封料,係依所冑以打線之方式將各 接腳之=位相互連接’藉以_輯晶粒之封裝。 但是由於制之記憶晶粒堆疊封裝係以打線之方式將各 接腳之腳位相互連接,雖然接線之方式較具有彈性,但對於,己 憶晶片顆粒之堆叠封裝而言,則需在該記憶晶粒之整個晶圓上 ,不同之層疊製作出不_線路,使得製作生產晶圓時所用之 先罩设計較為複雜’而增加生產管理之難度,並使得製 之增加,更無法依據客戶之特殊需求進行製作。 不 本創作之主要目的餘於,可龄雜 佈局= 於生絲理爾作成本及符合客制姆= ^目的’本創作係一種快閃記憶體晶片堆叠姓 =面=控制單元;以及多數相互堆4之晶粒,且各 曰曰粒兩面上係分職有多數相互導通之電源接腳、接地接腳、 M368188 接腳及輸人/出接腳係相互並 接職待條·腳係分别直上:=,而各選擇 腳及待命峨轉_術==^= 時依不同層疊騎需之導線部加 二™匈 腳及待命㈣接腳之間分別連 於= 之斷線部加以連接。 ⑺佈局將所需 【實施方式】 第-、2、3及第4圖』所示,係分別為本創作 ^解示意圖、本創作第—實施例之方塊示意 /;音_ 婦彳之縣撕及騎/忙雜腳連接狀態 肤離一立1帛實知例之選擇接腳及待命/忙碌接腳斷開 所示:本創作係—種快閃記憶體晶片堆疊結 冓八至乂係由一控制單元1以及多數晶粒2所構成。 上述所提之控制單元1係可為控制晶片。 各晶粒2係可為相互堆叠之快閃記憶體晶粒,且各晶粒2 :面上係刀別具有多數電源接腳2i、接地接腳22、輸入/ 出接腳2 3、選擇接腳2 4及待命/忙碌接㈣5,各電源接 腳^ 1接地接聊2 2及輸入/出接腳2 3係相互並聯後與控 制單兀1連接’而各選擇接腳2 4及待命/忙碌接腳2 5係分 別直接與控制單元1連接’且選擇接腳2 4及待命/忙綠接腳 2 5之間係分別連接有導線部2 6,並於各晶粒2之侧緣係分 别具有夕數與各電源接腳21、接地接腳2 2、輸入/出接腳 M368188 2 3、曰選擇接腳2 4及待命/忙碌接腳2 5連接之導通部2 7。如疋’藉由上述之結構構成一全新之快閃記憶體晶片堆聶 結構。 且 、當本創作於佈局設計時,係可先將多數晶粒2相互堆属, 並依不同層疊進佈局時之所需將各導通部2 7進行相^ 通,而讓各相對應或不相對應晶粒2兩面上之電源接腳2丄、 接地接腳2 2、輸入/出接腳2 3、選擇接腳2 =5依需求加以導通或不導通,之後再於各晶粒 同層疊所需將導線部20以雷射切斷方式加以斷 開’如此’即可使各晶粒2達到易於進行線路佈局、易於生產 管理、降低製作成本及符合客制化需求之姐。 、 請參閱『第5及第6圖』所示,係分別為本創作第 例之選擇接腳及待命/忙碌撕_狀態示鋼及本創作 實施例之選擇接腳及待命/忙綠接腳連接狀態示意圖。如騎 不.本創作除上述第一實施例所提結構型態之外,更可以本第 線路佈局之賴所刊之處在於, 邱^了^及抑忙碌接腳2 5之間係分別連接有斷線 佈局時依不同層疊將所需之斷線部2 8 或導體2 9印刷方式加以連接;如此,同 樣可達到上述所提第—實施例中所提之功效。 綜上所述,本__記鐘晶片堆疊結射有效改盖習 之種種缺點’可使各晶粒達到易於進行線路 倾权舰,進而使本創作 之產生此更妨、更實用、更符合使时 作專利申請之要件,麦依法提出專利申請。、確已符口創 M368188 准x上所述者,僅為本創作之較佳實施例而已,當不能以 此限定本創作實施之故,凡依本創作申請料範圍及創 作說明書内容所作之簡單的等效變化與修飾,皆應仍屬本創作 專利涵蓋之範圍内。 【圖式簡單說明】 第1圖係、本創作第一實施例之立體分解示意圖。 第2圖’係本創作第—實施例之方塊示意圖。 第3圖,係本創作第—實施例之選擇接腳及待命/忙綠接 腳連接狀態示意圖。 選擇接腳及待命/忙綠接 第4圖,係本創作第一實施例之 腳斷開狀態示意圖。 第5圖, 係本創作第二實施例之選擇接腳及 腳斷開狀態示意圖。 待命/忙碌接 擇接腳及待命/忙碌接 第6圖’係本創作第二實施例之選 腳連接狀態示意圖。 【主要元件符號說明】 控制單元1 晶粒2 電源接腳21 接地接腳2 2 輸入/出接腳2 3 選擇接腳2 4 M368188 待命/忙綠接腳2 5 導線部2 6 導通部2 7 斷線部2 8 導體2 9Press, the conventional flash memory die has a power pin, a ground pin, an input/output pin, a select pin, and a standby/busy machine on one side, and when the memory chips are entered, Stacking the sealing material, according to the way, the pins of each pin are connected to each other by the way of the wire. However, since the memory chip stack package is connected to each other by wire bonding, although the wiring method is more flexible, for the stacked package of the wafer particles, it is necessary to On the entire wafer of the die, different layers are fabricated to make the hood, which makes the design of the hood used in the production of the wafer more complicated, which increases the difficulty of production management and increases the system, and is not based on the customer. Special needs are produced. The main purpose of this creation is not the same, the age of the miscellaneous layout = the cost of the raw silk and the custom-made m = ^ purpose 'this creation is a flash memory chip stack surname = face = control unit; and most mutual heap 4 crystal grains, and each of the two sides of the granules are divided into a plurality of mutually connected power pins, ground pins, M368188 pins and input/exit pins are mutually connected to each other. :=, and each selection foot and standby 峨 _ surgery == ^= Depending on the different layers of the ride, the wire portion plus the two TM hrs and the standby (four) pins are connected to the broken line of the = respectively. (7) The layout will be required [Implementation] The first, second, third and fourth pictures are respectively shown in the schematic diagram of the creation, the block diagram of the first embodiment of the creation, and the sound of the box. And riding/busy miscellaneous connection state of the skin from the stand-up 1 帛 知 之 选择 选择 及 及 及 及 及 及 及 及 及 及 及 : : : : : : : : : : : : : : : : : : : : : : : : A control unit 1 and a plurality of crystal grains 2 are formed. The control unit 1 mentioned above can be a control chip. Each of the dies 2 can be stacked flash memory dies, and each of the dies 2 has a plurality of power pins 2i, ground pins 22, input/output pins 23, and selective connections. Foot 2 4 and standby/busy connection (4) 5, each power pin ^ 1 ground connection 2 2 and input / output pin 2 3 series are connected in parallel with the control unit ' 1 and each selection pin 2 4 and standby / The busy pin 2 5 is directly connected to the control unit 1 and the connection pin 2 4 and the standby/busy green pin 2 5 are respectively connected with the lead portion 2 6 and are respectively connected to the side edges of the respective crystal grains 2 Each of the power supply pins 21, the ground pin 2, the input/output pin M368188 2 3, the 曰 select pin 24, and the standby/busy pin 25 are connected to the conductive portion 27. For example, 上述' constitutes a new flash memory chip stack structure by the above structure. Moreover, when the layout is designed, the majority of the crystal grains 2 can be stacked one upon another, and the respective conductive portions 27 are connected according to different layouts, so that the corresponding or not Corresponding to the power pin 2丄 on both sides of the die 2, the ground pin 2, the input/output pin 2 3, the select pin 2 = 5 are turned on or off according to requirements, and then stacked on each die. It is necessary to disconnect the wire portion 20 by laser cutting so that each of the crystal grains 2 can reach a sister who is easy to perform circuit layout, is easy to manage, reduces manufacturing costs, and meets customization requirements. Please refer to the "5th and 6th" diagrams for the selection pin and standby/busy tear_state steel and the selection pin and standby/busy green pin of this creation example. Connection status diagram. In addition to the structure of the first embodiment described above, the creation of the first line layout is that the connection between Qiu ^ ^ and the busy pin 2 5 is respectively connected. In the case of a broken layout, the required disconnecting portion 28 or conductor 29 is printed in a different stacking manner; thus, the effects mentioned in the above-mentioned first embodiment can be achieved. In summary, the shortcomings of the __ 钟 钟 钟 钟 钟 钟 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦 麦In order to make the time for the patent application, Mai filed a patent application. It has been described in the M368188 standard, which is only the preferred embodiment of this creation. When it is not possible to limit the implementation of this creation, it is simple to make the scope of the application and the content of the creation manual. Equivalent changes and modifications shall remain within the scope of this Creative Patent. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective exploded view of the first embodiment of the present invention. Fig. 2 is a block diagram showing the first embodiment of the present invention. Fig. 3 is a schematic diagram showing the connection state of the selection pin and the standby/busy green pin of the present invention. Selecting the pin and standby/busy green connection Fig. 4 is a schematic diagram showing the disconnected state of the first embodiment of the present invention. Fig. 5 is a schematic view showing the selection pin and the disconnected state of the second embodiment of the present invention. Standby/Busy Pickup and Standby/Busy Connection Figure 6 is a schematic diagram of the connection state of the second embodiment of the present invention. [Main component symbol description] Control unit 1 Die 2 Power pin 21 Ground pin 2 2 Input/Output pin 2 3 Select pin 2 4 M368188 Standby/busy green pin 2 5 Wire part 2 6 Conduction part 2 7 Wire break 2 8 conductor 2 9

Claims (1)

M368188 六、申請專利範圍: 1 . -種快閃s己憶體晶片堆疊結構,其包括: 一控制單元;以及 多數晶粒,制目互堆疊,且各晶粒兩面 數相互導通之電_ 及待命/忙碌接腳,各電源接腳、接地接腳及輸:: ^並聯後触解元触,林·獅鱗命/忙碌 为別直接與控制單元連接,且選擇接腳及待命/忙碌接腳之間 係分別連接有導線部,可於各晶粒佈局時依* 之導線部加以斷開。 吓而 2·依申請專利範圍第i項所述之快閃記憶體晶片堆疊結構,其 中,該控制單元係可為控制晶片。 3 ·依申料概圍第1項所述之快閃記憶體晶#堆疊結構,其 中,各晶粒係可為快閃記憶體晶粒。 4·依申請專利範圍第1項所述之快閃記憶體晶片堆疊結構,其 中,各晶粒兩面上之各電源接腳、接地接腳、輸入/出接腳、 選擇接腳及待命/忙碌接腳連接係分別以設於側緣導通部相互 導通。 5·依申請專利範圍第1項所述之快閃記憶體晶片堆疊結構,其 中’各導線部係以雷射切斷方式加以斷開。 6 ·—種快閃記憶體晶片堆疊結構,其包括: 一控制單元;以及 多數晶粒,係相互堆疊,且各晶粒兩面上係分別設有多 數相互導通之電源接腳、接地接腳、輸入/出接腳、選擇接聊 M368188 及待命/忙碌接腳’各電源接腳、接地接腳及輸入/出接腳係相 互並聯後與控制單元連接’而各選擇接腳及待命/忙碌接腳係 分別直接與控制單元連接,且選擇接腳及待命/忙碌接腳之間 係分別連接有斷線部,可於各晶粒佈局時依不同層疊將所需 之斷線部加以連接。 7依中轉利範圍第6項職之快閃記髓晶片堆疊結構,其 中,該控制單元係可為控制晶片。 、 8 申請專利範圍第6項所述之快閃記憶體晶片堆疊結構,复 中,各晶粒係可為快閃記憶體晶粒。 、 互 中申j利㈣第6項所述之快閃記憶體晶片堆疊結構,其 選擇接上之各電源接腳、接地接腳、輸入/出接腳、 導通。4、叩/忙碌接腳連接係分別以設於侧緣導通部相 9M368188 VI. Patent application scope: 1. A flash s-resonance wafer stack structure, comprising: a control unit; and a plurality of crystal grains, which are stacked on each other, and the two sides of each crystal are electrically connected to each other _ and Standby/busy pins, each power pin, ground pin and input:: ^After the parallel connection, touch the meta-touch, Lin·Lion scale life/busy is not directly connected to the control unit, and select the pin and standby/busy connection Wires are connected between the legs, and can be disconnected according to the wire portion of each of the die layouts. The flash memory chip stack structure described in claim i, wherein the control unit is a control wafer. 3. According to the material of claim 1, the flash memory crystal stacked structure described in claim 1, wherein each of the crystal grains may be a flash memory crystal grain. 4. The flash memory chip stack structure according to claim 1, wherein each power pin, ground pin, input/output pin, select pin, and standby/busy on both sides of each die The pin connection systems are respectively electrically connected to each other by the side edge conduction portions. 5. The flash memory wafer stack structure of claim 1, wherein the wire portions are broken by a laser cutting method. a flash memory chip stack structure comprising: a control unit; and a plurality of dies stacked on each other, and each of the dies is provided with a plurality of mutually connected power pins and ground pins, Input/output pin, select to talk M368188 and standby/busy pin 'each power pin, ground pin and input/exit pin are connected in parallel with the control unit' and each select pin and standby/busy connection The foot systems are directly connected to the control unit, and the disconnecting portions are respectively connected between the selecting pins and the standby/busy pins, and the required disconnecting portions can be connected according to different stacking in each die layout. 7 The flash flash memory chip stack structure of the sixth item of the middle transfer range, wherein the control unit is a control wafer. 8. The flash memory chip stack structure described in claim 6 of the patent application, wherein each of the die systems may be a flash memory die. The flash memory chip stack structure described in item 6 of (b) (4), which is connected to each of the power pin, the ground pin, the input/output pin, and the turn-on. 4, 叩 / busy pin connection system is set to the side edge conduction part phase 9
TW098206272U 2009-04-16 2009-04-16 Stacking structure of flash memory chips TWM368188U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677040B (en) * 2018-12-20 2019-11-11 華邦電子股份有限公司 Integrated circuit and detection method for multi-chip status thereof
US10908211B2 (en) 2019-03-07 2021-02-02 Winbond Electronics Corp. Integrated circuit and detection method for multi-chip status thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677040B (en) * 2018-12-20 2019-11-11 華邦電子股份有限公司 Integrated circuit and detection method for multi-chip status thereof
US10908211B2 (en) 2019-03-07 2021-02-02 Winbond Electronics Corp. Integrated circuit and detection method for multi-chip status thereof

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