M345345 八、新型說明： '【新型所屬之技術領域】 本創作係有關於一種半導體裝置’特別係有關於一 種半導體封裝構造及其使用之複合銲線。 【先前技術】 在半導體裝置的封裝構造中，積體電路晶片必須與 線路基板或是導線架等基板作成電路聯結才能發揮電 性訊號傳遞的功能。習知晶片至基板之電性連接的方法 馨 有打線接合（wire bonding)、捲帶自動接合（tape automated bonding; TAB)與覆晶接合（flip chip)等。其 中，打線接合因其簡易性及便捷性而成為半導體封裝製 程中普通使用之晶片電性連接方法。打線接合是在高溫 下以超音波將銲線（如金線或銅線之細金屬線）藉由打 線機（wire bonder)提供並連接晶片上的銲墊和晶片載 體上連接線路的接指（finger)，以達成晶片與基板之間 φ 的訊號傳遞或是接地/電源的用途。 由於習知晶片之銲墊是鋁墊或銅墊，基板之接指之 金屬材質是銅或銅合金，銲墊與接指的表面容易產生金 屬乳化使付在打線接合時產生銲不黏（η ο η - s t i c k i n g ) 的現象。此外’利用超音波焊接銲線到銲墊或接指時， 須有效控制壓力、睹簡、、、田痒 & ^ 守間’皿度、熱能、及超音波功率等 條件，方能使其緊齋输A，# 士# 糸在鍵合右有其中一條件稍有疏忽， 則鲜線在銲塾或接指上之焊點則容易發生剝離之現象。 此外’隨著產品功能增加與小型化之趨勢，晶片密 4 M345345 度愈高且面積愈小以使每一片晶圓具有較高晶片產 能，這導致晶片的可配置銲墊的面積受限，必須縮短銲 墊之間的距離與銲墊面積，造成銲線之可壓銲面積縮 小。因此，在進行試驗半導體裝置耐用性之溫度循環試 驗時，打線接合之銲線容易發生焊點斷裂之瑕疵。尤其 以銲線之結球端下部發生裂痕較多，或與銲墊產生剝離 現象，嚴重影響半導體封裝產品之可靠度與運作效能。 如第1圖所示，一種習知打線連接之半導體封裝構 ® 造100主要包含一晶片載體110、一晶片120以及至少 一銲線130。該晶片載體110係具有至少一接指m。 該晶片1 20係為半導體材質並設置於該晶片載體1 1 0上 並具有位於其主動面上之一銲墊1 2 1。該銲線1 3 0係以 打線方式形成，該銲線1 3 0係具有一結球端1 3 3，該結 球端1 3 3係接合該晶片1 2 0之該銲墊1 2 1，另一端則接 合該晶片載體110之該接指111，使該晶片12〇與該晶 φ 片載體1 1 0之間形成電性連接。習知該銲線1 3 0係為細 長之可撓性金屬線，例如高純度金線，其線徑面係為圓 形（如第2圖所示），在小銲墊產品或在溫度較高的環境 下（例如溫度循環試驗），該銲線1 3 〇之結球端1 3 3易與 該銲墊1 2 1產生剝離或是裂痕。 如第3圖所示，為習知半導體封裝構造在打線製程 中之元件截面示意圖。首先，如第3圖A所示，利用打 線機（wire bonder)之一銲針（capillary) 1 0進行打線製 程，先於耐高溫之該銲針1 〇内導出該銲線i 3 〇。接著， 5 M345345 如第3圖B所示，刹田 〜用電子點火（spark discharge)技術 將該銲線1 3 〇之線屋钟a 又尾*而電極放電燒出一球體，而成為一 結球端13 3。如第4 ο敗一 圖所不，該結球端1 3 3之直徑係大 於3亥辉線1 3 0之直經。 ^ 之後，如弟3圖C所示，下降該 銲針10，利用該銲斜】 卞1 〇擠壓該結球端1 3 3並辅以壓力 及超音波振盈使該銲綠 于線1 3 0與該銲墊1 2丨接觸磨擦並予 以緊密鍵結。然而，^ I 一 $弟3圖D所示，在完成將該銲線 130與該銲墊121之雷a Λ △ 寬性連接後，該銲線1 3 0之結球端 1 3 3可能因上述提到的 . 的因素而與該銲墊1 2 1之鍵結能力 不^土，在溫度較馬的環也 衣丨兄下（例如溫度循環試驗）或是受 到外力拉扯時，該銲線 、、1 3 〇之該釔球端1 3 3會由該銲塾 121發生剝離’導致焊點盼々 τ X坪點脫洛。該銲線i 3 0之位置更產 生偏離與自由晃動，影塑 如警牛導體封裝產品之良率。 【新型内容】 本創作之主要目的係在於提供一種半導體封裝構造 及其使用之複合銲線，能增加蟬接鍵結能力，避免焊= 脫落，並能提升半導體封裝製程良率及產出值，進而降 低成本。 依據本創作，一種半導體封裝構造主要包含一晶片 載體、一晶片以及一複合銲線。該晶片載體係具有一接 指。該晶片係設置於該晶片載體並具有一銲墊。該複人 銲線係連接該接指與該銲墊，以電性連接該晶片載體與 該晶片，該複合銲線係包含一線主體以及複數條嵌埋於 該線主體内之金屬絲，其中該些金屬絲之硬度係不小於 6 M345345 該線主體，並且兮 係具有-在該結：、端主體係具有—結球端’每-金屬絲 指。本創作還揭示—之刺入端，用以刺入該銲墊或該接 線。 、1使用於半導體封裝構造之複合鮮 本創作的目的另 措施進一步實現。決其技術問題還可採用以下技術 在前述半導體 離，並且該此金屬，構…該些金屬絲係可為分 鸯、、、糸之硬度係大於該線主體。 在刚：4 +導體封生 ^ 成股。 灰構1^中，该些金屬絲係可為捻繞 該些金屬絲之硬度係可 該些金屬絲之材質係可 在前述半導體封袭構造中 概約等於該線主體 在前述半導體封裝 ^ 造中 選自於鈹（Be)、鈀（ ~ ^ "： A / )、鎳（Νι)、鐵（Fe)、銅（Cu)、銀（Ag)、 鉑（Pt)、鉻（Cr)與复人 其合金之其中之一。 在前述半導體封 J展構造中，該線主體之材質係可選 自於金（Au)、锡（s 、鋁（A1)、鉛（Pb)與其合金之其中 之一 〇 在前述半導體扭另 可展構造中，該線主體之導電性係可 大於該些金屬絲。 在前述半導體扭壯 、I構造中，該些金屬絲之溶點係可 大於該線主體之炫點。 在岫述半導體封裝構造中，該線主體之該結球端係 可鍵合於該銲墊，並且該銲墊具有複數個被該些金屬絲 7 M345345 刺入之凹洞。 在前述半導體封裝構造中，該些凹洞係可相對於該 些金屬絲之該些刺入端更為擴大，並且該線主體係填入 該些凹洞，以形成非平面金屬鍵合。 在前述半導體封裝構造中，該銲墊係可為一鋁墊。 在前述半導體封裝構造中，該晶片載體係可為一印 刷電路板。 由以上技術方案可以看出，本創作之半導體封裝構 ® 造及其使用之複合銲線，具有以下優點與功效： 一、 藉由銲線内嵌埋之複數條較硬金屬絲之一端可刺入 晶片之銲墊或是晶片載體之接指，以增加焊接鍵結 能力，可避免某一焊點脫落，故能提升製程良率及 產出值，進而降低成本。 二、 藉由銲線内嵌埋之複數條較硬金屬絲，以增加銲線 線體強度，防止銲線被拉斷。 Φ 三、利用嵌埋銲線内之多條金屬絲為分離狀，以提供在 每一銲墊（或是接指）的複數個凹洞，以利於金屬絲 穿刺銲墊（或是接指），達到電性連接。 四、 利用嵌埋銲線内之多條金屬絲擴大晶片之銲墊之凹 洞，以供銲線之線主體填入，達到非平面的金屬鍵 合，以增進銲線接合強度。 五、 利用嵌埋銲線内之多條金屬絲為捻繞成股，增加銲 線之韌度，可容許較低之金屬絲硬度而與銲線之線 主體概約相等。 8 M345345 【實施方式】 依據本創作之第一具體實施例’一種半導體封裝構 造舉例說明於第5圖之局部截面示意圖。該半導體封裝 構造200主要包含一晶片載體210、一晶片220以及至 少一複合銲線23〇。如圖所繪示者是一個複合銲線 2 3 0 ’亦可為位在該晶片2 2 0其中一侧邊之一排複合銲 線230。複數個複合銲線230可配置於該晶片220之單 一側邊、兩對應側邊、四周側邊或是中央位置。 該晶片載體2 1 〇係具有一接指2 11，可配置於該晶 片載體210之一上表面212。通常該晶片載體210係為 一印刷電路板、一導線架、一電路薄膜或各種晶片載板。 該晶片220係設置於該晶片載體210之該上表面212 並具有一銲墊221。該銲墊221係可為一铭墊或一銅 墊。該銲墊22 1可為複數個。該銲墊22 1係設置於該晶 片220之一主動面222之單一侧邊、兩對應側邊、四周 • 側邊或是中央位置。該主動面222並形成有各式積體電 路元件，電性連接至該銲墊22 1。該晶片220之材質係 可為矽、砷化鎵或其它半導體材質。在本實施例中，可 利用一黏晶層 240，例如膠帶、B階黏膠（B-stage adhesive)或是晶片貼附物 質（Die Attach Material， DAM)’以黏接該晶片220之一背面223至該晶片載體 210之該上表面212，故該晶片載體210之接指211可 接近該晶片載體2 1 〇之一黏晶區域（即被該晶片220之 覆蓋區域）。另可形成一可密封該晶片220與該複合銲 9 M345345 線23 0之封膠體（圖中未繪出）。 該複合銲線23 0係連接該接指2 1 1與該銲墊22 1， 以電性連接該晶片載體2 1 〇與該晶片220，該複合銲線 2 3 0係為可撓性金屬線。在本實施例中，該複合銲線2 3 0 係可為正向打線（forward bonding)形成，在打線接合 時，該複合銲線230在該晶片220之該銲墊221之一端 為結球端（ball bond)23 3，該複合銲線230在該晶片載 _ 體210上的該接指211之另一端為尾鍵合端（或稱訂合 式接合端，stitch bond)，此乃為一般傳統的打線技術， 除了能增加該複合銲線230於該晶片220之該銲墊221 之接合強度並可降低打線成本。具體而言，如第5及6 圖所示，該複合銲線230係包含一線主體231以及複數 條欲埋於該線主體231内之金屬絲232。其中該些金屬 絲2 3 2之硬度係不小於該線主體2 3丨，並且該線主體2 3 1 係具有一結球端2 3 3，每一金屬絲2 3 2係具有一在該結 藝球端233之刺入端234，用以刺入該銲墊221，可增加 該複合銲線230與該銲墊221之焊接鍵結能力（容後詳 述）。包含該線主體231的材料可先熔化以嵌埋該些金 屬絲232，再抽拉成細線。 请芩閱第7圖所示，本創作進一步說明該半導體封 裝構造200之打線製程，以彰顯本案的功效。 育先如第7圖A所示，利用打線機之一銲針2〇進行 打線製程，先於耐高溫之該銲針2〇内置入該複合得線 230,該複合銲線23〇係穿過該銲針2〇之通道。該複合 10 M345345 銲線230内嵌埋了複數條較硬之金屬絲232，可增加銲 線線體強度，防止銲線被拉斷。 接著，如第7圖B所示，利用電子點火技術將該複 合銲線2 3 0之線尾端電極放電燒出一球體，而成為該結 球端23 3。具體而言，該結球端233之直徑係大於該線 主體2 3 1之直徑（如第8圖所示），該些金屬絲2 3 2之熔 點係可大於該線主體2 3 1之熔點，利用高溫下形成之該 結球端2 3 3後，該些金屬絲2 3 2會維持條狀而突出於該 •結球端23 3，以形成該些刺入端234。 之後，如第7圖c所示，下降該銲針2 0，利用該鮮 針20擠壓該結球端233並辅以壓力及超音波振盤使該 複合銲線230之該線主體231與該銲墊221接觸磨擦並 予以緊密鍵結’該些刺入端2 3 4並刺入該銲塾2 2 1，能 增加焊接鍵結能力’可避免焊點脫落，故能提升製程良 率及產出值，進而降低成本。因此，打線參數可具有更 • 為寬廣的製程窗，例如壓力、時間、溫度、熱能、及超 音波功率具有更大的容許彈性，便可達到良好的焊接^ 質。具體而言，該晶片220之該主動面222係形成有一 保護層2 2 5 ’其係為電絕緣材料，用以保護該主動面 並覆蓋該主動面222上配置線路層（圖未繪出），但顯露 該銲墊221。 .最後，如第7圖D所示，完成將該複合銲線23〇與 該銲墊221之電性連接，並且位置能無偏誤的鍵合在指 定位置。詳細而言，如第5圖與第7圖c所示，該銲^ M345345 20係可往上拉引並將該複合銲線230之另一端鍵合在 該晶片載體2 1 0之該接指2 11上並切斷，使其成為一完 整之複合銲線230。M345345 VIII. New description: '[New technology field] This creation is about a semiconductor device', especially for a semiconductor package structure and its composite wire. [Prior Art] In the package structure of a semiconductor device, the integrated circuit chip must be circuit-connected to a substrate such as a circuit board or a lead frame to perform a function of electrical signal transmission. Conventional methods for electrically connecting a wafer to a substrate include wire bonding, tape automated bonding (TAB), and flip chip bonding. Among them, wire bonding has become a method of electrically connecting wafers commonly used in semiconductor packaging processes due to its simplicity and convenience. The wire bonding is to ultrasonically supply a bonding wire (such as a thin metal wire of a gold wire or a copper wire) by a wire bonder at a high temperature and connect the pad on the wafer and the connecting wire on the wafer carrier ( Finger) to achieve the signal transmission of φ between the wafer and the substrate or the use of ground/power. Since the solder pad of the conventional wafer is an aluminum pad or a copper pad, the metal material of the substrate is copper or copper alloy, and the surface of the pad and the finger is prone to metal emulsification, so that the solder is not sticky when the wire is bonded. ο η - sticking ) phenomenon. In addition, when using ultrasonic welding wire to the pad or finger, it is necessary to effectively control the pressure, simplification, itch, amp; ^ stipulation degree, heat energy, and ultrasonic power to make it Tight fasting A, #士# 糸There is a slight negligence in the right side of the bond, the solder joint on the soldering iron or the finger is prone to peeling off. In addition, as the product features increase and miniaturization, the higher the wafer density, the smaller the area and the smaller the area, the higher the wafer throughput per wafer, which results in a limited area of the configurable pads of the wafer. Shorten the distance between the pads and the pad area, resulting in a reduction in the bondable area of the wire. Therefore, in the temperature cycle test for testing the durability of the semiconductor device, the wire bonding wire is prone to breakage of the solder joint. In particular, cracks occur in the lower part of the ball end of the bonding wire, or peeling occurs with the bonding pad, which seriously affects the reliability and operational efficiency of the semiconductor package product. As shown in FIG. 1, a conventional wire-bonded semiconductor package 100 mainly includes a wafer carrier 110, a wafer 120, and at least one bonding wire 130. The wafer carrier 110 has at least one finger m. The wafer 120 is made of a semiconductor material and disposed on the wafer carrier 110 and has a pad 1 21 on its active surface. The bonding wire 130 is formed by wire bonding, the bonding wire 1 30 has a ball end 1 3 3 , and the ball end 1 3 3 is bonded to the pad 1 2 0 of the wafer 1 2 1 Then, the finger 111 of the wafer carrier 110 is bonded to form an electrical connection between the wafer 12 and the crystal chip carrier 110. It is known that the wire 1 30 is a slender flexible metal wire, such as a high-purity gold wire, and its wire diameter surface is circular (as shown in FIG. 2), in a small pad product or at a temperature In a high environment (for example, a temperature cycle test), the ball end 1 3 3 of the wire 1 3 is likely to be peeled off or cracked from the pad 1 2 1 . As shown in Fig. 3, it is a schematic cross-sectional view of a component of a conventional semiconductor package structure in a wire bonding process. First, as shown in Fig. 3A, a wire bonding process is performed using a capillary 10 of a wire bonder, and the bonding wire i 3 〇 is derived before the high temperature resistant pin 1 〇. Next, 5 M345345 As shown in FIG. 3B, the brake field is used to discharge the wire 1 3 to the wire house clock a and the tail by the spark discharge technique, and the electrode discharges a ball to become a ball. End 13 3. As shown in the 4th ο败图, the diameter of the ball end 1 3 3 is larger than the straight line of 3 Haihui line 1 300. ^ After that, as shown in Figure 3 of Figure 3, the soldering pin 10 is lowered, and the ball end 1 3 3 is pressed by the welding 】 1 〇 and the pressure and ultrasonic vibration are applied to make the welding green to the line 1 3 0 is in contact with the pad 1 2 磨 friction and tightly bonded. However, after the completion of the connection between the bonding wire 130 and the solder pad 121, the ball end 1 3 3 of the bonding wire 1 3 may be due to the above. The factors mentioned are not compatible with the bonding ability of the bonding pad 1 2 1 , and the bonding wire is used when the temperature is lower than that of the horse ring (for example, temperature cycle test) or when it is pulled by an external force. The ball end 1 3 3 of the 钇 ball will be peeled off by the wire ' 121, resulting in a solder joint 々 X X X ping point detachment. The position of the wire i 30 is more deviated from the free sloshing, and the yield of the product such as the Bullhorn conductor package product. [New content] The main purpose of this creation is to provide a semiconductor package structure and a composite bonding wire thereof, which can increase the bonding ability, avoid welding, fall off, and improve the yield and output value of the semiconductor packaging process. In turn, the cost is reduced. According to the present invention, a semiconductor package structure mainly comprises a wafer carrier, a wafer, and a composite bonding wire. The wafer carrier has a finger. The wafer is disposed on the wafer carrier and has a pad. The bonding wire is connected to the bonding pad and the bonding pad to electrically connect the wafer carrier and the wafer, the composite bonding wire comprising a wire body and a plurality of wires embedded in the wire body, wherein the wire bonding wire The hardness of these wires is not less than 6 M345345, and the tether has - at the end: the end main system has - the ball end - each wire finger. This creation also reveals the piercing end for piercing the pad or the wire. 1) The purpose of the composite creation of the semiconductor package structure is further achieved. In order to solve the technical problem, the following techniques may be employed in the foregoing semiconductor, and the metal wires may have a hardness greater than that of the wire body. In just: 4 + conductors sealed into ^ shares. In the ash structure, the metal wires may be the hardness of the wires, and the materials of the wires may be substantially equal to the wire body in the semiconductor package structure. It is selected from the group consisting of beryllium (Be), palladium ( ~ ^ ": A / ), nickel (Νι), iron (Fe), copper (Cu), silver (Ag), platinum (Pt), chromium (Cr) and One of the alloys of Fu Ren. In the foregoing semiconductor package structure, the material of the wire body may be selected from one of gold (Au), tin (s, aluminum (A1), lead (Pb) and its alloy, and the semiconductor may be twisted. In the expanded structure, the conductivity of the wire body may be greater than the wires. In the foregoing semiconductor torsion, I structure, the melting points of the wires may be greater than the dazzling point of the wire body. In the configuration, the ball end of the wire body can be bonded to the pad, and the pad has a plurality of holes pierced by the wires 7 M345345. In the foregoing semiconductor package structure, the holes The holes can be enlarged relative to the piercing ends of the wires, and the wire main system fills the holes to form a non-planar metal bond. In the foregoing semiconductor package structure, the pad can be In the foregoing semiconductor package structure, the wafer carrier can be a printed circuit board. As can be seen from the above technical solution, the semiconductor package structure of the present invention and the composite bonding wire used thereof have the following advantages. And efficacy: one The solder pad of the wafer or the finger of the wafer carrier can be pierced by one end of the plurality of hard metal wires embedded in the bonding wire to increase the bonding ability of the soldering wire, thereby avoiding a certain solder joint falling off, thereby improving the process Yield and output value, which in turn reduces costs. 2. A plurality of harder wires embedded in the wire to increase the strength of the wire and prevent the wire from being broken. Φ 3. Using embedded welding The plurality of wires in the wire are separated to provide a plurality of recesses in each of the pads (or the fingers) to facilitate the wire penetration of the pads (or fingers) to achieve electrical connection. The plurality of wires in the embedded wire are used to expand the pits of the pad of the wafer to fill the wire main body of the wire to achieve non-planar metal bonding to improve the bonding strength of the wire bonding. The plurality of wires in the buried wire are twisted into strands, increasing the toughness of the wire, allowing a lower wire hardness to be approximately equal to the wire body of the wire. 8 M345345 [Embodiment] According to the creation First Specific Embodiment 'A semiconductor package construction example The semiconductor package structure 200 mainly includes a wafer carrier 210, a wafer 220, and at least one composite bonding wire 23〇. As shown in the figure, a composite bonding wire 2 3 0 ' The composite bonding wire 230 may be disposed on one side of the wafer 220. The plurality of composite bonding wires 230 may be disposed on a single side, two corresponding sides, four sides or a central position of the wafer 220. The wafer carrier 2 1 has an interface 2 11 and can be disposed on an upper surface 212 of the wafer carrier 210. Typically, the wafer carrier 210 is a printed circuit board, a lead frame, a circuit film or various wafers. The wafer 220 is disposed on the upper surface 212 of the wafer carrier 210 and has a pad 221. The pad 221 can be an inscription pad or a copper pad. The pad 22 1 can be plural. The pad 22 1 is disposed on a single side, two corresponding sides, four sides, a side or a central position of one of the active faces 222 of the wafer 220. The active surface 222 is formed with various integrated circuit components electrically connected to the pad 22 1 . The material of the wafer 220 may be tantalum, gallium arsenide or other semiconductor materials. In this embodiment, a die bond layer 240, such as a tape, a B-stage adhesive, or a Die Attach Material (DAM)' can be used to bond the back surface of the wafer 220. 223 to the upper surface 212 of the wafer carrier 210, so that the finger 211 of the wafer carrier 210 can be adjacent to one of the wafer carrier 21 (ie, covered by the wafer 220). Alternatively, a sealant (not shown) that seals the wafer 220 from the composite weld 9 M345345 line 30 can be formed. The composite bonding wire 230 is connected to the bonding pin 21 1 and the bonding pad 22 1 to electrically connect the wafer carrier 2 1 〇 to the wafer 220. The composite bonding wire 2 3 0 is a flexible metal wire. . In this embodiment, the composite bonding wire 230 can be formed by forward bonding. When the wire bonding is performed, the composite bonding wire 230 is a ball end at one end of the pad 221 of the wafer 220 ( Ball bond) 23 3, the other end of the joint wire 211 of the composite wire 230 on the wafer carrier 210 is a tail bond end (or a stitch bond), which is a conventional The wire bonding technique can increase the bonding strength of the composite bonding wire 230 to the bonding pad 221 of the wafer 220 and can reduce the wire bonding cost. Specifically, as shown in Figs. 5 and 6, the composite wire 230 includes a wire body 231 and a plurality of wires 232 to be buried in the wire body 231. Wherein the hardness of the wires 2 3 2 is not less than the wire body 2 3 丨, and the wire body 2 3 1 has a ball end 2 3 3 , and each wire 2 3 2 has one in the knot art The piercing end 234 of the ball end 233 is used to penetrate the pad 221 to increase the solder bonding capability of the composite wire 230 and the pad 221 (described in detail later). The material containing the wire body 231 may be first melted to embed the metal wires 232 and then drawn into thin wires. Please refer to Figure 7, which further illustrates the wiring process of the semiconductor package structure 200 to demonstrate the efficacy of the case. As shown in Figure 7A, the first step is to use the welding pin 2〇 of the wire bonding machine to perform the wire-bonding process. The welding pin 2 is inserted into the composite wire 230 before the high temperature resistance, and the composite wire 23 is passed through. The soldering pin 2 is a channel. The composite 10 M345345 wire 230 is embedded with a plurality of harder wires 232 to increase the strength of the wire and prevent the wire from being broken. Next, as shown in Fig. 7B, the wire tail electrode of the composite bonding wire 2300 is discharged by electric ignition to burn a sphere to become the ball end 23 3 . Specifically, the diameter of the ball end 233 is greater than the diameter of the wire body 231 (as shown in FIG. 8), and the melting points of the wires 2 3 2 may be greater than the melting point of the wire body 2 31. After the ball end 2 3 3 formed at a high temperature, the wires 2 32 will maintain a strip shape and protrude from the ball end 23 3 to form the piercing ends 234. Thereafter, as shown in FIG. 7c, the soldering pin 20 is lowered, the ball end 233 is pressed by the fresh needle 20, and the line body 231 of the composite bonding wire 230 is supplemented by a pressure and an ultrasonic vibration plate. The pad 221 is in contact with the friction and is tightly bonded. The piercing ends 2 3 4 and the piercing of the pad 2 2 1 can increase the welding bonding ability to prevent the solder joints from falling off, thereby improving the process yield and production. Out of value, which in turn reduces costs. Therefore, the wire bonding parameters can have a wider process window, such as pressure, time, temperature, thermal energy, and ultrasonic power with greater allowable elasticity to achieve good soldering quality. Specifically, the active surface 222 of the wafer 220 is formed with a protective layer 2 2 5 ' as an electrically insulating material for protecting the active surface and covering the active surface 222 with a circuit layer (not shown). But the solder pad 221 is revealed. Finally, as shown in Fig. 7D, the composite bonding wire 23A is electrically connected to the bonding pad 221, and the position can be bonded to the designated position without any deviation. In detail, as shown in FIG. 5 and FIG. 7c, the soldering wire M345345 20 can be pulled up and the other end of the composite bonding wire 230 is bonded to the finger of the wafer carrier 2 1 0. 2 11 and cut off to make it a complete composite wire 230.
詳細而言，如第9圖所示，該線主體23 1之該結球 端233係可鍵合於該銲墊221，並且該銲墊221具有複 數個被該些金屬絲232刺入之凹洞224。該些凹洞224 係可相對於該些金屬絲232之該些刺入端234更為擴 大’並且該線主體23 1係填入該些凹洞224，以形成非 平面金屬鍵合，可增進該複合銲線23 0之接合強度。 具體而言，該些金屬絲232係可為分離（如第6及9 圖所示），可提供在該些銲墊22 1的該些個分散凹洞 224 ’以利於該些金屬絲232穿刺該些銲墊221，達到 電性連接。並且該些金屬絲232之硬度係大於該線主體 231，可增加該複合銲線230之線體強度，防止銲線被 拉斷。此外，該些金屬絲232係可為相同材質，並可為 相同粗細形狀，但不受限地，在另一較佳實施例中，該 些金屬絲232係可為不相同材質，不同材質擁有不同成 份組成和特性，以構成較佳組合，使整條之複合銲線 23〇具有極佳的機械強度而不易被拉斷。詳細而言，該 線主體23i之材質係可選自於金（Au)、錫（sn)、鋁（ai)、 釓（Pb)與其合金之其中之一。該些金屬絲2叨之材質係 可選自於鈹（Be)、鈀（Pd)、鎳（Ni)、鐵（以）、銅（cu)、銀 (Ag)、翻(Pt)、鉻(Cr)與其合金之其中之一。例如該線 主體如之材質係可為金，可提供較佳之可鍛性和延展 12 M345345 4 性；該些金屬絲232之材質係可為鈹，具有較高硬度與 較高之熔點。 較佳地，該線主體23 1之導電性係可大於該些金屬 絲232，依據電流集膚效應將由該線主體23 1提供電流 通道以達電性連接之功能，故由該些金屬線2；52提高焊 接之鍵結能力與鋼性，便可不考慮該些金屬線232的導 電性。 此外，本創作不限制打線之方向，在另一較佳變化 _ 例中，如第1 〇圖所示，該複合銲線2 3 0係可為逆向打 線（reverse bonding)形成。即將該複合銲線230之該社 球端233熱壓接於在該晶片載體210之該接指211，尾 踹則熱壓接在該晶片2 2 0之該銲塾2 2 1。位在該結球端 2 3 3之該些刺入端2 3 4，則刺入該接指2 1 1，增加該複 合銲線23 0與該接指2 1 1之焊接鍵結能力。 依據本創作之第二具體實施例，另一種半導體封梦 Φ 構造舉例說明於第11圖之局部截面示意圖。該半導體 封裝構造300主要包含一晶片載體210、一晶片220以 及一複合銲線2 3 0。其中與第一實施例相同的主要元件 將以相同符號標示，故可以理解亦具有上述功效，不再 予以贅述。 如第1 1圖所示，在本實施例中，該複合銲線2 3 〇在 該線主體23 1内之複數個金屬絲23 2係可為撿繞成股， 炎為不分離（如弟1 2圖所示），可組成一較粗之金屬絲， 增加該複合銲線2 3 0之勃度。較佳地，該些金屬絲2 3 2 13 M345345 之硬度係可概約等於該線主體23 1之硬度，即可容許較 低之金屬絲232硬度而與該複合銲線23〇之該線主體 23 1概約相等，而毋須採用高硬度材質之金屬絲232， 以增加材質之選用彈性。 具體而言’捻線的方法有以一條或四條金屬絲232 為中心’其餘周圍之金屬絲23 2以此為圓心向同一方向 捲繞之「同心检法」。也有以全部的金屬絲23 2為一體， φ 向同方向捲繞的「集合捻法」。也有採取折衷的「複合 捺法」。而將多條金屬絲232捻成一粗的複合銲線230。 在本實施例中’該複合銲線23 0係以集合捻法捲繞而 成。故使該些金屬絲232係可沿著該複合銲線230之一 中心線螺旋旋轉（如第1 3圖所示）。 此外’在本實例中，該複合銲線23 0之該線主體23 1 内係欣埋了四條金屬絲2 3 2並捻繞成股，但不受限地， 也了 /、有兩條或二條。在不同實施例中，每一複合銲線 鲁内了以包含更多之金屬絲232，藉以增加銲線強 度防止杯線被拉斷，當該刺入端2 3 4刺入該銲墊2 2 1 時此增加焊接鍵結能力，可避免焊點脫落，故能提升 製矛良率及產出值，進而降低成本。該線主體231可由 電錢方去形成在該些金屬、絲2 3 2之外徑表面。 、上所述’僅是本創作的較佳實施例而已，並非對 J乍作任何形式上的限制，雖然本創作已以較佳實施 例揭露如卜，# 声 然而並非用以限定本創作，任何熟悉本項 技術者’在不脫離本創作之中請專利範圍内，所作的任 14 M345345 皆涵蓋於本創作的技 何簡單修改、等效性變化與修飾 術範圍内。 【圖式簡單說明】 ^1圖：習知半導體封裝構造之局部截面示意圖。 ^ 23圖：.f知半導體封裝構造所使用之銲線截面示意圖。 .圖驾知半；體封裝構造在打線製程中之元件截面示 意圖。In detail, as shown in FIG. 9, the ball end 233 of the wire main body 23 1 can be bonded to the pad 221, and the pad 221 has a plurality of holes pierced by the wires 232. 224. The recesses 224 are enlarged relative to the piercing ends 234 of the wires 232 and the wire bodies 23 1 are filled into the holes 224 to form non-planar metal bonds, which can be improved. The bonding strength of the composite bonding wire 230. Specifically, the wires 232 can be separated (as shown in FIGS. 6 and 9), and the plurality of dispersing holes 224 ′ of the pads 22 1 can be provided to facilitate the puncture of the wires 232 . The pads 221 are electrically connected. Moreover, the hardness of the wires 232 is greater than the wire body 231, which can increase the strength of the wire of the composite wire 230 and prevent the wire from being broken. In addition, the wires 232 may be the same material and may have the same thickness, but without limitation, in another preferred embodiment, the wires 232 may be different materials, and different materials have different materials. The composition and characteristics of the different components are combined to form a preferred combination, so that the entire composite wire 23 has excellent mechanical strength and is not easily broken. In detail, the material of the wire main body 23i may be selected from one of gold (Au), tin (sn), aluminum (ai), bismuth (Pb) and its alloy. The materials of the wires 2 may be selected from the group consisting of beryllium (Be), palladium (Pd), nickel (Ni), iron (or), copper (cu), silver (Ag), turn (Pt), and chromium ( One of Cr) and its alloys. For example, the wire body may be made of gold, which provides better forgeability and extension 12 M345345 4; the wire 232 may be made of barium having a higher hardness and a higher melting point. Preferably, the wire body 23 1 has a conductivity greater than the wires 232, and the current body is provided by the wire body 23 1 to electrically connect according to the current skin effect, so that the wires 2 are 52 improves the bonding ability and rigidity of the solder, and the conductivity of the metal wires 232 can be ignored. Further, the present creation does not limit the direction of the wire bonding. In another preferred variation, the composite wire 2 30 can be formed by reverse bonding as shown in Fig. 1 . That is, the ball end 233 of the composite wire 230 is thermocompression bonded to the finger 211 of the wafer carrier 210, and the tail is thermocompression bonded to the pad 2 2 1 of the wafer 2200. The piercing ends 2 3 4 located at the ball end 2 3 3 pierce the fingers 2 1 1 and increase the solder bonding ability of the composite wire 230 and the finger 2 1 1 . According to a second embodiment of the present invention, another semiconductor encapsulation Φ configuration is illustrated in a partial cross-sectional view of FIG. The semiconductor package structure 300 mainly includes a wafer carrier 210, a wafer 220, and a composite bonding wire 230. The same elements as those in the first embodiment will be denoted by the same reference numerals, and it is understood that they have the above-mentioned effects and will not be described again. As shown in FIG. 1 , in the embodiment, the plurality of wires 23 2 of the composite wire 2 3 in the wire main body 23 1 can be wound into a strand, and the inflammation is not separated (such as As shown in Fig. 2, a thicker wire can be formed to increase the bristles of the composite wire 2300. Preferably, the hardness of the wires 2 3 2 13 M345345 can be approximately equal to the hardness of the wire main body 23 1 , that is, the lower wire 232 hardness can be allowed to be the same as the composite wire 23 23 1 is about equal, and it is not necessary to use a wire 232 of high hardness material to increase the flexibility of the material. Specifically, the method of "twisting" has a "concentric test" in which the remaining circumference of the wire 23 2 is wound in the same direction as the center of the wire. There is also a "collection method" in which all the wires 23 2 are integrated and φ is wound in the same direction. There is also a "composite method" that takes a compromise. The plurality of wires 232 are twisted into a thick composite wire 230. In the present embodiment, the composite bonding wire 230 is wound by a collective crucible method. Therefore, the wires 232 can be spirally rotated along a center line of the composite wire 230 (as shown in Fig. 13). In addition, in the present example, the wire main body 23 1 of the composite bonding wire 230 is buried with four wires 2 3 2 and twisted into a strand, but without limitation, also has two or Two. In various embodiments, each composite wire is included to contain more wires 232, thereby increasing the wire strength to prevent the cup wire from being broken, and piercing the pad 2 2 4 when the piercing end 2 3 4 penetrates the pad 2 2 At 1 o'clock, the welding bonding ability is increased to avoid the solder joint falling off, so that the spear yield and output value can be improved, thereby reducing the cost. The wire body 231 can be formed on the outer diameter surface of the metal and wire 2 3 2 by an electric money. The above description is merely a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the preferred embodiment, the sound is not intended to limit the creation. Anyone who is familiar with the technology 'without the scope of the patent, the 14 M345345 is covered by the simple modification, equivalence change and modification of the creation. [Simple description of the figure] ^1: A partial cross-sectional view of a conventional semiconductor package structure. ^ 23 Figure: Schematic diagram of the cross-section of the wire used in the semiconductor package construction. Figure shows the cross-section of the component package structure in the wire bonding process.
第圖·白知半導體封裝構造所使用之銲線在結球端之水 平截面示意圖。 第5圖：為依據本創作第—具體實施例的一種半導體封裝 構造之局部截面示意圖。 第6圖·為依據本創作第一具體實施例的該半導體封裝構 造所使用之銲線截面示意圖。 ^囷為依據本創作第一具體實施例的該半導體封裝構 造在打線製程中之元件截面示意圖。 第8圖：為依據本創作第一具體實施例的該半導體封裝構 造所使用之銲線在結球端之水平截面示意圖。 第9圖··為依據本創作第一具體實施例的該半導體封裝構 造在結球端之縱向截面示意圖。 第1 〇圖··為依據本創作第一具體實施例另一變化例的一 種半導體封裝構造之局部截面示意圖。 第11圖··為依據本創作第二具體實施例的另一種半導體 封裝構造之局部截面示意圖及所使用之銲線局部 放大截面示意圖。 15 M345345 第12圖：為依據本創作第二具體實施例的該半導體封裝 構造所使用之銲線放大截面示意圖。 第1 3圖·為依據本創作第二具體實施例的該半導體封裝 構k所使用之銲線局部放大之立體透視圖。 【主要元件符號說明】Figure 1. Schematic diagram of the horizontal cross section of the wire used in the package structure of Baizhi Semiconductor at the ball end. Fig. 5 is a partial cross-sectional view showing a semiconductor package structure in accordance with a first embodiment of the present invention. Fig. 6 is a cross-sectional view showing a wire used in the semiconductor package structure according to the first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view of an element of a semiconductor package constructed in accordance with a first embodiment of the present invention in a wire bonding process. Fig. 8 is a horizontal cross-sectional view showing the bonding wire used in the semiconductor package structure according to the first embodiment of the present invention at the ball end. Fig. 9 is a longitudinal cross-sectional view showing the semiconductor package structure according to the first embodiment of the present invention at the ball end. Fig. 1 is a partial cross-sectional view showing a semiconductor package structure according to another modification of the first embodiment of the present invention. Fig. 11 is a partial cross-sectional view showing another semiconductor package structure according to a second embodiment of the present invention and a partially enlarged cross-sectional view of the bonding wire used. 15 M345345 Fig. 12 is an enlarged schematic cross-sectional view of a bonding wire used in the semiconductor package construction according to the second embodiment of the present invention. Fig. 13 is a partially enlarged perspective perspective view of a bonding wire used in the semiconductor package k according to the second embodiment of the present invention. [Main component symbol description]
10 銲針 20 銲針 100 半導體封裝構造 110 晶片載體 111 接指 120 晶片 121 銲墊 130 銲線 133 結球端 200 半導體封裝構造 210 晶片興體 211 接指 212 上表面 220 晶片 221 銲墊 222 主動面 223 背面 224 凹洞 225 保護層 230 複合銲線 231 線主體 232 金屬絲 233 結球端 234 刺入端 240 黏晶層 300 半導體封裝構 造 1610 Solder pin 20 Solder pin 100 Semiconductor package structure 110 Wafer carrier 111 Finger 120 Wafer 121 Pad 130 Bond wire 133 Ball end 200 Semiconductor package structure 210 Wafer 211 Contact 212 Upper surface 220 Wafer 221 Pad 222 Active surface 223 Back surface 224 cavity 225 protective layer 230 composite wire 231 wire body 232 wire 233 ball end 234 piercing end 240 die layer 300 semiconductor package structure 16