M345344 八、新型說明： 【新型所屬之技術領域】 本創作係有關於-種半導體裝置，特別係有關於— 種具非陣列凸塊之覆晶封裝構造。 【先前技術】 按，在以往的半導體封裝構造内部由晶片至基板的 電性連接方式可區分為覆晶接合（fHp chip b〇nd)與打線 •連接（wh bond)兩大類。打線連接是晶片主動面朝上 (遠離基板）的型態設置於基板，並藉由銲線使晶片電性 連接至基板，晶片可供銲線接合的電極（或稱為銲墊）是 呈非陣列配置，例如位於晶片主動面之周邊區域或中央 區域。習知的窗π型球格陣列（wBGA)封裝構造所使用 的曰曰片便具有位於晶片主動面中央之電極。另一方面而 言，覆晶接合是預先在晶片主動面設置凸塊，以晶片主 動面翻轉（朝向基板）的型態設置於基板，並藉由凸塊電 •性連接至基板。由於凸塊提供晶片與基板之間一種較短 的電性連接路徑，可使晶片内更高工作頻率的積體電路 有良好的高頻訊號的傳輸品質。因此，覆晶接合是先 進半導體裝置的必然發展趨勢，愈來愈高工作頻率的晶 不㈢文限於銲線長度的封裝瓶頸而能求得更快的處 速度與更高的效能。 在覆晶接合過程中，凸塊必須呈陣列配置，否則晶 片無决獲得均勻而良好的支撐，導致晶片傾斜問題。因 即使晶片的電性功能相同，例如記憶體，但依打線 4 M345344 連接與覆晶接合之用途不同，晶片便會有所不同。換言 之’習知打線連接之晶片並無法進行覆晶接合，通常習 知覆晶接合之晶片須另外進行一重八 ^ 更刀配線路（RDL)製 程’以產生陣列配置並可供設詈Α換 且1 4 1,、σ又直凸塊之UBM銲墊。然 而在打線接合到覆晶接合之轉換過程，有人嘗試沿用習 知打線接合之晶片加以製作為覆晶接合之封裝型態，即 具非陣列凸塊之覆晶封裝構造，以使晶片具有共^性。 如能採用打線接合之晶片，則可省放去 | 日日乃 則T ,略重分配線路（RDL) 製程的時間與材料成木、維招嘉口 J丨τ取+ 縮妞產叩研發時程，深具降低 製造成本之誘因。 請參閱帛1圖所示，一種習知具非陣列凸塊之覆晶 封裝構1 0 0係包含一基板i丨〇、一打線接合之晶片 120、一封膠體150以及複數個外接端子17〇。該基板 11 〇係具有一上表面111、一下表面丨丨2以及複數個形 成在忒上表面1 1 1之接合墊1 1 3。該晶片1 2 〇係設置於 | 該基板1 1 0之該上表面1 1 i並具有複數個打線形成之結 線凸塊（stud bump)l 22，該些凸塊122係為非陣列配置 並以釘頭凸點焊接（SBB，stud bump bonding)方式接合 至該些接合墊1 1 3。例如當該晶片1 20原為適用於窗口 型球格陣列封裝之應用，該些凸塊1 22則位於該晶片 1 2 0之中央區域。該封膠體丨5 〇係壓模形成在該基板1丄〇 之該上表面111並密封該晶片12〇。該些外接端子170 係設置於該基板丨i 〇之該下表面i丨2。請參閱第2圖所 示’该覆晶封裝構造1 〇 〇之製造方法包含以下步驟：「提 5M345344 VIII. New Description: [New Technology Field] This creation is about a kind of semiconductor device, especially related to the flip chip package structure with non-array bumps. [Prior Art] According to the conventional semiconductor package structure, the electrical connection from the wafer to the substrate can be divided into two types: fHp chip b nd and wh bond. The wire bonding is a pattern in which the active surface of the wafer faces upward (away from the substrate), and the wafer is electrically connected to the substrate by a bonding wire. The electrode (or solder pad) to which the wafer can be bonded by the bonding wire is non-wired. The array configuration, for example, is located in a peripheral region or a central region of the active surface of the wafer. The ruthenium used in the conventional windowed π-type ball grid array (wBGA) package construction has electrodes located in the center of the active surface of the wafer. On the other hand, flip chip bonding is performed by previously providing a bump on the active surface of the wafer, and is placed on the substrate in a pattern in which the principal surface of the wafer is inverted (toward the substrate), and is electrically connected to the substrate by bumps. Since the bump provides a short electrical connection path between the wafer and the substrate, the integrated circuit of the higher operating frequency in the wafer can have good high-frequency signal transmission quality. Therefore, flip chip bonding is an inevitable development trend of advanced semiconductor devices. Increasingly, the operating frequency of the crystal is limited to the package bottleneck of the wire length and can achieve faster speed and higher efficiency. During the flip chip bonding process, the bumps must be arranged in an array, otherwise the wafer is inevitably obtained uniform and good support, resulting in wafer tilt problems. Because even if the electrical functions of the wafer are the same, such as memory, the wafer will be different depending on the purpose of the bonding of the wire 4 M345344 and the flip chip bonding. In other words, the conventional wafers that are connected by a wire cannot be flip-chip bonded. Generally, a flip chip bonded wafer must be additionally subjected to a single process (RDL) process to generate an array configuration and can be replaced. 1 4 1, σ and UBM pads with straight bumps. However, in the conversion process of wire bonding to flip chip bonding, it has been attempted to fabricate a package of flip-chip bonding using a conventional wire bonded wafer, that is, a flip chip package structure having non-array bumps, so that the wafer has a total of ^ Sex. If you can use the wire bonding chip, you can save it | Japanese and Japanese T, slightly redistributed line (RDL) process time and materials into wood, Wei Zhaojiakou J丨τ take + shrink girl production and development Cheng, has a deep incentive to reduce manufacturing costs. Referring to FIG. 1 , a conventional flip-chip package having a non-array bump includes a substrate i , a wire bonded wafer 120 , a gel 150 , and a plurality of external terminals 17 . . The substrate 11 has an upper surface 111, a lower surface 丨丨 2, and a plurality of bonding pads 1 1 3 formed on the upper surface 11 1 . The wafer 12 is disposed on the upper surface 1 1 i of the substrate 1 10 and has a plurality of wire-forming bump bumps 22, which are non-array configurations and A pad bump bonding (SBB, stud bump bonding) is applied to the bonding pads 113. For example, when the wafer 120 is originally suitable for use in a window type ball grid array package, the bumps 1 22 are located in a central region of the wafer 120. The sealant 丨5 压-type stamper is formed on the upper surface 111 of the substrate 1 并 and seals the wafer 12 〇. The external terminals 170 are disposed on the lower surface i2 of the substrate 丨i 。. Please refer to Fig. 2, the manufacturing method of the flip chip package structure 1 包含 包含 includes the following steps:
M345344 供基板」步驟1、「覆晶接合」步驟2、「封膠」 以及「設置外接端子」步驟4。在步驟2中，該晶 無支撐點，僅以該晶片1 2 0中央區域之該些凸塊 合至該基板1 1 〇之該些接合墊1 1 3，無法控制該晶 與該基板1 1 0之平行度與間隙。在「封膠」步驟 形成該封膠體1 5 〇之模流壓力沖擊該晶片1 2 〇而 生如同蹺蹺板般上下擺動的情況（如第丨圖所示） 該晶片1 20傾斜壓觸該基板丨丨〇之線路或是該 1 22之焊點斷裂，進而影響電性連接品質。並且 驟3中’缺乏周邊支撐力之該晶片120亦容易受 之影響而產生傾斜。而該些外接端子丨7〇則是在 中設置。 【新型内容】 有馨於此’本創作之主要目的係在於提供 陣列凸塊之覆晶封裝構造，能在覆晶接合與到 中&制晶片與基板之間的平行度與間陈，以 陣列凸塊之覆晶封雖 是曰曰封凌構造之品質。因此，本創 習知打線接合曰y 艮搔口曰曰片直接封裝成覆晶封裝構造 斜與凸塊焊點斷裂等問題。 本創作之次—B从 H的係在於提供一種具非陣 覆晶封装構造，能/ l在覆晶接合之過程中，僅控 基板之間的平行度與間隙，使得晶片可作XY ’月 故此以釘碩凸點焊接（SBB)方式接合至 創作的目的及解決其技術問題是採用以 步驟3 片120 122接 片120 3中， 易於發 ’造成 些凸塊 ，在步 到模流 步驟4 種具非 之過程 昇具非 能解決 晶片傾 凸塊之 晶片與 面震盪 fe ° 技術方 M345344 案來實現的。依據本創作之一種具非陣列凸塊之覆晶封 裝構le主要包含一基板、一晶片、複數個間隔球、複 數個黏著膠以及一封膠體。該基板係具有一上表面以及 一下表面，该上表面係形成有複數嗰接合墊。該晶片係 設置於該基板之該上表面，該晶片之一主動面係設有複 數個凸塊’其中該些凸塊係為非陣列設置並接合至該些 接合塾。該些間隔球係設置於該基板之該上表面以介設 於該基板與該晶片之間，該些間隔球係支撐該晶片之該 主動面之周邊。該些黏著膠係設置於該基板之該上表面 並黏附該些間隔球。該封膠體係形成於該基板之該上表 面並密封該晶片。 本創作的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述覆晶封裝構造中，該些間隔球的球徑係可界 定該基板與該晶片之間之間隙。 在前述覆晶封裝構造中，該黏著膠之材質係可為環 氧樹脂（epoxy)。 在前述覆晶封裝構造中，該基板係可具有複數個線 路，其係形成於該基板之該上表面。 在前述覆晶封裝構造中，該些間隔球係可不直接下 壓至該些線路。 在箣述復曰曰封裝構造中，可另包含一底部填充膠， 係填滿該基板與該晶片之間之間隙以密封該些凸塊。 在前述具非陣列凸塊之覆晶封裝構造中，該底部填 :M345344 充膠係可覆蓋該些線路。 在别述覆晶封裝構造中，可另包含複數個外接端 子，其係設置於該基板之該下表面。 在前述覆晶封裝構造中，該些凸塊係可為結線凸塊， 該些間隔球係可不黏著該晶片，僅用以控制該晶片與該基板 之間的平行度與間隙，當該晶片以釘頭凸點焊接（SBB)方式 接合至該基板，該晶片為XY平面震盪滑動。 _ 在前述覆晶封襞構造中，該晶片係可為記憶體晶片。 在前述覆晶封裝構造中，該晶片係可為跨封裝型態之 中尚頻記憶體晶片，其係選自於53 3Mhz至l 600Mhz的 第二代雙倍資料率同步動態隨機存取記憶體（DDR2 DRAM)記憶體晶片。 本創作還揭示另一種具非陣列凸塊之覆晶封裝構 造，主要包含一基板、一晶片、複數個間隔黏著件以及 一封膠體。該基板係具有一上表面以及一下表面，該上 表面係設有複數個接合塾。該晶片係設置於該基板之該 上表面’該晶片之一主動面係設有複數個凸塊，其中該 些凸塊係為非陣列設置並接合至該些接合墊。該些間隔 黏著件係設置於該基板之該上表面以介設於該基板與 該晶片之間，該些間隔黏著件係黏附該晶片之該主動面 之周邊。該封膠體係形成於該基板之該上表面並密封該 晶片，並且該封膠體係填滿該基板與該晶片之間之間隙 以密封該些凸塊。 由以上技術方案可以看出，本創作之具非陣列凸塊 8 :M345344 之覆晶封裝構造，右v ^ 有以下優點與功效： 一、利用間隔球痞n j^ α 八a間b黏著件之設置位置能提供 、 **力使在覆晶接合或/與封膠之過程 有晶片傾斜的問題。因此’打線接合之晶片 用陡可沿用而封裝成具非陣列凸塊之覆晶 造。 一、 藉由黏著膠黏接間隔球於基板上或是間隔黏 Φ 表面柔軟特性，以確保支撐效果。故能僅控 與基板之間的平行度與間隙，使得晶片可作 面震盡滑動進行釘頭凸點焊接（SBB)方式的 合。 二、 利用間隔黏著件具有電絕緣性之特性，能避 電性短路現象。 四、由於間隔球係不直接下壓基板之線路，能避 受到擠壓而受損。 _ 五、藉由底部填充膠或封膠體填入覆晶間隙，以 路並具有保護線路之功效，使得基板不需另 坪層，藉以降低製造成本。 【實施方式】 依據本創作之第一具體實施例，一種具非陣 之覆晶封裝構造舉例說明於第3圖之截面示意圖 圖為该覆晶封裝構造之製造流程圖。 該覆晶封裝構造200主要包含一基板210、 220、複數個間隔球230、複數個黏著膠240以 曰θ曰片周 中不會 具有共 封裝構 著件的 制晶片 ΧΥ平 覆晶接 免造成 免線路 覆蓋線 形成防 列凸塊 。第4 一晶片 及一封 9 M345344 膠體250。该基板210係具有一上表面211以及一下表 面2 1 2 ’該上表面2 1 1係形成有複數個接合墊2丨3。該 基板2 1 0係可為印刷電路板、陶瓷基板或玻璃基板。在 本實施例中，該些接合墊2 1 3係可為一直線或多條平行 直線的排列方式設置於該上表面2 1 1之中央區域（如第 4圖A所示）。 請參閱第3圖所示，該晶片220係設置於該基板210 _ 之該上表面2 1 1。該晶片220係可為記憶體晶片，更具 體地，該晶片220係可為DDR2或DDR3記憶體晶片。 並且，該晶片220之一主動面221係設有複數個凸塊 222，其中該些凸塊222係為非陣列設置並接合至該些 接合墊2 1 3。「非陣列設置」係指不是按照N行數乘以 Μ列數的矩陣方式排列，其中n與Μ是大於二的正整 數，並且凸塊設置區域遠小於該晶片220之該主動面 221，至少應在二分之一以下。換言之，該些凸塊222 ❿ 是不藉由重配置線路（RDL)製程的分散調整，而集中在 晶片主動面之某一區域。在本實施例中，該些凸塊222 係可位於該主動面22 1之中央區域並可為線性排列，其 中該些凸塊222係與該些接合墊213相互對應（如第4 圖Β所示）。該些凸塊222係可為金凸塊、銅凸塊或疋 其他導電材質之複合凸塊。在本實施例中，該些凸塊 222係為打線形成之結線凸塊（stud bump)，並以釘頭办 點焊接（SBB)方式接合至該些接合墊213。更具體而論’ 釘頭凸點焊接（SBB)係令該些凸塊222與該些接合墊213 10 :M345344 之間產生超音波震盪摩擦所形成之金金鍵合或其它金 屬鍵合。其中，超音波震盪是在XY平面（即是與晶片 主動面22 1平行的一平面）作快速往復微移動，以達到 低溫金屬鍵合。而較佳地，往復微移動方向應與該些凸 塊222的線性排列方向為垂直，以避免該些凸塊222在 超音波震堡過程產生短路接合。本創作之其中一具體功 效便是利用該些間隔球230與該些黏著膠240之結合關 _ 控制該晶片2 2 0與該基板2 1 〇之間的平行度與間隙，以 維持晶片支撐效果又可達成釘頭凸點焊接（SBb)方式的 覆晶接合，理由如下雨段所述。 請參閱第3圖所示，該些間隔球2 3 0係設置於該基 板2 1 0之該上表面2丨1，以介設於該基板2丨〇與該晶片 2 2 0之間，該些間隔球2 3 0係支撐該晶片2 2 0之該主動 面2 2 1之周邊。藉由這樣的組合，在覆晶接合步驟中， 該晶片220之主動面221並不被該些間隔球230黏著， φ 可作XY平面超音波震盪的滑動。具體而言，該些間隔 球230係遠離該晶片220之該些凸塊222且鄰近該晶片 之該主動面之周邊，以提供較佳的晶片可滑動支撐效 果。更具體而言，該些間隔球2 3 0之球徑係可不大於該 晶片220之該些凸塊222之高度，以確保該晶片220與 該基板2 1 0之間之鍵合。請參閱第3圖所示，該些間隔 球230的球徑係用以界定該基板210與該晶片220之間 之間隙S1，概約等於該晶片220之該主動面221至該 基板2 1 0之該上表面2 11之垂直距離。其中，該些間隔 M345344 辱 * 球2 3 0應具有相同的球徑。 請參閱第3圖所示，該些黏著膠 板2 1 0之該上表面2 1 1並黏附該些間 該些黏著膠240係用以將該些間隔球 2 1 0之該上表面2 1 1，以避免該些間嗎 在本實施例中，該些黏著膠240係不 該主動面221。該些黏著膠240的固 23 0能穩固設置於該基板2 1 0上，而 的固化可執行在覆晶接合步驟之後 23 0能用以界定上述之覆晶接合間隙 些黏著膠240沾附至該晶片220之言系 固化之前仍不會黏著該晶片220，以 晶接合步驟中可作ΧΥ平面的超音波 些黏著膠2 4 0係遠離該基板2 1 0之該 避免污染該些接合墊2 1 3。在本實施4 φ 之材質係可為環氧樹脂（epoxy)。 在本實施例中，請參閱第3圖所 可具有複數個線路2 1 4，其係形成於 表面21 1。較佳地，如第4圖A所示 係可不直接下壓至該些線路214，； 2 1 4受到擠壓的應力而受損，進而i 質。在本實施例中，請參閱第3圖所 與該些接合墊213係可為同一線路層 該些線路2 1 4係可為裸線設計，可不 240係設置於該基 P鬲球2 3 0。因此， 230限制在該基板 i球2 3 0產生位移。 黏接該晶片220之 化使得該些間隔球 在該些黏著膠240 ，以使該些間隔球 S1，並且，即使該 :主動面221，在未 使該晶片220在覆 震盪。較佳地，該 :些接合墊2 1 3，以 Η中，該黏著膠240 示，該基板2 10係 該基板2 1 0之該上 ，該些間隔球230 故可避免該些線路 影響電性傳輸的品 示，該些線路214 。在本實施例中， 被防焊層所覆蓋， 12 M345344 這是由於該晶片220在該些間隔球230之支持之τ ώ斗 ▼ <卜興该 基板2 1 0之間具有良好的平行度與精準的覆晶接人縫 隙。 請參閱第3圖所示，該封膠體25〇係形成於該基板 210之該上表面211並密封該晶片22〇，提供適當的封 裝保護並可防止塵埃污染。該封膠體2 5 〇係可為壓模（或 稱轉移成形，transfer molding)的技術加以形成。 , 在本實施例中，請參閱第3圖所示，該覆晶封裝構 造200可另包含一底部填充膠26〇，其係填滿該基板2 ι〇 與该晶片2 2 0之間之間隙s 1以密封該些凸塊2 2 2，以 避免應力集中在特定凸塊222而斷裂。該底部填充膠 260係可覆蓋該些線路214。具體而言，該底部填充膠 2 60係可猎封該些黏著膠24〇，其中該底部填充膠26〇 更覆蓋至δ亥晶片2 2 〇之局部側邊，有助於固定該晶片 220以避免該晶片22〇位移。由於該間隙si可精準控 | 制在一固定值’故利用毛細作用該底部填充膠2 6 〇能順 利地填滿該間隙S1，不會内藏氣泡。 在本實施例中，請參閱第3圖所示，該覆晶封裝構 把2 〇 〇可另包含複數個外接端子2 7 0，其係設置於該基 板210之該下表面212，以供作為輸入端及/或輸出端以 使該覆晶封裝構造2〇〇可表面接合到一外界裝置，例如 一印刷電路板（圖中未繪出）。該些外接端子27〇係可為 録球、錫貧、金屬接觸墊或插針。 因此’藉由該些間隔球23〇與該些黏著膠24〇之設 13 M345344 置位置能提供該晶片220之周邊較佳的支撐效果，使得 在覆晶接合時能使該晶片220達到平衡而不會產生上 下擺動，以及在封膠時能避免該晶片220受模流壓力影 響而產生傾斜，故該覆晶封裝構造200不會有晶片傾斜 之問題，更能確保該晶片220與該基板210之間之電性 連接品質。並且，該些黏著膠240係黏接該些間隔球 23 〇，故能防止因該些間隔球23 0產生位移而造成無法 _ 有效支撐該晶片220之問題。另可利用該底部填充膠 26〇使得該晶片220能更穩固的設置在該基板210上， 以避免該晶片220受模流壓力之影響產生傾斜，更可避 免因應力集中造成凸塊222焊點斷裂之問題。此外，該 底部填充膠260係覆蓋該些線路2 1 4，便可達到保護該 些線路2 1 4之功效，故該基板2 1 0不需另形成防焊層， 以節省製造成本。 本創作進一步說明前述非陣列凸塊之覆晶封裝 叹辑造 • 200之製造方法，舉例說明於第4圖之流程圖。 首先’明參閱弟4圖Α所不’提供該基板21 〇， 係具有該些接合墊2 1 3，利用點膠技術藉由一點膠、 1 0將該些黏著膠240局部點塗在該上表面2 1 1，以％ _ 乂避開 邊些線路214。並在該基板210之該上表面211 些黏著膠2 4 0的塗佈區内設置該些間隔球2 3 0，其中上 些間隔球23 0係不直接下壓至該些線路2丨4且該此 z 、 &間隔 球2 3 0係遠離該些接合墊2 1 3。該些黏著膠2 4 〇倍孝 ^ π點附 该些間隔球230，用以避免該些間隔球23〇位移。 14 M345344 接著，進行覆晶接合步驟。請參閱第4圖B所示， 將該晶片220以該主動面221朝向該上表面21 1之方式 設置於該基板210上，並使該晶片220之該些凸塊222 接合至該些接合墊2 1 3 (如第3圖所示），以達到該晶片 220與該基板210之電性互連。其中，該些凸塊222係 可為結線凸塊，並且該些凸塊2 2 2與該些接合墊2 1 3之 接合方式可為釘頭凸點焊接（SBB， stud bump 0 bonding)。在覆晶接合過程中，藉由該些間隔球230提 供該晶片220周邊之Z軸（縱向）支撐力，以避免該晶片 220產生傾斜（如第3圖所示），但不限制該晶片220在 XY平面（水平面）的滑移。 接著，請參閱第4圖C所示，利用一點膠針頭2 0 將具有高流動性之該底部填充膠260點塗在該基板2 1 0 之該上表面211。該底部填充膠260先塗劃在該晶片220 之一側邊或L形兩侧邊，並以毛細現象填滿該晶片220 φ 與該基板210之間之間隙S1，以密封該些凸塊222(如 第3圖所示）。 接著，請參閱第4圖D所示，烘烤固化該底部填充 膠260，以使該底部填充膠260填滿該基板210與該晶 片220之間之間隙S1(如第3圖所示）。請參閱第4圖D 所示，該底部填充膠260係可覆蓋至該晶片220之局部 側邊，當該底部填充膠260固化之後便能固定該晶片 220於該基板210上。其中，在覆晶接合步驟之後，該 些黏著膠240之固化可與該底部填充膠260之固化同時 15 M345344 進行’或者可在該底部填充膠260點塗形成之前。 之後，請參閱第4圖E所示，以壓模方法形成該封 膠體250於該基板210上，以密封該晶片220，藉以保 護該晶片220不被外界塵埃與水氣污染（如第3圖所 示）。最後，請參閱第4圖F所示，設置該些外接端子 270於該基板210之該下表面212，其中該些外接端子 2 7 0係為陣列排列。在本實施例中，該些外接端子2 7 0 係包含鲜球。 因此’本創作可以增加打線接合之晶片220之共用 性，特別是原本適用於窗口型球格陣列的打線接合晶 片’可以沿用並封褒成具非陣列凸塊之覆晶封裝構造 200，不會有晶片傾斜與凸塊焊點斷裂的問題。打線接 合之晶片不需要重配置線路（RDL)製程與凸塊下金屬承 座（UBM pad)，同一類晶片具有製程調整的方便性。在 DDR2 DRAM(Double-Data-Rate Two Synchronous 肇 Dynamic Random Access Memory，第二代雙倍資料率同 步動態隨機存取記憶體）半導體封裝之具體應用上，一 包含複數個晶片之晶圓不需要預先製作為打線接合或 疋覆晶接合型態，可先測試以確定晶片之可運算記憶體 時脈，並在晶圓切割之後，依可運算記憶體時脈作分 類。將可運算在 553Mhz、667Mhz、80〇Mhz 的 DDR2 記憶體晶片封裝成窗口型球格陣列封裝構造；將可運算 在 1 066Mhz、l 3 3 3Mhz、1 600Mhz 的 DDR2 記憶體晶片 封裝成本創作之具非陣列凸塊之覆晶封裴構造。ddr3 16 M345344 的應用方法亦是與上述相同。因此 類區段的記憶體 不同刀 型態，不會有低：能選擇性封裝成適用的封裝 的晶片，導致時脈晶片卻已為製成為陣列凸塊 低時脈運算的;；壯；1為窗口型球格陣列封裝構造或較 為打線接合的致也不會有高記憶體時脈晶片仍 的曰曰片，導致只能封裝成在低時脈運算的窗M345344 for Substrate" Step 1, "Crystal Bonding" Step 2, "Sealing" and "Setting External Terminals" Step 4. In step 2, the crystal is unsupported, and only the bumps in the central region of the wafer 1 0 0 are bonded to the bonding pads 1 1 3 of the substrate 1 1 , and the crystal and the substrate 1 1 cannot be controlled. 0 parallelism and clearance. In the "sealing" step, the molding pressure of the encapsulant is formed to impinge on the wafer 1 2 and the upper and lower sides of the wafer are swung up and down (as shown in the figure). The wafer 1 20 is obliquely pressed against the substrate. The line of the 或是 or the solder joint of the 1 22 breaks, which affects the quality of the electrical connection. And in the third step, the wafer 120 lacking the peripheral supporting force is also easily affected by the tilt. The external terminals 丨7〇 are set in the middle. [New content] This is the main purpose of this creation is to provide a flip-chip package structure of array bumps, which can be used in the flip-chip bonding and the parallelism between the wafer and the substrate. The overlay of the array bumps is the quality of the structure. Therefore, the inventor knows that the wire bonding 曰 y 艮搔 曰曰 直接 directly encapsulates into a flip chip package structure and the bump and bump joint breakage problems. The second step of this creation—B from H is to provide a non-clade crystal package structure that can control the parallelism and gap between the substrates during the flip chip bonding process, so that the wafer can be used as XY 'month Therefore, the purpose of bonding to the creation of the Stud bump welding (SBB) and solving the technical problem is to use the step 3 piece 120 122 in the piece 120 3 , which is easy to generate 'causes some bumps, step to mold flow step 4 The process is not able to solve the wafer tilting bump wafer and surface oscillating fe ° technology side M345344 case to achieve. According to the present invention, a flip-chip package having non-array bumps mainly comprises a substrate, a wafer, a plurality of spacer balls, a plurality of adhesives, and a gel. The substrate has an upper surface and a lower surface, the upper surface being formed with a plurality of tantalum bond pads. The wafer is disposed on the upper surface of the substrate, and one of the active faces of the wafer is provided with a plurality of bumps', wherein the bumps are non-arrayed and bonded to the joints. The spacer balls are disposed on the upper surface of the substrate to be disposed between the substrate and the wafer, and the spacer balls support the periphery of the active surface of the wafer. The adhesive layers are disposed on the upper surface of the substrate and adhere to the spacer balls. The encapsulation system is formed on the upper surface of the substrate and seals the wafer. The purpose of this creation and solving its technical problems can be further realized by the following technical measures. In the foregoing flip chip package structure, the ball diameter of the spacer balls defines a gap between the substrate and the wafer. In the above flip chip package structure, the material of the adhesive may be epoxy. In the foregoing flip chip package structure, the substrate may have a plurality of lines formed on the upper surface of the substrate. In the aforementioned flip chip package configuration, the spacer balls may not be directly pressed down to the lines. In the reticular encapsulation structure, an underfill may be further included to fill the gap between the substrate and the wafer to seal the bumps. In the above flip chip package structure with non-array bumps, the bottom fill: M345344 fill system can cover the lines. In the flip chip package structure, a plurality of external terminals may be further included on the lower surface of the substrate. In the foregoing flip chip package structure, the bumps may be junction bumps, and the spacer balls may not adhere to the wafer, only to control the parallelism and gap between the wafer and the substrate, when the wafer is A stud bump bonding (SBB) method is bonded to the substrate, which is oscillating and sliding in the XY plane. In the above flip chip sealing structure, the wafer system can be a memory wafer. In the foregoing flip chip package structure, the wafer system may be a cross-package type of a frequency-frequency memory wafer, which is selected from a second generation double data rate synchronous dynamic random access memory of 53 3 Mhz to l 600 Mhz. (DDR2 DRAM) memory chip. The present invention also discloses another flip chip package structure having non-array bumps, which mainly comprises a substrate, a wafer, a plurality of spacer adhesive members and a gel. The substrate has an upper surface and a lower surface, the upper surface being provided with a plurality of joints. The wafer is disposed on the upper surface of the substrate. One of the active faces of the wafer is provided with a plurality of bumps, wherein the bumps are non-array disposed and bonded to the bond pads. The spacers are disposed on the upper surface of the substrate to be disposed between the substrate and the wafer, and the spacers adhere to the periphery of the active surface of the wafer. The encapsulation system is formed on the upper surface of the substrate and seals the wafer, and the encapsulation system fills the gap between the substrate and the wafer to seal the bumps. It can be seen from the above technical solution that the non-array bump 8 of the present invention has a flip chip package structure of M345344, and the right v ^ has the following advantages and effects: 1. Using a spacer ball 痞nj^ α 八 ab b bonding member The set position provides the ability to force the wafer to tilt during the flip chip bonding or/and the encapsulation process. Therefore, the wire bonded wafer can be packaged into a flip chip with non-array bumps. First, the adhesive ball is adhered to the substrate by adhesive tape or the surface of the adhesive Φ surface is soft to ensure the support effect. Therefore, it is possible to control only the parallelism and the gap between the substrate, so that the wafer can be surface-sliding and sliding to perform the stud bump welding (SBB). Second, the use of the spacer adhesive has the characteristics of electrical insulation, which can avoid the short circuit phenomenon. 4. Since the spacer ball system does not directly press down the circuit of the substrate, it can be damaged by being squeezed. _5. Filling the flip-chip gap with the underfill or the sealant, and the effect of protecting the circuit, so that the substrate does not need another layer, thereby reducing the manufacturing cost. [Embodiment] According to a first embodiment of the present invention, a flip-chip package structure having a non-array is illustrated in a cross-sectional view of Fig. 3, which is a manufacturing flow chart of the flip chip package structure. The flip chip package structure 200 mainly includes a substrate 210, 220, a plurality of spacer balls 230, and a plurality of adhesives 240, so that the wafers without the co-packaged components in the 曰 曰 周 周 周 免 免 免 免 免The line-free coverage line forms an anti-column bump. The fourth wafer and a 9 M345344 colloid 250. The substrate 210 has an upper surface 211 and a lower surface 2 1 2 '. The upper surface 2 1 1 is formed with a plurality of bonding pads 2丨3. The substrate 210 can be a printed circuit board, a ceramic substrate or a glass substrate. In this embodiment, the bonding pads 2 1 3 may be disposed in a central line of the upper surface 21 1 in a straight line or a plurality of parallel straight lines (as shown in FIG. 4A). Referring to FIG. 3, the wafer 220 is disposed on the upper surface 21 of the substrate 210_. The wafer 220 can be a memory chip, and more specifically, the wafer 220 can be a DDR2 or DDR3 memory chip. Moreover, one of the active faces 221 of the wafer 220 is provided with a plurality of bumps 222, wherein the bumps 222 are non-arrayed and bonded to the bond pads 2 1 3 . "Non-array setting" refers to a matrix arrangement in which the number of N rows is multiplied by the number of columns, wherein n and Μ are positive integers greater than two, and the bump setting area is much smaller than the active surface 221 of the wafer 220, at least Should be less than one-half. In other words, the bumps 222 集中 are concentrated in a certain area of the active surface of the wafer without being dispersed by the reconfiguration line (RDL) process. In this embodiment, the bumps 222 may be located in a central region of the active surface 22 1 and may be linearly arranged, wherein the bumps 222 are corresponding to the bonding pads 213 (eg, FIG. 4) Show). The bumps 222 can be gold bumps, copper bumps or composite bumps of other conductive materials. In this embodiment, the bumps 222 are stud bumps formed by wire bonding, and are bonded to the bond pads 213 by a nail head welding (SBB). More specifically, the stud bump welding (SBB) causes the gold bumps or other metal bonds formed by the ultrasonic oscillating friction between the bumps 222 and the bond pads 213 10 : M345344. Among them, the ultrasonic oscillation is a rapid reciprocating micro-movement in the XY plane (i.e., a plane parallel to the active surface 22 1 of the wafer) to achieve low temperature metal bonding. Preferably, the direction of the reciprocating micro-movement is perpendicular to the linear arrangement direction of the bumps 222 to prevent the bumps 222 from short-circuiting during the ultrasonic shocking process. One of the specific effects of the present invention is to utilize the combination of the spacer balls 230 and the adhesives 240 to control the parallelism and gap between the wafer 220 and the substrate 2 1 以 to maintain the wafer support effect. Further, a flip chip bump bonding (SBb) type flip chip bonding can be achieved for the following reasons. Referring to FIG. 3 , the spacer balls 203 are disposed on the upper surface 2 丨 1 of the substrate 2 1 0 to be interposed between the substrate 2 丨〇 and the wafer 2 2 0. The spacer balls 203 support the periphery of the active surface 2 2 1 of the wafer 2 2 0 . With such a combination, in the flip chip bonding step, the active surface 221 of the wafer 220 is not adhered by the spacer balls 230, and φ can be oscillated as an XY plane. Specifically, the spacer balls 230 are spaced apart from the bumps 222 of the wafer 220 and adjacent to the periphery of the active surface of the wafer to provide a preferred wafer slidable support effect. More specifically, the ball diameter of the spacer balls 230 may be no greater than the height of the bumps 222 of the wafer 220 to ensure bonding between the wafer 220 and the substrate 210. Referring to FIG. 3, the ball diameter of the spacer balls 230 is used to define a gap S1 between the substrate 210 and the wafer 220, which is approximately equal to the active surface 221 of the wafer 220 to the substrate 2 1 0. The vertical distance of the upper surface 2 11 . Among them, the intervals M345344 insult * ball 2 3 0 should have the same ball diameter. Referring to FIG. 3, the upper surface 2 1 1 of the adhesive sheet 2 10 and the plurality of adhesives 240 are adhered to the upper surface 2 1 of the spacer balls 2 1 0 1. In order to avoid these, in the present embodiment, the adhesives 240 are not the active surface 221. The adhesive 30 of the adhesive 240 can be stably disposed on the substrate 210, and the curing can be performed after the flip-chip bonding step. The ceramic can be used to define the above-mentioned flip-chip bonding gap. The wafer 220 is still not adhered to the wafer 220 before curing. In the crystal bonding step, the ultrasonic layer can be used as a plane. The adhesives are away from the substrate 2 1 0 to avoid contamination of the bonding pads 2 . 1 3. In the present embodiment, the material of 4 φ may be epoxy. In the present embodiment, reference to Fig. 3 may have a plurality of lines 2 1 4 formed on the surface 21 1 . Preferably, as shown in Fig. 4A, the wires 214 may not be directly pressed down; 2 1 4 is damaged by the stress of the extrusion, and further, i. In this embodiment, please refer to FIG. 3 and the bonding pads 213 can be the same circuit layer. The wires 2 1 4 can be bare wire design, and the 240 wires can be disposed on the base P ball 2 3 0 . Therefore, 230 limits the displacement of the i-ball 2 3 0 on the substrate. Bonding the wafer 220 causes the spacer balls to be in the adhesives 240 to cause the spacer balls S1, and even if the active surface 221 is not, the wafer 220 is not covered. Preferably, the bonding pads 2 1 3 , in the middle of the crucible, the adhesive 240 shows that the substrate 2 10 is on the substrate 2 1 0 , the spacing balls 230 can avoid the wires from affecting the electricity The characteristics of the sexual transmission, the lines 214. In this embodiment, it is covered by the solder resist layer, 12 M345344, because the wafer 220 has good parallelism between the τ ▼ ▼ & & 该 该 基板 基板 基板 基板 基板 基板 基板 基板It is connected to the precise flip chip. Referring to Fig. 3, the encapsulant 25 is formed on the upper surface 211 of the substrate 210 and seals the wafer 22 to provide proper package protection and prevent dust contamination. The encapsulant 25 can be formed by a technique of compression molding (or transfer molding). In this embodiment, as shown in FIG. 3, the flip chip package structure 200 may further include an underfill 26 填 which fills the gap between the substrate 2 ι and the wafer 2 2 0 . s 1 to seal the bumps 2 2 2 to prevent stress from being concentrated on the specific bumps 222 to break. The underfill 260 can cover the lines 214. Specifically, the underfill 260 can seal the adhesive 24 〇, wherein the underfill 26 〇 covers the partial side of the δ 晶片 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The wafer 22 is prevented from being displaced. Since the gap si can be accurately controlled to a fixed value, the underfill S6 can be smoothly filled by capillary action to fill the gap S1 without trapping air bubbles. In this embodiment, as shown in FIG. 3, the flip chip package 2 can further include a plurality of external terminals 210, which are disposed on the lower surface 212 of the substrate 210 for use as The input and/or output are such that the flip chip package structure 2 can be surface bonded to an external device, such as a printed circuit board (not shown). The external terminals 27 can be a ball, tin lean, metal contact pads or pins. Therefore, the placement of the spacers 23 and the adhesives 24 M345344 can provide a better support effect around the periphery of the wafer 220, so that the wafer 220 can be balanced during flip chip bonding. The up-and-down swing does not occur, and the wafer 220 can be prevented from being tilted by the mold flow pressure during the sealing, so that the flip chip package structure 200 does not have the problem of wafer tilt, and the wafer 220 and the substrate 210 can be ensured. The quality of the electrical connection between. Moreover, the adhesive tapes 240 adhere to the spacer balls 23, so that the problem that the wafers 220 cannot be effectively supported due to the displacement of the spacer balls 230 can be prevented. The underfill 26 can be used to make the wafer 220 more stably disposed on the substrate 210 to prevent the wafer 220 from being tilted by the mold flow pressure, and to avoid the bump 222 solder joint due to stress concentration. The problem of breakage. In addition, the underfill 260 covers the lines 2 14 to achieve the protection of the lines 2 1 4 , so the substrate 210 does not need to form a solder resist layer to save manufacturing costs. This creation further illustrates the fabrication method of the above-described non-array bump flip chip package sniper 200, which is illustrated in the flow chart of FIG. Firstly, the substrate 21 is provided with the bonding pads 2 1 3, and the adhesives 240 are partially applied to the adhesive by a dispensing technique. The upper surface 2 1 1 avoids the side lines 214 with % _ 。. And the spacer balls 230 are disposed in the coating area of the upper surface 211 of the substrate 210, wherein the upper spacers are not directly pressed down to the lines 2丨4. The z, & spacing ball 203 is remote from the bonding pads 2 1 3 . The adhesive tapes 2 4 〇 孝 ^ π points are attached to the spacer balls 230 to avoid the displacement of the spacer balls 23 。. 14 M345344 Next, a flip chip bonding step is performed. As shown in FIG. 4B, the wafer 220 is disposed on the substrate 210 with the active surface 221 facing the upper surface 21 1 , and the bumps 222 of the wafer 220 are bonded to the bonding pads. 2 1 3 (as shown in FIG. 3) to achieve electrical interconnection of the wafer 220 with the substrate 210. The bumps 222 can be the junction bumps, and the bumps 2 2 2 can be joined to the bond pads 2 1 3 by stud bump bonding (SBB, stud bump 0 bonding). In the flip chip bonding process, the Z-axis (longitudinal) supporting force of the periphery of the wafer 220 is provided by the spacer balls 230 to prevent the wafer 220 from being tilted (as shown in FIG. 3), but the wafer 220 is not limited. Slip in the XY plane (horizontal plane). Next, referring to FIG. 4C, the underfill 260 having high fluidity is spot-applied to the upper surface 211 of the substrate 2 1 0 by using a single glue needle 20 . The underfill 260 is first coated on one side or the L-shaped side of the wafer 220, and fills the gap S1 between the wafer 220 φ and the substrate 210 by capillary phenomenon to seal the bumps 222. (as shown in Figure 3). Next, referring to FIG. 4D, the underfill 260 is baked and cured so that the underfill 260 fills the gap S1 between the substrate 210 and the wafer 220 (as shown in FIG. 3). Referring to FIG. 4D, the underfill 260 can cover a portion of the side of the wafer 220. After the underfill 260 is cured, the wafer 220 can be attached to the substrate 210. Wherein, after the flip chip bonding step, the curing of the adhesives 240 may be performed simultaneously with the curing of the underfill 260 15 M345344 or may be formed before the underfill 260 is applied. Thereafter, referring to FIG. 4E, the encapsulant 250 is formed on the substrate 210 by a stamper method to seal the wafer 220, thereby protecting the wafer 220 from external dust and moisture (eg, FIG. 3). Shown). Finally, referring to FIG. 4F, the external terminals 270 are disposed on the lower surface 212 of the substrate 210, wherein the external terminals 270 are arranged in an array. In this embodiment, the external terminals 207 comprise fresh balls. Therefore, the present invention can increase the commonality of the wire bonding wafers 220, in particular, the wire bonding wafers originally applicable to the window type ball grid array can be used and sealed into a flip chip package structure 200 having non-array bumps, without There is a problem of wafer tilt and bump solder joint breakage. The wire-bonded wafer does not require a reconfigurable line (RDL) process and a UBM pad. The same type of wafer has process adjustment convenience. In a specific application of a DDR2 DRAM (Double-Data-Rate Two Synchronous 肇Dynamic Random Access Memory) semiconductor package, a wafer containing a plurality of wafers does not need to be pre-processed. It can be tested as a wire bond or a flip chip bond type. It can be tested to determine the memory memory clock of the chip, and after the wafer is cut, it can be classified according to the memory clock. DDR2 memory chips that can be operated at 553Mhz, 667Mhz, and 80〇Mhz are packaged into a window-type ball grid array package structure; the DDR2 memory chip package that can be operated at 1 066Mhz, l 3 3 3Mhz, and 1 600Mhz is cost-effective. A flip-chip structure of non-array bumps. The application method of ddr3 16 M345344 is also the same as above. Therefore, the memory of the class segment is not different in the shape of the blade: it can be selectively packaged into a suitable packaged wafer, so that the clock chip has been made into an array bump low clock operation; For the window-type ball grid array package construction or wire bonding, there will be no high memory clock chip still 曰曰, resulting in only the window that is low-clock operation
h陣列封裝構造，故深具產業上利用性並明顯具 有減少不適用晶片冑量與增加製程彈性之功效。八 依據本創作之第二具體實施例，另一種具非陣列凸 塊之覆晶封裝構造舉例說明於第5圖之截面示意圖。該 覆晶封裝構造300主要包含一基板310、一晶片32〇、 複數個間隔黏著件340以及一封膠體35〇。該基板31〇 係具有一上表面311以及一下表面312，該上表面3ιι 係設有複數個接合墊3丨3。在本實施例中，該些接合墊 313係可位於該上表面311之中央區域。請參閱第$圖 所不’該晶片320係設置於該基板3 1 0之該上表面3丨i， 該晶片320之一主動面321係設有複數個凸塊322，其 中j些凸塊322係為非陣列設置並接合至該些接合塾 3 13。在本實施例中，該些凸塊322係可為金凸塊322， 例如，打線形成之結線凸塊。該些凸塊322至該些接合 塾313的接合方法係可利用釘頭凸點焊接（SBB)或是錫膏 火干接。δ亥晶片3 2 0係可為§己憶體晶片，特指一種跨封裝 型態之中高頻記憶體晶片，例如由533Mhz至1600Mhz 的第二代雙倍資料率同步動態隨機存取記憶體（DDR2 17 M345344 ^ DRAM)記憶體晶片。 請再參閱第5圖所示，該些間隔黏著件34〇係設置 於該基板3 1 0之該上表面3 11以介設於該基板3 1 0與該 晶片320之間，該些間隔黏著件340係黏附該晶片320 之該主動面321之周邊。該些間隔黏著件340係可遠離 而不接觸該些凸塊322。該些間隔黏著件34〇係可為電 絕緣性樹脂’以避免造成電性短路現象。在本實施例 _ 中’該些間隔黏著件340係可為兩面黏性膠帶或是B 階黏著膠塊，故可黏接該晶片3 20之該主動面3 2 1與該 基板310之β亥上表面311’以使該晶片320固設於該基 板3 1 0。較佳地，該間隔黏著件係具有表面柔軟特性。也 就是’該些間隔黏著件34〇用以黏附該晶片32〇的材料 為低模數’使得該晶片220在覆晶接合步驟時可作χγ 平面（水平面）的超音波震盪滑動或是微調。 請參閱第5圖所示，該封膠體3 50係形成於該基板 # 310之该上表面311並密封該晶片320，並且該封膠體 3 50係填滿該基板31〇與該晶片32〇之間之間隙s2以 密封該些凸塊3 22。在本實施例中，該基板3丨〇係可具 有複數個線路314，其係形成於該基板31〇之該上表面 3 11。較佳地，該封膠體3 50係可覆蓋該些線路314， 以避免該些線路314受到污染，故該基板3 1〇不需另形 成防焊層藉以減少製造成本。請再參閱第5圖所示，該 覆晶封裝構造3 00可另包含複數個外接端子3 7〇，其係 設置於該基板3 1 0之該下表面3 1 2，以供對外表面接合。 18 M345344 因此’藉由該些間隔黏著件3 4 Ο，在覆晶接合或/與 封膠之過程中，該些間隔黏著件34〇得以提供該晶片 320周邊之支撐力’藉此避免該晶片32〇產生傾斜與該 些凸塊322產生焊點斷裂之問題。 本創作進一步說明前述非陣列凸塊之覆晶封裝構造 之製造方法例舉說明於第6圖之流程圖。 首先，請參閱第6圖A所示，提供具有該些接合蛰 _ 3 1 3之該基板3 1 0，並利用點膠技術藉由一點膠針頭3 〇 將該些間隔黏著件3 4 0局部點塗在該基板3丨〇之該上表 面3 11，其中該些間隔黏著件34〇係遠離該些接合墊 3 1 3。該些間隔黏著件3 4 0係可局部覆蓋該基板3 1 〇之 該些線路3 1 4。由於該些間隔黏著件3 4 0係為電絕緣 性，故即使該些線路3 1 4為裸線亦不會造成電性短路之 問題。 接著，請參閱第6圖B所示，進行覆晶接合步驟， φ 以該晶片3 2 0之該主動面3 2 1朝向該基板3 1 0之方式設 置於該基板310上，並使該晶片320之該些凸塊322接 合至對應之該些接合墊3 1 3 (如第5圖所示），以達到該 晶片3 2 0與該基板3 1 0之電性互連。在覆晶過程中，該 晶片320之周邊可藉由該些間隔黏著件340得到支撐 力，故不會有晶片傾斜的問題（如第5圖所示）。 接著，請參閱第6圖C所示，烘烤該些間隔黏著件 3 40，以使該些間隔黏著件340固化以黏著該基板3 10 與該晶片320，並提供後續模封製程中該晶片320之周 19 M345344 邊較佳的支撐與固定效果。 之後，請參閱第6圖D所示，以壓模方法形成該封 膠體3 50於該基板31〇上並填滿該基板31〇與該晶片 320之間之間隙S2，以密封該晶片32〇與該些凸塊 3 22(如第5圖所示）。最後，請參閱第6圖E所示，設 置該些外接端子370於該基板31〇之該下表面312。汉 以上所述’僅是本創作的較佳實施例而已，並非對 _本創作作任何形式上的限制，雖然本創作已以較佳實施 例揭露如上，然而並非用以限定本創作，任何熟悉本項 技2者，在不脫離本創作之申請專利範圍内，所作的任 何簡單修改、等效性變化與修飾，皆涵蓋於本創 術範圍内。 、 【圖式簡單說明】 第1圖：習知具非陣列凸塊之覆晶封裝構造之截面示音 圖。 •第2圖：習知具非陣列凸塊之覆晶封裝構造之製造方法 流程方塊圖。 第3圖·依據本創作之第一具體實施例的一種具非陣列 凸塊之覆晶封裝構造之截面示意圖。 第4圖：依據本創作之第一具體實施例的該覆晶封裝構 造在製造流程中之元件示意圖。 第5圖··依據本創作之第二具體實施例的另—種具非陣 列凸塊之覆晶封裳構造之截面示意圖。 第6圖·依據本創作之第二具體實施例的該覆晶封裝構 20 M345344 造之製造流程圖。 【主要元件符號說明】 S1間隙 S2間隙 1 提供基板 2 覆晶接合 3 封膠The h-array package structure is industrially usable and has the effect of reducing the amount of unsuitable wafers and increasing the flexibility of the process. According to a second embodiment of the present invention, another flip chip package structure having non-array bumps is illustrated in cross-section of Fig. 5. The flip chip package structure 300 mainly includes a substrate 310, a wafer 32, a plurality of spacers 340, and a gel 35 〇. The substrate 31 has an upper surface 311 and a lower surface 312 which is provided with a plurality of bonding pads 3丨3. In this embodiment, the bonding pads 313 can be located in a central region of the upper surface 311. The wafer 320 is disposed on the upper surface 3丨i of the substrate 310. The active surface 321 of the wafer 320 is provided with a plurality of bumps 322, wherein the bumps 322 are 322. The non-array is arranged and bonded to the joints 313. In this embodiment, the bumps 322 can be gold bumps 322, for example, wire bumps formed by wire bonding. The bonding method of the bumps 322 to the bonding pads 313 can be performed by using a stud bump soldering (SBB) or a solder paste. The δ ray chip 3 2 0 can be a § memory wafer, especially a cross-package type medium-frequency high-frequency memory chip, for example, a second-generation double data rate synchronous dynamic random access memory from 533Mhz to 1600Mhz ( DDR2 17 M345344 ^ DRAM) memory chip. Referring to FIG. 5 again, the spacers 34 are disposed on the upper surface 3 11 of the substrate 310 to be disposed between the substrate 310 and the wafer 320. A member 340 adheres to the periphery of the active surface 321 of the wafer 320. The spacers 340 are remote from the bumps 322. The spacers 34 may be electrically insulating resins to avoid electrical short circuits. In the embodiment, the spacer adhesive 340 can be a double-sided adhesive tape or a B-stage adhesive adhesive, so that the active surface 3 2 1 of the wafer 3 20 and the substrate 310 can be bonded to the substrate. The upper surface 311' is such that the wafer 320 is fixed to the substrate 310. Preferably, the spacer adhesive has a surface softening property. That is, the material of the spacers 34 for adhering the wafer 32 is low modulus so that the wafer 220 can be subjected to ultrasonic oscillating sliding or fine adjustment of the χ γ plane (horizontal plane) in the flip chip bonding step. Referring to FIG. 5, the encapsulant 3 50 is formed on the upper surface 311 of the substrate #310 and seals the wafer 320, and the encapsulant 350 fills the substrate 31 and the wafer 32. A gap s2 is provided to seal the bumps 3 22 . In this embodiment, the substrate 3 can have a plurality of lines 314 formed on the upper surface 311 of the substrate 31. Preferably, the encapsulant 350 can cover the lines 314 to prevent the lines 314 from being contaminated, so that the substrate 3 1 does not need to form a solder resist layer to reduce the manufacturing cost. Referring to FIG. 5 again, the flip chip package structure 300 may further include a plurality of external terminals 3 7 〇 disposed on the lower surface 3 1 2 of the substrate 310 for bonding to the outer surface. 18 M345344 Therefore, by means of the spacer adhesives 34, the spacers 34 can provide a supporting force around the wafer 320 during flip chip bonding or/and sealing, thereby avoiding the wafer The 32 turns cause a problem that the bumps 322 cause solder joint breakage. The present invention further illustrates a method of manufacturing the flip chip package structure of the non-array bump described in the flowchart of FIG. First, referring to FIG. 6A, the substrate 3 1 0 having the joints 3 3 1 3 is provided, and the spacers are adhered by a dispensing technique 3 〇 by a dispensing technique 3 4 0 A local point is applied to the upper surface 311 of the substrate 3, wherein the spacers 34 are spaced away from the bonding pads 313. The spacers 300 4 can partially cover the lines 3 1 4 of the substrate 3 1 . Since the spacer adhesives are electrically insulating, even if the wires 3 14 are bare wires, there is no problem of electrical short circuit. Next, referring to FIG. 6B, a flip chip bonding step is performed, and φ is disposed on the substrate 310 such that the active surface 3 2 1 of the wafer 3 0 0 faces the substrate 310 . The bumps 322 of the 320 are bonded to the corresponding bonding pads 3 1 3 (as shown in FIG. 5) to achieve electrical interconnection between the wafer 320 and the substrate 310. During the flip chip process, the periphery of the wafer 320 can be supported by the spacers 340, so that there is no problem of wafer tilt (as shown in Fig. 5). Next, referring to FIG. 6C, the spacer adhesives 340 are baked to cure the spacers 340 to adhere the substrate 3 10 and the wafer 320, and provide the wafer in a subsequent molding process. Week 30 of 320 M345344 better support and fixing effect. Then, as shown in FIG. 6D, the encapsulant 350 is formed on the substrate 31 by a stamper method and fills a gap S2 between the substrate 31 and the wafer 320 to seal the wafer 32. And the bumps 3 22 (as shown in Fig. 5). Finally, referring to FIG. 6E, the external terminals 370 are disposed on the lower surface 312 of the substrate 31. The above description is merely a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to limit the creation, any familiarity. In the present invention, any simple modifications, equivalent changes and modifications made within the scope of the patent application are within the scope of the present invention. [Simplified description of the drawing] Fig. 1: A cross-sectional sound diagram of a flip chip package structure with non-array bumps. • Fig. 2: A manufacturing method for a flip chip package structure with non-array bumps. Fig. 3 is a schematic cross-sectional view showing a flip chip package structure having non-array bumps in accordance with a first embodiment of the present invention. Fig. 4 is a view showing the components of the flip chip package structure in the manufacturing process in accordance with the first embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing another embodiment of a flip-chip structure having non-array bumps according to a second embodiment of the present invention. Fig. 6 is a flow chart showing the manufacturing process of the flip chip package 20 M345344 according to the second embodiment of the present invention. [Main component symbol description] S1 gap S2 gap 1 Provide substrate 2 Flip chip bonding 3 Sealing
4 設置外接端子 10 點膠針頭 20 點 膠 針頭 30 100 覆晶封裝構造 110 基板 111 上 表 面 112 113 接合墊 120 晶片 122 凸 塊 150 封膠體 170 外接端子 200 覆晶封裝構造 210 基板 211 上 表 面 212 213 接合墊 214 線路 220 晶片 221 主 動 面 222 230 間隔球 240 黏 著 膠 250 260 底部填充膠 270 外接端子 300 覆晶封裝構造 310 基板 311 上 表 面 312 313 接合塾 314 線 路 320 晶片 321 主 動 面 322 340 間隔黏著件 350 封 膠 體 370 21 點膠針頭 下表面 下表面 凸塊 封膠體 下表面 凸塊 外接端子4 Set external terminal 10 Dispensing needle 20 Dispensing needle 30 100 Flip chip package structure 110 Substrate 111 Upper surface 112 113 Bonding pad 120 Wafer 122 Bump 150 Sealant 170 External terminal 200 Flip chip package structure 210 Substrate 211 Upper surface 212 213 Bond pad 214 line 220 wafer 221 active surface 222 230 spacer ball 240 adhesive 250 260 underfill 270 external terminal 300 flip chip package structure 310 substrate 311 upper surface 312 313 bonding 塾 314 line 320 wafer 321 active surface 322 340 spacer adhesive 350 sealant 370 21 Dispensing needle lower surface lower surface bump sealant lower surface bump external terminal