M343852 ’八、新型說明： 【新型所屬之技術領域】 本新型係關於一種消費型電子設備，尤其涉 及一種開機重置電路及使用其之電子設備。 【先前技術】 目前，各式電子產品之内部晶片，例如：中 〜央處理器（Central Processing Unit，CPU)、快 -閃（Flash)及專用積體電路（Application Specific _ Integrated Circuit，ASIC)等，在其上電時需要 重置訊號自動重置。在大多設計中，通常使用一 顆特定的重置晶片以提供可靠的重置訊號，或使 用微控制器，如：CPU、微控制器單元 (Micro-ControllerUnit，MCU)、可編程邏輯裝 置（Complex Programmable Logic Device，CPLD ) 及現場可編程門陣列（Field-Programmable Gate 鲁Array，FPGA)等，以程式計數或計時的方式於 開機特定時間後輸出重置訊號。 圖1所示係一種習知的開機重置電路，用於 在電路上電後產生重置訊號給 CPU 120、Flash 121及ASIC 122，其包括直流電源10及重置晶 片11。其中，直流電源1 〇輸出直流訊號給重置 晶片11，經該重置晶片11處理後產生重置訊號 重置 CPU 120、Flash 121 及 ASIC 122。 圖2所示係另一種習知的開機重置電路，同 6 M343852 " 樣用於在電路上電後產生重置訊號給 CPU ^ 220、Flash 221及ASIC 222，其包括直流電源 20及微控制器21。其中，直流電源20輸出直流 訊號給微控制器2 1，由該微控制器21經處理後 產生重置訊號重置CPU 220、Flash 221及ASIC 222 〇 ^ 習知的開機重置電路中，需要特定的重置晶 -片或微控制器來提供重置訊號。然，此兩種方式 *皆需要額外添置一顆晶片來完成重置訊號的產 生，重置晶片之參數皆由晶片薇商初始設定，在 後續的使用中難以調整，電路靈活性較差，而且 成本較高。 【新型内容】 有鑒於此，需提供一種開機重置電路，可靈 活調整重置參數，且具有較低的成本。 φ 此外，還需提供一種使用此開機重置電路的 ' 電子裝置，可靈活調整重置參數，且具有較低的 • 成本。 一種開機重置電路，與外部直流電源相連， 用於從該直流電源接收電源訊號並產生重置訊 號至晶片組，該開機重置電路包括延時電路、整 形電路及邏輯運算電路。其中，延時電路包括第 一延時單元，用於將接收到的電源訊號進行延 時，並輸出第一延時訊號；第二延時單元，用於 7 M343852 將該接收到的電源訊號進行延時，並輸出第二 時訊號。整形電路，與該延時電路相連，包括 一整形單元，與該第一延時單元相連，用於將 第一延時訊號進行整形，並輸出第一整形訊號 第二整形單元，與該第二延時單元相連，用於 該第二延時訊號進行整形，並輸出第二整形 '號。邏輯運算電路與該整形電路相連，用於根 -該第一整形訊號及第二整形訊號進行邏輯 *算，並輸出重置訊號。 一種電子設備，與外部直流電源相連，包 晶片組及開機重置電路。開機重置電路與外部 流電源相連，用於從該直流電源接收電源訊號 產生重置訊號以重置該晶片組，該開機重置電 包括延時電路、整形電路及邏輯運算電路。 中，延時電路包括第一延時單元，用於將接收 _的電源訊號進行延時，並輸出第一延時訊號； 二延時單元，用於將該接收到的電源訊號進行 時，並輸出第二延時訊號。整形電路，與該延 電路相連，包括第一整形單元，與該第一延時 元相連，用於將該第一延時訊號進行整形，並 出第一整形訊號；第二整形單元，與該第二延 單元相連，用於將該第二延時訊號進行整形， 輸出第二整形訊號。邏輯運算電路與該整形電 相連，用於根據該第一整形訊號及第二整形訊 延 第 該 9 將 訊 據 運 括 直 並 路 其 到 第 延 時 單 m 時 並 路 號 8 M343852 ' 進行邏輯運算，並輸出重置訊號至該晶片組。 ^ 藉由以下對具體實施方式詳細的描述結合 附圖，將可輕易的暸解上述内容及此項新型之諸 多優點。 【實施方式】 圖3所示係本新型一實施方式之電子設備2 ‘之模組圖。該電子設備 2包括開機重置電路 3 -以及晶片組34。其中，該開機重置電路3與外 *部直流電源3 0相連，用於接收電源訊號並產生 重置訊號至晶片組3 4，其包括延時電路31、整 形電路32及邏輯運算電路33。本實施方式中， 延時電路31包括第一延時單元311以及第二延 時單元312,整形電路32包括第一整形單元321 以及第二整形單元3 2 2，晶片組3 4包括但不限 於 CPU 341、Flash 342 以及 ASIC 343 等晶片。 φ 第一延時單元311與第二延時單元312並行 連接至該直流電源3 0，該第一延時單元311用 於將接收到的電源訊號進行延時，並輸出第一延 時訊號。同樣，該第二延時單元3 1 2用於將接收 到的電源訊號進行延時，並輸出第二延時訊號。 第一整形單元321與第一延時單元311相 連，用於將該第一延時訊號進行整形，並輸出第 一整形訊號。該第二整形單元322與該第二延時 單元 3 21相連，用於將該第二延時訊號進行整 9 M343852 '形，並輸出第二整形訊號。 ’ 邏輯運算電路33，與該整形電路32相連， 即，同時連接於第一整形單元321與第二整形單 元3 22，用於根據該第一整形訊號及第二整形訊 號進行邏輯運算，並輸出重置訊號至該晶片組 34 ° ’ 圖4所示係圖3中所示各元件之具體電路 -圖。其中，第一延時單元311包括第一電容C1 籲及第一電阻R1，其中第一電容C1用於對接收到 的電源訊號進行充電，第一電容C 1與第一電阻 R1依次串接於直流電源3 0及地之間。第二延時 單元312包括第二電容C2及第二電阻R2,其中 第二電容C 2用於對該接收到的電源訊號進行充 電，第二電阻R2與第二電容C2依次串接於該 直流電源3 0及地之間。 $ 本實施方式之開機重置電路3中，第一延時 單元311之第一電容C1及第一電阻R1與第二 延時單元312之第二電容C2及第二電阻R2之 參數皆可依實際電路需要進行調整、搭配。故， 延時電路3 1之延時時間可按需要進行調整，電 路靈活性較好。 第一整形單元 321包括第一施密特元件 U1，其具有輸入端及輸出端，該輸入端與第一 電容C1及第一電阻R1之公共節點A相連，其 M343852 輸出端與邏輯運算電路33相連，用於接收第一 延時訊號，並經整形後輸出該第一整形訊號。第 二整形單元322包括第二施密特元件U2，其具 有輸入端及輸出端，該輸入端與第二電容C2及 第二電阻R2之公共節點B相連，其輸出端與邏 輯運算電路33相連，用於接收第二延時訊號， 並經整形後輸出該第二整形訊號。 本實施方式中，該第一施密特元件U1及該 第二施密特元件 U2 係施密特反相觸發器 (74HC14 )。當該施密特反相觸發器被觸發時， 輸出低電平訊號；當該施密特反相觸發器不被觸 發時，輸出高電平訊號。通常，第一施密特元件 U1與第二施密特元件U2均具有高電壓準位及 低電壓準位，若初始輸入訊號的電壓高於該等施 密特元件之高電壓準位時，則以低電壓準位為觸 發電壓；若初始輸入訊號的電壓低於該等施密特 元件之低基準電壓時，則以高電壓準位為觸發電 壓。 在本實施方式中，第一施密特元件U1或第 二施密特元件U2之高電壓準位約介於2.5-2.6V 之間，低電壓準位約介於2.3-2.4V之間。 本新型之其他實施方式中，第一整形單元 321及第二整形單元322可根據不同晶片之規格 使用施密特觸發器或施密特反相觸發器，亦可以 11 M343852 ’ 由離散元件組成。故，該第一整形單元3 21及該 ’ 第二整形單元322之整形參數可調，即其觸發電 壓可根據需要進行調整，使得電路靈活性較好。 邏輯運算電路33包括第一二極體D1與第 二二極體 D2。第一二極體 D1之陽極與該第一 施密特元件U1之輸出端相連，用於接收該第一 ’整形訊號，其陰極輸出第一邏輯訊號。第二二極 -體D2之陽極與該第二施密特元件U2之輸出端 _相連，用於接收該第二整形訊號，其陰極輸出第 二邏輯訊號。本新型之其他實施方式中，邏輯運 算電路3 3可根據不同晶片規格之需要搭配不同 的數位元件，例如其可以係一或門運算器，亦可 以係其他邏輯門元件。 同時參閱圖 5之（a)、（b)及（c)，圖 5 係以開機重置電路3上電之瞬間為起始時間，故 φ此上電之瞬間設為初始之Oms，開機重置電路3 之工作原理詳述如下： 圖5(a)中，V(A)為第一延時訊號之波 形，V ( U 1 )為第一整形訊號之波形。在本實施 方式中，當直流電源3 0開始供電時，第一電容 C1被瞬間短路，電源訊號直接加載在第一電容 C1與第一電阻R1之公共節點A上，此時節點A 所輸出的第一延時訊號相當於該電源訊號。由於 該電源訊號之電壓高於第一施密特元件U1之高 12 ^M343852 9t ' 電壓準位，則以低電壓準位為觸發電壓， _ 施密特元件U1被觸發，並輸出低電平之 形訊號。 此後，第一電容 C1相對於電源訊 路，第一電容C1開始充電，第一延時訊 壓開始下降，至T2時刻，第一延時訊號 •剛好降至該低電壓準位之下，第一施密 -U1不被觸發，則輸出高電平之第一整形 參故，於開機瞬間至T2時刻，第一整形單 輸出低電平之第一整形訊號。於T2時刻 第一整形單元321輸出高電平之第一整史 圖5(b)中，V(B)為第二延時訊 形，V ( U2 )為第二整形訊號之波形，此 時單元3 1 2之工作原理與第一延時單元 反。在本實施方式中，當直流電源3 0開 $時，第二電容C2被瞬間短路，電源訊號3 ' 故此時第二電容C2與第二電阻R2之公兵 - 輸出之第二延時訊號為零。由於第二延時 電壓低於第二施密特元件U2之低電壓準 以高電壓準位為觸發電壓，故第二施密 U2不被觸發，則輸出高電平之第二整形 此後，第二電容C 2將電源訊號與地 並開始充電，電源訊號加載在節點 B上 二延時訊號之電壓在第二電容C2充電的 故第一 第一整 號是斷 號之電 之電壓 特元件 訊號。 元321 之後， 多訊號。 號之波 第二延 3 11相 始供電 L至地， 節點B 訊號之 位，則 特元件 訊號。 斷開， ，故第 情況下 13 M343852 開始上升，至τ 1時刻，第二延時訊號之電壓達 、 到該高電壓準位，第二施密特元件U2被觸發， 並輸出低電平之第二整形訊號。故第二整形單元 3 22在Τ1時刻前後輸出一由高電平至低電平的 第二整形訊號。 圖 5 ( c )係整合第一整形訊號及第二整形 -訊號後之重置訊號波形圖，其中V ( OUT )為邏 -輯運算電路 33輸出之重置訊號之波形。在 T1 _時刻之前，第一整形單元321輸出低電平之第一 整形訊號至第一二極體 D1，第二整形單元 322 輸出高電平之第二整形訊號至第二二極體D2, 故第一二極體D 1截止，第一邏輯訊號為低電平 訊號。此時，第二二極體D 2導通，第二邏輯訊 號為高電平訊號，故第二邏輯訊號使邏輯運算電 路33輸出高電平之電訊號。 $ 在T1-T2時刻之間，第一整形單元321輸 出低電平之第一整形訊號至第一二極體D1，第 二整形單元 322輸出低電平之第二整形訊號至 第二二極體 D2，故第一二極體 D1及第二二極 體D2皆截止，邏輯運算電路33輸出低電平之 電訊號。 在T2時刻之後，第一整形單元321輸出高 電平之第一整形訊號至第一二極體D1，第二整 形單元 322輸出低電平之第二整形訊號至第二 14 •M343852 二極體 D2，故第一二極體D1導通，第一邏輯 ’ 訊號為高電平。此時，第二二極體D2截止，第 二邏輯訊號為低電平，第一邏輯訊號使邏輯運算 電路33輸出高電平之電訊號。 在本實施方式中，該T1時刻約為電路上電 後之4 m s，該T 2時刻約為電路上電後之11 m s。 ' 綜上所述，在直流電源3 0開始供電之後， -邏輯運算電路33根據第一整形訊號及第二整形 ®訊號進行邏輯或運算，產生一由高電平至低電平 再至高電平的重置訊號，從而完成對晶片組 3 4 之重置。 本新型實施方式所提供之開機重置電路 3 透過兩路之延時電路31、兩路之整形電路32及 邏輯運算電路 33來產生重置訊號重置晶片組 34，各電路之參數可調，元件可按需要進行搭 $配，提高了電路的靈活性，且，降低成本。 綜上所述，本新型符合新型專利要件，爰依 法提出專利申請。惟，以上所述者僅為本新型之 較佳實施例，舉凡熟悉本案技藝之人士，在爰依 本案新型精神所作之等效修飾或變化，皆應包含 於以下之申請專利範圍内。 【圖式簡單說明】 圖1為一種習知開機重置電路之模組圖。 圖2為另一種習知開機重置電路之模組圖。 15 -M343852 圖 3為本新型一實施方式之開機重置電路之模 組圖。 圖4為本新型圖3之具體電路圖。 圖5為本新型圖4之訊號波形圖。 【主要元件符號說明】 直 流 電 源 10、 20、 30 -重 置 晶 片 11 CPU 120 ^ 220 、341 丨F1 as: h 121 、221 、342 ASIC 122 、222 、343 電 子 設 備 2 微 控 制 器 21 開 機 重 置 電 路 3 延 時 電 路 31 第 一 延 時 單 元 311 丨第 二 延 時 單 元 312 整 形 電 路 32 第 一 整 形 單 元 321 第 二 整 形 單 元 322 邏 輯 運 算 電 路 33 晶 片 組 34 第 一 電 容 C1 第 二 電 容 C2 第 — 電 阻 R1 16 M343852 •’第二電阻 R2 ^ 第一施密特元件 U1 第二施密特元件 U2 第一二極體 D 1 第二二極體 D 2M343852 ‘8. New Description: 【New Technical Fields Included】 This new type relates to a consumer electronic device, and more particularly to a power-on reset circuit and an electronic device using the same. [Prior Art] At present, internal chips of various electronic products, such as a central processing unit (CPU), a flash-flash, and an application specific integrated circuit (ASIC) It needs to reset the signal to automatically reset when it is powered on. In most designs, a specific reset chip is typically used to provide a reliable reset signal, or a microcontroller such as a CPU, Micro-Controller Unit (MCU), or programmable logic device (Complex) Programmable Logic Device (CPLD) and Field-Programmable Gate Array (FPGA), etc., output a reset signal after a specific time of booting by program counting or timing. A conventional power-on reset circuit is shown in FIG. 1 for generating a reset signal to the CPU 120, the flash 121, and the ASIC 122 after the circuit is powered up, and includes a DC power supply 10 and a reset wafer 11. The DC power source 1 outputs a DC signal to the reset chip 11, and the reset signal is processed by the reset chip 11 to generate a reset signal. The CPU 120, the Flash 121, and the ASIC 122 are reset. Figure 2 shows another conventional power-on reset circuit. The same as the 6 M343852 " is used to generate a reset signal to the CPU ^ 220, Flash 221 and ASIC 222 after the circuit is powered up, including DC power supply 20 and micro Controller 21. The DC power source 20 outputs a DC signal to the microcontroller 2 1. The microcontroller 21 processes the reset signal to reset the CPU 220, the Flash 221, and the ASIC 222. In the conventional power-on reset circuit, A specific reset crystal-chip or microcontroller is provided to provide a reset signal. However, both methods require an additional chip to complete the reset signal generation. The parameters of the reset chip are initially set by the wafer, which is difficult to adjust in subsequent use, the circuit flexibility is poor, and the cost is low. Higher. [New content] In view of this, it is necessary to provide a power-on reset circuit that can flexibly adjust the reset parameters at a lower cost. φ In addition, an electronic device using this power-on reset circuit is required to flexibly adjust the reset parameters with a lower cost. A power-on reset circuit is coupled to the external DC power source for receiving a power signal from the DC power source and generating a reset signal to the chip set. The power-on reset circuit includes a delay circuit, a shaping circuit, and a logic operation circuit. The delay circuit includes a first delay unit for delaying the received power signal and outputting the first delay signal, and a second delay unit for delaying the received power signal by the 7 M343852, and outputting the first Second time signal. The shaping circuit is connected to the delay circuit and includes an shaping unit connected to the first delay unit for shaping the first delay signal and outputting a second shaping unit of the first shaping signal, and is connected to the second delay unit. The second delay signal is used for shaping, and the second shaping 'number is output. The logic operation circuit is connected to the shaping circuit, and is configured to perform logic calculation on the first shaping signal and the second shaping signal, and output a reset signal. An electronic device connected to an external DC power source, including a chipset and a power-on reset circuit. The power-on reset circuit is connected to the external stream power source for receiving a power signal from the DC power source to generate a reset signal for resetting the chip set. The power-on reset circuit includes a delay circuit, a shaping circuit and a logic operation circuit. The delay circuit includes a first delay unit for delaying the power signal of the receiving_ and outputting the first delay signal; and a delay unit for performing the received power signal and outputting the second delay signal . The shaping circuit is connected to the extension circuit, and includes a first shaping unit connected to the first delay element for shaping the first delay signal and outputting a first shaping signal; a second shaping unit, and the second The extension unit is connected to shape the second delay signal to output a second shaping signal. The logic operation circuit is connected to the shaping circuit, and is configured to perform logic operations according to the first shaping signal and the second shaping delay, wherein the signal is sent to the first delay signal and the circuit number is 8 M343852 ' And output a reset signal to the chipset. The above and other advantages of the novel are readily apparent from the following detailed description of the embodiments of the invention. [Embodiment] FIG. 3 is a block diagram of an electronic device 2 of the present embodiment. The electronic device 2 includes a power-on reset circuit 3 - and a chip set 34. The power-on reset circuit 3 is connected to the external DC power supply 30 for receiving a power signal and generating a reset signal to the chip set 34. The power-on reset circuit 31 includes a delay circuit 31, a shaping circuit 32, and a logic operation circuit 33. In this embodiment, the delay circuit 31 includes a first delay unit 311 and a second delay unit 312. The shaping circuit 32 includes a first shaping unit 321 and a second shaping unit 32 2, and the chip group 34 includes but is not limited to the CPU 341. Flash 342 and ASIC 343 and other wafers. The first delay unit 311 and the second delay unit 312 are connected in parallel to the DC power supply 30. The first delay unit 311 is configured to delay the received power signal and output a first delay signal. Similarly, the second delay unit 3 1 2 is configured to delay the received power signal and output a second delay signal. The first shaping unit 321 is connected to the first delay unit 311 for shaping the first delay signal and outputting the first shaping signal. The second shaping unit 322 is connected to the second delay unit 321 for performing the second delay signal and outputting the second shaping signal. The logic operation circuit 33 is connected to the shaping circuit 32, that is, connected to the first shaping unit 321 and the second shaping unit 32, for performing logical operations according to the first shaping signal and the second shaping signal, and outputting Reset signal to the chip set 34 ° ' Figure 4 is a specific circuit diagram of the components shown in Figure 3. The first delay unit 311 includes a first capacitor C1 and a first resistor R1. The first capacitor C1 is used to charge the received power signal, and the first capacitor C1 and the first resistor R1 are serially connected to the DC. Power supply between 30 and ground. The second delay unit 312 includes a second capacitor C2 and a second resistor R2, wherein the second capacitor C2 is used to charge the received power signal, and the second resistor R2 and the second capacitor C2 are serially connected to the DC power source. 30 between the ground and the ground. In the power-on reset circuit 3 of the embodiment, the parameters of the first capacitor C1 and the first resistor R1 of the first delay unit 311 and the second capacitor C2 and the second resistor R2 of the second delay unit 312 can be implemented according to actual circuits. Need to adjust and match. Therefore, the delay time of the delay circuit 3 1 can be adjusted as needed, and the circuit flexibility is good. The first shaping unit 321 includes a first Schmitt element U1 having an input end and an output end. The input end is connected to the common node A of the first capacitor C1 and the first resistor R1, and the M343852 output end and the logic operation circuit 33 Connected to receive the first delay signal, and after shaping, output the first shaping signal. The second shaping unit 322 includes a second Schmitt element U2 having an input end and an output end. The input end is connected to the common node B of the second capacitor C2 and the second resistor R2, and the output end thereof is connected to the logic operation circuit 33. And configured to receive the second delayed signal, and after shaping, output the second shaped signal. In the present embodiment, the first Schmitt element U1 and the second Schmitt element U2 are Schmitt inverting triggers (74HC14). When the Schmitt inverting flip-flop is triggered, a low level signal is output; when the Schmitt inverting flip-flop is not triggered, a high level signal is output. Generally, the first Schmitt component U1 and the second Schmitt component U2 both have a high voltage level and a low voltage level. If the voltage of the initial input signal is higher than the high voltage level of the Schmitt components, The low voltage level is used as the trigger voltage; if the voltage of the initial input signal is lower than the low reference voltage of the Schmitt components, the high voltage level is used as the trigger voltage. In the present embodiment, the high voltage level of the first Schmitt element U1 or the second Schmitt element U2 is between about 2.5 and 2.6V, and the low voltage level is between about 2.3 and 2.4V. In other embodiments of the present invention, the first shaping unit 321 and the second shaping unit 322 may use a Schmitt trigger or a Schmitt inverting flip-flop according to different chip specifications, or may be composed of discrete elements 11 M343852 '. Therefore, the shaping parameters of the first shaping unit 3 21 and the second shaping unit 322 are adjustable, that is, the trigger voltage can be adjusted as needed, so that the circuit flexibility is better. The logic operation circuit 33 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the output of the first Schmitt element U1 for receiving the first 'shaped signal, and the cathode outputs the first logic signal. The anode of the second diode-body D2 is connected to the output terminal _ of the second Schmitt element U2 for receiving the second shaping signal, and the cathode thereof outputs the second logic signal. In other embodiments of the present invention, the logic operation circuit 33 can be matched with different digital components according to different wafer specifications, for example, it can be an OR gate operator or other logic gate components. Referring to (a), (b) and (c) of FIG. 5, FIG. 5 is the start time of the power-on reset circuit 3, so the instant of power-on is set to the initial Oms, and the power is turned on. The operation principle of the circuit 3 is detailed as follows: In FIG. 5(a), V(A) is the waveform of the first delay signal, and V(U1) is the waveform of the first shaping signal. In this embodiment, when the DC power supply 30 starts to supply power, the first capacitor C1 is instantaneously short-circuited, and the power signal is directly loaded on the common node A of the first capacitor C1 and the first resistor R1, and the output of the node A is outputted at this time. The first delay signal is equivalent to the power signal. Since the voltage of the power signal is higher than the voltage of the first Schmitt component U1 by 12 ^M343852 9t ', the low voltage level is used as the trigger voltage, and the Schmitt component U1 is triggered and outputs a low level. Shape signal. Thereafter, the first capacitor C1 is charged with respect to the power supply path, the first capacitor C1 starts to be charged, and the first delay signal begins to decrease. At the time T2, the first delay signal is just below the low voltage level, the first application When the secret-U1 is not triggered, the first shaping element of the high level is output. At the time of the start-up to the time T2, the first shaping unit outputs the first shaping signal of the low level. At the time T2, the first shaping unit 321 outputs the first level of the high level. In FIG. 5(b), V(B) is the second delayed signal, and V(U2) is the waveform of the second shaped signal. The working principle of 3 1 2 is opposite to that of the first delay unit. In this embodiment, when the DC power supply 30 is turned on, the second capacitor C2 is short-circuited instantaneously, and the power signal 3' is such that the second delay signal of the second capacitor C2 and the second resistor R2 is zero. . Since the second delay voltage is lower than the low voltage of the second Schmitt element U2 and the high voltage level is the trigger voltage, the second Schmitt U2 is not triggered, then the second shaping of the output high level is followed by the second The capacitor C 2 starts charging the power signal and the ground, and the power signal is loaded on the node B. The voltage of the second delay signal is charged in the second capacitor C2, so the first first whole number is the voltage component signal of the broken number. After the element 321, the signal is multi-signal. The wave of the second extension 3 11 phase power supply L to the ground, the position of the node B signal, the special component signal. Disconnected, so 13 M343852 starts to rise in the first case, until τ 1 time, the voltage of the second delay signal reaches the high voltage level, the second Schmitt component U2 is triggered, and the low level is output. Second plastic signal. Therefore, the second shaping unit 3 22 outputs a second shaping signal from high level to low level before and after the time of Τ1. Figure 5 (c) is a reset signal waveform diagram after integrating the first shaping signal and the second shaping signal, wherein V (OUT) is the waveform of the reset signal output by the logic circuit 33. Before the time T1, the first shaping unit 321 outputs a first shaping signal of a low level to the first diode D1, and the second shaping unit 322 outputs a second shaping signal of a high level to the second diode D2. Therefore, the first diode D 1 is turned off, and the first logic signal is a low level signal. At this time, the second diode D 2 is turned on, and the second logic signal is a high level signal, so the second logic signal causes the logic operation circuit 33 to output a high level electrical signal. Between the times T1 and T2, the first shaping unit 321 outputs a first shaping signal of a low level to the first diode D1, and the second shaping unit 322 outputs a second shaping signal of a low level to the second diode. The body D2 is such that the first diode D1 and the second diode D2 are both turned off, and the logic operation circuit 33 outputs a low level electrical signal. After the time T2, the first shaping unit 321 outputs a first shaping signal of a high level to the first diode D1, and the second shaping unit 322 outputs a second shaping signal of a low level to the second 14 • M343852 diode D2, so the first diode D1 is turned on, and the first logic 'signal is high. At this time, the second diode D2 is turned off, the second logic signal is low, and the first logic signal causes the logic operation circuit 33 to output a high level electrical signal. In the present embodiment, the time T1 is about 4 m s after the circuit is powered on, and the time T 2 is about 11 m s after the circuit is powered on. In summary, after the DC power supply 30 starts to supply power, the logic operation circuit 33 performs a logical OR operation according to the first shaping signal and the second shaping signal to generate a high level to a low level to a high level. The reset signal completes the reset of the chipset 34. The power-on reset circuit 3 provided by the new embodiment generates a reset signal reset chip set 34 through the two-way delay circuit 31, the two-way shaping circuit 32 and the logic operation circuit 33, and the parameters of the circuits are adjustable. It can be used as needed to increase the flexibility of the circuit and reduce costs. In summary, the new model complies with the new patent requirements and is filed under the law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional power-on reset circuit. 2 is a block diagram of another conventional power-on reset circuit. 15-M343852 FIG. 3 is a schematic diagram of a power-on reset circuit according to an embodiment of the present invention. 4 is a specific circuit diagram of FIG. 3 of the present invention. FIG. 5 is a waveform diagram of the signal of FIG. 4 of the present invention. [Main component symbol description] DC power supply 10, 20, 30 - Reset wafer 11 CPU 120 ^ 220 , 341 丨 F1 as: h 121 , 221 , 342 ASIC 122 , 222 , 343 Electronic device 2 Microcontroller 21 Power on reset Circuit 3 delay circuit 31 first delay unit 311 丨 second delay unit 312 shaping circuit 32 first shaping unit 321 second shaping unit 322 logic operation circuit 33 chip set 34 first capacitor C1 second capacitor C2 first - resistance R1 16 M343852 • 'Second resistance R2 ^ First Schmidt element U1 Second Schmidt element U2 First diode D 1 Second diode D 2
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