TWM318793U - Package structure of memory - Google Patents

Package structure of memory Download PDF

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Publication number
TWM318793U
TWM318793U TW96206784U TW96206784U TWM318793U TW M318793 U TWM318793 U TW M318793U TW 96206784 U TW96206784 U TW 96206784U TW 96206784 U TW96206784 U TW 96206784U TW M318793 U TWM318793 U TW M318793U
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Taiwan
Prior art keywords
memory
substrate
package structure
disposed
wafer
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TW96206784U
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Chinese (zh)
Inventor
En-Min Jow
Original Assignee
En-Min Jow
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Priority to TW96206784U priority Critical patent/TWM318793U/en
Publication of TWM318793U publication Critical patent/TWM318793U/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

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Description

M318793 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種半導體封裴結構，特別B 構。 、種冗憶體封裂結 【先前技術】 隨著記憶體容量需求的不斷提高，於記憶M318793 VIII. New Description: [New Technology Field] This creation is about a semiconductor sealing structure, especially B structure. , a kind of redundant memory blockade [previous technology] with the increasing demand for memory capacity, in memory

片堆疊成為一必然趨勢。第1圖所示為習知=憶裝結構中，晶 圖，如圖所示，記憶體晶片120與122疊置於基板11〇上封裝結構之示意 120、122係與控制晶片130並排設置（sid 。記憶體晶片 jf side ) 〇 11 a 體結構。基板110下方設置有複數個焊球16〇提供封裝體之對外 導電接點。然而，除了對記憶體容量的要求，如何達到輕薄短小 的尺寸亦是另一需克服的課題。 上亦設有至少-被動元件140。其中，記憶體晶片i2〇、广2 制晶片130係各自與基板110電性連接。封裝材料i5〇係包^ 憶體晶片120與122、控制晶片130與被動元件ι4〇構成一封裝Chip stacking has become an inevitable trend. 1 is a conventional=recall structure, a crystal pattern, as shown in the figure, the memory chips 120 and 122 are stacked on the substrate 11 and the package structure 120, 122 is arranged side by side with the control wafer 130 ( Sid. Memory chip jf side ) 〇11 a body structure. A plurality of solder balls 16 are disposed under the substrate 110 to provide external conductive contacts of the package. However, in addition to the memory capacity requirements, how to achieve a thin and light size is another problem to be overcome. At least a passive component 140 is also provided. The memory chip i2〇 and the wide wafer 130 are electrically connected to the substrate 110. The package material i5 〇 package ^ memory chip 120 and 122, the control chip 130 and the passive component ι4 〇 constitute a package

【新型内容】 為了解決上述問題，本創作目的之一係提供一種記憶體封裝 結構，藉由控制晶片設置於記憶體晶片下方基板開孔處，可縮小 整體記憶體封裝體之尺寸。 本創作目的之一係提供一種記憶體封裝結構，藉由控制晶片 設置於記憶體晶片下方基板開孔處，可增加容置記憶體晶片之空 間，利用封裝材料可一體成型製作成記憶卡結構。 5 M318793 為二達到上述目的，本創作—實施例之記憶體封裝結構，包 第T有—第一表面與—第二表面；一第一記憶體晶片，係 晶片承麵上並與基板電性連接；—穿孔，係設 二表面 上並板電μ接；至少一被動元件，係設置於基板上；以及= 料=包覆基板、第—記憶_、控編與被動元件並暴露出部2 【實施方式】 第圖第3圖、第4圖、第5圖與第6圖所示為本創作不同 例記憶體封裝結構之剖面側視圖。如第2圖所示，於本實施例中，^ 一基板10 ’此基板10係為一印刷電路板且具有電路於 ^材貝係由聚亞酿胺、玻璃、氧化銘、環氧樹脂、氧化皱與彈性物 其中之至少任—所構成。基板1()具有—第—表面與—第二表面。—第上 δ己憶體晶片20係設置於基板1〇之第一表面的一晶片承載區上，一點 二21设置於第一記憶體晶片2〇與基板1〇間用以固定第―: 10 基板1〇第-表面電性Ιΐ係利用複數條引線24讓第一記憶體晶片2〇與 彻接======㈣穿孔（圖上 34電性連接控制晶片％與基板H)於第二表面上。_線 另T於本實施例中，至少一被動元件4〇設置 土。-封裝材料50係包覆基板1〇、第一記憶體晶片2 弟表: 動元件4。、細與引線34並暴露出基 =3〇破 M318793[New Content] In order to solve the above problems, one of the objects of the present invention is to provide a memory package structure in which the size of the entire memory package can be reduced by controlling the wafer to be disposed at the substrate opening below the memory chip. One of the purposes of the present invention is to provide a memory package structure. By controlling the wafer to be disposed at the substrate opening below the memory chip, the space for accommodating the memory chip can be increased, and the memory card structure can be integrally formed by using the package material. 5 M318793 is the second object of the present invention, the memory package structure of the present invention, the package T has a first surface and a second surface; a first memory chip is a wafer carrier surface and is electrically connected to the substrate Connection; - perforation, two surfaces are connected to each other; at least one passive component is disposed on the substrate; and = material = cladding substrate, first memory, control and passive components and exposed portion 2 [Embodiment] FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are cross-sectional side views showing different memory package structures of the present invention. As shown in FIG. 2, in the present embodiment, the substrate 10' is a printed circuit board and has a circuit made of polyaramine, glass, oxidized, epoxy, Oxidation wrinkles and elastomers are at least any of them. The substrate 1() has a first surface and a second surface. The first δ hexamed body wafer 20 is disposed on a wafer carrying area on the first surface of the substrate 1 , and the 1-2 is disposed between the first memory chip 2 〇 and the substrate 1 固定 for fixing the first: 10 substrate 1 〇 first surface electrical 利用 system using a plurality of leads 24 to make the first memory wafer 2 〇 彻 = ====== (4) perforation (34 on the figure electrically connected to control the wafer% and substrate H) On the second surface. _ Line Another T In this embodiment, at least one passive component 4 is provided with soil. - The encapsulating material 50 is a cover substrate 1 and a first memory wafer 2: a moving element 4. , thin with lead 34 and exposed base = 3 broken M318793

根據上述，於</ ϊ *JU (圖上未示）與基板“二拉第—記憶體晶片2G係可利用複數個焊球 用綱一 22 如，4圖所不，於一實施例中，被動元件40亦可設置於基 板10之第二表面上，第一表面僅供設置記憶體晶片。 土According to the above, the </ ϊ *JU (not shown) and the substrate "two pull-memory wafer 2G system can utilize a plurality of solder balls for the first step 22, as shown in FIG. 4, in one embodiment. The passive component 40 can also be disposed on the second surface of the substrate 10. The first surface is only for the memory chip.

接續上述，請參照第5圖，於記憶體封裝結構中更包括複數 個導電接點60,如焊墊，設置於基板1〇所暴露出之第二表面上。 另，更包括複數個焊球62設置於焊墊上供辉接於其他元件上。 請參照第6圖，於一實施例中，記憶體封裝結構應用於記憶 卡封裝技術時，複數個導電接點60設置於基板1〇所暴露出之第 二表面上用作記憶卡對外電接之金手指。控制晶片3〇於基板1〇 開孔内設置於第一記憶體晶片20上，而被動元件40則設置於開 孔附近基板10第一表面上。因此’基板 10第一表面可完全 k供设置較大尺寸之記憶體晶片有效提局記憶卡内記憶體容 里。而封裝材料50則可一體成型的製作成記憶卡所需之外觀。 綜合上述，本創作記憶體封裝結構藉由控制晶片設置於記憶 體晶片下方基板開孔處，f縮小整體記憶體封裝體之尺寸。此 外’將被動元件設置於基板第二表面之開孔附近亦能縮小記憶體 封裝體之整體尺寸。另，本創作記憶體封裝結構應用於記憶卡封 装技術中，藉由控制晶片設置於記憶體晶片下方基板開孔處，可 增加基板第一表面容置記憶體晶片之空間，利用封裝材料則可一 體成型製作成記憶卡結構。此種設計可提高記憶卡内可封褒記憶 體晶片之空間以增加記憶體容量。 7 M318793 目的在為說t明本創作之技術思想及特點，其 施，當不能以之限定本創作^專 解本創作之内容並據以實 之精神所作之均等變化或專=:大凡依本創作所揭示 内。 乃應涵蓋在本創作之專利範圍 【圖式簡單說明】 第1圖所示為習知記憶體封裝結 不惠圖。 第2圖、第3圖、第4圖、第5圖與 憶體封裝結構之剖面側視圖。.一 6圖所示為本創作不同實施例記 【主要元件符號說明】 110 120 122 130 140 150 160 10 20 21In the above, referring to FIG. 5, a plurality of conductive contacts 60, such as solder pads, are further disposed on the second surface exposed by the substrate 1 in the memory package structure. In addition, a plurality of solder balls 62 are further disposed on the solder pads for connection to other components. Referring to FIG. 6 , in an embodiment, when the memory package structure is applied to the memory card packaging technology, a plurality of conductive contacts 60 are disposed on the second surface exposed by the substrate 1 to be used as a memory card for external electrical connection. The golden finger. The control chip 3 is disposed on the first memory chip 20 in the opening of the substrate 1 , and the passive element 40 is disposed on the first surface of the substrate 10 near the opening. Therefore, the first surface of the substrate 10 can be completely k for the memory chip of a larger size to effectively extract the memory contents in the memory card. The encapsulating material 50 can be integrally formed into a desired appearance of the memory card. In summary, the creative memory package structure reduces the size of the overall memory package by controlling the wafer to be disposed at the substrate opening below the memory chip. Further, the passive element is disposed near the opening of the second surface of the substrate to reduce the overall size of the memory package. In addition, the memory package structure is applied to the memory card packaging technology, and the control chip is disposed at the substrate opening below the memory chip, thereby increasing the space of the first surface of the substrate for accommodating the memory chip, and using the packaging material. The integrated molding is made into a memory card structure. This design increases the memory footprint of the memory card to increase the memory capacity. 7 M318793 The purpose is to explain the technical thoughts and characteristics of T Mingben's creation, and it is not possible to limit the creation of this creation by the content of the creation and to make equal changes or specialization according to the spirit of the truth. Within the creation of the creation. It should be covered in the patent scope of this creation. [Simple description of the drawing] Figure 1 shows the conventional memory package. Fig. 2, Fig. 3, Fig. 4, Fig. 5 and a cross-sectional side view of the memory package structure. Fig. 6 shows the different embodiments of the creation. [Main component symbol description] 110 120 122 130 140 150 160 10 20 21

22 基板 記憶體晶片 5己憶體晶片 控制晶片 被動元件 封裝材料 焊球 基板 第一記憶體晶片 黏著層 苐一 ^己憶體晶片 8 M318793 黏著層 引線 引線 控制晶片 黏著層 引線 被動元件 封裝材料 導電接點 焊球22 substrate memory chip 5 memory wafer control chip passive component packaging material solder ball substrate first memory wafer adhesion layer ^ ^ 己 体 体 8 8 M318793 adhesive layer lead wire control wafer adhesive layer lead passive component packaging material conductive connection Spot welding ball

Claims (1)

M318793 九、申請專利範圍： 1. 一種記憶體封裝結構，包含： 一基板，係具有一第一表面與一第二表面； 一第一記憶體晶片，係設置於該基板該第一表面之一晶片承載區上 並與該基板電性連接； 一穿孔’係設置於該基板之該晶片承載區上； 一控制晶片，於該穿孔内設置於該第一記憶體晶片上並與該基板電 性連接； 至少一被動元件，係設置於該基板上；以及 一封裝材料，係包覆該基板、該第一記憶體晶片、該控制晶片與該 被動元件並暴露出部分該第二表面。 2·如請求項1所述之記憶體封裝結構，其中該基板係為印刷電路 板0 3·如清求項1所述之記憶體封裝結構，其中該基板之材質係由聚 亞醯胺、玻璃、氧化鋁、環氧樹脂、氧化鈹與彈性物其中之至少任一所 構成。 、M318793 IX. Patent Application Range: 1. A memory package structure comprising: a substrate having a first surface and a second surface; a first memory chip disposed on the first surface of the substrate a wafer carrying region is electrically connected to the substrate; a through hole is disposed on the wafer carrying region of the substrate; a control wafer is disposed on the first memory wafer and electrically connected to the substrate Connecting; at least one passive component disposed on the substrate; and a packaging material covering the substrate, the first memory wafer, the control wafer and the passive component and exposing a portion of the second surface. The memory package structure according to claim 1, wherein the substrate is a printed circuit board. The memory package structure according to claim 1, wherein the material of the substrate is polyamine. At least one of glass, alumina, epoxy resin, cerium oxide and elastomer. , 5. 4·如請求項1所述之記憶體封裝結構，更包含一黏著層設置於該 第一記憶體晶片與該基板間。 6. 如凊求項1所述之記憶體封裝結構，更包含一電接結構電性連 接该第一記憶體晶片與該基板於該第一表面上。 7. 2叫求項5所述之記憶體封裝結構，其中該電接結構係為複數 條引線或複數個焊球。 求項1所述之記憶體封裝結構，更包含一打線接合結構電 性連接該控制晶片與該基板於該第二表面上。 ^求項1所述之記憶體封裝結構，更包含一黏著層設置於該 控制晶片與該第一記憶體晶片間。 =长項丨所述之記憶體封裝結構，其中該被動元件係設置於 邊基板之該第一表面上。 8. M318793 ”，其μ被動元件係設置於 ".二二所：封裝結構…含-第二記憶- 12.二 =:==:含，--13:==ή?^5. The memory package structure of claim 1, further comprising an adhesive layer disposed between the first memory chip and the substrate. 6. The memory package structure of claim 1, further comprising an electrical connection structure electrically connecting the first memory chip and the substrate to the first surface. 7. The memory package structure of claim 5, wherein the electrical connection structure is a plurality of leads or a plurality of solder balls. The memory package structure of claim 1 further comprising a wire bonding structure electrically connecting the control wafer and the substrate to the second surface. The memory package structure of claim 1, further comprising an adhesive layer disposed between the control wafer and the first memory chip. = The memory package structure of the long term, wherein the passive component is disposed on the first surface of the edge substrate. 8. M318793", its μ passive component is set in ". 22: package structure... contains - second memory - 12. 2 =: ==: contains, -13:==ή?^ 15.=^4所述之記憶想封裝結構，其中該些導電接點係為複 ΐ6·Ϊ = ^4所述之記憶體封裝結構，其中該些導電接點係為複 l7.=:=之記憶體封裝結構，更包含複_分別設15.=^4 The memory is intended to be a package structure, wherein the conductive contacts are memory package structures according to ΐ6·Ϊ = ^4, wherein the conductive contacts are complex l7.=:= The memory package structure, including the complex _ separately 1111
TW96206784U 2007-04-27 2007-04-27 Package structure of memory TWM318793U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8722457B2 (en) 2007-12-27 2014-05-13 Stats Chippac, Ltd. System and apparatus for wafer level integration of components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8722457B2 (en) 2007-12-27 2014-05-13 Stats Chippac, Ltd. System and apparatus for wafer level integration of components
TWI453843B (en) * 2007-12-27 2014-09-21 Stats Chippac Ltd System and apparatus for wafer level integration of components

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