M286511 八、新型說明： 【新型所屬之技術領域】 本創作係關於降壓轉換器、切換式調整器、以及功率轉換器。 【先前技術】 降壓轉換器(Buck Converters)普遍應用於電腦、通訊以及消費性產品中，用以將一 高輸入電壓準位(如12V)轉換為一較低電壓輸出(如3·3ν、2·5ν、、〇 9V···等）。其 中PWM(脈波寬度調變)切換係為電源轉換之主要技術，此外，一同步整流技術係用以 改良降壓轉換器於重載條件下的效率。 第一圖係繪示一習知之降壓轉換器。一開關20係耦接至該降壓轉換器之一輸入電 壓VIN。經由該開關20的動作將令該輸入電壓VlN之功率透過一電感器3〇轉換為一輸 出電壓V〇。由電阻器51與52所構成之一分壓器係粞接於該輸出電壓v〇與一接地參 考端之間。該分壓器並提供一正比於該輸出電壓V〇的訊號Vfb給一控制電路1〇，依據 該訊號VFB，該控制電路10輸出一切換訊號Swi，用以控制該開關2〇的導通/截止以達 到電壓調節之目的。一二極體22係耦接於該開關20與該接地參考端間，用以提供該 電感器30於開關20截止時之一電流循環路徑。 第二圖繪示一具有同步整流功能之習知降壓轉換器，一開關25係作為一同步整流 器，用以減少因第一圖中該二極體22之壓降所造成的功率損失。其中第一圖中之該二 極體22係可由第二圖中之一開關25之一寄生二極體23或外加的蕭特基二極體取代 之。一切換訊號SW2的邏輯位準係與該切換訊號Swi反向，用以導通/截止開關25。 第二A圖至第二D圖係纟會示該降壓轉換器之同步整流動作。參照第三a圖，當該 開關20導通，該開關25截止時，該輸入電壓VlN將供應一電流Ic透過該電感器3〇流 向一輸出電容40，藉以產生該輪出電壓v〇。該降壓轉換器的輸出係由該輸出電容4〇 兩端提供，同時，能量會被儲存於電感器30與電容器40之中。 5 M286511 如第三B圖繪示，當該開關20與該開關25截止時，該電感器3〇中所儲存的能量 將會透過開關25的寄生二極體23陸續供應至該降壓轉換器的輪出。隨後，如第三c 圖所示，該開關25便導通以減低該寄生二極體23的功率損失。於下個切換週期再次 導通該開關20以前，會先截止該開關25以避免發生跨導現象(cross c〇nducti〇n)造成之 短路。雖然同步整流動作能夠於重載條件下改善該降壓轉換器的效率，不過卻無法克 服在輕载條件下低效率的問題，該問題係由該輸出電容4〇的逆向放電現象所造成。如 第四圖所示，在輕載條件下，該電感器3〇中所儲存的能量在下次切換週期開始前便將 被元全釋放。因此該電容器4〇中所儲存的能量將透過電感器3〇與開關於逆向釋放。 再者，於輕載條件下，該降壓轉換器的主要功率損失與該切換訊號〜的切換頻 率F成正比，例如該電感器3〇的鐵損(c〇re 1〇ss)以及該開關2〇與於的切換損失。該降 壓轉換器的另-項主要功率損失義g該控織路1()的神;肖耗所造成。—切換週期 T係為該切換頻率F的倒數，其等式如下： T=1/F=(T ON-fT 〇FF) 其中τΟΝ與T〇FF分別為切換訊號〜的一導通時間(〇n行咖)與一截止時間_ time) 〇M286511 VIII. New Description: [New Technology Field] This creation is about buck converters, switching regulators, and power converters. [Prior Art] Buck Converters are commonly used in computers, communications, and consumer products to convert a high input voltage level (such as 12V) into a lower voltage output (such as 3·3ν, 2·5ν, 〇9V···, etc.). Among them, PWM (pulse width modulation) switching is the main technology of power conversion. In addition, a synchronous rectification technique is used to improve the efficiency of the buck converter under heavy load conditions. The first figure shows a conventional buck converter. A switch 20 is coupled to one of the input voltages VIN of the buck converter. The operation of the switch 20 causes the power of the input voltage V1N to be converted to an output voltage V〇 through an inductor 3〇. A voltage divider formed by resistors 51 and 52 is coupled between the output voltage v 〇 and a ground reference terminal. The voltage divider provides a signal Vfb proportional to the output voltage V〇 to a control circuit 1 〇. According to the signal VFB, the control circuit 10 outputs a switching signal Swi for controlling the on/off of the switch 2〇. In order to achieve the purpose of voltage regulation. A diode 22 is coupled between the switch 20 and the ground reference terminal to provide a current circulating path of the inductor 30 when the switch 20 is turned off. The second figure shows a conventional buck converter with synchronous rectification function. A switch 25 is used as a synchronous rectifier to reduce the power loss caused by the voltage drop of the diode 22 in the first figure. The diode 22 in the first figure may be replaced by a parasitic diode 23 of one of the switches 25 in the second figure or an additional Schottky diode. The logic level of a switching signal SW2 is opposite to the switching signal Swi for turning on/off the switch 25. The second A to second D diagrams show the synchronous rectification action of the buck converter. Referring to the third a diagram, when the switch 20 is turned on and the switch 25 is turned off, the input voltage V1N supplies a current Ic through the inductor 3 to an output capacitor 40, thereby generating the turn-on voltage v〇. The output of the buck converter is provided by the output capacitor 4 , at the same time, and energy is stored in the inductor 30 and the capacitor 40. 5 M286511 As shown in FIG. B, when the switch 20 and the switch 25 are turned off, the energy stored in the inductor 3〇 is continuously supplied to the buck converter through the parasitic diode 23 of the switch 25. The turn. Subsequently, as shown in the third c-picture, the switch 25 is turned on to reduce the power loss of the parasitic diode 23. Before the switch 20 is turned on again in the next switching cycle, the switch 25 is turned off first to avoid a short circuit caused by a transconductance phenomenon (cross c〇nducti〇n). Although the synchronous rectification operation can improve the efficiency of the buck converter under heavy load conditions, it cannot overcome the problem of low efficiency under light load conditions, which is caused by the reverse discharge phenomenon of the output capacitor 4〇. As shown in the fourth figure, under light load conditions, the energy stored in the inductor 3〇 will be fully released before the start of the next switching cycle. Therefore, the energy stored in the capacitor 4〇 will be reversely transmitted through the inductor 3〇 and the switch. Moreover, under light load conditions, the main power loss of the buck converter is proportional to the switching frequency F of the switching signal 〜, such as the iron loss (c〇re 1 〇 ss) of the inductor 3 以及 and the switch 2〇 and the switching loss. The other main power loss of the voltage-reducing converter is the result of the control of the weave 1(); - The switching period T is the reciprocal of the switching frequency F, and the equation is as follows: T = 1 / F = (T ON - fT 〇 FF) where τ ΟΝ and T 〇 FF are respectively an on-time of the switching signal ~ (〇n Line coffee) with a deadline _ time) 〇
=長該峨週射可降低功率損失。細，驗小W||與電 =F必須受限使其運作於極短的切換週期之中。為避:二 消耗。她«至.“、祕件下，可物換聊τ的延長錢低該降壓轉換器的功率 【新型内容】 具高ΙΓ目的係提供—種具有省電構件的降壓轉換器，用以於重、輕載條件下兼 同步整流切換裝置、以及一回 本創作提供i降壓轉換器，其包含-切換裝置、一 6 M286511 I晉健:換裝置侧於控讎达至該降轉鶴之輸出端的辨。朗步整流切換 步整流動作。該回授電路係依據負鶴件產生—_訊號。為節省輕載條 2的功⑽_帽鍋鱗，1—竭嫩鳴树生一紐訊 賴一省魏號。-第二電路齡考制授職與該紐訊舰生_絲換訊號以及一 田議魏分難繼職裝置與_步整細換裝置。触切換訊朗—戴止時間(off toe)係隨著貞載下降鱗長。該省電纖係職㈣換喊賊止_鼓關步整流 切換裝置與該降壓轉換器的部份控制電路以於輕载條件下達到省電目的。 為降低音頻雜訊，在該主切換訊號的一切換頻率落人音鮮以前，該主切換訊號與 該切換裝置便物用。當貞載增加，且該主讀峨賴城鮮超過音鱗，藉由該 回授訊號使得該主切換訊號係為啟用。 為讓本創作之上述和其他目的、特徵和優點能更纖碰，下文特舉較佳實施例， 並配合所附圖式，作詳細說明如下。 【實施方式】 參考第六圖，其繪示根據本創作實施例一降壓轉換器的一控制電路1〇的方塊圖。其 係包含-偏壓電路60、一回授電路80、一第一電路90與一第二電路7〇。該偏壓電路6〇 係供應該降壓轉換器中各電路的偏壓電流Ι0· ·ΙΝ. ·。一由電阻器51與52所構成的分壓 器係係耦接於該降壓轉換器的一輸出端與一接地參考端之間用以產生一訊號給該回 授電路80，該訊號VFB係與該降壓轉換器的一輸出電壓v〇成比例。該回授電路8〇依據 該δίΐ號Vfb產生一回授sfl號VB，用以表示負載條件。該第一電路90產生一振盪訊赛 PLS、一鋸齒波訊號VSAW、一省電訊號VG1以及一辅助控制訊號Vg2。 參考第一圖與第六圖，該第二電路70依據該回授訊號VB與該振盈訊號pLg;產生一 主切換訊號swl與一副切換訊號Sw2，以便控制一切換裝置2〇與一同步整流切換裝置 25。該切換裝置20係耦接至一輸入電壓V1N，用以控制傳送至該降壓轉換器之輸出端的 功率。該主切換訊號SW1的一戴止時間t〇ff係隨著負載的降低而增加。在該主切換訊號 Swi的該截止時間T0FF期間，該省電訊號VG1係可用來截止該降壓轉換器中的部份電路， 7 M286511 用以在域下翻省電的目的。該主切換喊Swi在其切細轉人音鮮之前將會停 用，以避免發生音頻雜訊。當負載增加，且令該主切換峨—的切換頻率高於音頻帶， 該回授訊號VB會使該主切換訊號Swi再次啟用。一旦該主切換訊號Swi的該截止時間 T〇FF因負載下降而延長時，該辅助控制織Vg2便可將該副城訊號—停用，用以截 止切換裝置25。所以，如第五A圖與第五3圖所分別繪示，本創作之降壓轉換器於重载 條件下的操作如同一具有同步整流功能的降壓轉換器，而於輕載條件下的操作則如同一 習知的降壓轉換器，以便改善該降壓轉換器的效率。 第七圖為根據本創作之該控制電路1〇的該偏壓電路6〇的一較佳實施例。該偏壓電 路60產生偏壓電流Ι()· ·Ιν· •。一能隙參考電壓電路11〇會產生一參考電壓與一參 • 考電壓vREF2。該參考電壓Vrefi係耦接至一第一電壓對電流轉換器，該第一電壓對電流 轉，器係由運算放大器112、一電阻器113與一電晶體114構成。該第一電壓對電流轉 換器依據該參考電壓V咖1以產生一定電流Ιιΐ4。一由電晶體115、116、117、118、⑽ 所構成的一第一電流鏡電路係依據該定電流In4產生偏壓電流Ι0··ΪΝ ·。該偏壓電流 1〇’ ·Ιν· ·係分別提供電源給該降壓轉換器中的各個電路。如第七圖所繪示，開關124、123 分別用來啟用與停用偏壓電流Ιν與Ιν+ι，以達成省電目的。開關124、123的導通或截止 則係受控於該省電訊號vG1。因此，該省電訊號Vgi會截止該降壓轉換器中在輕載下未 運作的電路。 第八圖係為根據本創作較佳實施例之該第二電路70的示意圖。該第二電路70包含 • 一正反器78，該正反器78之一輸入端D係由一供應電壓Vcc所提供，該正反器78之一 時脈輸入係由一來自反相器71所輸出的一反相振盪訊號/pLS所提供。一及閘乃的輸入 鈿係耦接至正反器78的一輸出、該反相振盪訊號/pls、以及該省電訊號Vgi。該及閘 79的一輸出係連接至一輸出緩衝電路用以產生該主切換訊號8谓。該輸出緩衝電路係由 及閘140、145以及反相器13〇、135所構成，用以避免切換裝置2〇與25發生跨導現象。 依據該振盪訊號PLS的下降緣以啟用該主切換訊號Swi。啟用該振盪訊號pLS與該省電 汛號vG1可停用該主切換訊號Swi。一反或閘76的一輸入係耦接至該及閘79的該輸出。 該副切換訊號SW2則係經由該反或閘76與該輸出緩衝電路而產生。所以，該副切換訊號 Sw2的相位與該主切換訊號Swi相反。該反或閘76的另一輸入係由該輔助控制訊號Vg2 供應。因此，當啟用輔助控制訊號丫似以節省電源時，便會截止該副切換訊號。 8 •6511 齡考第八圖，一比較器72白卜負輸入係由贿齒波訊號所供應。該比較器 的-正輸入則由該回授訊號Vb所供應，用以達成回授迴路控制。該比較器72的一輸 係雛至-及閘73的一輸入。該及閘73的一輸出則搞接至該正反器78的一重置輸 入。該及閘73的另-輸入係雛至一保護電路75的一輸出。該保護電路％包含過電壓、 過電流與過溫度保護功能，用以保護該降壓轉換器及與其相連的電路。因此，藉由該保 護電路75與該回授訊號Vb便可停止該主切換訊號‘發生作用。一偏壓電流^^該 偏壓電流IN+1分別提供電源給該保護電路75與該比較器72。在輕載條件下，偏壓電流 W々iN+2均會被停帛，以截止保護電路75與比較器72，用以降低功率消耗以達省電之 目的。 | 第九圖為根據本創作較佳實施例之該控制電路1〇的該回授電路8〇示意圖。該回授 電路80包含一轉導(trans-conductance)誤差放大器沿，其正輸入係由該參考電壓v_ 供應，其負輸入則由信號VFB供應。一電阻器82與一電容器83係耦接至該誤差放大器 81的一輸出以作為頻率補償用。一準位位移電晶體85的閘極會被連接至該轉導誤差放 大态81的該輸出；其源極係連接至由一電阻器86與一電阻器87組成之一衰減器，用以 產生回授訊號vB。偏壓電流^與In+3係供應電源給該轉導誤差放大器81。在輕載條件 下’該偏壓電流In+3係為停用’用以節省誤差放大器[的功率消耗。 第十圖為根據本創作較佳實施例之該控制電路10的該第一電路9〇示意圖。該第一 電路90包含一調變器1〇〇、一振盪電路與一省電電路，該調變器1〇〇其係由該回授訊號 • vB所供應，並依據該回授訊號Vb來產生一放電電流Id、一輕载訊號ν〇與一輔助控制 訊號VG2。該振盪電路包含一充電電流源150、一放電電流源ι6〇、一充電開關153、一 放電開關154、一電容器155與一振盪控制電路，用以產生該振盪訊號pLS與該鋸齒波 訊號VSAW。該省電電路係由一反及閘167所實施，其兩輸入係由該振盪訊號pLS與該 輕載訊號vD分別供應，用以產生該省電訊號vG1。該放電電流源係由電晶體151與152 組成之第一電流鏡所實施，該放電電流ID係透過該第一電流鏡電路耦接至該振盪控制電 路。該充電開關153係搞接於該充電電流源150與該電容器155之間。該放電開關154 係連接於該電容器155與該放電電流源的輸出之間。該振盪控制電路包含一具有高臨界 電壓VH的比較器161、一具有低臨界電壓VL的比較器162、一反及閘ι63、一反及閘 164與一反相器165。該比較器162與163均連接至該電容器155。該比較器161與162 的輸出會係連接至由該反及閘163與164所組成的閂鎖電路，用以產生振盪訊號pLs。 9 M286511 該放電開關154係由該振盪訊號PLS所控制其導通或截止，該放電開關153係透過該反 相器165由該振盪器訊號PLS所控制。藉由交替切換該充電開關153與該放電開關154, 便可產生振盪。 當負载降低，該放電電流b便會減少，而振盪訊號PLS的啟用時間則會隨之增加。 一旦負載低於臨界值，輕載訊號VD便啟用。當該輕載訊號VD與該振盪訊號PLS啟用時， 便會產生該省電訊號VG1。該充電電流源之一充電電流IA與該電容器155之電容值係決 定該主切換訊號Swi的最大導通時間TON。該放電電流ID與該電容器155係決定該主切 換訊號SW1的一截止時間TOFF。該充電電流Ια係為一定值電流，而該放電電流ID則會 隨著負載的變化而改變。 第^*一圖為根據本創作較佳實施例之該調變器100示意圖。該調變器1〇〇包含一 運鼻放大β 182 ’該運鼻放大器182係由該回授訊號Vb供應。一運算放大器181係由 該參考電壓VREF1供應。一電晶體185與一電阻器183結合運算放大器181與182組成 一第二電壓對電流轉換器’用以產生一電流I1SS。一旦該回授訊號VB低於該參考電壓 Vref2，該電流Ii85便會隨著該回授訊號VB的減少而增加。由電晶體186與187所組成 的一第二電流鏡電路係接收該電流IlSS，用以產生一電流Ii87。一定偏壓電流Ιι係供應 至由電晶體188、189、190與196所組成的一第三電流鏡電路，用以分別產生一電流 1½9、一電流Ii9〇與一電流11%。該電晶體187之一汲極係與該電晶體189之一汲極相連 接。由電晶體191、192、193、194與195所組成的一第四電流鏡電路係接收該電流Il89 與該電流I丨87的一差值電流，用以產生一電流、一電流ι193、一電流ιΐ94與一電流 I!95。該電晶體192之一汲極係與該電晶體190之一汲極相連接。該電晶體193之一汲 極係與該電晶體196之一沒極相連接。一反相緩衝器207的一輸入係輕接至該電晶體 193的該沒極。該反相緩衝器207的一輸出會產生輔助控制訊號Vg2。一開關2〇1的一 第一端係耦接至該電晶體194用以接收一電流I】94。該開關2〇1的一第二端係耦接至一 緩衝器205的一輸入。該電流lm與該電流^洲的差異電流會被供應至緩衝器2〇5的輸 入。一開關202係耦接至一電流用以產生該放電電流1〇。該緩衝器2〇5的一輸出係 控制該開關201與202的導通或截止。一反相器206係耦接至該緩衝器2〇5的該輸出， 用以產生該fe載訊號VD。該輕載訊號vD的臨界準位係為可調以用來消除音頻雜訊。 該故電電流ID係決定該主切換訊號Swi的切換頻率。當該主切換訊號的切換頻率 落入音頻帶時，該開關202便會截止，以便停用該放電電流Id與該切換訊號Swi，用 10 M286511 以消除音讎訊。當負載增加，該回授訊號Vb便會導通該開_ 電電流lD，而使触切換訊號Swi_換辭高於音鮮。 第十二圖綱本創作社切換訊號Swi的波糊。其中s_表蝴條件下的 主切換訊號’而S輝》表示輕載條件下的主切換訊號。當該缝訊號PLS被啟用時， 該主切換咖^觸_㈣軸蝴w祕讀職〜的最 大導通時間TON*為固定，以防止磁性元件發生飽和。 以上所述均僅為本創作之實施例，其目的並非限定本創作之申請專利範圍；孰習本 技藝的人讀㈣…凡在未麟本嚴觸私精神谓完紅等魏變雜飾均應 包含在下文申請專利範圍的範脅内。 【圖式簡單說明】 在此所附之圖表是用來妓描述本創作，並引用與包含詳細規格的一部份，以下的 圖表描繪出本創作的實施例，並配合詳細說明部分，用以解釋本創作的原理。 第一圖係繪示一習知的降壓轉換器。 第二圖係繪示一具有同步整流功能的習知降壓轉換器。 第-A圖至第二D圖係繪不第二圖之該習知降壓轉換㈣同步整流運作。 第四圖係繪示輕載條件下第二圖之該習知降壓轉換器之一反向放電現象。 Φ 帛五A目，崎示-冑鱗降雜換n㈣祕件。 第五B圖係緣示該高效率降壓轉換器於輕载條件下之運作。 第六圖係繪示本創作實施例之降壓轉換器的一控制電路方塊圖。 第七圖係繪示根據本創作實施例之該控制電路的一偏壓電路。 第八圖係繪示本創作實施例之該控制電路的一第二電路。 第九圖係繪示本創作實施例之該控制電路的—回授電路。 第十圖係繪示本創作實施例之該控制電路的一第一電路。 第十一圖係繪示本創作實施例之該第一電路的一調變器示意圖。 第十二圖係繪示本創作的切換訊號的波形圖。 11 ；M286511 【主要元件符號說明】 ίο:控制電路 22 :二極體 25 :開關 40 :電容器 52 :電阻器 70 ··第二電路 72 :比較器 75 :保護電路 78 :正反器 80 :回授電路 82 :電阻器 85 :電晶體 87 :電阻器 100 :調變器 112 :運算放大器 114〜119 :電晶體 124 :開關 135 :反向器 145 :及閘 151 :電晶體 153 :開關 155 :電容 161 :比較器 163 :反及閘 165 :反向器 181 ··運算放大器 183 :電阻器 201 ··開關 20 :開關 23 :寄生二極體 30 :電感器 51 :電阻器 60 :偏壓電路 71 :反向器 73 :及閘 76 :反或閘 79 ··及閘 81 :誤差放大器 83 :電容器 86 :電阻器 90 :第一電路 110 :能隙參考電壓電路 113 :電阻器 123 :開關 130 :反向器 140 :及閘 150 :充電電流源 152 :電晶體 154 :開關 160 :放電電流源 162 :比較器 164 :反及閘 167 :反及閘 182 :運算放大器 185〜196 :電晶體 202 ··開關 12= Long this shot can reduce power loss. Fine, small W|| and electric =F must be limited to operate in a very short switching cycle. To avoid: two consumption. She «to.", under the secret, can change the power of the buck converter to lower the power of the buck converter. [New content] The high-end purpose is to provide a buck converter with power-saving components for Under the heavy and light load conditions, the synchronous rectification switching device, and a copy of the original i-buck converter, including the -switching device, a 6 M286511 I Jinjian: changing the device side to control the reach of the descending crane The identification of the output end. The step-step rectification switching step rectification action. The feedback circuit is based on the negative crane piece to generate the -_ signal. To save the light load strip 2 work (10) _ cap pot scale, 1 - exhausted Ming Ming tree one Xun Lai, a province, Wei. - The second circuit age test and the new train ship _ silk exchange number and one Tian Wei Wei points difficult to succeed the device and _ step fine change device. Touch switch lang - wear The off-e time is as long as the load is reduced. The province's electric fiber department (4) exchanges the thief to stop the drum switch and the partial control circuit of the buck converter for light load conditions. To achieve the purpose of power saving. In order to reduce the audio noise, the main switching is performed before the switching frequency of the main switching signal falls into the sound. The number and the switching device are used for convenience. When the load is increased, and the main reading 峨 鲜 鲜 rarely exceeds the scale, the main switching signal is enabled by the feedback signal. For the above and other purposes of the present creation The features, advantages and advantages of the present invention are described in detail below with reference to the accompanying drawings. [Embodiment] Referring to the sixth figure, a step-down conversion according to the present embodiment is illustrated. A block diagram of a control circuit 1A includes a bias circuit 60, a feedback circuit 80, a first circuit 90 and a second circuit 7. The bias circuit 6 supplies the The bias current of each circuit in the buck converter is Ι0···. A voltage divider system composed of resistors 51 and 52 is coupled to an output terminal of the buck converter and a ground reference terminal. A signal is generated to the feedback circuit 80, and the signal VFB is proportional to an output voltage v〇 of the buck converter. The feedback circuit 8 generates a feedback sfl number according to the δίΐ Vfb. VB is used to indicate the load condition. The first circuit 90 generates an oscillation PLS, a sawtooth Wave signal VSAW, a power saving signal VG1 and an auxiliary control signal Vg2. Referring to the first and sixth figures, the second circuit 70 generates a main switching signal swl according to the feedback signal VB and the vibration signal pLg; A pair of switching signals Sw2 for controlling a switching device 2 and a synchronous rectifying switching device 25. The switching device 20 is coupled to an input voltage V1N for controlling power delivered to an output of the buck converter. The wear time t〇ff of the main switching signal SW1 increases as the load decreases. During the off time T0FF of the main switching signal Swi, the power saving signal VG1 can be used to cut off the buck converter. Part of the circuit, 7 M286511 is used to save power in the domain. The main switch shouts Swi will be disabled before it is cut to avoid audio noise. When the load is increased and the switching frequency of the main switch is higher than the audio band, the feedback signal VB causes the main switching signal Swi to be enabled again. Once the cutoff time T〇FF of the main switching signal Swi is extended due to the load drop, the auxiliary control woven Vg2 can deactivate the sub-city signal to stop the switching device 25. Therefore, as shown in FIG. 5A and FIG. 3 respectively, the buck converter of the present invention operates under heavy load conditions like a buck converter with synchronous rectification function, and under light load conditions. The operation is like a conventional buck converter to improve the efficiency of the buck converter. The seventh figure shows a preferred embodiment of the bias circuit 6A of the control circuit 1 according to the present invention. The bias circuit 60 generates a bias current Ι()··Ιν··. A bandgap reference voltage circuit 11 produces a reference voltage and a reference voltage vREF2. The reference voltage Vrefi is coupled to a first voltage-to-current converter. The first voltage-to-current converter is formed by an operational amplifier 112, a resistor 113 and a transistor 114. The first voltage-to-current converter generates a constant current Ιιΐ4 according to the reference voltage V. A first current mirror circuit formed by the transistors 115, 116, 117, 118, and (10) generates a bias current Ι0··· according to the constant current In4. The bias currents 1 〇 ' · Ι ν · provide power to the respective circuits in the buck converter. As shown in the seventh figure, the switches 124, 123 are used to enable and disable the bias currents Ιν and Ιν+ι, respectively, to achieve power saving purposes. The turning on or off of the switches 124, 123 is controlled by the power saving signal vG1. Therefore, the power-saving signal Vgi will cut off the circuit in the buck converter that is not operating under light load. The eighth figure is a schematic diagram of the second circuit 70 in accordance with a preferred embodiment of the present invention. The second circuit 70 includes a flip-flop 78. One of the input terminals D of the flip-flop 78 is provided by a supply voltage Vcc. One of the clock inputs of the flip-flop 78 is provided by an inverter 71. The output is supplied by an inverted oscillation signal /pLS. The input of the gate is coupled to an output of the flip-flop 78, the inverted oscillation signal /pls, and the power-saving signal Vgi. An output of the AND gate 79 is coupled to an output buffer circuit for generating the primary switching signal. The output buffer circuit is composed of gates 140 and 145 and inverters 13 and 135 to prevent transconductance of switching devices 2 and 25. The main switching signal Swi is enabled according to the falling edge of the oscillation signal PLS. The main switching signal Swi can be deactivated by enabling the oscillation signal pLS and the power saving signal vG1. An input of a reverse gate 76 is coupled to the output of the AND gate 79. The sub-switching signal SW2 is generated via the inverse gate 76 and the output buffer circuit. Therefore, the phase of the sub-switching signal Sw2 is opposite to the main switching signal Swi. The other input of the inverse gate 76 is supplied by the auxiliary control signal Vg2. Therefore, when the auxiliary control signal is enabled to save power, the sub-switching signal is turned off. 8 • The eighth picture of the 6511 age test, a comparator 72 white input is supplied by the bribe signal. The positive input of the comparator is supplied by the feedback signal Vb for feedback loop control. An input of the comparator 72 is coupled to an input of the AND gate 73. An output of the AND gate 73 is coupled to a reset input of the flip-flop 78. The other input of the AND gate 73 is coupled to an output of a protection circuit 75. The protection circuit % includes overvoltage, overcurrent and overtemperature protection functions to protect the buck converter and the circuit connected thereto. Therefore, the main switching signal _ can be stopped by the protection circuit 75 and the feedback signal Vb. A bias current, the bias current IN+1, supplies power to the protection circuit 75 and the comparator 72, respectively. Under light load conditions, the bias current W々iN+2 is stopped to turn off the protection circuit 75 and the comparator 72 to reduce power consumption for power saving purposes. The ninth drawing is a schematic diagram of the feedback circuit 8 of the control circuit 1 according to the preferred embodiment of the present invention. The feedback circuit 80 includes a trans-conductance error amplifier edge whose positive input is supplied by the reference voltage v_ and whose negative input is supplied by the signal VFB. A resistor 82 and a capacitor 83 are coupled to an output of the error amplifier 81 for frequency compensation. The gate of a level shifting transistor 85 is coupled to the output of the transducing error amplification state 81; the source is coupled to an attenuator comprised of a resistor 86 and a resistor 87 for generating The feedback signal vB. The bias current ^ and the In+3 supply power are supplied to the transimpedance error amplifier 81. Under light load conditions, the bias current In+3 is disabled to save power consumption of the error amplifier. FIG. 10 is a schematic diagram of the first circuit 9 of the control circuit 10 according to the preferred embodiment of the present invention. The first circuit 90 includes a modulator 1 , an oscillating circuit and a power saving circuit. The modulator 1 is supplied by the feedback signal v b and is based on the feedback signal Vb. A discharge current Id, a light load signal ν〇 and an auxiliary control signal VG2 are generated. The oscillating circuit comprises a charging current source 150, a discharging current source ι6, a charging switch 153, a discharging switch 154, a capacitor 155 and an oscillating control circuit for generating the oscillating signal pLS and the sawtooth signal VSAW. The power-saving circuit is implemented by a reverse gate 167. The two input systems are respectively supplied by the oscillation signal pLS and the light-load signal vD to generate the power-saving signal vG1. The discharge current source is implemented by a first current mirror composed of transistors 151 and 152, and the discharge current ID is coupled to the oscillation control circuit through the first current mirror circuit. The charging switch 153 is coupled between the charging current source 150 and the capacitor 155. The discharge switch 154 is connected between the capacitor 155 and the output of the discharge current source. The oscillation control circuit includes a comparator 161 having a high threshold voltage VH, a comparator 162 having a low threshold voltage VL, a gate ι 63, a gate 164 and an inverter 165. Both comparators 162 and 163 are connected to the capacitor 155. The outputs of the comparators 161 and 162 are coupled to a latch circuit comprised of the NAND gates 163 and 164 for generating an oscillating signal pLs. 9 M286511 The discharge switch 154 is turned on or off by the oscillation signal PLS, and the discharge switch 153 is controlled by the inverter signal 165 through the inverter signal PLS. By alternately switching the charging switch 153 and the discharging switch 154, oscillation can be generated. When the load is reduced, the discharge current b is reduced, and the activation time of the oscillation signal PLS is increased. Once the load is below the threshold, the light load signal VD is enabled. When the light-loaded signal VD and the oscillation signal PLS are enabled, the power-saving signal VG1 is generated. The charging current IA of the charging current source and the capacitance value of the capacitor 155 determine the maximum on-time TON of the main switching signal Swi. The discharge current ID and the capacitor 155 determine an off time TOFF of the main switching signal SW1. The charging current Ια is a constant current, and the discharging current ID changes as the load changes. Figure 1 is a schematic diagram of the modulator 100 in accordance with a preferred embodiment of the present invention. The modulator 1A includes a nose amplification β 182 '. The nose amplifier 182 is supplied by the feedback signal Vb. An operational amplifier 181 is supplied from the reference voltage VREF1. A transistor 185 in combination with a resistor 183, operational amplifiers 181 and 182, constitutes a second voltage to current converter ' for generating a current I1SS. Once the feedback signal VB is lower than the reference voltage Vref2, the current Ii85 increases as the feedback signal VB decreases. A second current mirror circuit composed of transistors 186 and 187 receives the current I1SS to generate a current Ii87. A certain bias current is supplied to a third current mirror circuit composed of transistors 188, 189, 190 and 196 for generating a current 11⁄29, a current Ii9, and a current 11%, respectively. One of the gates of the transistor 187 is connected to one of the gates of the transistor 189. A fourth current mirror circuit composed of transistors 191, 192, 193, 194 and 195 receives a difference current between the current I89 and the current I 丨 87 for generating a current, a current ι 193, and a current Ιΐ94 with a current I!95. One of the gates of the transistor 192 is connected to one of the drains of the transistor 190. One of the transistors 193 is connected to one of the transistors 196. An input of an inverting buffer 207 is lightly coupled to the pole of the transistor 193. An output of the inverting buffer 207 generates an auxiliary control signal Vg2. A first end of a switch 2〇1 is coupled to the transistor 194 for receiving a current I] 94. A second end of the switch 2〇1 is coupled to an input of a buffer 205. The difference current between the current lm and the current is supplied to the input of the buffer 2〇5. A switch 202 is coupled to a current for generating the discharge current 1〇. An output of the buffer 2〇5 controls the on or off of the switches 201 and 202. An inverter 206 is coupled to the output of the buffer 2〇5 for generating the fe-loaded signal VD. The threshold level of the light-loaded signal vD is adjustable to eliminate audio noise. The current electric current ID determines the switching frequency of the main switching signal Swi. When the switching frequency of the main switching signal falls into the audio band, the switch 202 is turned off to disable the discharging current Id and the switching signal Swi, and 10 M286511 is used to eliminate the audio signal. When the load increases, the feedback signal Vb turns on the ON_electric current lD, and the touch switching signal Swi_ is replaced by the sound. The twelfth map outlines the creative agency to switch the signal Swi. The main switching signal 'and S hui' under the s_ table condition indicates the main switching signal under light load conditions. When the slit signal PLS is enabled, the maximum switching time TON* of the main switching device is fixed to prevent saturation of the magnetic component. All of the above are only examples of the present invention, and the purpose is not to limit the scope of the patent application of this creation; the person who learns the skill of the art reads (4)...Where the spirit of the untouchable spirit is finished, the red is changed. It should be included in the scope of the patent application scope below. BRIEF DESCRIPTION OF THE DRAWINGS The drawings attached hereto are used to describe the creation, and to reference and include a part of the detailed specifications. The following diagrams depict an embodiment of the creation and are used in conjunction with the detailed description. Explain the principles of this creation. The first figure shows a conventional buck converter. The second figure shows a conventional buck converter with synchronous rectification function. The first to second figures D show the conventional step-down conversion (four) synchronous rectification operation of the second figure. The fourth figure shows the reverse discharge phenomenon of one of the conventional buck converters in the second diagram under light load conditions. Φ 帛 A A A, 崎 胄 胄 胄 胄 降 降 降 降 降 换 。 。 。 。 。 。 。. Figure 5B shows the operation of the high efficiency buck converter under light load conditions. Figure 6 is a block diagram showing a control circuit of the buck converter of the present embodiment. The seventh drawing shows a bias circuit of the control circuit according to the present embodiment. The eighth figure shows a second circuit of the control circuit of the present embodiment. The ninth drawing shows the feedback circuit of the control circuit of the present embodiment. The tenth figure shows a first circuit of the control circuit of the present embodiment. Figure 11 is a schematic diagram showing a modulator of the first circuit of the present embodiment. The twelfth figure shows the waveform diagram of the switching signal of the present creation. 11; M286511 [Description of main component symbols] ίο: Control circuit 22: Diode 25: Switch 40: Capacitor 52: Resistor 70 · Second circuit 72: Comparator 75: Protection circuit 78: Reactor 80: Back Circuit 82: Resistor 85: Transistor 87: Resistor 100: Modulator 112: Operational Amplifiers 114-119: Transistor 124: Switch 135: Inverter 145: and Gate 151: Transistor 153: Switch 155: Capacitor 161: Comparator 163: Inverting gate 165: Inverter 181 · Operational amplifier 183: Resistor 201 · Switch 20: Switch 23: Parasitic diode 30: Inductor 51: Resistor 60: Bias current Road 71: reverser 73: and gate 76: reverse or gate 79 ·· and gate 81: error amplifier 83: capacitor 86: resistor 90: first circuit 110: bandgap reference voltage circuit 113: resistor 123: switch 130: reverser 140: and gate 150: charging current source 152: transistor 154: switch 160: discharge current source 162: comparator 164: reverse gate 167: reverse gate 182: operational amplifiers 185 to 196: transistor 202 ··Switch 12
M286511 205 :緩衝器 206 :反相器 207 :反相缓衝器 I〇、Ii、In、In+1、 In+2、In+3 :偏壓電流 Ια :充電電流 Id :放電電流 PLS :振盪訊號 SW1 :主切換訊號 SW2 :副切換訊號 T〇ff :截止時間 T〇n :導通時間 Vb :回授訊號 Vcc :供應電壓 VD :輕載訊號 Vfb ··訊號 VG1 :省能訊號 VG2 :輔助控制訊號 VIN :輸入電壓 Vo :輸出電壓 VsAW :雜齒波訊號 Vrefi :參考電壓 VreF2 :參考電壓 13M286511 205: Buffer 206: Inverter 207: Inverting buffer I〇, Ii, In, In+1, In+2, In+3: Bias current Ια: Charging current Id: Discharge current PLS: Oscillation Signal SW1: main switching signal SW2: sub-switching signal T〇ff: cut-off time T〇n: on-time Vb: feedback signal Vcc: supply voltage VD: light-loaded signal Vfb ··signal VG1: energy-saving signal VG2: auxiliary control Signal VIN: input voltage Vo: output voltage VsAW: noise signal Vrefi: reference voltage VreF2: reference voltage 13