M278957 八、新型說明： 【新型所屬之技術領域】 本新型係關於一種電源啟動重置電路，尤其關於一種 可精確設定重置完成電壓之電源啟動重置電路。 【先前技術】 大部分的積體電路晶片通常設置有許多的電晶體與 φ 基本的邏輯電路單元。在開啟電源電壓之後，電源電壓從 零逐漸上升至一預定的穩定值，隨後使積體電路晶片在此 穩疋值下進行正常的操作。為了避免積體電路晶片之電晶 體與邏輯電路單元發生初始狀態不確定之狀況，必須在電 源電壓達到穩定的操作電壓位準之冑，對於積體電路晶片 之電晶體與邏輯電路單元進行重置階段之操作。因此，電 ^ ^ t ^ „ (P〇Wer.〇n Reset Circuit)#^ # ^ t ^ ^ 動重置k號，用以在電源電壓達到穩定值之前控制重置階 • 段之進行與終止，而確保穑轉 能。 、積體電路日日片具有確定的初始狀 典型上’同一個積濟堂？々曰 電源mb u 片可設計成允許其操作於 有各種穩定值之應用狀況。然而，無論電 壓之穩定值為何，積體電路 …、 ’、 -特定信0士 μ 皆要求在電源電壓達到某 「重置完成f^ 、成（口此以下稱此特定值為 在電源雷懕、圭$丨击m 、電路日日片之初始狀態必須 在笔源錢達到重置完成電 正當握你 ^ ^ IL 了 P已確疋以便開始進行 止吊知作。不幸地，習知 ^原啟動重置電路無法滿足此 4 M278957 項要求。 【新型内容】 …本新5L之目的在於提供一種電源啟動重置電路，可設 定並調整重置完成電壓。 依據本新型之電源啟動重置電路具有重置開始電 路重置το成電路、以及閃鎖電路。重置開始電路回應於 • t源電壓而產生重置開始信號。當該電源電壓達到一預定 的重置完成電壓時，重置完成電路產生重置完成信號。閃 2電路產生電源啟動重置信號，其具有第一狀態與第二狀 心a回應於重置開始信號，閂鎖電路使電源啟動重置信號 轉怨至第一狀態。回應於重置完成信號，閂鎖電路使電源 啟動重置信號轉態至第二狀態。 重置70成電路具有電壓偵測單元、參考電壓產生單 凡、以及電壓比較單元。電壓偵測單元產生一偵測電壓， f S代表電源電壓。參考電壓產生單元產生一參考電壓，其 關聯於重置完成電壓。電壓比較單元比較偵測電壓與參考 電壓，使得當偵測電壓達到參考電壓時，電壓比較單元被 觸發而產生重置完成信號。 在貫知例中，回應於重置開始信號，閂鎖電路賦能 重置兀成電路。在另一實施例中，閂鎖電路與重置完成電 路間設置有一延遲電路，用以在問鎖電路使電源啟動重置 化號處於第一狀態之後，經過一延遲時間後才賦能重置完 成電路。 5 M278957- L貫施方式】 下文中之說明與附圖將使本新型之 的、特徵、盥優戥语 ^ 月〗、其他目 ^坆點更明顯。茲將參照圖式詳細說明依# & 新型之較佳實施例。 5依據本 10之圖詳1顯不依據本新型第一實施例之電源啟動重置電路M278957 8. Description of the new type: [Technical field to which the new type belongs] This new type relates to a power-on reset circuit, especially a power-on reset circuit that can accurately set the reset completion voltage. [Prior art] Most integrated circuit chips are usually provided with many transistors and φ basic logic circuit units. After the power supply voltage is turned on, the power supply voltage gradually rises from zero to a predetermined stable value, and then the integrated circuit chip is allowed to perform normal operations at this stable value. In order to prevent the initial state of the transistor and logic circuit unit of the integrated circuit chip from being uncertain, the transistor and the logic circuit unit of the integrated circuit chip must be reset when the power supply voltage reaches a stable operating voltage level. Phase operation. Therefore, the power ^ ^ t ^ „(P〇Wer.〇n Reset Circuit) # ^ # ^ t ^ ^ resets the k number automatically to control the progress and termination of the reset phase before the power voltage reaches a stable value However, the integrated circuit chip has a certain initial state. “The same Jijitang?” The power supply MBu chip can be designed to allow its operation in applications with various stable values. However, Regardless of the stable value of the voltage, the integrated circuit ..., ',-a specific letter 0 μ μ requires that the power supply voltage reaches a certain "reset completed f ^, Cheng (hereafter referred to as this specific value in the power supply thunder, The initial state of the circuit board and the daily film must be reset when the pen source money is reached, and the electricity is properly held ^ ^ IL has been confirmed in order to start the suspension of knowledge. Unfortunately, the original ^ The reset circuit cannot meet the requirements of 4 M278957. [New content]… The purpose of this new 5L is to provide a power-on reset circuit that can set and adjust the reset completion voltage. According to this new type of power-on reset circuit, Reset the start circuit το 成Circuit and flash lock circuit. The reset start circuit generates a reset start signal in response to the t source voltage. When the power supply voltage reaches a predetermined reset completion voltage, the reset completion circuit generates a reset completion signal. Flash 2 The circuit generates a power-on reset signal, which has a first state and a second state a. In response to the reset start signal, the latch circuit turns the power-on reset signal to the first state. In response to the reset completion signal, the The lock circuit makes the power-on reset signal transition to the second state. The reset 70% circuit has a voltage detection unit, a reference voltage generation unit, and a voltage comparison unit. The voltage detection unit generates a detection voltage, f S stands for Power voltage. The reference voltage generating unit generates a reference voltage that is related to the reset completion voltage. The voltage comparison unit compares the detection voltage with the reference voltage so that when the detection voltage reaches the reference voltage, the voltage comparison unit is triggered to generate a reset Completion signal. In the conventional example, in response to the reset start signal, the latch circuit enables the resetting circuit. In another embodiment, the latch A delay circuit is provided between the circuit and the reset completion circuit, which is used to enable the reset completion circuit after a delay time after the interlock circuit makes the power-on reset reset number in the first state. 5 M278957- L 贯 施Mode] The following description and drawings will make the features, features, language, and other objectives of the new model more obvious. The detailed implementation of the new model will be described in detail with reference to the drawings. Ex. 5 According to the diagram of this 10, 1 shows the power-on reset circuit according to the first embodiment of the new model.
、、、田電路圖。參照圖i，電源啟動重 一重置開妒雷枚,， 且电浴包括 ]。電路11、一閂鎖電路12、以 路13。重詈鬥仏中 里罝凡成電 置開始電路11產生一重置開始信號RST， 加至閂鎖雷1， ‘ 電路12。重置完成電路13產生一重置完成信號 ™S且施加至閃鎖電路12。重置完成電路13係基於從 閃鎖電路12之輸出端所回授的賦能信號EN而啟動。回應 於重置開始信號RST與重置完成信號FNS，閂鎖電路U 決定電源啟動重置信號p〇R之狀態。電源啟動重置信號 POR係施加至積體電路晶片中之其他電路（未圖示）以進行 重置階段之操作。 重置開始電路1丨主要具有一電壓偵測單元以及一觸 發單元。電壓偵測單元產生一偵測電壓Vsen，用以代表電 源電壓vpw。電壓偵測單元得由電阻R1與電容C1串聯而 成之電容性分壓電路所實施。當電源電壓vpw從零開始上 升時，電阻R1與電容C1間之串聯耦合點A提供一隨著 電源電壓Vpw而變化之分壓，作為偵測電壓。觸發單 元得由一史米特觸發器（Schmidt Trigger)ST串聯一反相$ 所實施。史米特觸發器ST可視為係一具有磁滯效應 6 M278957, (Hysteresis)的反相器，用以防卜铛丨 Λ丨方止偵測電壓Vsen上可能存 之雜訊錯誤地造成觸發事件。 g +吧 Μ + ^ 一旦電源電壓vpw達到適當 的電壓而觸發史米特觸發5| A态ST，由重置開始電路u 生的重置開始信號RST係絲^ L 4 # 你施加一上升邊緣至閂鎖電路12 之第一輸入端S。回應於重置開始信號RST之上升邊緣， 閂鎖電路12使電源啟動重置俨啼可運緣 、 切置置4唬P〇R進入低位準狀熊， 便開始進灯重置階段。在圖i所示的實施例中，問鎖電 路12主要係由兩個交叉勉人 耦&的NAND邏輯閘所形成，但 二a電路12亦得由其他種類的邏輯閘所實施，只要其可 執行相同的邏輯運算功能。 …重^凡成電路13主要具有一開關單元、一電虔债测 Ιί传a參考電昼產生單元、以及一電壓比較單元。開關 :厥i個電晶體開關nl至n3所構成，分別用以控制 泣 可冤&產生早π、與電壓偵測單元之電 η1仏二賦此仏#b EN處於低位準時，三個電晶體開關 白不導通’因此無任何電流路徑形成於電源電壓 I:與地面電位間。換言之，藉由開關單元之設置，重置 ♦。路13可由賦能信號ΕΝ控制啟動與否，而僅在賦能 ^ Ν處於呵位準狀態時才進行操作。參考電壓產生單 元得由電p且R 9 & > /、一耦合成二極體的電晶體η4所構成，串 V ;電源電壓VPW與地面電位間，用以產生一參考電壓 因此，參考電壓大約等於一個二極體導通之壓 電晶？開目n2控制參考電壓產生單元之電流路徑。 。β偵測單几侍由電阻Ra與Rb所構成的電阻性分壓器所 7 M278957, 貫施，耦合於電源電壓vpw與地面電位間，用以產生一分 壓[Rb/(Ra+Rb)]*Vpw。電晶體開關n3控制電壓偵測單元之 電流路徑。 電壓比較單元主要具有由電晶體…與"所構成的差 動放大對，其係由電晶體？3與p4所構成之電流鏡所驅 動。電晶體開關ni控制電壓比較單元之電流鏡之電流路 徑。從電壓偵測單元而來的分壓[Rb/(Ra+Rb)]*v”係施加 至電晶體pi之閘極，而從參考電壓產生單元而來的參考 電絵Vref施加至電aa體p2之閘極。因此，電壓比較單元 基於分壓[Rb/dla+RWPV^與參考電壓Vref間之比較而決 疋重置元成k號FNS之狀態。當分壓[Rb/(Ra+Rb)]*Vpw小 於參考電壓Vref時，重置完成信號FNS處於高位準狀態。 一旦分壓[Rb/(Ra+Rb)]*Vpw達到參考電壓Vref，電壓比較 單元即受到觸發而使重置完成信號FNS進入低位準狀 態。重置完成信號FNS係施加至閂鎖電路12之第二輸入 端R。回應於重置完成信號FNS之下降邊緣，電源啟動重 置信號POR轉態成高位準，以便結束重置階段。 因此，藉著設定參考電壓Vref之值，即可精確地決定 重置階段之終止時機，亦即精確地控制重置完成電壓之 值，其係經由[(Ra+Rb)/Rb]*Vref計算而得。換言之，當電 源電壓Vpw上升至預先設定的重置完成電壓時，電源啟動 重置k號POR即受觸發而終止重置階段，以便積體電路晶 片預備好進行正常操作。 圖2顯示依據本新型第一實施例之電源啟動重置電路 M278957 10之操作波形時序圖。參照圖2，假設t 間10起由零逐漸上升、於時間η達到第—電壓V;:從時 時間η達到第二電麼V2、'並且於時間 y二於 且隨後即維持穩定。當電源 ：；：昼 電晶體之臨界電壓的狀況，亦即在大約0.7料Π 賦能信號EN與電源啟動重置信號p〇R因電路中所 雜政電谷而隨著電源電麼Vpw_起增大。再者此期：的 因為各電晶體均尚未導通，故並 ：， ㈣POR進入低位準狀態，因 置 厂"…發史米特觸發器ST。因此，時間電 階段之開始。 丁间1 1代表重置 f卢ElT日卞間η至T2，隨著電源電壓Vpw之增大，賦能芦 & N之向位準狀態亦增大。 繼續維持於地面Λ 胃室置“虎P〇R仍Circuit diagram of. Referring to FIG. I, the power supply is reset to turn on, and the electric bath includes]. The circuit 11, a latch circuit 12, and a circuit 13. The electric start circuit 11 generates a reset start signal RST, which is applied to the latch thunder 1, ‘circuit 12’. The reset completion circuit 13 generates a reset completion signal ™ S and applies it to the flash lock circuit 12. The reset completion circuit 13 is activated based on the enable signal EN fed back from the output terminal of the flash lock circuit 12. In response to the reset start signal RST and the reset completion signal FNS, the latch circuit U determines the state of the power-on reset signal pOR. The power-on reset signal POR is applied to other circuits (not shown) in the integrated circuit chip to perform operations in the reset phase. The reset start circuit 1 丨 mainly includes a voltage detection unit and a trigger unit. The voltage detection unit generates a detection voltage Vsen, which is used to represent the power supply voltage vpw. The voltage detection unit is implemented by a capacitive voltage dividing circuit formed by a resistor R1 and a capacitor C1 connected in series. When the power supply voltage vpw rises from zero, the series coupling point A between the resistor R1 and the capacitor C1 provides a divided voltage that varies with the power supply voltage Vpw as a detection voltage. The triggering unit is implemented by a Schmidt Trigger ST in series with an inverting $. The Schmitt trigger ST can be regarded as an inverter with hysteresis effect 6 M278957, (Hysteresis), in order to prevent possible noise caused by noise on the detection voltage Vsen. . g + bar M + ^ Once the power supply voltage vpw reaches the appropriate voltage, Schmitt triggers 5 | A state ST, the reset start signal RST generated by the reset start circuit u ^ L 4 # You apply a rising edge To the first input terminal S of the latch circuit 12. In response to the rising edge of the reset start signal RST, the latch circuit 12 causes the power supply to initiate a reset, set the power switch to a low level, and start the reset phase of the lamp. In the embodiment shown in FIG. I, the interlock circuit 12 is mainly formed by two NAND logic gates which are coupled to each other, but the second a circuit 12 may also be implemented by other types of logic gates, as long as the Performs the same logical operation functions. ... ^ Fancheng circuit 13 mainly has a switching unit, a reference voltage generation unit, and a voltage comparison unit. Switch: It consists of three transistor switches nl to n3, which are used to control the electric current & generating early π, and the voltage of the voltage detection unit η1. This is assigned when #b EN is at a low level. The crystal switch is not conducting, so no current path is formed between the power supply voltage I: and the ground potential. In other words, reset ♦ by setting the switch unit. The path 13 can be activated or not controlled by the enable signal EN, and is only operated when the enable ^ N is in a level state. The reference voltage generating unit is composed of an electric p and R 9 & > /, a transistor η4 coupled into a diode, a string V; a power supply voltage VPW and a ground potential for generating a reference voltage. Therefore, the reference Is the voltage approximately equal to a piezoelectric crystal with a diode on? Open head n2 controls the current path of the reference voltage generating unit. . The β detection unit is a resistive voltage divider composed of resistors Ra and Rb 7 M278957, which is coupled between the power supply voltage vpw and the ground potential to generate a partial voltage [Rb / (Ra + Rb) ] * Vpw. The transistor switch n3 controls the current path of the voltage detection unit. The voltage comparison unit mainly has a differential amplification pair composed of a transistor ... and " is it a transistor? Driven by a current mirror composed of 3 and p4. The transistor switch ni controls the current path of the current mirror of the voltage comparison unit. The partial voltage [Rb / (Ra + Rb)] * v ”from the voltage detection unit is applied to the gate of the transistor pi, and the reference voltage Vref from the reference voltage generation unit is applied to the electric aa body. The gate of p2. Therefore, the voltage comparison unit determines the state of resetting the element to k number FNS based on the comparison between the divided voltage [Rb / dla + RWPV ^ and the reference voltage Vref. When the divided voltage [Rb / (Ra + Rb )] * Vpw is lower than the reference voltage Vref, the reset completion signal FNS is at a high level. Once the voltage division [Rb / (Ra + Rb)] * Vpw reaches the reference voltage Vref, the voltage comparison unit is triggered and the reset is completed. The signal FNS enters a low level state. The reset completion signal FNS is applied to the second input terminal R of the latch circuit 12. In response to the falling edge of the reset completion signal FNS, the power-on reset signal POR transitions to a high level so that End the reset phase. Therefore, by setting the value of the reference voltage Vref, the termination timing of the reset phase can be accurately determined, that is, the value of the reset completion voltage is precisely controlled, which is determined by [(Ra + Rb) / Rb] * Vref. In other words, when the power supply voltage Vpw rises to a preset reset completion voltage The power-on reset K-number POR is triggered to terminate the reset phase, so that the integrated circuit chip is ready for normal operation. Figure 2 shows the operation waveform timing of the power-on reset circuit M278957 10 according to the first embodiment of the new model. Assume that referring to FIG. 2, it is assumed that from 10 to t, the voltage gradually rises from zero and reaches the first voltage V at time η; When the power supply:;: the critical voltage condition of the daylight crystal, that is, at about 0.7, the energization signal EN and the power-on reset signal p0R vary with the power supply voltage Vpw_ In this period: because the transistors have not been turned on yet, they are not: ㈣POR enters a low level state, because the factory " ... smits the Schmitt trigger ST. Therefore, the time of the electric phase begins. Ding Jian 1 1 means resetting the 卢 ElT sundial η to T2. With the increase of the power supply voltage Vpw, the state of the energizing reed & N also increases. Continue to be maintained on the ground Tiger P〇R still
開中’因為重置完成電路13 而^:二亦即前述各單元之電流路徑因賦能信號EN ”，電二…源電流1PW開始顯著地消耗。在時間 置2 =動重置信號p〇R轉態成高位準狀態而結束重 旬而又觸發重署壓VpW達到第二電壓V2(重置完成電 作妒ΕΝ;Π /成電路13之電壓比較單元。此外，賦能"Open in the middle" because of the reset completion circuit 13: Second, that is, the current paths of the aforementioned units are due to the enable signal EN ", and the second ... the source current 1PW starts to be consumed significantly. Set 2 at time = the reset signal p. R transitions to a high level state and ends the re-decade and triggers the re-deployment voltage VpW to reach the second voltage V2 (the reset is completed, and the voltage is compared to the voltage comparison unit of the circuit 13).
同時轉態成低位準狀態而中斷重置完成電W 厅有電 >>丨L路抱。（51 Α η士 消耗降低至零，並且電、：η以後’電源電流1PW 2 、-起上升至穩定值…重置信號P0R隨著電源電壓 M278957 圖3顯不依據本新型第二實施例之電源啟動重置電路 30之"羊細電路圖。圖3所示之電路元件中相同於圖1所示 之電路元件者係以相同的參考編號加以標示，且為簡化說 月I見下文省略其說明。第二實施例不同於第一實施例 之處在於圖3所示的第二實施例更包含一延遲電路14,用 以在閂鎖電路12受到重置開始信號RST觸發後，仍須經At the same time, the state is changed to a low level state and the reset is interrupted. There is electricity in the hall. ≫ (51 Α η The consumption is reduced to zero, and the power supply current 1PW 2 and-after the η rise to a stable value ... The reset signal P0R follows the power supply voltage M278957. Figure 3 shows that according to the second embodiment of the new model, &Quot; Sheep thin circuit diagram of the power-on reset circuit 30. Among the circuit elements shown in Fig. 3, those which are the same as those shown in Fig. 1 are marked with the same reference numbers, and for simplicity, I will omit them below The second embodiment differs from the first embodiment in that the second embodiment shown in FIG. 3 further includes a delay circuit 14 for triggering the latch circuit 12 after being reset by the reset start signal RST.
過一段延遲時間Tdly之後才賦能重置完成電路13以進行 操作，藉而更加節省電源電& w之消耗。具體而言，延 遲電路14主要具有一延遲電壓產生單元以及一邏輯控制 早凡。延遲電壓產生單元係由電晶體p5與電容C2串聯於 電源電壓Vpw與地面電位間而形成，用以產生一延遲電壓The reset completion circuit 13 is enabled to operate only after a delay time Tdly, thereby further saving power consumption & w. Specifically, the delay circuit 14 mainly has a delay voltage generating unit and a logic control element. The delay voltage generating unit is formed by a transistor p5 and a capacitor C2 connected in series between the power supply voltage Vpw and the ground potential to generate a delay voltage.
vdly。在電源電壓Vpw上升而導通電晶體p5之後，電容 C2被充電而使跨在其上的延遲電壓v叫逐漸增大。邏輯 控制單元主要係由NAND邏輯電路所組成，用以接收從閂 鎖電路12而來的回授信號FB與延遲電壓v…。在延遲電 路14之控制下，雖然回授信號FB在史米特觸發器§丁觸 發後即已立即轉態成高位準，但第二實施例之賦能信號 EN’仍舊被抑制於地面電位。必須等到延 % 土 v dly上升 至足夠使邏輯控制單元之NAND邏輯閘視之為高位準作 號時，第二實施例之賦能信號EN，才會轉態成高位準。請 注意延遲電路14亦得由其他類型的類比計時器或數位， 數器所實施，只要能提供並控制所期望的延遲時間即 可。 y 圖 4顯示依據本新型第二實施例之電源啟動重置電路 10 M278957 3〇 t操作波形時序圖。參照圖4,第二實 FB實質上係相同於第一二”二……信號 tb . Ba 、弟 Λ施例之賦能信號ΕΝ，因為兩者 皆為問鎖電路12之輸 巧句者 間、内，雖然電源== 之延遲時 付⑽仏 動重置信號P0R已經轉態至地面電 進行重置階段，但第二實施例之賦能 :vdly. After the power supply voltage Vpw rises and the crystal p5 is turned on, the capacitor C2 is charged and the delay voltage v across it is gradually increased. The logic control unit is mainly composed of a NAND logic circuit for receiving the feedback signal FB and the delay voltage v ... from the latch circuit 12. Under the control of the delay circuit 14, although the feedback signal FB immediately transitions to a high level after the Schmitt trigger § D is triggered, the enabling signal EN 'of the second embodiment is still suppressed to the ground potential. It is necessary to wait until the delay% soil v dly rises enough to make the NAND logic gate of the logic control unit be regarded as the high-level signal, and then the enable signal EN of the second embodiment will transition to the high level. Please note that the delay circuit 14 may also be implemented by other types of analog timers or digits, as long as it can provide and control the desired delay time. y FIG. 4 shows a timing diagram of the operation power-on reset circuit 10 M278957 30 t according to the second embodiment of the present invention. Referring to FIG. 4, the second real FB is substantially the same as the first two “two… signals tb. Ba and the enable signal EN of the embodiment Λ, because both of them are between the losers of the interlock circuit 12. Inside, although the automatic reset signal P0R has been switched to the ground power for the reset phase when the power supply == is delayed, the enabling of the second embodiment is:
ΓΓ::ν而抑制電源電…消耗。只有二 而使ϋ成施狀Μ信號ΕΝ，才轉11成高位準 至Τ① 3開始進行操作。因此，僅在時間Τεν 曰1，電源電流1PW才顯著地消耗。 明，：ί本新型.業已藉由較佳實施例作為例示加以說 地Γ、解者為：本新型不限於此被揭露的實施例。相反 的各錄7意欲涵蓋對於熟習此項技藝之人士而言係明顯 據it改與相似配置。因此，中請㈣範圍之範圍應根 貝的.全釋，以包容所有此類修改與相似配置。 【圖式簡單說明】 圖1顯示依據本新型第一實施例之電源啟動重置電路 之詳細電路圖。 圖2顯示依據本新型第一實施例之電源啟動重置電路 之操作波形時序圖。 圖3顯示依據本新型第二實施例之電源啟動重置電路 之詳細電路圖。 圖4顯示依據本新型第二實施例之電源啟動重置電路 之操作波形時序圖。 11 M278957、ΓΓ :: ν suppresses power consumption ... Only when the signal M is turned into a signal M2, it turns 11 to a high level and starts to operate at T①3. Therefore, the power supply current 1PW is consumed significantly only at the time Tεν = 1. It is clear that: This new model has been described by taking the preferred embodiment as an example. The solution is that the new model is not limited to the disclosed embodiment. The opposite record 7 is intended to cover those who are familiar with this skill. Therefore, the scope of China ’s request should be fully explained to accommodate all such modifications and similar configurations. [Brief description of the drawings] FIG. 1 shows a detailed circuit diagram of a power-on reset circuit according to the first embodiment of the present invention. FIG. 2 shows a timing chart of operation waveforms of the power-on reset circuit according to the first embodiment of the present invention. FIG. 3 shows a detailed circuit diagram of a power-on reset circuit according to a second embodiment of the present invention. FIG. 4 shows a timing chart of operation waveforms of the power-on reset circuit according to the second embodiment of the present invention. 11 M278957,
【主要元件符號說明】 10, 30 電源啟動重置 11 重置開始電路 12 閂鎖電路 13 重置完成電路 14 延遲電路 Cl，C2 電容 Rl，R2, Ra，Rb 電阻 nl〜n4，pl〜p5 電晶 RST 重置開始信號 FNS 重置完成信號 POR 電源啟動重置信 EN，EN’ 賦能信號 FB 回授信號 V v pw 電源電壓 V s en 偵測電壓 Vref 參考電壓 Vdly 延遲電壓 I p w 電源電流 電路 體 號 12[Description of main component symbols] 10, 30 Power-on reset 11 Reset start circuit 12 Latch circuit 13 Reset completion circuit 14 Delay circuit Cl, C2 Capacitors Rl, R2, Ra, Rb Resistors nl ~ n4, pl ~ p5 Crystal RST reset start signal FNS reset completion signal POR power start reset signal EN, EN 'enable signal FB feedback signal V v pw power supply voltage V s en detection voltage Vref reference voltage Vdly delay voltage I pw power supply current circuit Body number 12