TWM276199U - Peak voltage detector with leakage current compensation - Google Patents

Description

M276199 8. Description of the new type: [Technical field to which the new type belongs] This creation relates to a voltage peak detector, especially using a differential amplifier, a charging transistor, and a capacitor. Complementary qjos electronic circuits with leakage current compensation to obtain accurate voltage peaks. [Prior technology] A voltage peak detector is an electronic circuit that can measure the maximum value of a voltage waveform. In other words, the input of the circuit is a changing voltage signal, and its output is the maximum of the input voltage waveform. value. In many applications, the peak value of the input voltage signal must be measured and then retained as a direct current type φ for subsequent analysis and use. The peak value of a burst is often more useful than its average value. For example, when performing a destructive test, it is necessary to track down and maintain the peak signal, and measure the amount of voltage signal degradation on the transmission medium, analog to digital Converters (A / d, Maximum likelihood decoding system) and pulse signal detection circuits used to detect nuclear radiation also need voltage peak detectors. Prior art, voltage peak detection The simplest method of the detector is to let the input voltage signal pass through the diode and charge the capacitor in order to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V (IN) is greater than the voltage of the capacitor C The diode D is turned on, and then performs the charging function until the input voltage V (IN) reaches its maximum value, and the capacitor c cannot continue to be charged. At this time, the output voltage V (〇UT) represents the input voltage V (IN). Peak. Due to the existence of diode D between the output and input, this circuit cannot accurately detect the true peak value of the input voltage V (IN). In other words, the output voltage ν (〇ϋτ) and the input voltage V ( There is always an error between the peaks of IN) = polar body on voltage vd. That is, MAX (V (OUT)) = MAX (V (IN))-Vd, as shown in the second picture (this picture is OrCAD PSpice The results of transient analysis simulation). Β For many applications, the above-mentioned error of the diode on-voltage vd is undesired, and the voltage difference will be different due to the use of different diodes, which may cause Undesirable effects or unpredictable consequences. One in order to be able to accurately detect the peak voltage of the input, another commonly used prior art system uses one amplifier, 0P1 and 0P2, two diodes D1, and two resistors. And R1, and an electrical device C to form a voltage peak detector, as shown in the third figure, the transient simulation result of OrCAD PSpice M276199 is shown in the fourth figure. Among them, 0P1 is a An accurate half-wave rectifier. When the input voltage V (IN) is greater than the capacitor voltage V (C), the diode D1 will transmit the bias voltage to the capacitor C1. Finally, the capacitor voltage V (C) will be equal to the input voltage V ( The peak voltage of IN) is quite close, and the detected output voltage V (OUT) will also be The peak voltage of the input voltage V (IN) is quite close, and there will no longer be an error in the diode conduction voltage Vd between the output terminal and the input terminal as shown in the second figure. When the input voltage V (IN) is less than the capacitance When the voltage is V (C), the diode D2 will be turned on, and the diode will be cut off and the capacitor C will no longer be charged. This makes the detected output voltage ν (ουτ) equal to the input voltage V (IN) peak voltage. Although the voltage peak detector in the third figure can accurately detect the peak voltage, its circuit structure is complex and the occupied chip area is large, which is not conducive to the requirements of integrated circuits. To date, many voltage peak detector technologies have been proposed, such as those disclosed in U.S. Patent Nos. US5304939, 5502746, 5560027, 5969545, 6051998, 6064238, and 6468261 and the Republic of China Patent No. 8822G146 Other technologies can accurately detect the peak voltage of the input signal, but because these voltage peak detectors use more than one operational amplifier, there are defects such as a complicated circuit structure and a large chip area. Recently, several technologies that do not require the use of precision voltage peak detectors for operational amplifiers have been proposed. "For example, as disclosed in China Lai Zhuan No. 9Q119722 and the proposal, these technologies are: differential amplification || and _The circuit-spinned operational amplifier composed of a current mirror does not use the operational amplifier H, so it has multiple functions such as a fresh circuit structure, a small area, and a favorable miniaturization. However, because the differential amplifiers used in these technologies have two symmetrical load transistors and use a current mirror, there is still room for improvement in reducing the number of transistors required for the voltage peak detector. in. In addition, 'these technologies do not take into account the effect of leakage current. Before the voltage peak detector completes the detection of the input voltage peak to the output voltage (v⑽τ), it is strange that there is a gate difference and therefore there is a leakage current. Yes, but the above-mentioned technology does not take into account this leakage current effect. In view of this, the main purpose of this creation is to propose a novel voltage spike detector that not only can accurately detect the peak of the rugged signal, but also has a simple circuit structure, a small chip, and is conducive to Multiple functions such as miniaturization of the device, taking into account the effect of leakage current. [New content] The voltage peak detector proposed in this creation is composed of a differential amplifier i, a charging transistor 2, with M276199 and -capacitance ϋ c, where the differential amplifier n is asymmetric The structure is designed, that is, only one side of the load transistor is used, and the load transistor and the charge transistor together form a current mirror, so it can be compared with the traditional precision voltage peak detector (the 9th The voltage peak detectors disclosed in patents Nos. 119722 and 90131188) have two pM0s transistors. In addition, the voltage peak detector proposed in this paper can also effectively compensate the leakage current. [Embodiment] 〃 According to the above purpose, the present invention proposes a novel voltage peak detector, as shown in the fifth figure, which is composed of a differential amplifier, a charging transistor 2, and a capacitor c. The differential amplifier 1 is designed using an asymmetrical circuit configuration, which is composed of a surface transistor transistor leg, MN2 and brain, and a four-cell β-body MF1. Among them, the NMOS transistor The cis1 and MN2 series are used as drivers, the pMOS transistor MP1 is used as a transistor load, and the leg MOS transistor 3 is used to provide a reference current for the differential amplifier. The gates of the cis transistor MN1 and MN2 respectively receive the input voltage signal ν ^) and the output voltage feedback signal V⑽T) of the detector. The sources are connected together and connected to cis ^ 3 The NMOS transistor MN3 is connected to a control bias voltage Vc, and the source is connected to ground. The drain of the NMOS transistor MN3 is connected to the drain of the PMMOS transistor MP1 and the power supply voltage Vdd. ; The source of the pM0s transistor Mpl is connected to the power supply voltage Vdd, and the gate and the drain are connected together and connected to the gate of the charging transistor MP2. Please refer to the fifth figure again. The charging transistor system is composed of a PMMOS transistor Mp2. The source of the PMMOS transistor MP2 is connected to the power supply voltage Vdd, the gate and the gate of the PMOS transistor MP1, and nm MOS transistor • The drain of body 1 is connected, while the non-pole is connected to the capacitor C and the gate of NMOS transistor MN2. For the convenience of explanation, the following derivation process describes the metal-oxide-semiconductor transistor as the simplest model (that is, the level 1 model) in the pspice, and does not consider the channel length modulation (annel length modulation) effect. However, in the subsequent simulation verification, all transistor parameters (including channel length modulation effects) in rCAD pspice were considered. According to the circuit shown in the fifth figure, when the input voltage signal V (IN) is greater than the output voltage signal ν (〇υτ), the current Id (MN1) will be greater than Id (MN2), and

Id (MN1) + Id (MN2) = Id (MN3) ⑴ again

Id (MN1) = -Id (MP1) ⑵ Because the PMOS transistors MP1 and MP2 form a current mirror, so M276199 ⑶ -Id (MP1) = -Id (MP2), so the capacitor C can be charged. When the charging operation reaches the peak voltage of V (OUT) equal to the input voltage signal v (in), the current Id (MN1) = Id (MN2) = γ id (MN3) ⑷ At this time, the capacitor C will still be charged. However, according to the transfer characteristic curve of the differential amplifier, the output voltage signal ν (〇υτ) must be higher than the input peak voltage U by an excess voltage (0verSh〇〇tv〇ltage referred to as v〇s) in order to convert the 臓 transistor. ugly

Forced to a cut-off state. When _S «MN1 stops miscellaneous, the charging transistor stops charging capacitor C. At this time, the output voltage signal 0101] 1 ^ is V (OUT) = Vpeak + V〇S (5 ). Since the tritium transistor MN2 works in the saturation region, and the NMOS transistor MN1 enters the cut-off region from the saturation region, VGS2 & VGS1 can be obtained from the following current equation:

Id (MN2) = Id (MN3) (β)

Id (MN1) = 〇 ⑺ so the excess voltage Vos is equal to

Vos = VGS2-VGS1 ⑻ After 'when the input voltage signal V (IN) drops from the peak voltage, the current-Id (MP1) = -Id (MP2) = 〇 because the parasitic transistor leg has entered the cut-off state. ⑼ Therefore, the charging salt does not charge the capacitor HG, so the input voltage signal ν (〇υτ) will still be fixed at the voltage of equation (5). It is known from equation (5) that the value of the output electric signal ν⑽τ) is higher than the input peak voltage U by an excess voltage Vos. The excess voltage VGS _ is shown in the equation. If all the surface transistors have the same The zero bias threshold voltage yTO (ZeiO-bias threshGld voltage) and the transconductance parameter KP ^ Transconductance parameter), the zero bias threshold voltage ~ and the transconductance parameter κρ are one of the model parameters of the metal-oxide semiconductor, Equation (8) can be rewritten as V〇s = [2 · Id (MN3) · 1 / KP · 1 / (W / L) mn2] 1/2 (1〇) where (W / Dm means NMOS transistor MN2 Effective channel width-to-length ratio. For the extrapolation of excess voltage v0s, refer to Kenneth K · Lake and Willy MG · Sansen, co-authored by McGRAW-Hill, Design of analog integrated circuits and systems, No. 357 M276199 Go to page 375. Please refer to the fifth figure again. When the _s transistor operates in the saturation region, the equation can be further rewritten as V0S = [(W / L) mn3 / (W / L) mn2] 1/2 · (Vc-Vto) (11) where '(W / L) «represents the effective channel width-to-length ratio of the NM0S transistor brain, and 1Vc represents the control bias (ie, NM0S transistor M The gate-source voltage of N3) is based on the channel width-to-length ratio of the transistor MN2 (w / l). Mn 2 is equal to 10, and the channel width-to-length ratio of the NM0S transistor is equal to 1). Limit voltage

Vto is equal to G · 5 volts, and the control bias Ve is equal to Q. 6 volts. For example, the excess voltage is equal to still volts. ·. The value of the over-voltage Vos is one of the inherent errors of the voltage peak detector, but this inherent error can just be used to compensate the output of the voltage peak detector due to capacitor leakage current and due to external circuit operation. When the voltage drop caused by the voltage peak detector detects the input peak voltage K and the waiting time before the input peak voltage is taken too long, the leakage current effect of the capacitor cannot be ignored. Fortunately, the output of the electrical peak detector due to capacitor leakage current and voltage drop caused by external circuit capture can be properly compensated for the voltage drop by setting the control bias Vc appropriately. The control bias Vc can be easily obtained by rewriting equation (U), that is,

Vc = Vto + [(W / L) MN 2 / (W / L) mn 3] 1/2. Vos (12) Therefore, if the output of the voltage peak detector is known due to capacitor leakage current and external circuit If the generated voltage drop is captured, the voltage drop can be set equal to the excess voltage vos, and the value of the control bias Vc required to avoid the drop in the effective mine can be estimated _ through the calculation of equation ⑽. . 9 1 The OrCAD PSpice transient analysis simulation result of the voltage peak detector proposed in this creation, as shown in the figure, the simulation results can confirm that the voltage peak detector proposed in this creation can be accurate and effective Ground to detect the peak voltage of the input voltage waveform. The sixth figure is simulated with a level 3 model and using 0.35 micron CMOS process parameters (the zero bias threshold voltage Vt of its PM_ crystal and surface transistor. -0.5V and 0.5V, respectively), and The power supply voltage Vdd is equal to 5.0 volts, and the control bias voltage Vc is equal to 0.6 volts. The channel width-to-length ratio of the PM0S power ΘΘMP1 and MP2 are both (210.35 / 0.35μm), and the channel width of the fiMOS transistor MN1 The aspect ratio is (〇 · 35μιη / 0 · 35μιη), and the channel width-length ratio of the NM0S transistor MN2 is (1010 ^ ». Βδμιη) ^ \

The capacitance of the capacitor is 1PF. It can be seen from the results in the sixth figure that when the control bias voltage Vc is equal to 0.6 volts, the output voltage signal ν (ουτ) is strangely higher than the input peak voltage Vpeak by 0 015 volts. Lake · 015 Volts The excess voltage Vos is the inherent error of the voltage peak detector. This inherent error can be used to compensate for the voltage peak U M276199 output terminal due to leakage current and external power Voltage drop. From the above analysis, it can be seen that the voltage peak detector proposed in this paper can be accurately and effectively given the leakage current of the voltage peak detector and the voltage drop caused by the external circuit capture. Detect the peak voltage of the input voltage waveform. The voltage peak detector of this creation can be connected in parallel with a switch at both ends of the capacitor c when in use. This = relationship is used to provide a -discharge path to discharge the charge stored on the capacitor, which is beneficial to the next input voltage signal. Peak detection. [Creation effect] The voltage peak detector proposed in this creation has the following effects: (1) = Precision · Since this creation can set the control bias voltage Vc appropriately, the corresponding super-voltage Vos can be used to Cancel the capacitor leakage current and the voltage drop error caused by the external circuit capture, so that the external circuit can accurately capture the peak voltage of the input voltage waveform; ⑵ Conducive to the miniaturization of the device: due to the voltage peak proposed in this creation The detector only uses paste transistors, 3 · 0S transistors, and 1 capacitor, so it is not only a novel and simple circuit architecture, the number of transistors used is small, and it does not require an operational amplifier, which is also beneficial. Miniaturization of the device. Although this work outlines and describes the preferred embodiment selected, those skilled in the art will appreciate that any form or detail of possible changes may be made without departing from the spirit and scope of the work. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation. M276199 [Schematic description] The first picture shows the circuit diagram of the voltage peak detector in the first prior art; the second picture shows the transient analysis of the input voltage signal and the output voltage signal of the voltage peak detector in the first picture Timing diagram, the third diagram shows the circuit diagram of the voltage peak detector in the second prior art; the fourth diagram shows the timing diagram of the transient analysis of the input voltage signal and the output voltage signal of the voltage peak detector of the third diagram; The fifth figure is a circuit diagram showing a voltage peak detector of the preferred embodiment of the present invention; the sixth figure is a timing diagram showing the transient analysis of the input voltage signal and the output voltage signal of the present voltage peak detector. [Description of Symbols] 1 Differential amplifier 2 Charging transistor V (IN) Input voltage signal V (OUT) Output voltage signal Vc Control bias voltage Vdd Power supply voltage C Capacitor D Diode D1 Diode D2 Diode 0P1 Operational amplifier 0P2 Operational amplifier MP1 First PMOS transistor MP2 Second PM0S transistor Li 1 First NMOS transistor MM3 Third NMOS transistor MN2 Second NMOS transistor

Claims (1)

M276199 9. Scope of patent application: 1. A voltage peak detector with leakage current compensation for detecting the peak value of the input voltage signal, which includes: ', an input terminal' for providing an input voltage signal; an output terminal 'To output the peak voltage of the input voltage signal; a power supply voltage to provide the power supply voltage and reference ground required by the voltage peak detector; a differential amplifier (1) with a unilateral load transistor for Accepts and compares the input voltage signal and the voltage signal on the capacitor, and provides the charging current signal to the charging transistor; a 1 transistor (2) is used to flow through the unilateral load transistor of the differential amplifier (1) The current amount 'to provide a capacitor with the same amount of charging current as the current amount; and a capacitor (C), one end of which is connected to the charging transistor (2) so as to accept the supply of the charging transistor (2) Charging current, and the other end is connected to the reference ground; where the differential amplifier (1) with a single-sided load transistor includes: a single-sided load transistor, which consists of A PMOS transistor (MP1), the source of the first pjjos transistor (MP1) is connected to the power supply voltage, the gate and drain are connected together, and the gate of the charging transistor (2) is connected; The source of the first NMOS transistor (MN1) is connected to the source of the second nmos transistor (MN2) and the drain of the third NMOS transistor (MN3). The gate is used to receive the input voltage signal and the sink The pole is connected to the gate of the charging transistor (2) and the pole of the first pMOS transistor (MP1); the source of the first NMOS transistor (MN2) is connected to the first NMOS transistor. The source of the crystal (MN1) and the drain of the third MOS transistor (MN3) are connected, the gate is used to receive the voltage signal on the capacitor, and the drain is connected to the power supply voltage; and a second NMOS transistor (MN3), whose source is connected to the reference ground, the gate is connected to the control bias (Vc), and the drain is connected to the sources of the first and second NMOS transistors (legs) and ⑽2); the charging The transistor is composed of a second PMOS transistor (MP2). The source of the second PMOS transistor (MP2) is connected to the power supply voltage, and the gate is connected to the first PMOS transistor. (MPl) and the gate of transistor _M〇s (dirty) is connected to the drain, the gate and drain of the one end of the capacitor and a second transistor _§ (Li 2) is connected to the electrode. 2. The voltage peak detector as described in item 1 of the patent application scope, further comprising: 12 M276199 A switch, the open relationship is connected in parallel with the capacitor to provide a discharge path for storing the The discharge of electric charge is conducive to the peak detection of the next input voltage signal. 3. The voltage peak detector according to item 2 of the scope of patent application, wherein the open relationship is composed of a metal-oxide semi-electric crystal. ⑤ 13