TWM253771U - Low noise probe head - Google Patents

Low noise probe head Download PDF

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Publication number
TWM253771U
TWM253771U TW93203726U TW93203726U TWM253771U TW M253771 U TWM253771 U TW M253771U TW 93203726 U TW93203726 U TW 93203726U TW 93203726 U TW93203726 U TW 93203726U TW M253771 U TWM253771 U TW M253771U
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TW
Taiwan
Prior art keywords
substrate
low
patent application
detection head
noise detection
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TW93203726U
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Chinese (zh)
Inventor
John Liu
Yeong-Her Wang
Yau-Rung Li
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW93203726U priority Critical patent/TWM253771U/en
Publication of TWM253771U publication Critical patent/TWM253771U/en

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Description

M253771 創作說明(1) 新型所屬之技術領域 之探測 本創作係有關於一種探測卡〔p r 〇 b e c a r d〕 頭’特別係有關於一種低雜訊探測頭。 【先則技術】 ^ 信號在傳輸過程,多少都會受到一些不需要的額外能 里的干擾’此額外能量即是所謂的雜訊〔n〇丨se〕,雜訊 的f擾,通常都會造成信號的失真,其來源除了來自系統 卜、亦有可此由接收糸統本身產生。為了消除在積體電 f測《式過程中之雜訊,習知地係在該探測頭之外部額外裝 口又有複數個旁路電容器〔by-pass capacit〇r〕,然而 容易影響探針位置與高度之配置,並且每一旁路電容器 個別地以表面接合〔SMT〕或銲接技術接合於該探測頭,” 且該探測頭需要特別設計出用以連接該些旁路 路,製造成本較高。 令益〈綠M253771 Creation Instructions (1) Probing in the New Technical Field This creation relates to a probe card [p r 〇 b e c a r d] head 'especially to a low-noise probe head. [Prior art] ^ During the transmission of a signal, it will be affected by some unwanted extra energy. This extra energy is the so-called noise [n〇 丨 se], which usually causes signal interference. In addition to the source of the distortion, it can also be generated by the receiving system itself. In order to eliminate the noise in the process of integrated electric measurement, conventionally, there are a plurality of bypass capacitors [by-pass capacit〇r] on the external installation of the probe, but it is easy to affect the probe Position and height configuration, and each bypass capacitor is individually joined to the probe head by surface bonding [SMT] or welding technology, "and the probe head needs to be specially designed to connect the bypass paths, and the manufacturing cost is higher . Ling Yi <Green

I 美國專利第5, 373, 231號係揭示有一種具有外建式 路電容之探測裝置,該探測裝置係包含有一同軸探 〔coaxiai probe〕、一線路探針〔wire pr〇be〕以及嗖 在該同轴探針與該線路探針之間的電容器 〔capacitor〕,該同軸探針與該線路探 一探測卡〔印刷電路板〕,今雷办毋/ _ 且接裝,又於 同軸探針與該線路探針,以械式軟性連接該 針〔cantueve…be〕裝並/僅適用於懸臂式探 裝A ’不適用高密度探測I U.S. Patent No. 5,373,231 discloses a detection device with an external road capacitance. The detection device includes a coaxial probe (coaxiai probe), a line probe (wire prObe), and The capacitor [capacitor] between the coaxial probe and the line probe, and the coaxial probe and the line probe a probe card [printed circuit board]. It can be mechanically connected to the line probe with the needle [cantueve ... be] installed and / only for cantilever type A 'not suitable for high-density detection

M253771 四、創作說明(2) 之平面式探測頭。 【新型内容】 本創作之主要目的係在於提供一種低雜訊探測頭,利 ,至少一容置腔形成於一第一基板,該容置腔内係設有至 少一旁路電容〔by-pass capacitor〕,以減少測試信號 在傳輸過程中被雜訊干擾的程度。 本創作之次一目的係在於提供一種低雜訊探測頭,利 用一第二接地層形成於一第二基板之上表面與下表面之 間’分隔一電源層與複數個探觸端之間,以形成屏蔽效應 〔shielding effectiveness〕,達到降低雜訊之功效。 依本創作之低雜訊探測頭,其係包含一第一基板、一 第一基板、至少一旁路電容〔by-pass capacitor〕及複 數個探觸端’該第一基板係具有一上表面及一下表面,該 第一基板係形成有一第一接地層及至少一容置腔,該第一 接地層係形成於該第一基板之該上表面,該容置腔係形成 於該第一基板之該上表面及該下表面之間,該第二基板係 設於該第一基板之該下表面,該第二基板係具有一上表面 及一下表面,該第二基板係形成有一電源層及一第二接地 層,該電源層係形成於該二基板之該上表面與該第一基板 之該下表面之間’該第二接地層係形成於該二基板之該上 表面與該下表面之間,該旁路電容係設於該容置腔内,該 旁路電容係電性連接該第一基板之該第一接地層與該第二 基板之電源層’當測試信號在傳輸過程中,有不正常之電 流產生時’該不正常之電流可經由該旁路電容導接至該第M253771 Fourth, the flat-type probe of the creation description (2). [New content] The main purpose of this creation is to provide a low-noise detection head. At least one accommodating cavity is formed on a first substrate. The accommodating cavity is provided with at least a bypass capacitor. ] In order to reduce the extent to which the test signal is disturbed by noise during transmission. A second objective of this creation is to provide a low-noise probe head that uses a second ground layer formed between the upper surface and the lower surface of a second substrate to 'separate a power layer from a plurality of probe terminals. In order to form shielding effectiveness [shielding effectiveness], to achieve the effect of reducing noise. The low-noise detection head according to the present invention includes a first substrate, a first substrate, at least a by-pass capacitor, and a plurality of probe terminals. The first substrate has an upper surface and On the lower surface, the first substrate is formed with a first ground layer and at least one receiving cavity. The first ground layer is formed on the upper surface of the first substrate. The receiving cavity is formed on the first substrate. Between the upper surface and the lower surface, the second substrate is disposed on the lower surface of the first substrate, the second substrate has an upper surface and a lower surface, and the second substrate is formed with a power source layer and a A second ground layer is formed between the upper surface of the two substrates and the lower surface of the first substrate. The second ground layer is formed between the upper surface and the lower surface of the two substrates. In the meantime, the bypass capacitor is disposed in the accommodating cavity, and the bypass capacitor is electrically connected to the first ground layer of the first substrate and the power layer of the second substrate when the test signal is being transmitted, When abnormal current is generated, it should be abnormal Current may be connected to the second capacitor via the bypass guide

第7頁 M253771 四、創作說明(3) &quot; -- 一基板之該第—接地層,以減少測試信號被雜訊干Λ的程 度,該些探觸端係設於該第二基板之該下表面,用以探觸 待測積體電路。 【實施方式】 參閱所附圖式,本創作將列舉以下之實施例說明。 依本創作之第一具體實施例,請參閱第1圖,一種低 雜訊探測頭1 00係主要包含有一第一基板11 0、一第二基板 120、至少一旁路電容13〇〔by-pass capacit〇r〕及複數 個探觸端140,該第一基板11()係為一矽基板、玻璃基板或 陶究基板,其係具有一上表面丨u及一下表面丨丨2,該第一 〇 基板110係形成有一第一接地層113、至少一容置腔114及 複數個定位槽孔11 5,該第一接地層丨丨3係為一金屬箔層, 其係形成於該第一基板1 1 〇之上表面丨丨1 ,該第一接地層 11 3係在該旁路電容1 3 〇裝設於該容置腔丨丨4内後所形成, 该谷置腔11 4係以雷射鑽孔或利用精密铸造形成該第一基 板11 0時即直接形成,該容置腔丨丨4係形成於該第一基板 110之上表面111與下表面112之間,在本實施例中,該容 置腔内114係設有一銲料層11 6,該些定位槽孔11 5係形成 於該第一基板11 0之周邊,以供調整機構〔圖未繪出〕微 調整該探測頭1 0 0之位置,該第二基板1 2〇係設於該第一基❶ 板110之下表面112,該第二基板120係為一石夕基板、玻璃 基板或陶瓷基板,以與該第一基板11 〇之材質相同為佳, 該第二基板1 20係具有一上表面1 21及一下表面122,該第 二基板1 2 0係形成有一電源層1 2 3、一第二接地廣1 2 4、複Page 7 M253771 IV. Creative Instructions (3) &quot;-The first-ground plane of a substrate, to reduce the extent to which the test signal is disturbed by noise. The probe terminals are provided on the second substrate. The lower surface is used to probe the circuit of the product under test. [Embodiment] With reference to the attached drawings, the present invention will enumerate the following embodiment descriptions. According to the first specific embodiment of this creation, please refer to FIG. 1. A low noise detection head 100 series mainly includes a first substrate 110, a second substrate 120, and at least one bypass capacitor 13〇 [by-pass capacit〇r] and a plurality of probe terminals 140, the first substrate 11 () is a silicon substrate, a glass substrate or a ceramic substrate, which has an upper surface 丨 u and a lower surface 丨 丨 2, the first substrate 〇Substrate 110 is formed with a first ground layer 113, at least one receiving cavity 114, and a plurality of positioning slots 115. The first ground layer 丨 3 is a metal foil layer, which is formed on the first substrate. 1 1 〇 upper surface 丨 丨 1, the first ground layer 11 3 is formed after the bypass capacitor 1300 is installed in the accommodating cavity 丨 丨 4, the valley locating cavity 134 is a mine The first substrate 110 is formed by drilling or precision casting. The accommodating cavity 4 is formed between the upper surface 111 and the lower surface 112 of the first substrate 110. In this embodiment, In the accommodating cavity 114, a solder layer 116 is provided, and the positioning slots 115 are formed around the first substrate 110. An adjustment mechanism (not shown in the figure) finely adjusts the position of the probe head 100, the second substrate 120 is disposed on the lower surface 112 of the first base plate 110, and the second substrate 120 is a stone eve The substrate, the glass substrate or the ceramic substrate is preferably the same material as the first substrate 110. The second substrate 120 has an upper surface 121 and a lower surface 122, and the second substrate 120 has a surface Power layer 1 2 3, a second ground 1 2 4, complex

第8頁 M253771 四、創作說明(4) 數個重分配跡線125及複數個導通孔126,該電源層123與 §亥第一接地層1 2 4之材質均係為金屬層,該電源層12 3係 形成於該第二基板120之上表面121與該第一基板11〇之下 表面112之間,該第二接地層124係以積層〔multi-layer〕技術内埋於該第二基板1 20,而形成於該第二基板 120之上表面121與下表面122之間,該些重分配跡線125係 設於該第二基板120之下表面122,該些導通孔1 26係貫穿 該第二基板120之上表面121與下表面122,並連接該些重 分配跡線125,該旁路電容1 30係設於該第一基板11 〇之容 置腔11 4内,並經由一迴銲〔ref low〕過程與該銲料層11 6 結合,而固設於該容置腔11 4内,該旁路電容1 30係電性連 接該第一基板110之第一接地層113與該第二基板12〇之電 源層123,該些探觸端140係設於該第二基板120之下表面 I 2 2,並與該些重分配跡線1 2 5電性連接,用以探觸待測積 體電路〔圖未繪出〕,較佳地,該探測頭1 〇 〇另包含有一 第三基板150,該第三基板150係設於該第一基板11〇之上 表面111 ’該第三基板150係形成有一凹槽151,用以裝設 一介面板200,傳輸測試信號,該介面板2〇〇係形成有複數 個接觸端210,該些接觸端2 10係與該第一基板1 1〇電性連 接。 § 4探測頭1 0 0在傳輸測試信號過程中,有不正常之 電流產生時,該不正常之電流可經由設置在該容置腔1 1 4 内之旁路電容130導接至該第一基板11〇之第一接地層 II 3 ’以減少測試信號被雜訊干擾的程度,此外,該第二Page 8 M253771 4. Creation instructions (4) Several redistribution traces 125 and a plurality of vias 126. The materials of the power supply layer 123 and §1 first ground layer 1 2 4 are metal layers. The power supply layer 12 3 is formed between the upper surface 121 of the second substrate 120 and the lower surface 112 of the first substrate 110. The second ground layer 124 is embedded in the second substrate by a multi-layer technology. 120, formed between the upper surface 121 and the lower surface 122 of the second substrate 120, the redistribution traces 125 are disposed on the lower surface 122 of the second substrate 120, and the vias 126 are penetrated The upper surface 121 and the lower surface 122 of the second substrate 120 are connected to the redistribution traces 125. The bypass capacitor 130 is disposed in the accommodating cavity 114 of the first substrate 110 and passes through a receiving cavity 114. The process of "ref low" is combined with the solder layer 11 6 and fixed in the accommodating cavity 11 4. The bypass capacitor 1 30 is electrically connected to the first ground layer 113 of the first substrate 110 and the first ground layer 113. The power source layer 123 of the second substrate 120. The probe terminals 140 are disposed on the lower surface I 2 2 of the second substrate 120 and are redistributed with the traces. 1 2 5 is electrically connected for detecting the integrated circuit (not shown in the figure). Preferably, the detection head 100 further includes a third substrate 150, and the third substrate 150 is disposed on the The upper surface 111 of the first substrate 110 is formed with a groove 151 for mounting a dielectric panel 200 for transmitting a test signal. The dielectric panel 200 is formed with a plurality of contact terminals 210. The contact ends 2 10 are electrically connected to the first substrate 1 10. § 4 When an abnormal current is generated during the transmission of the test signal from the probe 1 0 0, the abnormal current can be connected to the first through a bypass capacitor 130 provided in the accommodating cavity 1 1 4 The first ground layer II 3 ′ of the substrate 11 is used to reduce the degree to which the test signal is disturbed by noise. In addition, the second

M253771 四、創作說明(5) 基板120之第二接地層124係形成於該第二基板11〇之電源 層123與該些探觸端140之間,以形成屏蔽效應 〔shielding effectiveness〕,降低電源層21所產生之 電磁波傳播〔propagation〕效應或散射〔scattering〕 效應而造成之雜訊,增益該低雜訊探測頭1 〇 〇之功效。 依本創作之第二具體實施例,請參閱第2圖,一種低 雜探測頭3 0 0係主要包含有一基板31 0、至少一旁路電容 320〔 by-pass capacitor〕,該基板310 係可為一矽基 板、玻璃基板或陶瓷基板,該基板3 10係具有一上表面311 及一下表面312,該基板310之上表面311係用以對應一介 面板40 0,該介面板400係形成有一金屬層410,該基板310 之下表面31 2係用以對應待測積體電路〔圖未繪出〕,該 基板31 0係形成有複數個導通孔3 1 3、複數個重分配跡線 314、二接地/電源層315及至少一容置腔316,其中該些導 通孔313係貫穿該基板31〇之上表面311與下表面312,並連 接該些重分配跡線3 1 4,該些重分配跡線31 4係設於該基板 310之下表面312,並電性連接複數個探觸端330,該些探 觸端330係形成於該基板31〇之下表面312,該接地/電源層 315係以積層〔mui t i-layer〕技術内埋於該基板31 〇,而 形成於該基板310之上表面311及下表面312之間,該容置 腔31 5係形成於該基板31 〇之上表面3 11及該接地/電源層 315之間,並顯露於該基板3 1〇之上表面311,該容置腔内 316係設有一銲料層317,該旁路電容32〇係設於該基板31() 之容置腔316 ’並與該銲料層317結合,使得該旁路電容M253771 IV. Creation instructions (5) The second ground layer 124 of the substrate 120 is formed between the power layer 123 of the second substrate 110 and the probe terminals 140 to form a shielding effectiveness and reduce the power supply. The noise caused by the propagation effect or the scattering effect generated by the layer 21 gains the effect of the low-noise detection head 1000. According to the second specific embodiment of this creation, please refer to FIG. 2. A low-noise detection head 3 0 0 mainly includes a substrate 3 0 and at least a bypass capacitor 320 [by-pass capacitor]. The substrate 310 may be A silicon substrate, a glass substrate, or a ceramic substrate. The substrate 3 10 has an upper surface 311 and a lower surface 312. The upper surface 311 of the substrate 310 corresponds to a dielectric panel 400. The dielectric panel 400 is formed with a metal layer. 410, the lower surface 31 2 of the substrate 310 is used to correspond to the integrated circuit to be tested (not shown in the figure). The substrate 3 10 is formed with a plurality of vias 3 1 3, a plurality of redistribution traces 314, 2 The ground / power layer 315 and at least one receiving cavity 316, wherein the vias 313 penetrate the upper surface 311 and the lower surface 312 of the substrate 31, and connect the redistribution traces 3 1 4 and the redistributions. The trace 31 4 is disposed on the lower surface 312 of the substrate 310 and is electrically connected to a plurality of probe terminals 330. The probe terminals 330 are formed on the lower surface 312 of the substrate 31. The ground / power layer 315 It is embedded in the substrate 31 using the mui t i-layer technology, and It is formed between the upper surface 311 and the lower surface 312 of the substrate 310. The accommodating cavity 315 is formed between the upper surface 3 11 and the ground / power layer 315 of the substrate 31, and is exposed on the substrate 3 On the upper surface 311, a solder layer 317 is disposed in the accommodation cavity 316, and the bypass capacitor 32 is disposed in the accommodation cavity 316 'of the substrate 31 () and combined with the solder layer 317, so that Bypass capacitor

M253771 四、創作說明(6) 320係與該基板310之接地/電源層315電性連接, 例中,當該探測頭300用以測試待測積體電路時, 兮 介面板400接合,當該探測頭3〇〇與該介面板4〇〇接了 獅…電容32〇係與該介面板4〇〇之金;二^ 接觸,用以導接在傳輸測試信號過程中產生之不正 流,減少測試信號被干擾的程度。 本之保護範圍當視後附之申請專利範圍所界定者 ,壬可熟知此項技藝者,在不脫離本創作之精神和f 圍内所作之任冑變化與修改,均屬於本創作之保護範圍。M253771 4. Creation instructions (6) 320 is electrically connected to the ground / power layer 315 of the substrate 310. For example, when the probe 300 is used to test the integrated circuit under test, the dielectric panel 400 is bonded. The probe 300 is connected to the interface panel 400. The capacitor 32 is the gold of the interface panel 400. Two contacts are used to guide the unbalanced current generated during the transmission of the test signal and reduce The degree to which the test signal is disturbed. The scope of protection of this book is defined by the scope of the patent application attached to it. Anyone who is familiar with this skill can make any changes and modifications that do not depart from the spirit and f of this creation, which are all within the scope of protection of this creation. .

第11頁 M253771 圖式簡單說明 【圖式簡單說明】 第1圖··依據本創作之第一具體實施例 頭之截面示意圖;及 第2圖·依據本創作之第二具體實施例 頭之截面示意圖。 一種低雜訊探測 一種低雜訊探測 元件符號簡單說明 1 0 0探測頭 11 〇第一基板 113第一接地層 116刼料層 120第二基板 123 電源層 126 導通孔 130 旁路電容 140探觸端 150第三基板 2 0 0介面板 300探測頭 310基板 31 3 導通孔 31 6 容置腔 320 旁路電容 330 探觸端 111上表面 114容置腔 1 21 上表面 1 2 4第二接地層 151 凹槽 21 〇接觸端 311 上表面 31 4重分配跡線 31 7鲜料層 112下表面 11 5 定位槽孔 1 2 2下表面 1 2 5重分配跡線 31 2下表面 31 5接地/電源層Page 11 M253771 Brief description of the drawings [Simplified description of the drawings] Figure 1 ·· Sectional diagram of the head according to the first embodiment of the present creation; and Figure 2 · Section of the head of the second embodiment according to the creation schematic diagram. A low-noise detection A simple description of the low-noise detection element symbol 1 0 0 probe head 11 0 first substrate 113 first ground layer 116 material layer 120 second substrate 123 power layer 126 via 130 bypass capacitor 140 probe End 150 Third substrate 2 0 0 Interface panel 300 Probe head 310 Substrate 31 3 Through hole 31 6 Receiving cavity 320 Bypass capacitor 330 Upper surface of the probe end 111 Receiving cavity 1 21 Upper surface 1 2 4 Second ground layer 151 Groove 21 〇Contact end 311 Upper surface 31 4 Redistribution trace 31 7 Fresh material layer 112 Lower surface 11 5 Positioning slot 1 2 2 Lower surface 1 2 5 Redistribution trace 31 2 Lower surface 31 5 Ground / Power Floor

第12頁 M253771 圖式簡單說明 400介面板 410 金屬層 Φ Φ ιι·ϋΐ 第13頁Page 12 M253771 Brief description of the diagram 400 Interface panel 410 Metal layer Φ Φ ι · ϋΐ Page 13

Claims (1)

M253771M253771 【申請專利範圍】 1、 一種低雜訊探測頭,包含·· 第基板’其係具有一上表面及一下表面,該第一 基板係形成有一第一接地層及至少一容置腔,該第一接地 層係形成於該第一基板之該上表面,該容置腔係形成於該 第一基板之該上表面及該下表面之間; 、” 一第二基板,其係設於該第一基板之該下表面,該第 二基板係具有一上表面及一下表面,該第二基板係形成有 一電源層及一第二接地層,該電源層係形成於該第二基板 之該上表面與該第一基板之該下表面之間,該第二接地層 係开&gt; 成於該第二基板之該上表面與該下表面之間; 至少一旁路電容〔by-pass capacitor〕,其係設於 該第一基板之該容置腔内,該旁路電容係電性連接該第一 基板之該第一接地層與該第二基板之電源層;及 複數個拉觸端’其係設於該第二基板之該下表面,用 以探觸待測積體電路。 2、 如申請專利範圍第1項所述之低雜訊探測頭,其另包 含複數個重分配跡線,其係設於該第二基板之該下表面, 該些重分配跡線係電性連接該些探觸端。 3、 如申請專利範圍第2項所述之低雜訊探測頭,其中該 第二基板係形成有複數個導通孔,其係連接該些重分配/跡 線。 一刀-、 4、如申請專利範圍第1項所述之低雜訊探測頭,其另包 含一銲料層,其係設於該容置腔内。[Scope of patent application] 1. A low-noise detection head, which includes a first substrate having an upper surface and a lower surface. The first substrate is formed with a first ground layer and at least one receiving cavity. A ground layer is formed on the upper surface of the first substrate, and the accommodating cavity is formed between the upper surface and the lower surface of the first substrate; and a second substrate disposed on the first substrate The lower surface of a substrate, the second substrate has an upper surface and a lower surface, the second substrate is formed with a power source layer and a second ground layer, and the power source layer is formed on the upper surface of the second substrate And the lower surface of the first substrate, the second ground layer is formed &gt; formed between the upper surface and the lower surface of the second substrate; at least one by-pass capacitor, Is located in the accommodating cavity of the first substrate, and the bypass capacitor is electrically connected between the first ground layer of the first substrate and the power layer of the second substrate; and a plurality of pull contacts It is arranged on the lower surface of the second substrate for detecting the contact A measurable body circuit 2. The low-noise detection head described in item 1 of the scope of patent application, further comprising a plurality of redistribution traces, which are provided on the lower surface of the second substrate, and the redistributions The traces are electrically connected to the probe terminals. 3. The low-noise detection head described in item 2 of the patent application scope, wherein the second substrate is formed with a plurality of vias, which are connected to the redistributions. / Trace. One-knife- 4. The low-noise detection head as described in item 1 of the patent application scope, further comprising a solder layer, which is disposed in the accommodating cavity. M253771 五、申請專利範圍 5、 如申請專利範圍第1項所述之低雜訊探測頭,其中該 第一基板係形成有複數個定位槽孔。 6、 如申請專利範圍第1項所述之低雜訊探測頭,其另包 含一第三基板,其係設於該第一基板之該上表面。 7、 如申請專利範圍第4項所述之低雜訊探測頭,其中該 第三基板係形成有一凹槽。 8、 如申請專利範圍第丨項所述之低雜訊探測頭,其中該 第一基板係選自於矽基板、玻璃基板與陶瓷基板之其中之 9、一種低雜訊探測頭,包含: 一基板,其係具有一上表面及一下表面,該基板係布 成有一接地/電源層及至少一容置腔,該接地/電源層係形 成於該上表面及該下表面之間,該容置腔係形成於該上表 面及該接地/電源層之間;及 至少一旁路電容〔by_pass capacU〇r〕,其係設於 該基板之該容置腔,該旁路電容係與該基板之該接地/電 源層電性連接。 其中該 10、如申請專利範圍第9項所述之低雜訊探測頭 容置腔係顯露於該基板之該上表面。 其另包 ^專利範圍第9項所述之低雜訊探測頭 3 —鋒料層,其係設於該容置腔内。 其另包 12、如申請專利範圍第9 含複數個探觸端,其係形成於該基低板雜二探二頭 1 3、如申請專利範圍第丨2 μ下表面。 員所述之低雜訊探測頭,其另爸 M253771M253771 5. Scope of patent application 5. The low-noise detection head described in item 1 of the scope of patent application, wherein the first substrate is formed with a plurality of positioning slots. 6. The low-noise detection head described in item 1 of the patent application scope further includes a third substrate, which is disposed on the upper surface of the first substrate. 7. The low-noise detection head according to item 4 of the scope of patent application, wherein the third substrate is formed with a groove. 8. The low-noise detection head as described in item 丨 of the patent application scope, wherein the first substrate is selected from the group consisting of a silicon substrate, a glass substrate, and a ceramic substrate. 9. A low-noise detection head, including: A substrate having an upper surface and a lower surface, the substrate is arranged into a ground / power layer and at least one receiving cavity, and the ground / power layer is formed between the upper surface and the lower surface, and the receiving A cavity is formed between the upper surface and the ground / power layer; and at least one bypass capacitor [by_pass capacUr] is provided in the receiving cavity of the substrate, and the bypass capacitor is connected to the substrate of the substrate. The ground / power plane is electrically connected. Wherein, the low-noise detection head accommodating cavity as described in item 9 of the scope of patent application is exposed on the upper surface of the substrate. It additionally includes the low-noise detection head 3 described in the patent scope No. 3-the front layer, which is arranged in the accommodation cavity. Its additional package 12. If the patent application scope No. 9 contains a plurality of probe terminals, it is formed on the base low plate hybrid two probe heads 1 3. Such as the patent application scope No. 2 μ lower surface. The low-noise probe described by the crew member, his other father M253771 五、申請專利範圍 含複數個重分配跡線,其係設於該基板之該下表面,該此 重分配跡線係電性連接該些探觸端。 / 一 14、如申請專利範圍第丨3項所述之低雜訊探測頭,其中該 基板係形成有複數個導通孔,其係連接該些重分配跡線。 1 5、如申請專利範圍第9項所述之低雜訊探測頭,其中該 第一基板係選自於矽基板、玻璃基板與陶瓷基板之其中之5. Scope of patent application Contains a plurality of redistribution traces, which are provided on the lower surface of the substrate. The redistribution traces are electrically connected to the probe terminals. / A 14. The low-noise detection head according to item 3 of the patent application scope, wherein the substrate is formed with a plurality of vias connected to the redistribution traces. 15. The low-noise detection head according to item 9 of the scope of patent application, wherein the first substrate is selected from the group consisting of a silicon substrate, a glass substrate, and a ceramic substrate.
TW93203726U 2004-03-11 2004-03-11 Low noise probe head TWM253771U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI392872B (en) * 2009-04-10 2013-04-11 Chipmos Technologies Inc Probe card assembly and probe holder thereof
TWI426281B (en) * 2006-04-24 2014-02-11 Advantest Singapore Pte Ltd Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426281B (en) * 2006-04-24 2014-02-11 Advantest Singapore Pte Ltd Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array
TWI392872B (en) * 2009-04-10 2013-04-11 Chipmos Technologies Inc Probe card assembly and probe holder thereof

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