TWM240057U - Multiple-step inner lead of leadframe - Google Patents

Description

M240057 V. Creation Description (1) [Technical Field to which the New Type belongs] This creation relates to a stacked multi-chip structure, especially to a lead frame stacked multi-chip structure. 2. [Previous Technology] In the pursuit of high efficiency and low cost, how to accelerate product minimization and high-density packaging has become an important goal for the electronics industry. The packaging density of integrated circuit products is limited by the area of the chip that can be fixed and the height of the chip. A commonly used method to increase the density of the assembly is to stack the wafers vertically to complete the assembly. Referring to the first figure, this figure shows a structure of a common multi-chip stacked structure. A wafer 1 2 0 and a wafer 1 3 0 are vertically stacked on a lead frame wafer holder 1 0 0 with an adhesive layer 15 0, and a plurality of inner pins 1 0 2 surround the lead frame wafer holder 1 0 0 around. The plurality of metal wires 1 2 2 and the plurality of metal wires 1 3 2 respectively connect the active surfaces of the wafers 120 and 130 to the inner pins 102. U.S. Patent No. 6,118,176 discloses a stacked wafer structure capable of stacking two wafers. The wafers are stacked on the same side of the leadframe wafer holder, and the leadframes are made in steps to carry the wafers purely. US Patent No. 6,0 8 7, 7 1 8 discloses a stacked semiconductor wafer structure. The main function of the inner pin in this creation is to carry the chip. U.S. Patent No. 5,804,874 discloses a Lead-on-Chip. The main function of the inner pin used in this creation is to carry the chip. US Patent No. 5,5 3 0, 2 8 1 Patent and US M240057 V. Creative Instructions (2) National Patent No. 4, 9 8 7, 4 7 3 Patent respectively disclose staggered arrangement of inner pins extending to different planes , Used to shorten the metal welding wire and prevent the welding wire from staggering. U.S. Patent No. 5,29,0 61 discloses a multi-chip stacking structure. The upwardly extending inner pins are respectively extended to different planes to shorten the metal bonding wires and prevent the bonding wires from being staggered. There are still many disadvantages to be overcome in the above-mentioned conventional literature. For example, the design of its pins will make the process more complicated, such as welding technology in different directions, thus adding additional equipment costs and process difficulties. In addition, the special design of the pads and inner pins will also increase the construction cost and the difficulty of the process. 0 g Stacked wafers have a special function compared to the existing standard two-wafer meter or variable meter. The chip-on-surface soldering pads are mixed and have a more quasi-production effect. For the benefit, the wireframe type polycrystalline leadframe chip holder on the stacked structure is designed to face different positions. The other is not easy to control and more compatible. The other side is facing the same. You can use the existing production on stacked wafers. In the past, the wire structure or repeated stacking was often limited and only stacked. Orientation, product, and wire bonding frame chip lead frame is suitable for less construction of the main paddle.) This requires the needle process to damage the wire during the special process, so there is no need to slot the pins on the chip stacking process and avoid the socket. There are two types of special knots. One is on both sides. Because the two crystals make special reversal technology and set the wafer on one of the wafers, the same side cannot be used. Because the wafer is made with a special stacking structure, the wires are set to overlap the short-circuits and the slots are combined with these structures In heap structure, or process technology

Page 6 M240057 V. Creative Instructions (3) The technique is complicated and difficult to control. 3. [New Content] One of the objectives of this creation is to improve the structural design of the leads in the lead frame to reduce the difficulty of bonding wires and increase the yield of multi-chip stacked structures. Another purpose of this creation is to provide a lead frame type stacked multi-chip structure, in which the leads in the lead frame are designed in a step shape. Another purpose of this creation is to provide a ladder-shaped lead frame-type stacked multi-chip mounting structure with lead pins designed in stages to reduce the difficulty of bonding wires and increase the feasibility of multi-chip stacked mounting.

According to the above purpose, the present invention provides a lead frame type stacked multi-chip structure, which includes at least the following components. A lead frame chip holder and a plurality of upward stepped pins surround the lead frame chip holder. Each of the stepped pins has a number of horizontal levels. A first wafer is on the leadframe wafer holder and an active face of the first wafer is facing up and facing away from the leadframe wafer holder. A plurality of first metal wires connect a first horizontal layer of the stepped pins to the active surface of the first chip, wherein the first horizontal layer of the stepped pins is close to the lead frame chip holder. A second wafer is stacked on the first wafer and a driving surface of the second wafer faces upward and faces away from the lead frame wafer holder. A plurality of second metal wires connect a second horizontal layer of the stepped pins to the master of the second chip. M240057 5. Creation instructions (4) Moving surface, in which the second horizontal layer of the stepped pins The system extends upward from the first level. For example, the application of the broad description, the detailed work after the detailed description, the long-term meeting, the wide application, and the example, which does not include the application, the description should also be set in detail. In the first form, the production of the book is not profitable, and the narrative outside the warehouse is a description of Daji's description. The details of the description are detailed in the inch, the rule is detailed, and the figure is outside. Wei, Shi. Fang uses the knowledge of the three and the rules to apply the degree of recognition and then to the actual creation. Actually, the scope, scope and scope of the indeterminate depth, as well as his detailed description of his work, provide a lead frame type stacked multi-chip structure, in which the lead frame has stepped inner pins. The stepped inner pins can be adjusted according to the height and number of stacked chips. At the same time, different types of stepped inner pins can be designed for different bonding wire technology features. Referring to the second figure A, this figure is an embodiment of the creation. A first wafer 20 and a second wafer 30 are vertically stacked on a lead frame wafer holder 10. Among them, an active surface of the first wafer 20 and an active surface of the second wafer 30 are both facing upward and facing away from the lead frame wafer holder 10. The first wafer 20 and the second wafer 30 are stacked and adhered using a solid adhesive layer 50. This structure further includes an adhesive layer for fixing the first chip 20 on the lead frame chip holder 10. There are a plurality of step-shaped inner pins 12 surrounding the lead frame chip holder 10. Stepped

Page 8 M240057 V. Creation Instructions (5) Inner pin 12 has several horizontal levels. For example, stepped inner pin 12 has a first horizontal level and a second horizontal level. The first level is the closest to the wire. The wafer holder 10 and the second stage extend upward from the first stage. Here, the angle between any pair of horizontal steps is greater than ninety degrees. There are a plurality of first metal wires 22 connecting the first layer of the stepped inner pins 12 to the active surface of the first chip 20. There are a plurality of second metal wires 32 connecting the second layer of the step-shaped inner pins 12 to the active surface of the second chip 30. Referring to the second diagram B and the second diagram C, it is another embodiment of the present invention. Among them, the same reference numerals in different drawings represent the same objects, so the description will not be repeated. In these embodiments, the first wafer 20 and the second wafer 30 use a liquid adhesive 52, such as epoxy resin, to adhere to the stack. Referring to FIG. 2C, the angle between any pair of horizontal steps of the stepped inner pins 14 in this structure may be ninety degrees or slightly less than ninety degrees. A plurality of first metal wires 24 connect the first layer of the stepped inner pins 14 to the active surface of the first chip 20. Referring to FIG. 3A, an embodiment of the present invention is directed to stacking more than three multi-chip structures. A third wafer 40 is stacked and adhered to the second wafer 30 using a solid adhesive layer 5 4, and an active side of the third wafer 40 faces upward and faces away from the lead frame wafer holder 10. There are a plurality of stepped inner pins 16 surrounding the lead frame chip holder 10 and the inner pins 16 have three levels (a first horizontal level, a second horizontal level, and a third horizontal level), The third horizontal stratum extends upward from the second horizontal stratum. There are a plurality of third metal wires 4 2 connecting the third layer of the inner pins 16 to the third chip 40.

Page 9 M240057 V. Creation Instructions (6) Active side. Here, the included angle of any pair of horizontal steps of the stepped inner pins 16 is greater than ninety degrees. Refer to Figures 3B and 3C, which are directed to other embodiments of stacking three or more multi-chip structures. In these embodiments, the first wafer 20, the second wafer 30, and the third wafer 40 are sequentially stacked using a liquid adhesive layer 52 and a liquid adhesive layer 56. Referring to FIG. 3C, in this structure, the cool angle of any pair of horizontal steps of the stepped inner pins 18 may be ninety degrees or slightly less than ninety degrees. In this creation, the design of stepped inner pins can be designed with different types of stepped inner pins according to different bonding wire technology characteristics, such as the normal bonding method (norma 1 bond) and reverse bonding method (reverse bond). If the included angle of any pair of horizontal layers of the stepped inner pin is 90 degrees or slightly less than 90 degrees, it can be applied to the welding operation using the reverse wire method and can effectively improve the yield during welding. If the included angle of any pair of horizontal layers of the stepped inner pins is greater than 90 degrees, it can be applied to the welding operation using the normal wire bonding method. The stepped inner pins in this creation can be adjusted according to the height and number of stacked wafers and different technical characteristics of the bonding wire. This creation can effectively overcome the shortcomings of the conventional technology. This stepped inner pin only needs to be formed by one or more stamping using the lead in the original lead frame, which is the same as the general lead frame manufacturing process. And the multi-wafer packaging process and equipment of this creative structure are exactly the same as the single-wafer packaging, no additional packaging process is required.

Page 10 M240057 V. Creative Instructions (7) Preface and equipment. The height and number of inner pin levels can be adjusted for different stacked chip heights and numbers, to optimize the bonding wire structure, and reduce the bonding wire height and length. In the molding process, it reduces the contact between different bonding wires and bonding wire offset. In addition, different types of stepped inner pins can be designed according to the technical characteristics of the bonding wire, reducing the difficulty on the bonding wire to improve the feasibility of multi-chip assembly.

In summary, the present invention provides a lead frame type stacked multi-chip structure. In this structure, the active surfaces of the wafers with circuits are all facing up and stacked on the same side of the leadframe wafer holder. In the structure, the lead in the lead frame has a continuous step shape, and the shape has a shape larger than a right angle and a shape slightly smaller than a right angle. Stepped inner pins that are larger than the right angle shape can be applied to the normal wire bonding method or reverse wire bonding method, and stepped inner pins that are slightly smaller than the right angle shape can be applied to the reverse wire bonding method. The stacking of wafers can be cured using solid or liquid glue. This creation can be used to stack wafers of the same or different sizes, as well as wafers of the same or different functions. Furthermore, this creation can be applied to constructing more than three wafers.

The above is only a preferred embodiment of this creation, and is not intended to limit the scope of the patent application for this creation; all other equivalent changes or modifications made without departing from the spirit disclosed by this creation shall be included in the following Within the scope of patent application. M240057 Brief description of the drawings 5. [Simplified description of the drawings] The first diagram is a schematic cross-sectional view of a conventional stacked multi-chip structure. Figures 2A to 2C are schematic cross-sectional views of the stacked polycrystalline wafer structure disclosed in this work. Figures 3A to 3C are not intended to be cross-sections of the stacked polycrystalline wafer structure according to the present disclosure. Representative symbols of the main parts: 1 0 lead frame wafer holder 1 2 stepped pins 1 4 stepped pins 1 6 stepped pins 1 8 stepped pins 20 first chip 2 2 first metal wire 2 4 first Metal wire 3 0 Second chip 3 2 Second metal wire 3 4 Second metal wire 4 0 Third chip 4 2 Third metal wire 5 0 Adhesive layer

Page 12 M240057 Brief description of the drawing 5 2 Adhesive layer 5 4 Adhesive layer 5 6 Adhesive layer 10 0 Lead frame wafer holder 10 2 Lead frame pins 1 2 0 Chip 12 2 First metal wire 13 0 Chip 13 2 Second metal Wire 1 5 0 Adhesive layer #

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Claims (1)

M240057 6. Scope of patent application 1. A lead frame stacked multi-chip-a lead frame wafer holder; a plurality of upward stepped pins, each of which is divided into a first chip on an active surface of the lead frame A plurality of first metal wires are connected to the first level and back to the first level of the first chip. The first horizontal level is close to the second chip. The first active side is directed upward and back. The level of the plurality of second metal wires connected to the lead to the main and the second level of the second chip is from the first 2. As in any one of the above two levels of the patent application, a clip 3 For example, the above-mentioned structure structure of any two of the above two horizontal levels includes at least: surrounding the leadframe wafer holder, there are several horizontal levels: on the wafer holder, wherein the wireframe of the first wafer is A wafer holder, connected to the first hydrodynamic surface of the stepped pins, wherein the wireframe wafer holders of the stepped pins; on a wafer, the wireframe wafer holder of the second wafer, and connected to the wafer holders Stepped A second hydrodynamic surface of the pins, wherein the horizontal levels of the stepped pins extend upward. Stacked multi-chip structure, where the angle is greater than or equal to ninety degrees. The stacked multi-chip structure has an included angle slightly less than 90 degrees. 4. For example, the stacked multi-chip mounting structure in the scope of patent application No. 1 further includes an adhesive layer for fixing the first wafer on the lead frame wafer holder. M240057 6. Application for patent scope 5. For application for patent The stacked multi-chip structure of the first item of the scope, which further includes an adhesive layer for stacking the second wafer on the first wafer. 6. The stacked multi-chip structure of the fifth item of the patent application In the structure, the above adhesive layer can be selected from the following: a solid adhesive layer and a liquid adhesive. 7. If the stacked multi-chip structure of the first patent application scope includes a third chip stacked on the second chip. 8. The stacked multi-chip structure of claim 7 in which the active surface of the third chip is facing upward and facing away from the lead frame chip holder. 9. For example, the stacked multi-chip structure of the scope of patent application No. 7 further includes an adhesive layer for stacking the third wafer on the second wafer. In a stacked multi-chip structure, the above adhesive layer can be selected from the following: a solid adhesive layer and a liquid adhesive. 11. A lead frame stacked multi-chip structure includes at least: Page 15 M240057 VI. Patent application scope: a leadframe wafer holder; a plurality of upward stepped pins surround the leadframe wafer holder, each of which has a number of horizontal levels: a first chip On the leadframe wafer holder, an active surface of the first wafer faces upward and faces away from the leadframe wafer holder; a plurality of first metal wires connect a first horizontal layer of the stepped pins to the The active surface of the first wafer, wherein the first horizontal layer of the stepped pins is close to the leadframe wafer holder; a second wafer is stacked on the first wafer, and an active surface of the second wafer The second metal wires connect a second horizontal layer of the stepped pins to the active surface of the second chip, wherein the stepped pins are The second horizontal layer extends upward from the first horizontal layer; a third chip is stacked on the second chip, wherein an active surface of the third chip is facing upward and facing away from the lead frame wafer holder; A plurality of third metal wires connect a third horizontal layer of the stepped pins to the active surface of the third chip, wherein the third horizontal layer of the stepped pins is from the second horizontal layer Extend upwards. 1 2. According to the stacked multi-chip mounting structure of the scope of application for patent No. 11, wherein the cool angle of any of the two horizontal levels is greater than or equal to ninety degrees. 1 3. For the stacked multi-chip structure of item 11 in the scope of patent application, an angle between any of the above two horizontal levels is slightly less than ninety degrees. M240057 6. Scope of patent application 1 4. The stacked multi-chip structure of item 11 of the patent application scope further includes an adhesive layer for fixing the first chip on the lead frame chip holder. 1 5. The stacked multi-chip mounting structure according to the scope of patent application 1 1 further includes an adhesive layer for stacking the second wafer on the first wafer 16. As the scope of patent application scope 1 5 According to the stacked multi-chip structure, the above-mentioned adhesive layer can be selected from the following: a solid adhesive layer and a liquid adhesive. 1 7. The stacked multi-wafer structure according to item 11 of the application, further comprising an adhesive layer for stacking the third wafer on the second wafer. 1 8. The stacked multi-chip mounting structure according to item 17 of the scope of patent application, wherein the above adhesive layer can be selected from the following: a solid adhesive layer and a liquid adhesive. Page 17