TWI856700B - Display - Google Patents

Abstract

A display includes a display device and a first driving device, the display device includes a first pixel circuit configured to adjust a first voltage difference from a first voltage difference value to a second voltage difference value according to a first voltage signal and emit light according to the first voltage difference, the first driving device includes a first switch configured to supply a second voltage signal to a first node to output the first voltage signal and a second switch configured to supply the first reference voltage signal to the first node to output the first voltage signal. When the first voltage difference has the first voltage difference value, the second voltage signal has a first voltage level. When the first voltage difference has the second voltage difference value, the second voltage signal has a second voltage level. The first reference voltage signal has a third voltage level between the first voltage level and the second voltage level. The second voltage difference value is approximately equal to the negative first voltage difference value.

Description

Display

This disclosure relates to a display technology, and more particularly to a display and a method of operating the display.

In order to increase contrast, the display uses both negative liquid crystal and positive liquid crystal to emit light. However, using both negative liquid crystal and positive liquid crystal to emit light requires a higher operating voltage, which leads to an increase in the energy consumption of the integrated circuit (IC) driving the display. Therefore, how to design to solve the above problem is an important topic in this field.

The present invention includes a display device, a first pixel circuit, the first pixel circuit is used to adjust a first voltage difference from a first voltage difference value to a second voltage difference value according to a first voltage signal, and emit light according to the first voltage difference; a first driving device, including a first switch, used to provide the second voltage signal to a first node to output the first voltage signal; a second switch, used to provide the first reference voltage signal to a first node; Provided to the first node to output a first voltage signal, wherein when the first voltage difference has a first voltage difference value, the second voltage signal has a first voltage level, and when the first voltage difference has a second voltage difference value, the second voltage signal has a second voltage level, the first reference voltage signal has a third voltage level between the first voltage level and the second voltage level, and the second voltage difference value is approximately equal to the negative first voltage difference value.

An embodiment of the present invention includes a method for operating a display, including maintaining a first voltage signal at a first voltage level during a first period; maintaining the first voltage signal at a second voltage level during a second period; maintaining the first voltage signal at a third voltage level during a third period; maintaining a voltage difference of a light-emitting element by the first voltage signal during the first period, the second period, and the third period, wherein the first period, the second period, and the third period are arranged sequentially and continuously, and the second voltage level is less than one of the first voltage level and the third voltage level, and greater than the other of the first voltage level and the third voltage level.

In this article, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate with each other or interact with each other. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present case.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which this case belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this case, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "comprise" specify the presence and/or parts of the features, regions, entireties, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and/or combinations thereof.

The following will disclose multiple implementations of the present invention with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

FIG. 1A is a schematic diagram of a display 100A according to an embodiment of the present invention. As shown in FIG. 1A , the display 100A includes a display device 110 and a driving device 120. In some embodiments, the driving device 120 is used to provide voltage signals S1-S5 to the display device 110. In various embodiments, the driving device 120 can provide various amounts of voltage signals to the display device 110.

As shown in FIG. 1A , the display device 110 includes pixel circuit rows PCR1 to PCR5. Each of the pixel circuit rows PCR1 to PCR5 includes a plurality of pixel circuits coupled in series with each other. The driving device 120 includes driving circuits DC1 to DC5. In some embodiments, the driving circuits DC1 to DC5 are respectively used to output voltage signals S1 to S5. The pixel circuit rows PCR1 to PCR5 are respectively used to perform light-emitting operations according to the voltage signals S1 to S5. In various embodiments, the display device 110 may include various numbers of pixel circuit rows. In various embodiments, the driving device 120 may include various numbers of driving circuits.

FIG. 1B is a schematic diagram of a driving device 100B according to an embodiment of the present invention. The driving device 100B is an embodiment of the driving device 120 shown in FIG. 1A. As shown in FIG. 1B, the driving device 100B includes driving circuits 121 and 122 and a circuit 130. In some embodiments, the circuit 130 is used to output voltage signals VS1 and VS2 according to voltage signals V1 and V2. The driving circuits 121 and 122 are used to operate according to the voltage signals VS1 and VS2, respectively. In some embodiments, the voltage signal V1 has a different voltage level from the voltage signal V2. For example, the voltage level of the voltage signal V1 is 2 V, and the voltage level of the voltage signal V2 is 8 V. In some embodiments, the circuit 130 can be implemented by a multiplexer or an inverter.

The driving circuit 121 includes a pull-up control circuit PUC1, pull-up circuits PU1 and PU2, and pull-down circuits PD1 and PD2. The driving circuit 122 includes a pull-up control circuit PUC2, pull-up circuits PU3 and PU4, and pull-down circuits PD3 and PD4.

In some embodiments, the pull-up control circuit PUC1 is used to control the pull-up circuits PU1 and PU2. The pull-up circuit PU1 is used to output the gate signal G1. The pull-up circuit PU2 is used to output the voltage signal VC1 according to the voltage signal VS1. The pull-up control circuit PUC2 is used to control the pull-up circuits PU3 and PU4. The pull-up circuit PU3 is used to output the gate signal G2. The pull-up circuit PU4 is used to output the voltage signal VC2 according to the voltage signal VS2. Each of the pull-up circuits PU1 and PU3 and the pull-down circuits PD1 and PD3 is used to receive the reference voltage signal VSS. Each of the pull-up circuits PU2 and PU4 and the pull-down circuits PD2 and PD4 is used to receive the reference voltage signal VREF.

In some embodiments, the reference voltage signal VSS has a ground voltage level. The reference voltage signal VREF has a voltage level VR1. The voltage level VR1 is greater than the ground voltage level. For example, the voltage level VR1 is 5 volts, and the ground voltage level is 0 volts. In some embodiments, the voltage level VR1 is between the voltage level of the voltage signal V1 and the voltage level of the voltage signal V2.

As shown in FIG. 1B , arrows A1 and A2 represent the control of the pull-up circuit PU3 of the driving circuit 122 over the pull-down circuits PD1 and PD2 of the driving circuit 121. Details of the arrows A1 and A2 are further described in the following embodiment of FIG. 2A .

1B and 1A, two of the driving circuits DC1 to DC5 can be implemented by driving circuits 121 and 122. For example, driving circuits DC1 and DC5 are implemented by driving circuits 121 and 122, respectively.

FIG. 2A is a schematic diagram of a display 200A corresponding to the display 100A shown in FIG. 1A according to an embodiment of the present invention. As shown in FIG. 2A , the display 200A includes a driver circuit 220 and a pixel circuit 210. In some embodiments, the driver circuit 220 is used to output a voltage signal VC1 and a gate signal G1, and the pixel circuit 210 is used to perform a light-emitting operation according to the voltage signal VC1 and the gate signal G1.

As shown in FIG. 2A , the driving circuit 220 includes a pull-up control circuit 221, pull-up circuits 222 and 223, pull-down circuits 224 and 225, and capacitors C201 and C202. In some embodiments, the pull-up control circuit 221 is used to control the voltage level of the node N21. The pull-up circuit 222 is used to control the voltage levels of the nodes N23 and N24 according to the voltage level of the node N21. The pull-up circuit 223 is used to control the voltage level of the node N25. The pull-down circuit 224 is used to control the voltage levels of the nodes N21~N24. The pull-down circuit 225 is used to control the voltage level of the node N25.

As shown in FIG. 2A , the pull-up control circuit 221 includes a switch T201. The pull-up circuit 222 includes switches T202 and T203. The pull-up circuit 223 includes a switch T212. The pull-down circuit 224 includes switches T204 to T211. The pull-down circuit 225 includes a switch T213.

As shown in FIG. 2A, the first end and the control end of the switch T201 are used to receive the control signal ST1. The second end of the switch T201 is coupled to the node N21. The first end of each of the switches T202 and T203 is used to receive the clock signal HC1. The second end of the switch T202 is coupled to the node N23. The control end of each of the switches T202 and T203 is coupled to the node N21. The second end of the switch T203 is coupled to the node N24. The first end of each of the switches T204, T205 and T208 is coupled to the node N21. The second end of each of the switches T204~T209 and T211 is used to receive the reference voltage signal VSS. The control end of each of the switches T204 and T211 is used to receive the control signal ST3. The control end of each of the switches T205 and T207 is used to receive the control signal ST0. The first end of each of the switches T206 and T207 is coupled to the node N22. The control end of the switch T206 is coupled to the node N21. The control end of each of the switches T208 to T210 is coupled to the node N22. The first end of the switch T209 is coupled to the node N23. The first end of each of the switches T210 and T211 is coupled to the node N24. The second end of the switch T210 is used to receive the reference voltage signal VSSG. The first end of the switch T212 is used to receive the voltage signal VS1. The second end of the switch T212 and the first end of the switch T213 are coupled to the node N25. The control end of the switch T212 is coupled to the node N21. The second end of the switch T213 is used to receive the reference voltage signal VREF. The control end of the switch T213 is used to receive the control signal P1 at the node N22. The first end of capacitor C201 is coupled to node N21. The second end of capacitor C201 is coupled to node N24. The first end of capacitor C202 is used to receive clock signal HC1. The second end of capacitor C202 is coupled to node N22.

In some embodiments, the absolute value of the voltage level of the reference voltage signal VSSG is higher than the ground voltage level. For example, the voltage level of the reference voltage signal VSSG is -6 volts, and the ground voltage level is 0 volts.

As shown in FIG. 2A , the pixel circuit 210 includes a switch T214 and a capacitor C203. The first end of the switch T214 is used to receive the voltage signal SL1. The second end of the switch T214 is coupled to the node N26. The control end of the switch T214 is coupled to the node N24. The first end of the capacitor C203 is coupled to the node N26. The second end of the capacitor C203 is coupled to the node N25.

Referring to FIG. 1A and FIG. 2A, pixel circuit 210 is an embodiment of a pixel circuit in pixel circuit row PCR1. Driver circuit 220 is an embodiment of driver circuit DC1. Voltage signal VC1 is an embodiment of voltage signal S1. Gate signal G1 is an embodiment of voltage signal S1. Referring to FIG. 1B and FIG. 2A, driver circuit 220 is an embodiment of driver circuit 121. Pull-up control circuit 221 is an embodiment of pull-up control circuit PUC1. Pull-up circuit 222 is an embodiment of pull-up circuit PU1. Pull-up circuit 223 is an embodiment of pull-up circuit PU2. Pull-down circuit 224 is an embodiment of pull-down circuit PD1. Pull-down circuit 225 is an embodiment of pull-down circuit PD2.

FIG. 2B is a circuit diagram of a circuit 200B according to an embodiment of the present invention. In some embodiments, the circuit 200B is used to output a voltage signal VS1 according to clock signals CK1 and CK2 and voltage signals V1 and V2.

As shown in FIG. 2B , circuit 200B includes switches T221 and T222. In some embodiments, the first end of switch T221 is used to receive voltage signal V1. The second end of switch T222 is used to receive voltage signal V2. The second end of switch T221 and the first end of switch T222 are used to output voltage signal VS1 at node N27. The control end of switch T221 is used to receive clock signal CK1. The control end of switch T222 is used to receive clock signal CK2. Clock signals CK1 and CK2 are complementary clock signals.

2B and 2A , in some embodiments, the first terminal of the switch T212 is coupled to the node N27 to receive the voltage signal VS1 . 2B and 1B , in some embodiments, the circuit 200B is an embodiment of the circuit 130 .

FIG. 2C is a circuit diagram of a circuit 200C according to an embodiment of the present invention. In some embodiments, the circuit 200C is used to output a voltage signal VS1 according to a clock signal CK1, voltage signals V1 and V2.

As shown in FIG. 2C , circuit 200C includes switches T223 and T224. In some embodiments, the first terminal and the control terminal of switch T223 are used to receive voltage signal V2. The second terminal of switch T224 is used to receive voltage signal V1. The second terminal of switch T223 and the first terminal of switch T224 are used to output voltage signal VS1 at node N28. The control terminal of switch T224 is used to receive clock signal CK1.

Compared to FIG. 2B , the control end of switch T223 is used to receive the voltage signal V2 instead of the clock signal CK2, so that switch T223 remains on. The control end of switch T224 is used to receive the clock signal CK1. Switches T223 and T224 are designed as switches of different sizes. In some embodiments, the smaller the volume of the switch, the greater the resistance of the switch. For example, the volume of switch T223 is smaller than the volume of switch T224, so that the resistance of switch T223 is greater than the resistance of switch T224.

Correspondingly, when the switch T224 is turned off, the voltage signal VS1 has the voltage level of the voltage signal V2. When the switch T224 is turned on, since the resistance of the switch T223 is much larger than the resistance of the switch T224, the switch T223 can be regarded as turned off, so that the voltage signal VS1 has the voltage level of the voltage signal V1.

2C and 2A, in some embodiments, the first terminal of the switch T212 is coupled to the node N28 to receive the voltage signal VS1. Referring to FIG. 2C and 1B, in some embodiments, the circuit 200C is an embodiment of the circuit 130.

FIG. 2D is a timing diagram 200D of the operation of the display 200A according to an embodiment of the present invention. As shown in FIG. 2D, the timing diagram 200D includes periods P201 to P211 arranged sequentially and continuously. During the periods P201 to P211, the clock signals HC1, CK1 and CK2, the gate signal G1, the control signals ST1 to ST3 and P1 operate between the voltage levels VH and VL. The control signal Q1 operates between the voltage levels VQ, VH and VL. The voltage signal VC1 operates between the voltage levels V01, VR1 and V02. The voltage signal SL1 operates between the voltage levels V03 and V04. The luminescence signal PX1 operates between the voltage levels V03 to V07.

In some embodiments, reference voltage signals VSS and VSSG have voltage level VL. Voltage level VH is greater than voltage level VL. Voltage level VQ is greater than voltage level VH. Voltage level V02 is greater than voltage level VR1. Voltage level VR1 is greater than voltage level V01. For example, voltage level V02 is 8 volts, voltage level VR1 is 5 volts, and voltage level V01 is 2 volts. Voltage level V04 is greater than voltage level V03. For example, voltage level V04 is 10 volts, and voltage level V03 is 0 volts. Voltage level V06 is greater than voltage level V04. Voltage level V04 is greater than voltage level V05. Voltage level V05 is greater than voltage level V03. Voltage level V03 is greater than voltage level V07. For example, voltage level V06 is 13 volts, voltage level V04 is 10 volts, voltage level V05 is 5 volts, voltage level V03 is 0 volts, and voltage level V07 is -3 volts.

In some embodiments, before the period P201, the control signal ST0 (not shown in the figure) has a voltage level VH, so that each of the switches T205 and T207 is turned on. At this time, the switch T207 provides the reference voltage signal VSS to the node N22 to reset the voltage level of the node N22 to the voltage level VL, and turns off each of the switches T208~T210 and T213. The switch T205 outputs the reference voltage signal VSS to the node N21 to reset the voltage level of the node N21 to the voltage level VL, so that each of the switches T202, T203, T206 and T212 is turned off.

Referring to FIG. 2D and FIG. 2B , in some embodiments, during the period P201-P206, the clock signal CK1 is at the voltage level VH, so that the switch T221 is turned on. The clock signal CK2 is at the voltage level VL, so that the switch T222 is turned off. At this time, the switch T221 outputs the voltage signal V1 to the node N27, so that the voltage signal VS1 has a voltage level V01.

During the period P207-P211, the clock signal CK1 is at the voltage level VL, so that the switch T221 is turned off. The clock signal CK2 is at the voltage level VH, so that the switch T222 is turned on. At this time, the switch T222 outputs the voltage signal V2 to the node N27, so that the voltage signal VS1 has a voltage level V02.

Referring to FIG. 2D and FIG. 2C , in some embodiments, during the period P201-P206, the clock signal CK1 is at the voltage level VH, so that the switch T224 is turned on. At this time, the switch T224 outputs the voltage signal V1 to the node N28, so that the voltage signal VS1 has a voltage level V01. During the period P207-P211, the clock signal CK1 is at the voltage level VL, so that the switch T224 is turned off. At this time, the switch T223 outputs the voltage signal V2 to the node N28, so that the voltage signal VS1 has a voltage level V02.

During period P201, the clock signal HC1, the control signals Q1, ST1-ST3, P1 and the gate signal G1 have a voltage level VL. The voltage signal VC1 has a voltage level VR1. The voltage signal SL1 has a voltage level V04. The light-emitting signal PX1 has a voltage level V05.

During period P202, control signal ST1 has voltage level VH, so that switch T201 is turned on to provide control signal ST1 to node N21. At this time, control signal Q1 has voltage level VH, so that switches T202, T203 and T212 are turned on to provide voltage signal VS1 to node N25. Voltage signal VC1 has voltage level V01.

During period P203, the clock signal HC1 has a voltage level VH, so that the turned-on switches T202 and T203 output the clock signal HC1 to nodes N23 and N24. The control signal ST2 and the gate signal G1 have a voltage level VH. At this time, the switch T214 is turned on to output the voltage signal SL1 to the node N26, so that the light-emitting signal PX1 has a voltage level V04. The capacitor C201 adjusts the voltage level of the node N21 from the voltage level VH to the voltage level VQ through capacitive coupling. At this time, there is a first voltage difference between the light-emitting signal PX1 and the voltage signal VC1.

During period P204, the control signal ST3 has a voltage level VH, so that the switches T204 and T211 are turned on to output the reference voltage signal VSS to the nodes N21 and N24. The control signal Q1 and the gate signal G1 have a voltage level VL, so that the switches T212 and T214 are turned off.

During period P205, the clock signal HC1 has a voltage level VH, so that the capacitor C202 adjusts the voltage level of the node N22 from the voltage level VL to the voltage level VH through capacitive coupling. The control signal P1 has a voltage level VH, so that the switch T213 is turned on to output the reference voltage signal VREF to the node N25, so that the voltage signal VC1 has a voltage level VR1. The capacitor C203 adjusts the voltage level of the node N26 from the voltage level V04 to the voltage level V06 through capacitive coupling.

During period P206, the clock signal HC1, the control signals P1, Q1, ST1-ST3 and the gate signal G1 have a voltage level VL. At this time, the switches T201-T214 are turned off.

During period P207, control signal ST1 has voltage level VH, so that switch T201 is turned on to provide control signal ST1 to node N21. At this time, control signal Q1 has voltage level VH, so that switches T202, T203 and T212 are turned on to provide voltage signal VS1 to node N25. Voltage signal VC1 has voltage level V02. Voltage signal SL1 has voltage level V03.

During period P208, the clock signal HC1 has a voltage level VH, so that the turned-on switches T202 and T203 output the clock signal HC1 to nodes N23 and N24, and the control signal ST2 and the gate signal G1 have a voltage level VH. At this time, the switch T214 is turned on to output the voltage signal SL1 to the node N26, so that the light-emitting signal PX1 has a voltage level V03. The capacitor C201 adjusts the voltage level of the node N21 from the voltage level VH to the voltage level VQ through capacitive coupling. At this time, there is a second voltage difference between the light-emitting signal PX1 and the voltage signal VC1.

During period P209, the control signal ST3 has a voltage level VH, so that the switches T204 and T211 are turned on to output the reference voltage signal VSS to the nodes N21 and N24. The control signal Q1 and the gate signal G1 have a voltage level VL, so that the switches T212 and T214 are turned off.

During period P210, clock signal HC1 has voltage level VH, so that capacitor C202 adjusts the voltage level of node N22 from voltage level VL to voltage level VH through capacitive coupling. Control signal P1 has voltage level VH, so that switch T213 is turned on to output reference voltage signal VREF to node N25, so that voltage signal VC1 has voltage level VR1. Capacitor C203 adjusts the voltage level of node N26 from voltage level V03 to voltage level V07 through capacitive coupling.

During period P211, the clock signal HC1, the control signals P1, Q1, ST1-ST3 and the gate signal G1 have a voltage level VL. At this time, the switches T201-T214 are turned off.

In some cases, in order to increase the contrast of the display panel and speed up the response time, a higher operating voltage is required for the light-emitting operation. However, at a fixed operating voltage level, the circuit components need to maintain a higher supply voltage level to maintain the voltage difference required for the pixel circuit to emit light, which increases the energy consumption of the integrated circuit.

Compared to the above, in some embodiments of the present disclosure, the pixel circuit 210 emits light in the periods P203-P206 and P208-P211 according to the voltage difference between the voltage signal VC1 and the light-emitting signal PX1, wherein the voltage difference has a first voltage difference in the period P203-P206, and has a second voltage difference in the period P208-P211, and the second voltage difference is approximately equal to the negative first voltage difference. In this way, under a variable operating voltage level, the circuit element can be supplied with a lower voltage level to maintain the voltage difference required for the pixel circuit 210 to emit light, so that the energy consumption of the integrated circuit is reduced.

Referring to FIG. 2A and FIG. 1B , the driving circuit 220 is an embodiment of the driving circuit 121. Arrow A1 represents the control of the pull-up circuit PU3 on the pull-down circuit 224, for example, the pull-up circuit PU3 provides a control signal ST3 to the pull-down circuit 224. Arrow A2 represents the control of the pull-up circuit PU3 on the pull-down circuit 225, for example, the pull-up circuit PU3 adjusts the voltage level of the node N22 by the control signal ST3.

FIG. 3A is a schematic diagram of a display 300A corresponding to the display 100A shown in FIG. 1A according to an embodiment of the present invention. As shown in FIG. 3A , the display 300A includes a driver circuit 320 and a pixel circuit 310. In some embodiments, the driver circuit 320 is used to output a voltage signal VC3 and a gate signal G1, and the pixel circuit 310 is used to perform a light-emitting operation according to the voltage signal VC3 and the gate signal G1.

Referring to FIG. 3A and FIG. 2A , display 300A is a variation of display 200A. The numbering scheme of FIG. 3A is similar to the numbering scheme of FIG. 2A . For the sake of brevity, the following discussion will focus on the differences between FIG. 3A and FIG. 2A rather than the similarities.

Compared to the display 200A, the display 300A includes a driver circuit 320, a pixel circuit 310, and a pull-up circuit 323 instead of the driver circuit 220, the pixel circuit 210, and the pull-up circuit 223. In some embodiments, the pull-up circuit 323 and the pull-down circuit 225 are used to control the node N35. The pixel circuit 310 is used to receive the voltage signal VC3.

As shown in FIG. 3A , the pull-up circuit 323 includes a switch T312. The first end of the switch T312 is used to receive the voltage signal VS1. The second end of the switch T312 is used to output the voltage signal VC3 at the node N35. The control end of the switch T312 is used to receive the control signal Q2. The pixel circuit 310 includes a switch T314 and a capacitor C303. The first end of the switch T314 is used to receive the voltage signal SL1. The second end of the switch T314 is coupled to the node N36. The control end of the switch T314 is coupled to the node N24. The first end of the capacitor C203 is coupled to the node N36. The second end of the capacitor C303 is coupled to the node N35.

FIG. 3B is a timing diagram 300B of the operation of the display 300A according to an embodiment of the present invention. As shown in FIG. 3B, the timing diagram 300B includes sequentially and continuously arranged periods P301-P311. During the periods P301-P311, the control signal Q2 operates between the voltage levels VQ, VH and VL.

Please refer to FIG. 3B and FIG. 2D , the operation of the clock signals HC1, CK1 and CK2, the gate signal G1, the control signal Q1, the voltage signal VC3 and the light-emitting signal PX1 during the period P301 to P311 is similar to the operation during the period P201 to P211. Therefore, some descriptions are not repeated.

During period P302, the control signal Q2 has a voltage level VH, so that the switch T312 is turned on to provide the voltage signal VS1 to the node N35. The voltage signal VC3 has a voltage level V01.

During period P304, the control signal Q2 has a voltage level VL, so that the switch T312 is turned off to stop providing the voltage signal VS1 to the node N35.

During period P307, the control signal Q2 has a voltage level VH, so that the switch T312 is turned on to provide the voltage signal VS1 to the node N35. The voltage signal VC3 has a voltage level V02.

During period P309, the control signal Q2 has a voltage level VL, causing the switch T312 to be turned off to stop providing the voltage signal VS1 to the node N35.

The operation of the control signal Q2 during the periods P301, P305, P306, P310 and P311 is similar to the operation of the control signal Q1 during the periods P301, P305, P306, P310 and P311. Therefore, part of the description will not be repeated.

Please refer to FIG. 3A and FIG. 1B. In some embodiments, the control signal Q2 is the control signal Q1 from other driving circuits. For example, the driving circuit 320 corresponds to the driving circuit 121. The control signal Q2 of the driving circuit 320 is the control signal Q1 from the driving circuit 122. In some variations, the control signal Q2 can be adjusted from the voltage level VL to the voltage level VH at any time during the periods P302 and P307.

In the embodiment shown in FIG. 3B , after the gate signal G1 changes from the voltage level VH to the voltage level VL, the control signal Q2 still has the voltage level VQ to extend the charging time of the pixel circuit 310.

FIG. 4A is a schematic diagram of a display 400A corresponding to the display 100A shown in FIG. 1A according to an embodiment of the present invention. As shown in FIG. 4A , the display 400A includes a driver circuit 420 and a pixel circuit 410. In some embodiments, the driver circuit 420 is used to output a voltage signal VC4 and a gate signal G1, and the pixel circuit 410 is used to perform a light-emitting operation according to the voltage signal VC4 and the gate signal G1.

As shown in FIG. 4A , the driving circuit 420 includes a pull-up control circuit 421, pull-up circuits 422 and 423, pull-down circuits 424 and 425, and a capacitor C401. In some embodiments, the pull-up control circuit 421 is used to control the voltage level of the node N41. The pull-up circuit 422 is used to control the voltage level of the nodes N43 and N44 according to the voltage level of the node N41. The pull-up circuit 423 is used to control the voltage level of the node N45. The pull-down circuit 424 is used to control the voltage level of the nodes N41~N44 and N47. The pull-down circuit 425 is used to control the voltage level of the node N45.

As shown in FIG. 4A , the pull-up control circuit 421 includes a switch T401. The pull-up circuit 422 includes switches T402 and T403. The pull-up circuit 423 includes a switch T412. The pull-down circuit 424 includes circuits 431 and 432 and switches T404 and T405. The circuit 431 includes switches T421 to T429. The circuit 432 includes switches T431 to T439. The pull-down circuit 425 includes a switch T413.

As shown in FIG. 4A , the first end and the control end of the switch T401 are used to receive the control signal ST4. The second end of the switch T401, the control end of each of T402 and T403, and the first end of each of T404, T405, T427, and T437 are coupled to the node N41. The first end of each of the switches T402 and T403 is used to receive the clock signal HC1. The second end of the switch T402 and the first end of each of the switches T428 and T438 are coupled to the node N43. The second end of the switch T403 and the first end of each of the switches T429 and T439 are coupled to the node N44. The second end of each of the switches T404, T405, T423~T428, and T433~T438 is used to receive the reference voltage signal VSS. The control end of the switch T404 is used to receive the control signal ST5. The control end of the switch T405 is used to receive the control signal ST0. The first end of the capacitor C401 is coupled to the node N41. The second end of the capacitor C401 is coupled to the node N44.

The first end and control end of switch T421 and the first end of switch T422 are used to receive the clock signal LC1. The second end of switch T421, the control end of switch T422 and the first end of each of switches T423 and T425 are coupled to node N48. The second end of switch T422, the first ends of switches T424 and T426 and the control end of each of switches T427~T429 are coupled to node N42. The control end of each of switches T423 and T424 is used to receive the control signal Q42. The control end of each of switches T425 and T426 is used to receive the control signal Q1. The second end of each of switches T429 and T439 is used to receive the reference voltage signal VSSG.

The first end and control end of switch T431 and the first end of switch T432 are used to receive the clock signal LC2. The second end of switch T431, the control end of switch T432 and the first end of each of switches T433 and T435 are coupled to node N49. The second end of switch T432, the first ends of switches T434 and T436 and the control end of each of switches T437~T439 are coupled to node N47. The control end of each of switches T433 and T434 is used to receive the control signal Q42. The control end of each of switches T435 and T436 is used to receive the control signal Q1.

The first end of the switch T412 is used to receive the voltage signal VS1. The second end of the switch T412 and the first end of the switch T413 are coupled to the node N45. The control end of the switch T412 is used to receive the control signal Q43. The second end of the switch T413 is used to receive the reference voltage signal VREF. The control end of the switch T413 is used to receive the control signal P42.

As shown in FIG. 4A , the pixel circuit 410 includes a switch T414 and a capacitor C403. The first end of the switch T414 is used to receive the voltage signal SL1. The second end of the switch T414 is coupled to the node N46. The control end of the switch T414 is coupled to the node N44. The first end of the capacitor C403 is coupled to the node N46. The second end of the capacitor C403 is coupled to the node N45.

Referring to FIG. 4A and FIG. 1A, pixel circuit 410 is an embodiment of a pixel circuit in pixel circuit row PCR1. Driver circuit 420 is an embodiment of driver circuit DC1. Voltage signal VC4 is an embodiment of voltage signal S1. Referring to FIG. 4A and FIG. 1B, driver circuit 420 is an embodiment of driver circuit 121. Pull-up control circuit 421 is an embodiment of pull-up control circuit PUC1. Pull-up circuit 422 is an embodiment of pull-up circuit PU1. Pull-up circuit 423 is an embodiment of pull-up circuit PU2. Pull-down circuit 424 is an embodiment of pull-down circuit PD1. Pull-down circuit 425 is an embodiment of pull-down circuit PD2.

When the clock signal LC1 has a voltage level VH, the switch T421 is turned on. The node N48 has a voltage level VH, which turns on the switch T422. At this time, the node N42 has a voltage level VH, which turns on the switches T427 and T429 to output the reference voltage signals VSS and VSSG to the nodes N41 and N44, respectively. The control signals P41, Q1, and G1 have voltage levels VQ, VH, and VL, respectively.

When the control signal Q1 has a voltage level VH, the switch T426 is turned on to output the reference voltage signal VSS to the node N42, so that the control signal P41 has a voltage level VL.

Clock signals LC1 and LC2 alternately have voltage levels VH, so that circuits 431 and 432 are alternately activated. Circuit 432 operates according to clock signal LC2 in a manner similar to circuit 431 operating according to clock signal LC1, and the switches of circuit 431 are coupled to each other in a manner similar to circuit 432. Therefore, some descriptions are not repeated.

FIG. 4B is a timing diagram 400B of the operation of the display 400A according to an embodiment of the present invention. As shown in FIG. 4B, the timing diagram 400B includes sequentially and continuously arranged periods P401 to P406. During the periods P401 to P406, the control signal P42 operates between the voltage levels VH and VL. The voltage signal VC4 operates between the voltage levels V01 and VR1.

Referring to FIG. 4B and FIG. 3B , the operation of the clock signal HC1, the gate signal G1, the control signals Q1 and Q2, and the light-emitting signal PX1 during the period P401 to P406 is similar to the operation during the period P301 to P306. Therefore, some descriptions are not repeated.

During period P404, control signal P42 has voltage level VH, so that switch T413 is turned on to provide reference voltage signal VREF to node N45. At this time, voltage signal VC4 has voltage level VR1. In this way, node N45 can be maintained at voltage level V01 for a longer time, so that the charging time of node N46 is increased.

FIG. 5A is a schematic diagram of a display 500A corresponding to the display 100A shown in FIG. 1A according to an embodiment of the present invention. As shown in FIG. 5A , the display 500A includes a driver circuit 520 and a pixel circuit 510. In some embodiments, the driver circuit 520 is used to output a voltage signal VC5 and a gate signal G1, and the pixel circuit 510 is used to perform a light-emitting operation according to the voltage signal VC5 and the gate signal G1.

Referring to FIG. 5A and FIG. 4A , display 500A is a variation of display 400A. The numbering scheme of FIG. 5A is similar to the numbering scheme of FIG. 4A . For the sake of brevity, the following discussion will focus on the differences between FIG. 5A and FIG. 4A rather than the similarities.

Compared to display 400A, display 500A includes a driver circuit 520 and a pixel circuit 510 instead of driver circuit 420 and pixel circuit 410. Driver circuit 520 includes a pull-up circuit 523 and a pull-down circuit 525 instead of pull-up circuit 423 and pull-down circuit 425. Pull-up circuit 523 includes switches T512 and T514. Pull-down circuit 525 includes switch T513. In some embodiments, pull-up circuit 523 and pull-down circuit 525 are used to control node N55. Pixel circuit 510 is used to receive voltage signal VC5.

As shown in FIG. 5A , the first end of each of the switches T512 and T514 is used to receive the voltage signal VS1. The second end of each of the switches T512 and T514 and the first end of the switch T513 are used to output the voltage signal VC5 at the node N55. The control end of the switch T512 and the control end of the switch T514 are used to receive the control signals Q52 and Q54, respectively. The second end and the control end of the switch T513 are used to receive the reference voltage signal VREF and the control signal P54, respectively.

As shown in FIG. 5A , the pixel circuit 510 includes a switch T514 and a capacitor C503. The first end of the switch T514 is used to receive the voltage signal SL1. The second end of the switch T514 is coupled to the node N56. The control end of the switch T514 is coupled to the node N44. The first end of the capacitor C503 is coupled to the node N56. The second end of the capacitor C503 is coupled to the node N55.

FIG. 5B is a timing diagram 500B of the operation of the display 500A according to one embodiment of the present invention. As shown in FIG. 5B, the timing diagram 500B includes sequentially and continuously arranged periods P500 to P506. During the periods P500 to P506, the control signal P54 operates between the voltage levels VH and VL. The control signals Q52 to Q54 operate between the voltage levels VQ, VH and VL. The voltage signal VC5 operates between the voltage levels V01 and VR1.

Please refer to Figure 5B and Figure 4B. The operation of the clock signal HC1, the gate signal G1 and the control signal Q1 during the period P502~P506 is similar to the operation during the period P402~P406. Therefore, some descriptions will not be repeated.

During period P501, control signal Q54 has a voltage level VH, causing switch T514 to be turned on to provide voltage signal VS1 to node N55. Voltage signal VC5 has a voltage level V01.

During period P502, the control signal Q52 has a voltage level VH, causing the switch T512 to be turned on to provide the voltage signal VS1 to the node N55. The voltage signal VC5 has a voltage level V01.

During period P505, the control signal P54 has a voltage level VH, causing the switch T513 to be turned on to provide the reference voltage signal VREF to the node N55. At this time, the voltage signal VC5 has a voltage level VR1.

In some variations, the control signal Q54 can be adjusted from the voltage level VL to the voltage level VH at any time during the period P501. The control signal Q52 can be adjusted from the voltage level VL to the voltage level VH at any time during the period P502. The control signal P54 can be adjusted from the voltage level VL to the voltage level VH at any time during the period P504.

In the embodiment shown in FIG. 5B , before the gate signal G1 changes from the voltage level VL to the voltage level VH, the control signal Q54 still has the voltage level VQ to extend the charging time of the pixel circuit 510. After the gate signal G1 changes from the voltage level VH to the voltage level VL, the control signal Q52 still has the voltage level VQ to extend the charging time of the pixel circuit 510. After the control signal Q52 changes from the voltage level VQ to the voltage level VL, the control signal P54 has the voltage level VH to extend the charging time of the pixel circuit 510.

FIG. 6A is a schematic diagram of a driving circuit 620 corresponding to the driving circuit 220 shown in FIG. 2A according to an embodiment of the present invention. As shown in FIG. 6A , in some embodiments, the driving circuit 620 is used to output voltage signals VC1 and VC6 and a gate signal G1.

Referring to FIG. 6A and FIG. 2A , the driver circuit 620 is a variation of the driver circuit 220 . The numbering scheme of FIG. 6A is similar to the numbering scheme of FIG. 2A . For the sake of brevity, the following discussion will focus on the differences between FIG. 6A and FIG. 2A rather than the similarities.

Compared to the driving circuit 220, the driving circuit 620 includes a pull-up circuit 623 and a pull-down circuit 625 instead of the pull-up circuit 223 and the pull-down circuit 225. The pull-up circuit 623 includes a switch T212 and a switch T612. The pull-down circuit 625 includes a switch T213 and a switch T613. In some embodiments, the pull-up circuit 623 and the pull-down circuit 625 are used to control the node N25 and the node N65.

As shown in FIG. 6A , the first end of the switch T612 is used to receive the voltage signal VS6. The second end of the switch T612 and the first end of the switch T613 are used to output the voltage signal VC6 at the node N65. The control end of the switch T612 is used to receive the control signal Q1 at the node N21. The second end of the switch T613 is used to receive the reference voltage signal VREF. The control end of the switch T613 is used to receive the control signal P1 at the node N22.

In some embodiments, when the voltage signal VS1 has a voltage level V01, the voltage signal VS6 has a voltage level V02. When the voltage signal VS1 has a voltage level V02, the voltage signal VS6 has a voltage level V01.

FIG. 6B is a schematic diagram of a display 600A showing further details of the display 100A shown in FIG. 1A according to one embodiment of the present invention. As shown in FIG. 6B , the display 600A includes a display device 610 and drive circuits 620A to 620D. In some embodiments, each of the drive circuits 620A and 620B is used to output voltage signals C61 and C62. Each of the drive circuits 620C and 620D is used to output voltage signals C63 and C64.

As shown in FIG. 6B , in the X direction, the driver circuits 620A and 620C are located on a first side of the display device 610, such as the left side. The driver circuits 620B and 620D are located on a second side of the display device 610, such as the right side. In some embodiments, the display device 610 is at least used to perform a light-emitting operation according to the voltage signals C61-C64. In various embodiments, various numbers of driver circuits can provide various numbers of voltage signals to the display device 610.

As shown in FIG. 6B , the display device 610 includes pixel circuits PC21 to PC24 and PC31 to PC34. In the X direction, the pixel circuits PC21 to PC24 are arranged in sequence, and the pixel circuits PC31 to PC34 are arranged in sequence. In the Y direction, the pixel circuits PC21 to PC24 are located above the pixel circuits PC31 to PC34. Each of the pixel circuits PC21 to PC24 is coupled in series with each other. Each of the pixel circuits PC31 to PC34 is coupled in series with each other. Each of the pixel circuits PC21 and PC23 is used to perform a light-emitting operation according to a voltage signal C61. Each of the pixel circuits PC22 and PC24 is used to perform a light-emitting operation according to a voltage signal C62. Each of the pixel circuits PC31 and PC33 is used to perform a light-emitting operation according to a voltage signal C63. Each of the pixel circuits PC32 and PC34 is used to perform a light-emitting operation according to the voltage signal C64. In various embodiments, the display device 610 may include various numbers of pixel circuits in the X direction and the Y direction, respectively.

As shown in FIG. 6B , the driving circuit 620A includes switches T621 to T624. The driving circuit 620B includes switches T625 to T628. In some embodiments, the control end of each of the switches T621, T623, T625, and T627 is used to receive the control signal Q1. The first end of each of the switches T621 and T627 is used to receive the voltage signal VS1. The first end of each of the switches T623 and T625 is used to receive the voltage signal VS6. The second end of each of the switches T621 and T625 and the first end of each of the switches T622 and T626 are used to output the voltage signal C61 at the node N61. The second end of each of the switches T623 and T627 and the first end of each of the switches T624 and T628 are used to output the voltage signal C62 at the node N62. The control end of each of the switches T622, T624, T626 and T628 is used to receive the control signal P1. The second end of each of the switches T622, T624, T626 and T628 is used to receive the reference voltage signal VREF.

Referring to FIG. 6B and FIG. 6A , each of the driving circuits 620A-620D can be implemented by the driving circuit 620. For example, the voltage signals C61 and C63 correspond to the voltage signal VC1. The voltage signals C62 and C64 correspond to the voltage signal VC6. The switches T621 and T625 correspond to the switch T212. The switches T622 and T626 correspond to the switch T213. The switches T623 and T627 correspond to the switch T612. The switches T624 and T628 correspond to the switch T613.

Referring to FIG. 6B and FIG. 1A , display device 610 is an embodiment of display device 110. Pixel circuits PC21 to PC24 are embodiments of pixel circuits in one of pixel circuit rows PCR1 to PCR5. Pixel circuits PC31 to PC34 are embodiments of pixel circuits in another of pixel circuit rows PCR1 to PCR5. For example, pixel circuits PC21 to PC24 correspond to pixel circuits in pixel circuit row PCR2, and pixel circuits PC31 to PC34 correspond to pixel circuits in pixel circuit row PCR3. Voltage signals C61 and C62 are embodiments of one of voltage signals S1 to S5. Voltage signals C63 and C64 are embodiments of another of voltage signals S1 to S5. For example, voltage signals C61 and C62 correspond to voltage signal S2, and voltage signals C63 and C64 correspond to voltage signal S3. Driver circuits 620A and 620B are embodiments of one of driver circuits DC1 to DC5. Driver circuits 620C and 620D are embodiments of another of driver circuits DC1 to DC5. For example, driver circuits 620A and 620B correspond to driver circuit DC2. Driver circuits 620C and 620D correspond to driver circuit DC3.

The embodiment shown in FIG. 6B is a one-to-one dual-side dual-driver panel design. In this way, the circuit load can be reduced and the uniformity and stability of the voltage signal can be increased.

FIG. 7A is a schematic diagram of a driving circuit 720 corresponding to the driving circuit 220 shown in FIG. 2A according to an embodiment of the present invention. In some embodiments, the driving circuit 720 is used to output a voltage signal VC1 and a gate signal G1. The driving circuit 720 is used to output a voltage signal VC6 and a gate signal G1.

Referring to FIG. 7A and FIG. 6A , driver circuit 720 is a variation of driver circuit 620 . The numbering scheme of FIG. 7A is similar to the numbering scheme of FIG. 6A . For the sake of brevity, the following discussion will focus on the differences between FIG. 7A and FIG. 6A rather than the similarities.

Compared to the driving circuit 620, in some embodiments, the pull-up circuit 623 of the driving circuit 720 includes the switch T212 and does not include the switch T612. The pull-down circuit 625 includes the switch T213 and does not include the switch T613. For example, the driving circuit 720A shown in FIG. 7B. In some embodiments, the pull-up circuit 623 of the driving circuit 720 includes the switch T612 and does not include the switch T212. The pull-down circuit 625 includes the switch T613 and does not include the switch T213. For example, the driving circuit 720B shown in FIG. 7B.

FIG. 7B is a schematic diagram of a display 700A showing further details of the display 100A shown in FIG. 1A according to one embodiment of the present invention. As shown in FIG. 7B , the display 700A includes a display device 610 and drive circuits 720A to 720D. In some embodiments, the drive circuit 720A is used to output a voltage signal C61. The drive circuit 720B is used to output a voltage signal C62. The drive circuit 720C is used to output a voltage signal C63. The drive circuit 720D is used to output a voltage signal C64.

Referring to FIG. 7B and FIG. 6B , display 700A is a variation of display 600A. The numbering scheme of FIG. 7B is similar to the numbering scheme of FIG. 6B . For the sake of brevity, the following discussion will focus on the differences between FIG. 7B and FIG. 6B rather than the similarities.

As shown in FIG. 7B , in the X direction, the driving circuits 720A and 720C are located on a first side of the display device 610, such as the left side, and the driving circuits 720B and 720D are located on a second side of the display device 610, such as the right side.

As shown in FIG. 7B , the driving circuit 720A includes switches T721 and T722. The driving circuit 720B includes switches T723 and T724. In some embodiments, the control end of each of the switches T721 and T723 is used to receive the control signal Q1. The first end of the switch T721 is used to receive the voltage signal VS1. The first end of the switch T723 is used to receive the voltage signal VS6. The second end of the switch T721 and the first end of the switch T722 are used to output the voltage signal C61 at the node N71. The second end of the switch T723 and the first end of the switch T724 are used to output the voltage signal C62 at the node N72. The control end of each of the switches T722 and T724 is used to receive the control signal P1. A second end of each of the switches T722 and T724 is used to receive a reference voltage signal VREF.

Figure 7B shows a one-to-one dual-side single-driver panel design. This can reduce the number of switches and the space occupied by the driver circuit.

FIG. 8A is a schematic diagram of a driving circuit 820 corresponding to the driving circuit 220 shown in FIG. 2A according to an embodiment of the present invention. In some embodiments, the driving circuit 820 is used to output a voltage signal VC1 and a gate signal G1. The driving circuit 820 is used to output a voltage signal VC6 and a gate signal G1. The driving circuit 820 includes a pull-up circuit 823 and a pull-down circuit 825.

FIG. 8B is a schematic diagram of a display 800A showing further details of the display 100A shown in FIG. 1A according to one embodiment of the present invention. As shown in FIG. 8B , the display 800A includes a display device 810 and driver circuits 820A to 820F. In some embodiments, driver circuits 820E and 820F are used to output a voltage signal C63. Driver circuits 820C and 820D are used to output a voltage signal C62 at a node N82. Driver circuits 820A and 820B are used to output a voltage signal C61 at a node N81.

Referring to FIG. 8B and FIG. 6B , display 800A is a variation of display 600A. The numbering scheme of FIG. 8B is similar to the numbering scheme of FIG. 6B . For the sake of brevity, the following discussion will focus on the differences between FIG. 8B and FIG. 6B rather than the similarities.

As shown in FIG. 8B , in the X direction, the driving circuits 820A, 820C, and 820E are located on a first side of the display device 810, such as the left side. The driving circuits 820B, 820D, and 820F are located on a second side of the display device 810, such as the right side. In some embodiments, the display device 810 is at least used to perform a light-emitting operation according to the voltage signals C61-C63. In various embodiments, various numbers of driving circuits can provide various numbers of voltage signals to the display device 810.

As shown in FIG. 8B , the display device 810 includes pixel circuits PC21 to PC24, PC31 to PC34, and PC41 to PC44. In the X direction, the pixel circuits PC21 to PC24 are arranged in sequence, and the pixel circuits PC31 to PC34 are arranged in sequence, and the pixel circuits PC41 to PC44 are arranged in sequence. In the Y direction, the pixel circuits PC21 to PC24 are located above the pixel circuits PC31 to PC34, and the pixel circuits PC31 to PC34 are located above the pixel circuits PC41 to PC44. Each of the pixel circuits PC21 to PC24 is coupled in series with each other. Each of the pixel circuits PC31 to PC34 is coupled in series with each other. Each of the pixel circuits PC41 to PC44 is coupled in series with each other. Each of the pixel circuits PC21 and PC23 is used to perform a light-emitting operation according to the voltage signal C63. Each of the pixel circuits PC22, PC24, PC32 and PC34 is used to perform a light emitting operation according to the voltage signal C62. Each of the pixel circuits PC31, PC33, PC41 and PC43 is used to perform a light emitting operation according to the voltage signal C61. In various embodiments, the display device 810 may include various numbers of pixel circuits in the X direction and the Y direction, respectively.

As shown in FIG. 8B , the driving circuit 820A includes switches T821 and T822. The driving circuit 820B includes switches T825 and T826. The driving circuit 820C includes switches T823 and T824. The driving circuit 820D includes switches T827 and T828.

Figure 8B shows a one-to-two panel design with double-side and double-drivers. This can reduce the number of switches and the margin occupied by the driver circuit, while maximizing the opening rate.

Although the contents of this disclosure have been disclosed as above by way of embodiments, they are not intended to limit the contents of this disclosure. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the contents of this disclosure. Therefore, the protection scope of the contents of this disclosure shall be subject to the scope defined by the attached patent application.

100A, 200A, 300A, 400A, 500A, 600A, 700A, 800A: Display 110, 610, 810: Display device 120, 100B: Driver device PCR1~PCR5: Pixel circuit array DC1~DC5, 121, 122, 220, 320, 420, 520, 620, 620A~620D, 720, 720A~720D, 820, 820A~820F: Driver circuit 210, 310, 410, 510, PC21~PC24, PC31~PC34, PC41~PC44: Pixel circuit 130, 200B, 200C, 431, 432: Circuit PUC1, PUC2, 221, 421: Pull-up control circuit PU1, PU2, PU3, PU4, 222, 223, 323, 422, 423, 523, 623, 823: Pull-up circuit PD1, PD2, PD3, PD4, 224, 225, 424, 425, 525, 625, 825: Pull-down circuit C201~C203, C303, C401, C403, C503: Capacitor S1~S5, V1, V2, VC1~VC6, VS1, VS2, SL1, C61~C64: Voltage signal G1, G2: Gate signal ST0~ST5, P1, Q1, Q2, P41, P42, Q42, P54, Q52~Q54: control signal HC1, CK1, CK2, LC1, LC2: clock signal PX1: light signal VSS, VSSG, VREF: reference voltage signal N21~N28, N35, N36, N41~N49, N55, N56, N61, N62, N65, N71, N72, N81, N82: node T201~T214, T221~T224, T312, T314, T401~T405, T412~T414, T421~T429, T431~T439, T512~T514, T612, T613, T621~T628, T721~T724, T821~T828: switch A1, A2: arrow 200D, 300B, 400B, 500B: timing diagram VH, VL, VQ, V01~V07, VR1: voltage level P201~P211, P301~P311, P401~P406, P500~P506: period X, Y: direction

FIG. 1A is a schematic diagram of a display according to one embodiment of the present invention. FIG. 1B is a schematic diagram of a driving device according to one embodiment of the present invention. FIG. 2A to FIG. 5A are schematic diagrams of a display corresponding to the display shown in FIG. 1A according to one embodiment of the present invention. FIG. 2B and FIG. 2C are circuit diagrams of a circuit according to one embodiment of the present invention. FIG. 2D, FIG. 3B, FIG. 4B, and FIG. 5B are timing diagrams of the operation of a display according to one embodiment of the present invention. FIG. 6A, FIG. 7A, and FIG. 8A are schematic diagrams of a driving circuit corresponding to the driving circuit shown in FIG. 2A according to one embodiment of the present invention. Figures 6B, 7B and 8B are schematic diagrams of displays showing further details of the display shown in Figure 1A according to one embodiment of the present invention.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

200A: Display

210: Pixel circuit

220:Drive circuit

221: Pull-up control circuit

222, 223: Pull-up circuit

224, 225: Pull-down circuit

C201~C203: Capacitor

VC1, VS1, SL1: voltage signal

G1: Gate signal

ST0~ST3, P1, Q1: control signal

HC1: Clock signal

PX1: Luminous signal

VSS, VSSG, VREF: reference voltage signal

N21~N26: Node

T201~T214: switch

Claims (8)

A display device includes: a display device including a first pixel circuit, the first pixel circuit is used to adjust a first voltage difference from a first voltage difference value to a second voltage difference value according to a first voltage signal, and emit light according to the first voltage difference; a first driving device including: a first switch, used to provide a second voltage signal to a first node to output the first voltage signal; a second switch, used to provide a first reference voltage signal to the The first node outputs the first voltage signal, wherein when the first voltage difference has the first voltage difference value, the second voltage signal has a first voltage level, and when the first voltage difference has the second voltage difference value, the second voltage signal has a second voltage level, the first reference voltage signal has a third voltage level between the first voltage level and the second voltage level, and the second voltage difference value is approximately equal to the negative first voltage difference value. The display as described in claim 1 further comprises: a third switch, a control end of the third switch is coupled to a control end of the first switch, and a first end of the third switch is coupled to a control end of the second switch. A display as described in claim 1, wherein the second switch is used to provide the first reference voltage signal to the first node according to a control signal, and the first pixel circuit is further used to emit light according to a gate signal, when the gate signal is adjusted from a third voltage level to a fourth voltage level, the control signal is maintained at the fourth voltage level, and when the gate signal is maintained at the fourth voltage level, the control signal is adjusted from the fourth voltage level to the third voltage level. The display as described in claim 1 further comprises: a third switch for providing the second voltage signal to the first node according to a first control signal, wherein the first switch is used to provide the second voltage signal to the first node according to a second control signal, when the first control signal has a third voltage level, the second control signal has a fourth voltage level, when the first control signal has a fifth voltage level, the second control signal has the third voltage level, when the first control signal has the fourth voltage level, the second control signal has the fifth voltage level, and the third voltage level is greater than the fourth voltage level and less than the fifth voltage level. A display as described in claim 1, wherein the display device further includes a second pixel circuit, the second pixel circuit is used to emit light according to a third voltage signal; the first driving device further includes: a third switch, used to provide a fourth voltage signal to a second node to output the third voltage signal; a fourth switch, used to provide the first reference voltage signal to the second node to output the third voltage signal, when the second voltage signal has the first voltage level, the fourth voltage signal has the second voltage level, and when the second voltage signal has the second voltage level, the fourth voltage signal has the first voltage level. The display as described in claim 5 further comprises: a second driving device for providing the first voltage signal to the first pixel circuit and for providing the third voltage signal to the second pixel circuit, wherein the first driving device, the first pixel circuit, the second pixel circuit and the second driving device are arranged in sequence. A display as described in claim 1, wherein the display device further comprises a second pixel circuit, the second pixel circuit is used to emit light according to a third voltage signal, the display further comprises a second driving device, the second driving device is used to generate the third voltage signal according to a fourth voltage signal and the first reference voltage signal, when the second voltage signal has the first voltage level, the fourth voltage signal has the second voltage level, and when the second voltage signal has the second voltage level, the fourth voltage signal has the first voltage level, and the first driving device, the first pixel circuit, the second pixel circuit and the second driving device are arranged in sequence. The display device as claimed in claim 1, wherein the display device further comprises a second pixel circuit, the second pixel circuit is used to emit light according to a third voltage signal; the display device further comprises a second driving device, the second driving device is used to generate the third voltage signal according to a fourth voltage signal and the first reference voltage signal, when the second voltage signal has the first voltage level, the fourth voltage signal has The second voltage level, and when the second voltage signal has the second voltage level, the fourth voltage signal has the first voltage level, the first driving device, the first pixel circuit, the second pixel circuit and the second driving device are arranged in sequence in a first direction, and the first pixel circuit and the second pixel circuit are arranged in sequence in a second direction, and the first direction is different from the second direction.

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