TWI853179B - Stacked oled microdisplay with low-voltage silicon backplane - Google Patents

Stacked oled microdisplay with low-voltage silicon backplane Download PDF

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TWI853179B
TWI853179B TW110124008A TW110124008A TWI853179B TW I853179 B TWI853179 B TW I853179B TW 110124008 A TW110124008 A TW 110124008A TW 110124008 A TW110124008 A TW 110124008A TW I853179 B TWI853179 B TW I853179B
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oled
light
transistor
transistors
microdisplay
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TW202217785A (en
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約翰 哈默
傑佛瑞 史賓德勒
馬里納 E 康達科法
博恩德 里奇特
飛利浦 瓦騰伯格
捷爾德 邦克
烏韋 沃格爾
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美商Oled沃克斯有限責任公司
德商弗恩赫發展應用公司
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Abstract

A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the light emitting OLED stack has three or more OLED units between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane comprises at least two transistors with their channels connected in series between an external power source V DD, and the bottom electrode of the OLED stack. The light-emitting OLED stack preferably has a Vth of at least 7.5 V or more. The control circuit can include a protection circuit comprised of a p-n diode, preferably a bipolar junction transistor.

Description

具有低電壓矽背板之堆疊式有機發光二極體微顯示器Stacked organic light emitting diode microdisplay with low voltage silicon backplane

本申請案係關於OLED微顯示器,且更確切而言係關於具有低電壓矽背板之堆疊式OLED微顯示器。This application relates to an OLED microdisplay, and more specifically to a stacked OLED microdisplay with a low voltage silicon backplane.

通常,一微顯示器小於2英吋對角線(大約5 cm),乃至一超小顯示器大小小於0.25"對角線。在大多數情形下,微顯示器之解析度係高的且像素間距通常為5至15微米。首次在1990年代末投入商用時,微顯示器通常用於背面投影TV、頭戴式顯示器及數位相機取景器。近年來,如智慧型手錶等裝置已利用此等顯示器之高解析度及低功耗。預期接下來的幾年微顯示器會激增,其中全球市場之複合年增長率預計為20%。驅動此增長之潮流之一將係越來越多地採用近眼顯示器、擴增實境裝置及虛擬實境裝置,例如頭戴式顯示器(HMD)、抬頭顯示器(HUD)及電子取景器(EVF)。Typically, a microdisplay is less than 2 inches diagonal (about 5 cm), with an ultra-small display size less than 0.25" diagonal. In most cases, the resolution of microdisplays is high and the pixel pitch is typically 5 to 15 microns. When first commercialized in the late 1990s, microdisplays were commonly used in rear projection TVs, head-mounted displays, and digital camera viewfinders. In recent years, devices such as smart watches have taken advantage of the high resolution and low power consumption of these displays. Microdisplays are expected to proliferate over the next few years, with the global market expected to grow at a CAGR of 20%. One of the trends driving this growth will be the increasing adoption of near-eye displays, augmented reality devices, and virtual reality devices, such as head-mounted displays (HMDs), head-up displays (HUDs), and electronic viewfinders (EVFs).

存在兩個主要微顯示器類別。第一種係一投影微顯示器,其涉及投射至一表面上之一高倍放大影像。投影微顯示器之類型包含背面投影TV及緊湊資料投影機。第二種係一近眼顯示器(NED),其由透過一目鏡(例如,一虛擬實境頭戴機或攝錄影機取景器)觀察之一高倍放大虛擬影像組成。此等顯示器越來越多地用於用於HMD及HUD,尤其用於軍事及醫療行業中。There are two main categories of microdisplays. The first is a projection microdisplay, which involves projecting a highly magnified image onto a surface. Types of projection microdisplays include rear projection TV and compact data projectors. The second is a near-eye display (NED), which consists of a highly magnified virtual image viewed through an eyepiece (e.g., a virtual reality headset or camera viewfinder). These displays are increasingly used in HMDs and HUDs, especially in the military and medical industries.

兩種類型之微顯示器具備優於習用直觀式顯示器(例如,平板LCD)之顯著優點。與其他顯示器類型相比,微顯示器之優點包含能夠自一非常小輕量級源顯示器單元產生一大影像,使其容易整合至例如穿戴裝備等空間受限技術中;能夠形成大像素容量,從而執行高解析度及清晰度;且能夠達到更大功率效率。解析度及亮度越高且功耗越低,則微顯示器之品質越好。然而,微顯示器製造者所面臨之挑戰係生產成本相對高且需要高亮度及高對比度以及長操作壽命。Both types of microdisplays offer significant advantages over conventional intuitive displays such as flat-panel LCDs. Advantages of microdisplays over other display types include the ability to produce a large image from a very small, lightweight source display unit, making them easily integrated into space-constrained technologies such as wearables; the ability to create large pixel capacities, allowing for high resolution and clarity; and the ability to achieve greater power efficiency. The higher the resolution and brightness and the lower the power consumption, the better the quality of the microdisplay. However, the challenges facing microdisplay manufacturers are relatively high production costs and the need for high brightness and high contrast as well as long operating lifetimes.

微顯示器可透過各種顯示器技術製成,包含透過矽基液晶(LCoS)、液晶顯示器(LCD)、數位微鏡裝置(DMD)、數位光處理(DLP)製成;且最近透過微LED(發光二極體)及有機發光二極體(OLED)製成。Microdisplays can be made using a variety of display technologies, including liquid crystal on silicon (LCoS), liquid crystal display (LCD), digital micromirror device (DMD), digital light processing (DLP), and more recently, microLEDs (light emitting diodes) and organic light emitting diodes (OLEDs).

近年來LCD已佔領微顯示器市場。LCD技術之優勢在於高亮度、相對低成本及一相對簡單製造程序。LCD之使用已使裝置製造商能夠隨時間推移減小微顯示器組件之大小。LCD顯示器當前用於某些HMD、HUD、EVF、以及熱成像眼鏡與穿戴裝備中。然而,LCD微顯示器需要一光源或背光與用於調變光之一液晶陣列一起形成一影像。此技術存在限制,例如偏振、色彩空間、最大照度限制、LC溫度靈敏度、視角、LCD透射與消光比、系統限制尺寸及其他,此無法提供所有所期望效能特性。LCDs have dominated the microdisplay market in recent years. The advantages of LCD technology are high brightness, relatively low cost, and a relatively simple manufacturing process. The use of LCDs has enabled device manufacturers to reduce the size of microdisplay components over time. LCD displays are currently used in certain HMDs, HUDs, EVFs, and thermal imaging goggles and wearables. However, LCD microdisplays require a light source or backlight together with a liquid crystal array for modulating the light to form an image. This technology has limitations, such as polarization, color space, maximum illumination limitations, LC temperature sensitivity, viewing angles, LCD transmission and extinction ratios, system size limitations, and others, which do not provide all of the desired performance characteristics.

基於微LED技術之微顯示器可具備優於LCD微顯示器之優點,例如自發射、一較大色域、寬視角、較好對比度、較快再新率、較低功耗(與影像相關)及寬操作溫度範圍。當前,微LED微顯示器係基於標準LED所採用之一標準氮化鎵(GaN)晶圓。此方法能夠以一相對低價格提供不存在壽命問題之高照度顯示器裝置。通常,將標準GaN晶圓圖案化成微LED陣列。然後,藉由對微LED陣列與電晶體進行整合產生微LED顯示器。然而,由於個別微LED之間存在色彩及照度差異,因此此方法存在幾個製造憂慮,包含微LED單片地形成於電晶體之上、像素間隔、呈色及空間均勻性。Microdisplays based on microLED technology can have advantages over LCD microdisplays, such as self-emission, a larger color gamut, wide viewing angles, better contrast, faster refresh rates, lower power consumption (image related) and a wide operating temperature range. Currently, microLED microdisplays are based on a standard gallium nitride (GaN) wafer used for standard LEDs. This approach can provide high-illuminance display devices without lifetime issues at a relatively low price. Typically, a standard GaN wafer is patterned into a microLED array. The microLED display is then produced by integrating the microLED array with transistors. However, this approach presents several manufacturing concerns due to color and illumination variations between individual micro-LEDs, including monolithic formation of the micro-LEDs on transistors, pixel spacing, color rendering, and spatial uniformity.

OLED技術同樣具有針對微顯示器之微LED技術之諸多有吸引力特徵。其係自發光的,具有出色影像品質,與LCD或LCoS相比非常高效且具有一超高顯色度及寬色彩空間。自發光OLED裝置優於背光裝置(例如LCD)之重要優點在於,每一像素僅產生影像所需要之強度,而背光像素產生最大強度隨後吸收不需要光。此外,由於OLED層可真空沈積或直接塗佈於電晶體背板上,因此在電晶體之上形成一OLED比形成一微LED更容易且成本更低。另一方面,OLED所具有之照度及壽命可係有限的。OLED technology shares many of the attractive features of microLED technology for microdisplays. It is self-luminous, has excellent image quality, is very efficient compared to LCD or LCoS and has a very high color rendering and wide color space. An important advantage of self-luminous OLED devices over backlit devices such as LCDs is that each pixel produces only the intensity required for the image, while the backlight pixels produce maximum intensity and then absorb the unwanted light. In addition, since the OLED layers can be vacuum deposited or coated directly on the transistor backplane, it is easier and less expensive to form an OLED on top of the transistor than a microLED. On the other hand, OLEDs can have limited illumination and lifetime.

解決運動模糊問題對OLED微顯示器(其係取樣保持型顯示器)中之控制電路系統而言亦係重要的(參見https://www.blurbusters.com/faq/oled-motion-blur/;中2018年12月28的「Why Do Some OLEDs Have Motion Blur?」及https://www.soundandvision.com/content/motion-resolution-issue-oled-tvs中2015年1月15日的「Is Motion Resolution an Issue with OLED TVs」)。Resolving the motion blur problem is also important for the control circuitry in OLED microdisplays, which are sample-and-hold type displays (see “Why Do Some OLEDs Have Motion Blur?” at https://www.blurbusters.com/faq/oled-motion-blur/, December 28, 2018, and “Is Motion Resolution an Issue with OLED TVs” at https://www.soundandvision.com/content/motion-resolution-issue-oled-tvs, January 15, 2015).

減輕取樣保持所導致之運動模糊之唯一方式係縮短顯示一圖框之時間量。此可藉由使用額外再新(較高Hz)或經由再新之間的黑暗週期(閃爍)來實現。對於OLED微顯示器而言,最佳解決方案係藉由同時關斷整個作用區域或藉由一「捲動」技術「開閉」顯示影像,其中依序一次僅關斷顯示影像之一部分。「捲動」技術係較佳的。像素關斷時間非常短且遠低於人眼可覺察之臨限值以避免可感知的閃爍。在控制電路系統中包含一開閉電晶體,在透過一選擇線啟動該開閉電晶體時防止電流流過OLED且藉由將OLED像素「關斷」所期望時間週期來轉變發射,以此來實現此目的。換言之,開閉電晶體係一開關電晶體,原因在於其僅「接通」或「關斷」像素而不調節電壓或電流。然而,在一影像顯示時間(通常被稱為圖框時間)之一部分內關斷像素之此解決方案僅增大每當OLED「接通」時該OLED對經增大照度之需要,此乃因其係圖框內眼睛所感知到之平均照度。減小運動模糊之開閉可適用於為OLED堆疊供電之任何方法,例如電流控制或PWM。The only way to reduce the motion blur caused by sample-and-hold is to shorten the amount of time a frame is displayed. This can be done by using extra refreshes (higher Hz) or via dark periods between refreshes (flicker). For OLED microdisplays, the best solution is to "turn" the displayed image "on and off" by turning off the entire active area at the same time or by a "scrolling" technique where only a portion of the displayed image is turned off at a time in sequence. The "scrolling" technique is preferred. The pixel off time is very short and well below the threshold for the human eye to avoid perceptible flicker. This is accomplished by including a switch transistor in the control circuitry that, when activated via a select line, prevents current from flowing through the OLED and switches emission by turning the OLED pixel "off" for the desired time period. In other words, a switch transistor is a switch transistor in that it simply turns the pixel "on" or "off" without regulating voltage or current. However, this solution of turning the pixel off for a portion of an image display time (commonly referred to as the frame time) simply increases the need for increased illumination of the OLED each time it is "on" because this is the average illumination perceived by the eye within the frame. Switching to reduce motion blur can be applied to any method of powering the OLED stack, such as current control or PWM.

自成本及可製造性之角度看,利用矽背板之OLED微顯示器非常有吸引力。舉例而言,參見 Ali等人之「Recent advances in small molecule OLED-on-Silicon microdisplays」, Proc. of SPIE Vol. 7415 74150Q-1, 2006; Jang等人之J. Information Display, 20(1), 1-8 (2019); Fujii等人之4032ppi High-Resolution OLED Microdisplay」, SID 2018 DIGEST, p. 613;US2019/0259337;Pr ache, Displays, 22(2), 49 (2001); Vogel等人之2018 48 thEuropean Solid-State Device Research Conference, p. 90, Sept. 2018;及 Wartenberg等人之「High Frame-Rate 1" WUXGA OLED Microdisplay and Advanced Free-Form Optics for Ultra-Compact VR Headsets」, SID Proceedings, 49 (1),第40至5頁,514 (2018)。 OLED microdisplays using silicon backplanes are very attractive from a cost and manufacturability perspective. For example, see Ali et al., “Recent advances in small molecule OLED-on-Silicon microdisplays”, Proc. of SPIE Vol. 7415 74150Q-1, 2006; Jang et al., J. Information Display, 20(1), 1-8 (2019); Fujii et al., 4032ppi High-Resolution OLED Microdisplay”, SID 2018 DIGEST, p. 613; US2019/0259337; Prache , Displays, 22(2), 49 (2001); Vogel et al., 2018 48th European Solid-State Device Research Conference, p. 90, Sept. 2018; and Wartenberg et al., “High Frame-Rate 1" WUXGA OLED Microdisplay and Advanced Free-Form Optics for Ultra-Compact VR Headsets”, SID Proceedings, 49 (1), pp. 40–5, 514 (2018).

微顯示器需要非常高照度以在所有環境條件下皆有用,例如在陽光明亮之戶外。甚至在受控環境條件下,例如在VR谷歌中,需要非常高照度來形成一沉浸式視覺體驗。來自顯示器之非常高照度允許使用較低效率光學器件,該等較低效率光學器件較小、重量較輕且成本較低,從而產生更具競爭力之一頭戴機。當前,最先進OLED微顯示器不提供所期望之照度。Microdisplays require very high illumination to be useful in all environmental conditions, such as outdoors in bright sunlight. Even in controlled environmental conditions, such as in VR headsets, very high illumination is required to create an immersive visual experience. Very high illumination from the display allows the use of less efficient optics that are smaller, lighter, and less expensive, resulting in a more competitive headset. Currently, state-of-the-art OLED microdisplays do not provide the desired illumination.

舉例而言,串接OLED微顯示器之製造商之一新聞發佈闡述可能夠遞送2.5k尼特之全色彩產品,但承認5k尼特將係一更期望目標(參見https://www.kopin.com/kopin-to-showcase-latest-advances-in-its-lightning-oled-microdisplay-line-up-at-ces-2020/, dated Jan 7, 2020)。某些製造商提出應達到10k尼特或高於10k尼特之目標(參見https://hdguru.com/calibration-expert-is-10000-nits-of-brightness-enough/, dated Jul 26, 2018)。2020年6月20日之一最近新聞發佈(https://www.businesswire.com/news/home/20200630005205/en/Kopin-Announces-Breakthrough-ColorMax%E2%84%A2-Technology-Unparalleled-Color)闡述發射>1000尼特之一串接(2堆疊) OLED顯示器。亦宣佈,「預期透過將OLED沈積條件最佳化進一步提高亮度(>2000尼特)及色彩保真度。藉由包含用於增強輸出耦合效率之一結構,可在幾年內將OLED微顯示器之亮度增大至>5000尼特」。For example, a press release from one maker of tandem OLED microdisplays states that it may be possible to deliver full-color products at 2.5k nits, but acknowledges that 5k nits would be a more desirable goal (see https://www.kopin.com/kopin-to-showcase-latest-advances-in-its-lightning-oled-microdisplay-line-up-at-ces-2020/, dated Jan 7, 2020). Some manufacturers have proposed targets of 10k nits or more (see https://hdguru.com/calibration-expert-is-10000-nits-of-brightness-enough/, dated Jul 26, 2018). A recent press release on June 20, 2020 (https://www.businesswire.com/news/home/20200630005205/en/Kopin-Announces-Breakthrough-ColorMax%E2%84%A2-Technology-Unparalleled-Color) describes a tandem (2-stacked) OLED display emitting >1000 nits. It was also announced that "further improvements in brightness (>2000 nits) and color fidelity are expected by optimizing OLED deposition conditions. By including a structure for enhanced output coupling efficiency, the brightness of OLED microdisplays could be increased to >5000 nits within a few years."

增大OLED裝置發射之光總量之一個解決方案係將多個OLED單元堆疊於彼此頂部上,因此自該堆疊發射之總光係每一個別單元發射之光之和。然而,雖然自此等OLED堆疊發射之總光基於個別OLED發光單元之總數目增加,但驅動OLED堆疊所需之電壓亦基於驅動每一獨立OLED單元之電壓增加。舉例而言,若在一給定電流下一發光OLED單元需要3V來產生250尼特,則在相同電流下兩個此單元之一堆疊將需要6V遞送500尼特,3單元之一堆疊將需要9V來遞送750尼特,以此類推。One solution to increasing the total amount of light emitted by an OLED device is to stack multiple OLED cells on top of each other so that the total light emitted from the stack is the sum of the light emitted by each individual cell. However, while the total light emitted from such an OLED stack increases based on the total number of individual OLED light-emitting cells, the voltage required to drive the OLED stack also increases based on the voltage required to drive each individual OLED cell. For example, if a single light-emitting OLED cell requires 3V to produce 250 nits at a given current, then a stack of two such cells at the same current will require 6V to deliver 500 nits, a stack of 3 cells will require 9V to deliver 750 nits, and so on.

OLED堆疊係眾所周知的;舉例而言,US7273663、US9379346、US9741957、US 9281487及US2020/0013978全部皆闡述發光OLED單元之多個堆疊之OLED堆疊,每一OLED單元由中間連接層或電荷產生層分隔開。 Springer等人的Optics Express, 24 (24), 28131 (2016)報告具有2個及3個發光單元之OLED堆疊,其中每一單元具有一不同色彩。已報告具有多達六個發光單元之OLED堆疊(2016年5月23日至27日加利福尼亞州舊金山SID Display Week 2016中Spindler等人的「High Brightness OLED Lighting」)。 OLED stacks are well known; for example, US7273663, US9379346, US9741957, US 9281487, and US2020/0013978 all describe OLED stacks of multiple stacks of light-emitting OLED cells, each separated by an intermediate connecting layer or charge generating layer. Springer et al., Optics Express, 24 (24), 28131 (2016) report OLED stacks with 2 and 3 light-emitting cells, each of which has a different color. OLED stacks with up to six light-emitting cells have been reported (Spindler et al., "High Brightness OLED Lighting" at SID Display Week 2016, San Francisco, California, May 23-27, 2016).

然而,將需要較高驅動電壓之此種多堆疊OLED方法難以應用於微顯示器應用。一問題係微顯示器亦需要具有高解析度,此需要個別像素之大小必須儘可能小且微顯示器之作用(發光)區域含有儘可能多的像素。此需要背板之控制電路系統中之電晶體係小的,但大小足以在不會造成永久損壞或電流洩漏之情況下應對所需電壓及電流。However, this multi-stacked OLED approach, which would require relatively high drive voltages, is difficult to apply to microdisplay applications. One problem is that microdisplays also need to have high resolution, which requires that the size of the individual pixels must be as small as possible and that the active (light-emitting) area of the microdisplay contain as many pixels as possible. This requires that the transistors in the control circuitry of the backplane be small, but large enough to handle the required voltages and currents without causing permanent damage or current leakage.

通常,隨著電晶體變小,由於洩漏電流及其他故障機制而無法處置較高功率,因此電壓額定值變低。較小較低電壓電晶體在閘極處具有較薄絕緣層,因此其亦具有更靜態電流洩漏。因此,需要較高電壓之OLED裝置通常使用能夠處置較高電壓之較大電晶體。WO2008/057372論述與微顯示器中之像素電路大小減小相關聯之問題及先前技術。舉例而言,亦參見 O. Prache, Journal of the Society for Information Display, 10(2), 133 (2002); O. Prache, 「Active Matrix Molecular OLED Microdisplays, Displays, 22, 49-56 (2001);且 Howard等人的「Microdisplays based upon organic lighat emitting diodes」, IBM J. of Res. & Dev.,45 (1),15 (2001)論述需要在低電壓下提供高照度及一大對比度比率之矽背板上微顯示器。 Typically, as transistors get smaller, the voltage rating gets lower because they cannot handle higher powers due to leakage current and other failure mechanisms. Smaller, lower voltage transistors have thinner insulation at the gate, so they also have more quiescent current leakage. Therefore, OLED devices that require higher voltages typically use larger transistors that can handle the higher voltages. WO2008/057372 discusses the problems and prior art associated with the reduction in pixel circuit size in microdisplays. For example, see also O. Prache , Journal of the Society for Information Display, 10(2), 133 (2002); O. Prache , "Active Matrix Molecular OLED Microdisplays, Displays, 22, 49-56 (2001); and Howard et al., "Microdisplays based upon organic lighat emitting diodes", IBM J. of Res. & Dev., 45 (1), 15 (2001) for discussing the need for microdisplays on silicon backplanes that provide high illumination and a large contrast ratio at low voltages.

此外,當使用MOSFET p通道電晶體將一恆定電流自處於V DD下之一電源提供至陰極電壓為V CATHODE之一OLED時,總電壓必須大以為電晶體供電且將OLED「接通」至高亮度。然而,若使用一低電壓p通道電晶體控制一12V OLED時,則當試圖關斷OLED以形成一黑色像素時,電晶體之電流洩漏將係高的且OLED將繼續發射,此乃因(V anode– V cathode)將仍大於OLED臨限值電壓。在OLED微顯示器中,由於OLED像素在應係黑暗時將繼續發光,因此穿過驅動電晶體之電流洩漏將減小對比度。此效應將使得純黑色(不發射)變成灰色且減小純黑色與純白色之間的色調等級之量值。此係不期望的。 Furthermore, when using a MOSFET p-channel transistor to provide a constant current from a power supply at VDD to an OLED with a cathode voltage of VCATHODE , the total voltage must be large to power the transistor and turn the OLED "on" to high brightness. However, if a low voltage p-channel transistor is used to control a 12V OLED, then when trying to turn the OLED off to form a black pixel, the current leakage from the transistor will be high and the OLED will continue to emit because ( Vanode - Vcathode ) will still be greater than the OLED threshold voltage. In an OLED microdisplay, current leakage through the drive transistor will reduce contrast because the OLED pixel will continue to emit light when it should be dark. This effect will make pure black (no emission) appear gray and reduce the magnitude of the tonal scale between pure black and pure white. This is undesirable.

需要藉由利用具有高照度且具有高電壓要求之OLED堆疊增大矽背板上OLED微顯示器之效能以發光。然而,矽背板上之控制電路系統必須能夠在大小不會顯著增大之條件下處置增大的電壓及電流需求,以維持OLED之作用區域內之解析度及像素間距。確切而言,控制電路系統應藉由透過TFT防止或最小化電流洩漏來維持對比度。對比度係當像素應係「關斷」、「黑色」或不發射(通常,影像信號碼值(CV) = 0)時與當像素應係完全「接通」、「白色」或處於最大發射下(通常,影像信號CV = 255)時之間的光發射差異。There is a need to increase the performance of OLED microdisplays on silicon backplanes by utilizing OLED stacks with high illumination and with high voltage requirements to emit light. However, the control circuitry on the silicon backplane must be able to handle the increased voltage and current requirements without a significant increase in size to maintain the resolution and pixel pitch within the active area of the OLED. Specifically, the control circuitry should maintain contrast by preventing or minimizing current leakage through the TFT. Contrast is the difference in light emission between when a pixel should be "off," "black," or not emitting (typically, image signal code value (CV) = 0) and when the pixel should be fully "on," "white," or at maximum emission (typically, image signal CV = 255).

通常,在製造背板之半導體晶圓代工行業中,具有一5 V或更小操作範圍之類比電晶體被視為標準「低電壓」(LV)電晶體。此外常見的是,電壓額定值通常具有一10%安全性限制,從而允許在「5 V電晶體」甚至5.5 V電晶體之壽命不降級之條件下可靠操作;此足夠高以允許在OLED動態電壓範圍中存在某一程度之過電壓及驅動電路額外負擔電壓。雖然電壓極限通常應用於通向電晶體之任何一對觸點(閘極、源極、汲極、主體(亦被稱為塊體或井))之間,但其特別適用於最大閘極-汲極電壓以使得在此等條件下電晶體之效能通常運作43,000小時之規定範圍內。有時,根據電晶體之設計,其他觸點對之電壓極限可更高(例如,7 V)但此電晶體仍被稱為一LV或5 V電晶體。由於5 V類比電晶體能夠與傳統TTL邏輯電壓位準相容以實現積體電路(IC)晶片之間的通信,因此行業內廣泛提供5 V類比電晶體。隨著輸入-輸出通信之電壓不斷下降(例如,3.3 V與1.8 V標準),此等5 V電晶體亦有時稱為中等電壓(MV)電晶體,使得LV標籤變為較新的「較低-電壓」類比電晶體。雖然如LV及MV等相對性標籤可隨時間而改變,但在此專利申請案中,術語LV或「低電壓」指代一額定值為5 V或低於5 V之電晶體,且術語MV或「中等電壓」指代電壓額定值高於5 V之電晶體。亦通常可使用較高電壓類比電晶體,但在IC製作行業內確切電壓並未像5 V電晶體一樣被標準化。舉例而言,例如汽車等行業中通常需要較高電壓電晶體。Typically, in the semiconductor foundry industry that manufactures backplanes, analog transistors with an operating range of 5 V or less are considered standard "low voltage" (LV) transistors. It is also common that the voltage ratings usually have a 10% safety limit, allowing reliable operation without degradation of the life of "5 V transistors" or even 5.5 V transistors; this is high enough to allow for a certain degree of overvoltage in the OLED dynamic voltage range and additional load voltage for the driver circuit. Although voltage limits generally apply between any pair of contacts to a transistor (gate, source, drain, body (also called bulk or well)), they specifically apply to the maximum gate-drain voltage so that the performance of the transistor under these conditions is typically within the 43,000 hour specification. Sometimes, depending on the design of the transistor, the voltage limits of other contact pairs can be higher (for example, 7 V) but the transistor is still called an LV or 5 V transistor. 5 V analog transistors are widely available in the industry because they are compatible with traditional TTL logic voltage levels for communication between integrated circuit (IC) chips. As voltages for input-output communications continue to drop (e.g., 3.3 V and 1.8 V standards), these 5 V transistors are sometimes referred to as medium voltage (MV) transistors, making the LV designation a newer "low-voltage" analog transistor. Although relative designations such as LV and MV can change over time, in this patent application, the term LV or "low voltage" refers to a transistor rated at 5 V or less, and the term MV or "medium voltage" refers to transistors with voltage ratings greater than 5 V. Higher voltage analog transistors are also commonly used, but the exact voltage is not standardized within the IC manufacturing industry like the 5 V transistors. For example, higher voltage transistors are often required in industries such as automotive.

目前,可使用具有低電壓5 V驅動電晶體之矽背板,此種矽背板使用串接(兩個發光OLED單元被一個CGL分隔開)OLED堆疊來發光。舉例而言,參見 Cho等人的Journal of Information Display, 20(4), 249-255, 2019; https://www.ravepubs.com/oled-silicon-come-new-joint-venture/, published 2018; Xiao, 「Recent Developments in Tandem White Organic Light-Emitting Diodes」, Molecules, 24, 151 (2019)。此等實例之照度不足以滿足技術需要。 Currently, silicon backplanes with low voltage 5 V drive transistors are available, which use tandem (two light-emitting OLED units separated by a CGL) OLED stacks to emit light. For example, see Cho et al., Journal of Information Display, 20(4), 249-255, 2019; https://www.ravepubs.com/oled-silicon-come-new-joint-venture/, published 2018; Xiao, "Recent Developments in Tandem White Organic Light-Emitting Diodes", Molecules, 24, 151 (2019). The illumination of these examples is not enough to meet the technical requirements.

Han等人的「Advanced Technologies for Large-Sized OLED Displays」第3章,10.5772/intechopen.74869 (2018)。此綜述文章闡述三堆疊白色OLED方案以及包含具有兩個串聯連接電晶體之技術在內的背板技術的進步,但係分開而不是組合闡述。此參考亦指出此兩個電晶體背板「由於線負載大且充電時間短因而難以用於大型高解析度面板」且因此將一不同類型之背板電路系統用於其裝置中。 Han et al., “Advanced Technologies for Large-Sized OLED Displays,” Chapter 3, 10.5772/intechopen.74869 (2018). This review article describes the triple-stacked white OLED scheme and advances in backplane technology, including technology with two series-connected transistors, but separately rather than in combination. The reference also notes that this two-transistor backplane “is difficult to use for large, high-resolution panels due to large line loads and short charging times” and therefore uses a different type of backplane circuitry in their device.

Liu等人的J. Cent. South Univ., 19, 1276−1282 (2012)揭示Si晶片微顯示器上之一OLED中具有兩個串聯連接p通道電晶體的一3T1C電路。 Liu et al., J. Cent. South Univ., 19, 1276−1282 (2012) disclose a 3T1C circuit with two series-connected p-channel transistors in an OLED on a Si chip microdisplay.

Zeng等人的「A Novel Pixel Circuit with Threshold Voltage Variation Compensation in Three-Dimensional AMOLED on Silicon Microdisplays」, P-27, SID 2019 Digest, p. 1313闡述用於驅動一矽背板上之一AMOLED顯示器之一4T1C像素電路。其揭示使用串聯連接於一電源與一OLED之間的兩個p通道低電壓電晶體。第一電晶體用於驅動OLED且控制供應至OLED之電流。第二電晶體係用於在程式運行期間關斷OLED之一開關電晶體。以上電路亦含有額外電晶體來判定並補償V th變化。 Zeng et al., “A Novel Pixel Circuit with Threshold Voltage Variation Compensation in Three-Dimensional AMOLED on Silicon Microdisplays,” P-27, SID 2019 Digest, p. 1313, describes a 4T1C pixel circuit for driving an AMOLED display on a silicon backplane. It discloses the use of two p-channel low-voltage transistors connected in series between a power source and an OLED. The first transistor is used to drive the OLED and control the current supplied to the OLED. The second transistor is a switching transistor that turns off the OLED during program operation. The above circuit also contains additional transistors to determine and compensate for Vth variations.

US9,066,379闡述適合於一OLED微顯示器之控制電路系統。其揭示使用串聯連接於一電源與一OLED之間的兩個p通道低電壓電晶體。第一電晶體係用於驅動OLED且控制供應至OLED之電流。第二電晶體係用於開閉(關斷)OLED之一開關電晶體。電路亦需要一第三電晶體,該第三電晶體係位於開關電晶體與OLED之間的一中等電壓或高電壓p通道電晶體。此第三電晶體之用途係每當在OLED之「關斷」週期期間(V ss-V cathode)大於OLED臨限值電壓時防止電流流動至OLED。 US9,066,379 describes a control circuit system suitable for an OLED microdisplay. It discloses the use of two p-channel low voltage transistors connected in series between a power source and an OLED. The first transistor is used to drive the OLED and control the current supplied to the OLED. The second transistor is a switching transistor used to turn the OLED on and off. The circuit also requires a third transistor, which is a medium voltage or high voltage p-channel transistor located between the switching transistor and the OLED. The purpose of this third transistor is to prevent current from flowing to the OLED whenever the voltage ( Vss - Vcathode ) is greater than the OLED critical voltage during the "off" cycle of the OLED.

Pashmineh等人之「High-voltage circuits for power management on 65nm CMOS」, Adv. Radio Sci., 13, 109–120, 2015闡述基於串聯連接(亦通常被稱為「堆疊式」電晶體)堆疊式低電壓CMOS電晶體之高電壓電路。 Pashmineh et al., “High-voltage circuits for power management on 65nm CMOS”, Adv. Radio Sci., 13, 109–120, 2015, describe high-voltage circuits based on stacked low-voltage CMOS transistors connected in series (also commonly referred to as “stacked” transistors).

Dawson等人之「The Impact of the Transient Response of Organic Light Emitting Diodes on the Design of Active Matrix OLED Displays」, International Electronic Devices Mtg 1998, 875-878闡述具有兩個串聯連接p通道電晶體之一像素電路。 Dawson et al., "The Impact of the Transient Response of Organic Light Emitting Diodes on the Design of Active Matrix OLED Displays", International Electronic Devices Mtg 1998, 875-878, describes a pixel circuit having two p-channel transistors connected in series.

Kwak等人之「Organic Light-Emitting Diode-on-Silicon Pixel Circuit Using the Source Follower Structure with Active Load for Microdisplays」, Japanese Journal of Applied Physics, 50, 03CC05 (2011)闡述具有三個串聯連接p通道電晶體及一過電壓保護電路之一像素電路。此參考指出由於OLED之操作電壓高於MOSFET之操作電壓,因此需要「一過電壓保護電路」來防止金屬氧化物半導體場效電晶體(MOSFET)崩潰。U5760477及US9066379亦闡述一保護電路之用途。 Kwak et al., "Organic Light-Emitting Diode-on-Silicon Pixel Circuit Using the Source Follower Structure with Active Load for Microdisplays", Japanese Journal of Applied Physics, 50, 03CC05 (2011) describes a pixel circuit having three series-connected p-channel transistors and an overvoltage protection circuit. This reference states that since the operating voltage of an OLED is higher than the operating voltage of a MOSFET, an "overvoltage protection circuit" is required to prevent the metal oxide semiconductor field effect transistor (MOSFET) from collapsing. U5760477 and US9066379 also describe the use of a protection circuit.

Vogel等人之SID 2017 DIGEST文章77-1第1125至1128頁揭示在一低電壓OLED Si微顯示器中使用一保護電路來擴大OLED電壓操作範圍。 Vogel et al., SID 2017 DIGEST article 77-1, pages 1125 to 1128, disclose the use of a protection circuit in a low voltage OLED Si microdisplay to extend the OLED voltage operating range.

US6580657、WO2009072205及CN200488960中揭示對OLED實行過電壓保護之其他參考文獻。US9059123、US9299817、US9489886、US20080316659及US20200202793揭示在OLED顯示器之像素控制電路中使用n-p接面二極體,例如雙極接面電晶體。Other references for overvoltage protection of OLEDs are disclosed in US6580657, WO2009072205 and CN200488960. US9059123, US9299817, US9489886, US20080316659 and US20200202793 disclose the use of n-p junction diodes, such as bipolar junction transistors, in pixel control circuits of OLED displays.

揭示兩個串聯連接電晶體之額外專利參考包含:CN109166525、US20140125717、US7196682、US6229506、US9262960、US7443367、US6930680、US10614758、WO2019019590、US6946801、US7755585、US8547372、US8786591、US8797314、US9818344、US2018/0211592及US10269296。以下參考文獻揭示具有三個串聯連接電晶體之像素電路:US9324266、US9384692、US10600366、US7180486、US9858863及US20190279567。Additional patent references disclosing two series-connected transistors include: CN109166525, US20140125717, US7196682, US6229506, US9262960, US7443367, US6930680, US10614758, WO2019019590, US6946801, US7755585, US8547372, US8786591, US8797314, US9818344, US2018/0211592, and US10269296. The following references disclose pixel circuits having three series-connected transistors: US9324266, US9384692, US10600366, US7180486, US9858863, and US20190279567.

US9059123及US9489886揭示在OLED顯示器之像素控制電路中使用n-p接面二極體,例如雙極接面電晶體。US9059123 and US9489886 disclose the use of n-p junction diodes, such as bipolar junction transistors, in pixel control circuits of OLED displays.

闡述一種包括位於一矽基背板之頂部上之一發光OLED堆疊之微顯示器,該矽基背板具有可個別定址像素及控制電路系統,其中該發光OLED堆疊具有位於一頂部電極與一底部電極之間的三個或更多個OLED單元;且矽基背板之該控制電路系統包括用於每一可個別定址像素之至少兩個電晶體,該至少兩個電晶體之通道串聯連接於一外部電源V DD與該OLED堆疊之該底部電極之間。 A microdisplay is described that includes a light-emitting OLED stack located on top of a silicon-based backplane, the silicon-based backplane having individually addressable pixels and a control circuit system, wherein the light-emitting OLED stack has three or more OLED units located between a top electrode and a bottom electrode; and the control circuit system of the silicon-based backplane includes at least two transistors for each individually addressable pixel, and the channels of the at least two transistors are connected in series between an external power supply VDD and the bottom electrode of the OLED stack.

如以上之微顯示器,其中該發光OLED堆疊之臨限值電壓V th至少7.5 V或大於7.5 V,或較佳地至少10 V或大於10 V。 In the microdisplay as above, the threshold voltage Vth of the light-emitting OLED stack is at least 7.5 V or greater, or preferably at least 10 V or greater.

如以上微顯示器中之任一者,其中該OLED堆疊包括四個或更多個OLED發光單元。As in any of the above microdisplays, wherein the OLED stack comprises four or more OLED light-emitting units.

如以上微顯示器中之任一者,其中該OLED發光單元各自被一電荷產生層(CGL)彼此分隔開,或其中該底部電極係分段式的且每一區段與背板中之控制電路系統電接觸,或其中該OLED堆疊係頂部發射式的。As in any of the above microdisplays, wherein the OLED light emitting units are each separated from each other by a charge generation layer (CGL), or wherein the bottom electrode is segmented and each segment is electrically contacted with the control circuit system in the backplane, or wherein the OLED stack is top emitting.

如以上微顯示器中之任一者,其中該OLED堆疊形成一微腔,其中分段式底部電極與該頂部電極之間的實體距離在所有像素上皆係恆定的。A microdisplay as in any of the above, wherein the OLED stack forms a microcavity in which the physical distance between the segmented bottom electrode and the top electrode is constant across all pixels.

如以上微顯示器中之任一者,其中具有其等通道串聯連接之電晶體兩者皆額定為5 V或低於5 V,或其中最靠近電源之電晶體係一驅動電晶體且額定為5 V或低於5 V,且最靠近OLED之該底部電極之電晶體係一開關電晶體且額定為大於5 V。A microdisplay as in any of the above, wherein the transistors having their equal-channel series connection are both rated at 5 V or less, or wherein the transistor closest to the power supply is a drive transistor and is rated at 5 V or less, and the transistor closest to the bottom electrode of the OLED is a switching transistor and is rated greater than 5 V.

如以上微顯示器中之任一者,其中具有其等通道串聯連接之該兩個電晶體兩者皆係p通道電晶體,或其中具有其等通道串聯連接之該兩個電晶體各自位於單獨井中。As in any of the above microdisplays, wherein the two transistors having their equal-channel series connection are both p-channel transistors, or wherein the two transistors having their equal-channel series connection are each located in a separate well.

如以上微顯示器中之任一者,其中該控制電路系統另外包括具有一p通道電晶體或二極體之一保護電路。該保護電路可包括一p-n二極體,且其中該p-n接面二極體之陰極連接至OLED堆疊之底部電極之節點,且陽極連接至一電壓參考V REF或一電流參考I REFAs in any of the above microdisplays, wherein the control circuit system further includes a protection circuit having a p-channel transistor or diode. The protection circuit may include a pn diode, and wherein the cathode of the pn junction diode is connected to the node of the bottom electrode of the OLED stack, and the anode is connected to a voltage reference V REF or a current reference I REF .

如上文所闡述之保護電路,其中該二極體係一雙極接面電晶體。該雙極接面電晶體可係一NPN電晶體,其中基極連接至一電壓源V PROTECT或一電流源I PROTECT,射極連接至與OLED堆疊之底部電極連接之一節點,且集電極連接至電壓源V DD。BJT之基極可係隔離的。 As described above, the protection circuit, wherein the diode is a bipolar junction transistor. The bipolar junction transistor may be an NPN transistor, wherein the base is connected to a voltage source V PROTECT or a current source I PROTECT , the emitter is connected to a node connected to the bottom electrode of the OLED stack, and the collector is connected to the voltage source V DD . The base of the BJT may be isolated.

如以上保護電路,其中雙極接面電晶體位於與具有其等通道串聯連接之兩個電晶體分離之一井中,或其中具有其等通道串聯連接之該兩個電晶體皆係p通道電晶體且各自位於單獨n井中且雙極接面電晶體係位於一單獨p井中之一NPN電晶體。As in the above protection circuit, the bipolar junction transistor is located in a well separated from the two transistors having their equal-channel series connection, or the two transistors having their equal-channel series connection are both p-channel transistors and each is located in a separate n-well and the bipolar junction transistor is an NPN transistor located in a separate p-well.

如上文所闡述之微顯示器中之任一者,其另外包括位於該OLED堆疊頂部上之一RGB彩色濾光器陣列(CFA),其中該等個別紅色濾光器、綠色濾光器、藍色濾光器與分段式底部電極配準以形成R、G、B像素;或其另外包括位於OLED堆疊頂部上之一RGBW彩色濾光器陣列(CFA),其中個別紅色濾光器、綠色濾光器、藍色濾光器及透明或無色濾光器與分段式底部電極配準以形成R、G、B及W像素。Any of the microdisplays as described above, further comprising an RGB color filter array (CFA) located on top of the OLED stack, wherein the individual red filters, green filters, blue filters are aligned with the segmented bottom electrode to form R, G, B pixels; or it further comprises an RGBW color filter array (CFA) located on top of the OLED stack, wherein the individual red filters, green filters, blue filters and transparent or colorless filters are aligned with the segmented bottom electrode to form R, G, B and W pixels.

微顯示器提供非常高照度及對比度且具有一小像素間距尺寸。Microdisplays provide very high illumination and contrast with a small pixel pitch size.

相關申請案之交叉參考Cross-reference to related applications

本申請案主張以下申請案之優先權:標題為「STACKED OLED MICRODISPLAY WITH LOW-VOLTAGE SILICON BACKPLANE」且於2020年1月28日提出申請的代理人案號為OLWK-0021-USP之美國臨時美國申請案62/966,757以及標題亦為「STACKED OLED MICRODISPLAY WITH LOW-VOLTAGE SILICON BACKPLANE」且於2020年7月21日提出申請的代理人案號為OLWK-0021-USP2之美國臨時美國申請案63/054387。This application claims priority to U.S. provisional U.S. application 62/966,757, filed on January 28, 2020, with attorney docket number OLWK-0021-USP, and entitled “STACKED OLED MICRODISPLAY WITH LOW-VOLTAGE SILICON BACKPLANE” and U.S. provisional U.S. application 63/054387, filed on July 21, 2020, with attorney docket number OLWK-0021-USP2, also entitled “STACKED OLED MICRODISPLAY WITH LOW-VOLTAGE SILICON BACKPLANE”.

出於本發明之目的,術語「之上」或「上方」意指所涉及結構位於另一結構上方,即位於與基板相對之一側上。「頂部」、「最上部的」或「上部的」指代遠離基板之一側或表面,而「底部」、「最底部」或「底部」指代最靠近基板之一側或表面。除非另有指明,否則「位於…之上」應解釋為兩個結構可直接接觸或該兩個結構之間可存在中間層。提及「層」,應理解一單個層具有兩側或兩個表面(最上部及最底部);在某些例項中,「層」可表示被視為整體之多個層並不僅限於一單個層。For the purposes of the present invention, the term "on" or "above" means that the structure in question is located above another structure, that is, on a side opposite to the substrate. "Top", "uppermost" or "upper" refers to a side or surface farthest from the substrate, while "bottom", "bottommost" or "bottom" refers to a side or surface closest to the substrate. Unless otherwise specified, "located above..." should be interpreted as two structures can be directly in contact or there can be an intermediate layer between the two structures. When referring to a "layer", it should be understood that a single layer has two sides or two surfaces (topmost and bottommost); in some examples, "layer" can mean multiple layers considered as a whole and is not limited to a single layer.

就發光單元或層而言,R指示主要發射紅色光(> 600 nm,期望在620至660 nm之範圍中)之一層,G指示主要發射綠色光(500至600 nm,期望在540至565 nm範圍內)之一層,且B指示主要發射藍色光(<500 nm,期望在440至485 nm範圍內)之一層。重要的是應注意,R、G及B層可產生在所指示範圍之外的某種程度光,但量始終小於主要色彩。Y (黃色)指示一層發射大量R光及G光,但一B光之量更少。「LEL」意指發光層。除非另有指明,否則波長係真空值而非原位值。With respect to light emitting units or layers, R indicates a layer that primarily emits red light (>600 nm, desirably in the range of 620 to 660 nm), G indicates a layer that primarily emits green light (500 to 600 nm, desirably in the range of 540 to 565 nm), and B indicates a layer that primarily emits blue light (<500 nm, desirably in the range of 440 to 485 nm). It is important to note that the R, G, and B layers may produce some degree of light outside the indicated range, but the amount is always less than the primary colors. Y (yellow) indicates a layer that emits a lot of R and G light, but a much smaller amount of B light. "LEL" means light emitting layer. Unless otherwise indicated, wavelengths are vacuum values, not in situ values.

一個別OLED發光單元可產生單一「色彩」光(即R、G、B或例如Y、C (藍綠)或W(白色)等2種或更多種主要色彩之一組合)。單一色彩光可在OLED單元內由色彩相同之一或多個發射體之一單個層或多個層產生,每一層具有主要發射在相同色彩內之相同或不同發射體。一單個OLED單元亦可藉由具有如下層在一單個OLED單元內提供兩種色彩之一組合(即R+G、R+B、G+B):發射兩種色彩之光之一單個發射體之一層、具有兩個不同發射體之一層或各自發射一種但不同色彩之多個單獨層之組合。一單個OLED單元亦可藉由具有以下層提供白色光(R、G及B之一組合):發射所有三個色彩之光之一層或多個單獨層之組合,該多個單獨層各自發射單一(但不同)色彩,該等色彩之和係白色。個別OLED發光單元可具有一單個發光層或可具有一個以上發光層(彼此直接毗鄰或彼此被一中間層分隔開)。個別發光單元亦可含有各種非發射層,例如電洞傳輸層、電子傳輸層、阻擋層及此項技術中已知的用於提供期望效應(例如,促進發射及管理跨越發光單元之電荷轉移)之其他層。An individual OLED light emitting cell can produce a single "color" of light (i.e., R, G, B, or a combination of 2 or more primary colors such as Y, C (cyan), or W (white)). A single color of light can be produced within the OLED cell by a single layer or multiple layers of the same color or multiple emitters, each layer having the same or different emitters emitting primarily in the same color. A single OLED cell can also provide a combination of two colors (i.e., R+G, R+B, G+B) within a single OLED cell by having a layer of a single emitter emitting two colors of light, a layer with two different emitters, or a combination of multiple separate layers that each emit one but different color. A single OLED cell can also provide white light (a combination of R, G, and B) by having a layer that emits light of all three colors or a combination of individual layers that each emit a single (but different) color, the sum of which is white. Individual OLED light-emitting cells can have a single light-emitting layer or can have more than one light-emitting layer (directly adjacent to each other or separated from each other by an intermediate layer). Individual light-emitting cells can also contain various non-emissive layers, such as hole transport layers, electron transport layers, blocking layers, and other layers known in the art to provide desired effects (e.g., promoting emission and managing charge transfer across the light-emitting cell).

由於OLED發光單元可包括多個層,因此一個別單元有時被稱為「堆疊」,其可能與具有多個單元之一OLED裝置混淆。在此應用中,一「堆疊式」OLED具有至少兩個OLED發光單元,該至少兩個OLED發光單元在一基板之上堆疊於彼此頂部上,因此裝置內存在多個光源。在本發明之堆疊式OLED中,個別OLED發光單元彼此係被一電荷產生層(CGL)而不是被單獨且獨立控制之中間電極分隔開。為對一OLED發光單元加以考量,必須將藉由一CGL將其與另一光產生單元分隔開。因此,毗鄰於OLED發光單元中之一者但未藉由一CGL與該OLED發光單元分隔開之一發光層不考慮作為一單獨單元。在堆疊內,個別OLED發光單元中之所有或某些可相同或全部可彼此不同。在OLED堆疊內,別OLED發光單元可按照任何次序放置於頂部陰極與底部陰極之間。堆疊式OLED可係單色的(OLED堆疊之每一像素主要發射相同色彩之光,例如綠色光)或可具有多模式發射(其中每一像素發射2種或更多種色彩之光(例如,黃色或白色)或其中不同像素發射不同色彩之光以使得總體發射含有2種或更多種色彩之光)。Because OLED light-emitting cells can include multiple layers, an individual cell is sometimes referred to as a "stack," which can be confused with an OLED device having multiple cells. In this application, a "stacked" OLED has at least two OLED light-emitting cells stacked on top of each other on a substrate so that there are multiple light sources within the device. In the stacked OLED of the present invention, individual OLED light-emitting cells are separated from each other by a charge generation layer (CGL) rather than by separate and independently controlled intermediate electrodes. In order for an OLED light-emitting cell to be considered, it must be separated from another light-generating cell by a CGL. Therefore, a light-emitting layer that is adjacent to one of the OLED light-emitting cells but is not separated from the OLED light-emitting cell by a CGL is not considered as an individual cell. Within a stack, all or some of the individual OLED light emitting units may be the same or all may be different from one another. Within an OLED stack, the individual OLED light emitting units may be placed between the top cathode and the bottom cathode in any order. Stacked OLEDs may be monochromatic (each pixel of the OLED stack emits primarily the same color of light, such as green light) or may have multi-mode emission (where each pixel emits 2 or more colors of light (e.g., yellow or white) or where different pixels emit different colors of light so that the overall emission contains 2 or more colors of light).

在某些情形中,可在顯著光發射開始回到電壓軸之後藉由I-V曲線之直線外推估計OLED堆疊之臨限值電壓(V th)。由於此方法因OLED之I-V回應曲線在其回應範圍內無法呈完全線形而並不準確,因此以此方式計算之值不準確。此量度之一大致範圍係+/-10%。更準確而言,可將臨限值電壓界定為暴露陽極層之電流密度不超過0.2 mA/cm 2且存在至少某些可靠可偵測照度(即,至少5 cd/A)的電壓。此此應用中所使用之方法。 In some cases, the threshold voltage ( Vth ) of the OLED stack can be estimated by straight-line extrapolation of the IV curve after significant light emission begins to return to the voltage axis. Since this method is not accurate due to the fact that the IV response curve of an OLED is not completely linear over its response range, the value calculated in this way is not accurate. One approximate range for this measure is +/-10%. More precisely, the threshold voltage can be defined as the voltage at which the current density exposing the anode layer does not exceed 0.2 mA/ cm2 and there is at least some reliably detectable illumination (i.e., at least 5 cd/A). This is the method used in this application.

在下文中,電晶體可被稱為「接通」或「關斷」。在一「關斷」電晶體中,預期將信號發送至閘極以使得沒有電流將通過端子;換言之,該信號(通常,CV = 0)指示該信號要求沒有電流通過該電晶體以使得不是將電晶體關斷,而是將該電晶體調節成「關斷的」。在此等情形中,即使一電晶體可係「關斷的」,仍可存在某些電流洩漏。同樣地,在一「接通」電晶體中,預期將信號發送至閘極以使得至少某些電流將通過端子;換言之,該信號(通常,CV=大於0但小於255)指示該影像要求像素進行某些程度之發射以使得不是將電晶體「接通」,而是將電晶體調節成「接通的」。類似地,像素或OLED可根據影像之要求被稱為「接通」或「關斷」,且因此將適當信號發送至像素或OLED。Hereinafter, a transistor may be referred to as being "on" or "off." In an "off" transistor, it is expected that a signal is sent to the gate so that no current will pass through the terminal; in other words, the signal (usually, CV = 0) indicates that the signal requires no current to pass through the transistor so that instead of turning the transistor off, the transistor is regulated to be "off." In such cases, even though a transistor may be "off," there may still be some current leakage. Likewise, in an "on" transistor, it is expected that a signal will be sent to the gate so that at least some current will pass through the terminal; in other words, the signal (usually, CV = greater than 0 but less than 255) indicates that the image requires the pixel to emit to a certain degree so that instead of turning the transistor "on", the transistor is modulated to be "on." Similarly, the pixel or OLED can be said to be "on" or "off" depending on the requirements of the image, and the appropriate signal is sent to the pixel or OLED accordingly.

矽背板源自於一矽晶圓(亦被稱為一片塊或基板)。其係用於製作積體電路之一半導體薄片,例如一晶體矽(c-Si)。晶圓用作置於晶圓中及晶圓上之微電子裝置之基板。其經歷諸多微製作程序,例如對各種材料進行摻雜、離子植入、蝕刻、薄膜沈積及光微影圖案化。最後,藉由晶圓切割將個別微電路分離並封裝為一積體電路。晶圓係由具有一規則晶體結構之晶體生長而成,其中矽呈具有一晶格間隔之一菱形立方體結構。當切割成晶圓時,表面在幾個相對方向中之一者上對準,該等方向被稱為晶體定向。矽晶圓通常不是100%純矽,而是最初形成有一定摻雜濃度之硼、磷、砷或銻雜質,將該等雜質添加至熔融體中且將晶圓界定為塊體n型或p型。參見「Flat Panel Display Manufacturing」, Souk, L., Ed., 2018中之第7章以供內部參考。期望矽背板係一單晶Si晶圓。The silicon backplane is derived from a silicon wafer (also called a chip or substrate). It is a semiconductor thin sheet, such as a crystalline silicon (c-Si), used to make integrated circuits. The wafer serves as the substrate for the microelectronic devices placed in and on the wafer. It undergoes a number of microfabrication processes, such as doping of various materials, ion implantation, etching, thin film deposition, and photolithographic patterning. Finally, the individual microcircuits are separated and packaged into an integrated circuit by wafer dicing. Wafers are grown from crystals with a regular crystal structure, in which the silicon is in a rhombic cubic structure with a lattice spacing. When cut into wafers, the surfaces are aligned in one of several relative directions, which are called crystal orientations. Silicon wafers are typically not 100% pure silicon, but are initially formed with certain doping concentrations of boron, phosphorus, arsenic or antimony, which are added to the melt and define the wafer as either bulk n-type or p-type. See Chapter 7 in "Flat Panel Display Manufacturing", Souk, L., Ed., 2018 for internal reference. The silicon backplane is expected to be a single crystal Si wafer.

為了為堆疊式OLED之操作提供控制電路系統,薄膜電晶體(TFT)以及其他組件(例如電容器、電阻器、連接配線或匯流排條等)設置於矽晶圓之表面上。舉例而言,參見T. Arai的「High Performance TFT Technologies for the AM-OLED Display manufacturing」, Thesis, Nara Institute of Science and Technology, 2016、M.K. Han的Proc. of ASID ’06, 8-12 Oct, New Delhi、US9066379及US10163998。應理解,TFT可包含或可不包含矽晶圓作為TFT結構之一部分,或者可由沈積於表面上之單獨材料製備而成。To provide control circuitry for the operation of the stacked OLED, thin film transistors (TFTs) and other components (e.g., capacitors, resistors, connecting wiring or bus bars, etc.) are disposed on the surface of the silicon wafer. For example, see T. Arai, "High Performance TFT Technologies for the AM-OLED Display manufacturing", Thesis, Nara Institute of Science and Technology, 2016, M.K. Han, Proc. of ASID '06, 8-12 Oct, New Delhi, US9066379, and US10163998. It should be understood that the TFT may or may not include a silicon wafer as part of the TFT structure, or may be made of a separate material deposited on the surface.

可使用各種半導體材料製成TFT。一基於矽TFT之特性取決於矽之晶體狀態;即,半導體層可係無定形矽、微晶體矽,或半導體層可退火成多晶矽(包含低溫多晶矽(LTPS)及雷射退火)。TFTs can be made using a variety of semiconductor materials. The characteristics of a silicon-based TFT depend on the crystalline state of the silicon; that is, the semiconductor layer can be amorphous silicon, microcrystalline silicon, or the semiconductor layer can be annealed into polycrystalline silicon (including low temperature polysilicon (LTPS) and laser annealing).

具有適合控制電路系統之矽背板之製造係一眾所周知、被理解且可預測技術。然而,由於製造程序及裝備之成本及複雜性,建造製造一特定背板之設施通常不切實際。相反,行業中廣泛採用一晶圓代工模型,其中微電子裝置之功能特性已變得更加標準化。此標準化允許設計與製造分開。遵循適當設計規則之一設計由具有可相容製造方法之不同公司製造起來可更容易且更便宜。因此,矽背板上之控制電路系統通常僅限於使用自背板製造商提供之各種選項選擇之標準組件。舉例而言,一矽背板製造商可提供將額定為1.8 V、2.5 V、3.3 V、5 V、8 V及12 V之各種標準電晶體設計包含於一客戶設計中之選項,但將不能夠提供(沒有很大成本)所提供設計中不包含之電晶體。The fabrication of silicon backplanes with suitable control circuitry is a well-known, understood, and predictable technology. However, due to the cost and complexity of the manufacturing process and equipment, it is often impractical to build a facility to manufacture a specific backplane. Instead, a foundry model is widely adopted in the industry, in which the functional characteristics of microelectronic devices have become more standardized. This standardization allows the separation of design and manufacturing. A design that follows appropriate design rules can be easier and cheaper to manufacture by different companies with compatible manufacturing methods. Therefore, the control circuitry on the silicon backplane is usually limited to the use of standard components selected from a variety of options provided by the backplane manufacturer. For example, a silicon backplane manufacturer may offer the option of including various standard transistor designs rated for 1.8 V, 2.5 V, 3.3 V, 5 V, 8 V and 12 V in a customer design, but will not be able to offer (without significant cost) transistors that are not included in the offered design.

出於申請案之目的,「低電壓」(LV)被界定為經設定大小、經設計且經評估以安全且可靠地以5 V或小於5 V操作之該等類比微電子組件。「高電壓」(HV)微電子裝置通常被視為處於18 V至25 V之範圍內。「中等電壓」(MV)微電子裝置通常被視為介於LV與HV之間的微電子裝置。應注意,此等電壓額定值由製造商設定且製造商不推薦超出每一電晶體之設定最大電壓。For the purposes of this application, "low voltage" (LV) is defined as those analog microelectronic components that are sized, designed, and rated to operate safely and reliably at 5 V or less. "High voltage" (HV) microelectronic devices are generally considered to be in the range of 18 V to 25 V. "Medium voltage" (MV) microelectronic devices are generally considered to be microelectronic devices between LV and HV. It should be noted that these voltage ratings are set by the manufacturer and that the manufacturer does not recommend exceeding the set maximum voltage for each transistor.

互補金屬氧化物半導體(CMOS)技術使用p型及n型金屬氧化物半導體場效電晶體(MOSFET)來實現複雜積體電路。根據製造程序,可使用不同電壓域(即,1.8 V、2.5 V、3.3V、5 V、12 V等)。在所有電壓域中,MOSFET電晶體具有一汲極、源極、閘極及塊體/井。MOSFET之基極係基板;就一n通道FET而言,基板係具有低摻雜率之一p型摻雜基板或井;就一p通道FET而言,基板係具有低摻雜率之一n型摻雜井。源極區及汲極區由n通道FET或p通道FET之n型或p型之高度摻雜區形成。受控通道形成於源極與汲極之間,與一薄氧化物隔離且通常覆蓋有一層多晶矽以用作一閘極。FET之所有四個端子(源極、汲極、閘極、基板/井)由金屬觸點連接至金屬互連層,該金屬互連層最後連接至OLED。Complementary metal oxide semiconductor (CMOS) technology uses p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) to realize complex integrated circuits. Depending on the manufacturing process, different voltage domains can be used (i.e., 1.8 V, 2.5 V, 3.3 V, 5 V, 12 V, etc.). In all voltage domains, the MOSFET transistor has a drain, source, gate, and bulk/well. The base of the MOSFET is the substrate; for an n-channel FET, the substrate is a p-type doped substrate or well with a low doping rate; for a p-channel FET, the substrate is an n-type doped well with a low doping rate. The source and drain regions are formed by highly doped regions of either n-type or p-type for n-channel FETs or p-channel FETs. The controlled channel is formed between the source and drain, isolated with a thin oxide and usually covered with a layer of polysilicon to serve as a gate. All four terminals of the FET (source, drain, gate, substrate/well) are connected by metal contacts to a metal interconnect layer, which is ultimately connected to the OLED.

一微顯示器之發射區域係小的且為達成必要像素間距,每一像素之控制電路系統之空間係有限的。就一全色彩微顯示器而言,每一個別像素之控制電路所佔用之空間應不超過100平方微米且較佳地不超過50平方微米。就所有像素發射相同色彩之一單色微顯示器而言,由於所需之像素較少,因此控制電路系統之空間可大出3至4倍。The emission area of a microdisplay is small and to achieve the necessary pixel pitch, the space for the control circuitry of each pixel is limited. For a full-color microdisplay, the space occupied by the control circuitry of each individual pixel should not exceed 100 square microns and preferably not exceed 50 square microns. For a monochrome microdisplay where all pixels emit the same color, the space for the control circuitry can be 3 to 4 times larger because fewer pixels are required.

在一適合低電壓5 V電晶體中,所有端子中之任一對端子之間的最大電壓不可超出5 V以免損壞裝置。將一典型安全餘裕定為10%過電壓在一短週期內係可接受的。額定為大於5 V之一中等電壓電晶體(例如,額定為7.5 V之中等電壓電晶體)具有與一5 V電晶體大致相同之設置,但具有一較厚閘極氧化物及較大幾何形狀(通道寬度及長度)以耐受較高電壓。因此,MV電晶體將通常較大且佔用比一對應LV電晶體多之空間。In a suitable low voltage 5 V transistor, the maximum voltage between any pair of terminals of all terminals must not exceed 5 V to avoid damage to the device. A typical safety margin is considered acceptable for a 10% overvoltage over a short period of time. A medium voltage transistor rated for greater than 5 V (e.g., a medium voltage transistor rated for 7.5 V) has roughly the same setup as a 5 V transistor, but with a thicker gate oxide and larger geometry (channel width and length) to withstand the higher voltage. Therefore, an MV transistor will generally be larger and take up more space than a corresponding LV transistor.

儘管可不考慮電壓額定值製作處於任何大小範圍中之電晶體,但適合於微顯示器應用的額定為5 V之一低電壓MOS電晶體具有不超過20平方微米且較佳地不超過10平方微米之總面積。適合於微顯示器應用之一5 V電晶體之一通道面積(通道長度×通道寬度)應不超過1平方微米且較佳地不超過0.30平方微米。兩個電晶體觸點應各自不超過1平方微米且較佳地不超過0.30平方微米。Although transistors can be made in any size range regardless of voltage rating, a low voltage MOS transistor rated for 5 V suitable for microdisplay applications has a total area of no more than 20 square microns and preferably no more than 10 square microns. A channel area (channel length x channel width) of a 5 V transistor suitable for microdisplay applications should be no more than 1 square micron and preferably no more than 0.30 square microns. The two transistor contacts should each be no more than 1 square micron and preferably no more than 0.30 square microns.

出於申請案之目的,適合於保護電路之一BJT係對NPN及PNP兩者類型而言通用設定係垂直的。對於一NPN BJT而言,集電極形成為具有低p摻雜之共同矽基板(塊體)之低摻雜深n井。基極形成為深n井內部之p井且藉由一高度摻雜p區連接。BJT之射極由p井內部之一高度摻雜n區形成。射極區之典型大小係約500 nm×500 nm且較佳地不超過0.30平方微米以使得像素大小很小。BJT之所有端子(塊體、基極、射極、集電極)中之任一對端子之間的最大電壓不可超出5 V以免損壞裝置。將一典型安全餘裕定為10%過電壓在一短週期內係可接受的。For the purposes of the application, a BJT suitable for the protection circuit is a vertical one with a common configuration for both NPN and PNP types. For an NPN BJT, the collector is formed as a low doped deep n-well with a common silicon substrate (bulk) with low p doping. The base is formed as a p-well inside the deep n-well and connected by a highly doped p-region. The emitter of the BJT is formed by a highly doped n-region inside the p-well. The typical size of the emitter region is about 500 nm x 500 nm and preferably does not exceed 0.30 square microns to make the pixel size very small. The maximum voltage between any pair of terminals of all the terminals of the BJT (bulk, base, emitter, collector) must not exceed 5 V to avoid damage to the device. A typical safety margin of 10% overvoltage is acceptable for a short period of time.

OLED微顯示器(通常稱為「AMOLED」)由OLED像素之一作用矩陣組成,該等OLED像素在電啟動時產生光(冷光),已沈積或整合至位於一矽晶片上之一電晶體陣列上,其中該陣列用作一系列開關以控制流動至每一個別像素之電流。通常,此連續電流流動由位於每一像素處之至少兩個電晶體控制(以觸發冷光),其中一個電晶體開始及停止對一儲存電容器之充電且控制另一電晶體,其中此另一電晶體提供處於在形成流向像素之一恆定電流所需之位準下的一電壓源。在某些實施例中,控制由另一電晶體(通常被稱為一驅動電晶體)提供之電流的電晶體(通常被稱為一掃描電晶體或選擇電晶體)係藉由一選擇線控制,該選擇線由一列中之所有像素共用。掃描電晶體傳遞之信號係由一資料線供應,該資料線由一行中之所有像素共用。OLED microdisplays (often referred to as "AMOLEDs") consist of an active matrix of OLED pixels that generate light (luminescence) when electrically activated, deposited or integrated onto a transistor array on a silicon chip, where the array acts as a series of switches to control the current flowing to each individual pixel. Typically, this continuous current flow is controlled by at least two transistors at each pixel (to trigger luminescence), one of which starts and stops charging a storage capacitor and controls another transistor, where the other transistor provides a voltage source at the level required to create a constant current flowing to the pixel. In some embodiments, a transistor (often called a scan transistor or select transistor) that controls the current provided by another transistor (often called a drive transistor) is controlled by a select line that is common to all pixels in a row. The signal delivered by the scan transistor is supplied by a data line that is common to all pixels in a row.

此在圖1中加以圖解說明,圖1表示先前技術AMOLED像素設計之最簡單形式。具有像素記憶體之最簡單AMOLED像素使用兩個電晶體及一個電容器。電流驅動電晶體MP2通常自供應電壓V DD連接至OLED之陽極。一個電晶體(MP2)為OLED驅動電流,且另一電晶體MP1 (亦被稱為一掃描電晶體)用作一開關以對一電壓取樣並將該電壓保持至所展示之儲存電容器C1上。一資料線(供應V DATA)控制電流V DD通過驅動電晶體MP2。一選擇線控制MP1且因此控制電容器C1之充電。通常,電晶體具有本質電容,因此根據電晶體之該本質電容及通過電晶體之洩漏電流,可不需要額外電容。 This is illustrated in Figure 1, which shows the simplest form of a prior art AMOLED pixel design. The simplest AMOLED pixel with pixel memory uses two transistors and a capacitor. The current drive transistor MP2 is typically connected to the anode of the OLED from the supply voltage VDD . One transistor (MP2) drives the current for the OLED, and the other transistor MP1 (also called a scanning transistor) is used as a switch to sample a voltage and hold it on the storage capacitor C1 shown. A data line (supply VDATA ) controls the current VDD through the drive transistor MP2. A select line controls MP1 and therefore controls the charging of capacitor C1. Typically, transistors have intrinsic capacitance, so based on the intrinsic capacitance of the transistor and the leakage current through the transistor, no additional capacitance may be required.

在圖1之後的圖中,為清晰起見各圖式中皆省略所存在之任何電容器。一電容器之存在係選用的且電路可視需要不具有電容器或具有任何數目個電容器。電容器之參考電壓可係V DD或某一其他電壓。 In the figures following FIG. 1 , any capacitor present is omitted from the figures for clarity. The presence of a capacitor is optional and the circuit may have no capacitors or any number of capacitors as desired. The reference voltage for the capacitor may be V DD or some other voltage.

注意,臨限值電壓(V th)、載子遷移率或串聯電阻之變化將直接影響驅動TFT之OLED電流之均勻性且因此影像顯示器之亮度。影響不均勻電流之一個主要因素係OLED驅動電晶體之臨限值電壓(V th)變化。像素可需要控制電路系統做出其他類型之補償,例如OLED材料隨時間而老化、降級或燒機、作用區域上之不均衡或不均勻或金屬連接線之電壓降。另外,TFT提供之控制電路系統可需要控制例如由PWM遞送至像素之電流之時序。包含各種類型補償及驅動方案之OLED之控制電路系統之設計已成為備受關注之課題且已提出諸多方法。此等補償電路另外亦可存在於具有三個或更多個堆疊之堆疊式OLED之控制電路系統中。 Note that variations in the threshold voltage ( Vth ), carrier mobility or series resistance will directly affect the uniformity of the OLED current driving the TFT and therefore the brightness of the image display. One major factor affecting non-uniform current is variations in the threshold voltage ( Vth ) of the OLED drive transistors. The pixel may require control circuitry to make other types of compensation, such as aging, degradation or burn-in of the OLED material over time, unevenness or non-uniformity over the active area or voltage drops in metal interconnects. In addition, the control circuitry provided by the TFT may need to control the timing of the current delivered to the pixel, such as by PWM. The design of control circuit systems for OLEDs including various types of compensation and driving schemes has become a topic of much attention and many methods have been proposed. These compensation circuits may also be present in control circuit systems for stacked OLEDs having three or more stacks.

意外發現,具有三個或更多個堆疊之OLED堆疊所需之高電壓/電流可由包括具有其等通道串聯連接之至少兩個電晶體之一控制電路處置。此有時被稱為「堆疊式電晶體」。期望,串聯連接電晶體中之一者係一低電壓驅動電晶體且另一者係一開關電晶體。此配置允許在TFT沒有顯著電流洩漏之情況下驅動OLED像素,以使得在不損失對比度之情況下獲得高亮度。It was unexpectedly discovered that the high voltage/current required for an OLED stack having three or more stacks can be handled by a control circuit comprising at least two transistors having their channels connected in series. This is sometimes referred to as a "stacked transistor". Desirably, one of the series-connected transistors is a low voltage drive transistor and the other is a switching transistor. This configuration allows the OLED pixel to be driven without significant current leakage from the TFT, so that high brightness is obtained without loss of contrast.

確切而言,驅動TFT與開關電晶體係串聯連接的,以使得驅動電晶體之一第一端子電連接至(且更靠近)一外部電源,驅動電晶體之一第二端子電連接至開關電晶體之一第一端子且開關電晶體之一第二端子電連接至(且更靠近) OLED堆疊之底部電極。此一配置允許OLED堆疊以比為不發生大量電流洩漏或不會實體損壞低電壓電晶體而設計之個別電晶體高的一較電壓操作。Specifically, the driving TFT and the switching transistor are connected in series so that a first terminal of the driving transistor is electrically connected to (and closer to) an external power source, a second terminal of the driving transistor is electrically connected to a first terminal of the switching transistor, and a second terminal of the switching transistor is electrically connected to (and closer to) the bottom electrode of the OLED stack. This configuration allows the OLED stack to operate at a higher voltage than individual transistors designed without significant current leakage or physical damage to the low voltage transistors.

圖2中展示此基本控制電路配置,其中一p通道驅動電晶體T1在一第一端子(就p通道電晶體而言,源極)上連接至V DD(外部電源)且在一第二端子(在p通道電晶體中,汲極)上連接至一開關電晶體T2。經由資料線及一直列選擇電晶體T3控制驅動電晶體T1之閘極,直列選擇電晶體T3之閘極係透一選擇線SELECT1控制。開關電晶體T2在一第一端子(源極)上自T1之第二端子接收電流(當接通T1時)且在一第二端子(汲極)上連接至OLED之底部電極。開關電晶體T2之閘極由選擇線SELECT2直接控制。驅動電晶體T1及開關電晶體T2串聯連接。當選擇「接通」T1及T2時,電流流動至OLED堆疊之底部電極且OLED堆疊發光。若選擇T2「關斷」,則無論T1是「接通」還是」關斷」,沒有電流流動至OLED堆疊。在某些實施例中,開關電晶體T2可提供一開閉功能以防止運動模糊。若T1係「關斷」的,則無論T2是「接通」還是」關斷」,OLED將不發光。 This basic control circuit configuration is shown in FIG2 , where a p-channel driver transistor T1 is connected to V DD (external power supply) at a first terminal (source in the case of a p-channel transistor) and to a switch transistor T2 at a second terminal (drain in the case of a p-channel transistor). The gate of the driver transistor T1 is controlled via the data line and a series select transistor T3, the gate of which is controlled via a select line SELECT1. The switch transistor T2 receives current from the second terminal of T1 at a first terminal (source) (when T1 is turned on) and is connected to the bottom electrode of the OLED at a second terminal (drain). The gate of the switch transistor T2 is directly controlled by the select line SELECT2. The driving transistor T1 and the switching transistor T2 are connected in series. When T1 and T2 are selected to be "on", current flows to the bottom electrode of the OLED stack and the OLED stack emits light. If T2 is selected to be "off", no current flows to the OLED stack regardless of whether T1 is "on" or "off". In some embodiments, the switching transistor T2 can provide an on-off function to prevent motion blur. If T1 is "off", no matter whether T2 is "on" or "off", the OLED will not emit light.

在圖2中,具有位於V DD與OLED電極之底部電極之間的至少兩個串聯連接電晶體之背板之控制電路系統係一驅動電晶體及一開關電晶體。在此應用中,一驅動電晶體具有根據正在顯示之影像將流動至OLED像素之電壓及電流調節至一適當位準的功能,且一開關電晶體具有接通及關斷流動至OLED像素之電流以提供一開閉功能的用途。舉例而言,在微顯示器之操作期間,開關電晶體T2中斷自驅動電晶體T1流動至OLED堆疊之底部電極之電力,因此在圖框時間之一部分內不發光(黑色)。此不同於掃描電晶體T3,掃描電晶體T3僅在圖框時間之一非常小部分內(例如,對於具有1200列之一顯示器而言,1/1200)接通以給一儲存電容器充電(圖2中未展示)。通常,在相同最大操作電壓下,一開關電晶體之大小可小於一驅動電晶體。然而,若需要開關電晶體像在具有三個或更多個堆疊之一OLED之控制電路系統中一樣處置較,則其可大於驅動電晶體且額定為一較高電壓。 In Figure 2, the control circuitry of the backplane having at least two series connected transistors between VDD and the bottom electrode of the OLED electrode is a driver transistor and a switch transistor. In this application, a driver transistor has the function of regulating the voltage and current flowing to the OLED pixel to an appropriate level according to the image being displayed, and a switch transistor has the purpose of turning the current flowing to the OLED pixel on and off to provide a switching function. For example, during operation of the microdisplay, the switch transistor T2 interrupts the power flowing from the driver transistor T1 to the bottom electrode of the OLED stack, and therefore does not emit light (black) during a portion of the frame time. This is different from the scanning transistor T3, which is turned on only for a very small fraction of the frame time (e.g., 1/1200 for a display with 1200 rows) to charge a storage capacitor (not shown in FIG. 2 ). Typically, a switching transistor can be smaller in size than a driving transistor at the same maximum operating voltage. However, if the switching transistor needs to be handled more like in the control circuitry of an OLED with three or more stacks, it can be larger than the driving transistor and rated for a higher voltage.

期望,驅動電晶體(T1)比開關電晶體(T2)更靠近電源V DD,開關電晶體(T2)更靠近OLED之底部電極。較佳地至少驅動電晶體係一p通道MOSFET電晶體,且更佳地,驅動電晶體及開關電晶體兩者皆係p通道MOSFET電晶體。兩個串聯連接電晶體可皆為LV,皆為MV,或者一個LV電晶體及一個MV電晶體。較佳地其皆為LV電晶體以減小像素電路之過大小。然而,在某些實施例中,驅動電晶體係LV而開關電晶體係MV。 Desirably, the driver transistor (T1) is closer to the power supply VDD than the switch transistor (T2), which is closer to the bottom electrode of the OLED. Preferably at least the driver transistor is a p-channel MOSFET transistor, and more preferably, both the driver transistor and the switch transistor are p-channel MOSFET transistors. The two series-connected transistors can be both LV, both MV, or one LV transistor and one MV transistor. Preferably they are both LV transistors to reduce oversizing of the pixel circuit. However, in some embodiments, the driver transistor is LV and the switch transistor is MV.

儘管圖2中僅圖解說明p通道電晶體,可使用n通道電晶體或n通道電晶體與p通道電晶體之一混合。在此等情形中,將需要鑒於通道電晶體與p通道電晶體之間的極性差異適當地重新配置電路系統。此外,此控制電路中視需要可包含其他微電子組件,例如其他電晶體、電容器及電阻器。Although only p-channel transistors are illustrated in FIG. 2 , n-channel transistors or a mixture of n-channel transistors and one of the p-channel transistors may be used. In such cases, the circuit system will need to be appropriately reconfigured in view of the polarity difference between the n-channel transistor and the p-channel transistor. In addition, other microelectronic components such as other transistors, capacitors, and resistors may be included in this control circuit as desired.

此項技術中已知,MOSFET電晶體需要一本徵主體二極體連接來視需要發揮效能。由於一MOSFET電晶體之結構,固有地存在一寄生二極體且該寄生二極體可影響電晶體之操作。通常,本徵主體二極體在內部或外部連接至一電源以施加一偏壓。此等主體連接亦被稱為「塊體連接」或「電晶體井」以及其他術語。在圖3中展示此種連接,在圖3中IBD1、IBD2及IBD3係連接至一單獨電壓源V DD2之本徵主體二極體(對於T1、T2及T3而言)。此等電晶體可共用同一井以實現本徵主體二極體連接。然而,用於為T1及T2供應電力之同一電源V DD亦可用於IBD;即,V DD及V DD2係一共同源。 It is known in the art that MOSFET transistors require an intrinsic body diode connection to function as desired. Due to the structure of a MOSFET transistor, a parasitic diode is inherently present and can affect the operation of the transistor. Typically, the intrinsic body diode is connected to a power supply internally or externally to apply a bias. These body connections are also called "bulk connections" or "transistor wells" and other terms. Such a connection is shown in Figure 3, where IBD1, IBD2 and IBD3 are intrinsic body diodes (for T1, T2 and T3) connected to a separate voltage source VDD2 . These transistors can share the same well to achieve the intrinsic body diode connection. However, the same power supply V DD used to power T1 and T2 can also be used for IBD; that is, V DD and V DD2 are a common source.

然而,可期望電晶體中之一或多者在其位於Si背板上之單獨井中浮動以避免超出組件中之任一者之操作電壓範圍。確切而言,當第一驅動電晶體及開關電晶體兩者皆係p通道電晶體時,每一電晶體可位於其自己單獨的n井中。與兩個電晶體皆位於同一n井中可達成之動態電壓範圍相比,此准許動態電壓範圍更大以達到對OLED之控制。串聯連接電晶體使用隔離、浮動或不同井在此項技術中係已知的,例如參見US9066379、US5764077、US7768299、US9728528及JP2016200828。However, it may be desirable to float one or more of the transistors in their separate wells on the Si backplane to avoid exceeding the operating voltage range of any of the components. Specifically, when both the first drive transistor and the switch transistor are p-channel transistors, each transistor may be located in its own separate n-well. This allows a larger dynamic voltage range to achieve control of the OLED than can be achieved if both transistors are located in the same n-well. Series connection of transistors using isolated, floating or different wells is known in the art, see, for example, US9066379, US5764077, US7768299, US9728528 and JP2016200828.

此在圖4中予以圖解說明,在圖4中T1佔用其自己的井,如虛線所指示,且經由IBD1透過與V DD2之一連接被施加偏壓;且T2佔用一不同井,如虛線所指示,由與電晶體源(V DD)之一不同單獨連接IBD2加偏壓。在圖4之實施例中,施加至每一IBD之偏壓係不同的且因此每一n井彼此獨立。 This is illustrated in Figure 4 where T1 occupies its own well, as indicated by the dashed line, and is biased via IBD1 through a connection to one of VDD2 , and T2 occupies a different well, as indicated by the dashed line, and is biased by a separate connection IBD2 to one of the transistor sources ( VDD ). In the embodiment of Figure 4, the bias applied to each IBD is different and therefore each n-well is independent of the others.

圖2至圖4中所展示之實施例在設計及用於驅動具有三個或更多個堆疊之一OLED之操作方面具有幾個優點。在設計中,由於所有電晶體皆為相對小LV電晶體,如一般在大多數晶圓代工廠中常見的,因此此電路可非常緊湊。所有電晶體可皆為p通道電晶體,所有n井皆被加偏壓至V DD,此使得不需要隔離井或浮動井。此等特徵可允許解析度非常高及大小很小之微顯示器設計具有非常緊湊像素電路設計。 The embodiments shown in FIGS. 2-4 have several advantages in design and operation for driving an OLED having three or more stacks. In design, the circuit can be very compact because all transistors are relatively small LV transistors, as is common in most foundries. All transistors can be p-channel transistors, and all n-wells are biased to V DD , which eliminates the need for isolation wells or floating wells. These features can allow very high resolution and very small size microdisplay designs with very compact pixel circuit designs.

圖5A展示具有三個串聯電晶體之一控制電路。圖5A中所展示之電路類似於圖2中所展示之電路,但在圖5A中一第三電晶體T4串聯連接於電源V DD與驅動電晶體T1之源極之間。如所展示,T4之閘極係由資料線及一直列選擇電晶體T5控制,直列選擇電晶體T5之閘極係由一選擇線SELECT3控制。圖5A中之線SELECT2及SELECT3可以相同或不同電壓供應一信號,可同時或在不同時間切換,或可根據操作條件保留不切換。 FIG. 5A shows a control circuit having three series transistors. The circuit shown in FIG. 5A is similar to the circuit shown in FIG. 2 , but in FIG. 5A a third transistor T4 is connected in series between the power supply V DD and the source of the drive transistor T1. As shown, the gate of T4 is controlled by the data line and a column select transistor T5, the gate of which is controlled by a select line SELECT3. The lines SELECT2 and SELECT3 in FIG. 5A may be supplied with a signal at the same or different voltages, may be switched at the same time or at different times, or may be left unswitched depending on operating conditions.

期望,所添加電晶體T4可係一第二驅動電晶體以使得在電源V DD與OLED之底部電極之間係兩個驅動電晶體(T4及T1)及一個開關電晶體(T2),以上所有電晶體串聯。在此情形中,供應至T4之閘極之信號亦可與供應至T1之信號相同且可經由T3/SELECT1供應。雖然圖5A展示以一個資料線及兩個選擇線來進行資料控制之一設計,但可使用具有兩個資料線及一個選擇線之一類似設計。 Desirably, the added transistor T4 may be a second driver transistor so that between the power supply VDD and the bottom electrode of the OLED are two driver transistors (T4 and T1) and a switch transistor (T2), all in series. In this case, the signal supplied to the gate of T4 may also be the same as the signal supplied to T1 and may be supplied via T3/SELECT1. Although FIG. 5A shows a design with one data line and two select lines for data control, a similar design with two data lines and one select line may be used.

在存在三個或更多個串聯電晶體之實施例中,該等電晶體可係LV電晶體與MV電晶體之一組合。較佳地,該等電晶體全部皆係LV電晶體以減小像素電路之大小。此等多個電晶體可係p通道電晶體、n通道電晶體或一混合。較佳地所有電晶體皆係p通道電晶體。若存在n通道電晶體與p通道電晶體之一混合,則較佳地至少一個驅動電晶體係一p通道電晶體且更佳地係一LV電晶體。開關電晶體較佳地係LV電晶體;然而,當必須擴大背板電路之操作範圍同時遵循個別電晶體之電壓限制時,可期望使用一或多個MV開關電晶體。In embodiments where there are three or more series transistors, the transistors may be a combination of LV transistors and one of MV transistors. Preferably, all of the transistors are LV transistors to reduce the size of the pixel circuit. These multiple transistors may be p-channel transistors, n-channel transistors, or a mixture. Preferably all transistors are p-channel transistors. If there is a mixture of n-channel transistors and one of p-channel transistors, preferably at least one drive transistor is a p-channel transistor and more preferably an LV transistor. The switching transistors are preferably LV transistors; however, when the operating range of the backplane circuit must be expanded while complying with the voltage limitations of the individual transistors, it may be desirable to use one or more MV switching transistors.

在多個串聯電晶體中之任一者係一種類型之情形中,相同型之多個共同電晶體可共用相同井以減小設計大小。然而,為擴大背板電路之操作範圍同時遵循個別電晶體之電壓限制,可必須將相同型之電晶體置於單獨井區中。In the case where any of the multiple series transistors is of one type, multiple common transistors of the same type can share the same well to reduce the design size. However, to expand the operating range of the backplane circuit while complying with the voltage limitations of the individual transistors, it may be necessary to place transistors of the same type in separate wells.

圖5B展示具有與圖5A中所展示之驅動電晶體類似之兩個驅動電晶體之一控制電路之一示意性,其中兩個驅動電晶體係由一位準移位電路(LSC)控制。一位準移位電路係用於將信號自一個邏輯位準或電壓域轉化為另一邏輯位準或電壓域的一電路,通常用於解決一系統之各個部分之間的電壓不相容。為清晰起見,不展示內部組件及通向LSC之所有連接(例如V DD、接地及其他可能輸入連接)。在此實施例中,LSC基於信號SELECT1及來自資料線之信號設定驅動電晶體T4及T1之閘極電壓,以使得跨T4及T1之總電壓始終大約相等地分離於兩個驅動電晶體之間。眾所周知,小邏輯電晶體可用於此功能。 FIG5B shows a schematic of a control circuit with two drive transistors similar to those shown in FIG5A, where the two drive transistors are controlled by a level shift circuit (LSC). A level shift circuit is a circuit used to convert signals from one logical level or voltage domain to another logical level or voltage domain, often used to resolve voltage incompatibilities between portions of a system. For clarity, the internal components and all connections to the LSC (e.g., VDD , ground, and other possible input connections) are not shown. In this embodiment, LSC sets the gate voltages of driver transistors T4 and T1 based on signal SELECT1 and the signal from the data line so that the total voltage across T4 and T1 is always approximately equally split between the two driver transistors. As is known, small logic transistors can be used for this function.

OLED型微顯示器通常在背板之MOSFET型控制電路系統中含有一保護電路以限制流過電晶體之電量以防止損壞。期望OLED具有三個或更多個堆疊式單元之微顯示器之背板之控制電路系統中包含一保護電路以達到此目的,此乃因使此等裝置發射所需之功率相對高。一保護電路應維持或「箝位」OLED之底部電極處之電壓,以使得在OLED不發射時該電壓不低於一所期望電壓位準。此等保護電路亦可被稱為「電壓維持」電路。OLED type microdisplays typically contain a protection circuit in the MOSFET type control circuitry of the backplane to limit the amount of electricity flowing through the transistors to prevent damage. It is desirable to include a protection circuit in the control circuitry of the backplane of an OLED microdisplay having three or more stacked cells to achieve this goal, since the power required to make these devices emit is relatively high. A protection circuit should maintain or "clamp" the voltage at the bottom electrode of the OLED so that it does not fall below a desired voltage level when the OLED is not emitting. Such protection circuits may also be referred to as "voltage holding" circuits.

為保護控制電路系統中存在之低電壓電晶體且保持於晶圓代工廠所設定的電晶體之規定操作範圍內,將期望保護電路維持像素之堆疊式OLED之底部電極處之一黑色位準電流(CV=0或像素「關斷」)係低於4 µA/cm2,或更期望針對一Vth大約為7.5 V之3單元堆疊式OLED維持於2 µA/cm2或低於2 µA/cm2。對於4單元堆疊式OLED裝置而言,期望類似黑色位準電流,且一典型Vth係大約10 V。To protect the low voltage transistors present in the control circuitry and to stay within the specified operating range of the transistors set by the foundry, the protection circuitry would be expected to maintain a black level current (CV = 0 or pixel "off") at the bottom electrode of the pixel's stacked OLED below 4 µA/cm2, or more desirably at or below 2 µA/cm2 for a 3-cell stacked OLED with a Vth of about 7.5 V. Similar black level currents are expected for 4-cell stacked OLED devices, with a typical Vth of about 10 V.

圖6展示與圖2中所展示之控制電路類似但增加了一保護電路之一示意性控制電路。在此特定實施例中,保護電路包括一p通道電晶體,該p通道電晶體在一端上連接至位於T2之汲極與OLED之底部電極之間的一節點且在另一端上連接至一電源(在此實例中,一參考電壓V REF(所有像素共用))。T6之閘極亦連接至節點。因此,二極體連接電晶體T6限制T2之最低汲極電壓以防止其崩潰。可存在其他電子組件作為此電路之一部分,其他電子組件未展示。此配置類似於 Kwak等人所闡述之配置,但p通道電晶體之一端連接至接地而非V REFFIG6 shows a schematic control circuit similar to that shown in FIG2 but with the addition of a protection circuit. In this particular embodiment, the protection circuit includes a p-channel transistor connected on one end to a node between the drain of T2 and the bottom electrode of the OLED and on the other end to a power source (in this example, a reference voltage V REF (common to all pixels)). The gate of T6 is also connected to the node. Thus, the diode-connected transistor T6 limits the minimum drain voltage of T2 to prevent it from crashing. There may be other electronic components as part of this circuit, which are not shown. This configuration is similar to that described by Kwak et al., but one end of the p-channel transistor is connected to ground instead of V REF .

然而,使用具有三個或更多個單元之一OLED之較高電壓要求所致的問題在使用一保護電路利用圖6中所展示之一MOSFET電晶體例時仍存在。在此實施例中,與使用一MV驅動電晶體及開關電晶體且去掉保護電路相比,使用一LV或MV MOSFET電晶體(即,T6)達成對LV驅動電晶體及開關電晶體之保護並不會使得像素設計顯著變小。However, the problems caused by the higher voltage requirements of using an OLED with three or more cells still exist when using a protection circuit with a MOSFET transistor example shown in Figure 6. In this embodiment, the use of a LV or MV MOSFET transistor (i.e., T6) to achieve protection for the LV drive transistor and switch transistor does not make the pixel design significantly smaller than using a MV drive transistor and switch transistor and eliminating the protection circuit.

圖7展示與圖6中所展示之保護電路類似之一保護電路,但在圖7中p通道電晶體T6被二極體D4取代。期望,保護電路中之二極體D4係一p-n接面二極體。一p-n二極體係允許電在一個方向上而不在另一(相反)方向上流動的一電路元件。P-n二極體可在容易電流流動之方向上具有一正向偏壓或在電流流動很少或沒有電流流動之情況下具有一反向偏壓。此p-n二極體可以不同方式形成於CMOS設計中;舉例而言,作為在一n井中具有高度摻雜p區之一垂直二極體。D4在一端上連接至位於T2之汲極與OLED之底部電極之間的一節點,且在另一端上連接至一電源45,電源45係一參考電壓V REF或一參考電流I REFFIG. 7 shows a protection circuit similar to the protection circuit shown in FIG. 6 , but in FIG. 7 the p-channel transistor T6 is replaced by a diode D4. Desirably, the diode D4 in the protection circuit is a pn junction diode. A pn diode is a circuit element that allows electricity to flow in one direction but not in the other (opposite) direction. A pn diode can have a forward bias in the direction where current flows easily or a reverse bias where little or no current flows. This pn diode can be formed in a CMOS design in different ways; for example, as a vertical diode with a highly doped p region in an n-well. D4 is connected on one end to a node between the drain of T2 and the bottom electrode of the OLED, and on the other end to a power source 45, which is a reference voltage VREF or a reference current IREF .

圖8展示與圖7中所展示之保護電路類似之一保護電路。在圖8中,保護電路之二極體D4具體而言係BJT1、一BJT (雙極接面電晶體),BJT之集電極(C)連接至V DD,射極(E)連接至T2與OLED堆疊之底部電極之間的一節點且基極(B)連接至一電源50,電源50係一電壓源V PROTECT或一電流源I PROTECT。在保護電路中使用一BJT之一個益處係電流自基極電流放大為集電極電流。若期望,BJT之集電極可連接至與V DD不同之一單獨電源。電源V PROTECT或I PROTECT可由所有像素共用。應注意,V PROTECT或I PROTECT可係恆定的或可不恆定,而是可根據想要OLED發射還是不發射而變化。此可在與一開關電晶體搭配使用時有利於透過開閉減小顯示器之持久度。在圖8A中,BJT1係一「NPN」型BJT電晶體(較佳),但亦可係在設計上存在適當改變之一「PNP」電晶體。 FIG8 shows a protection circuit similar to the protection circuit shown in FIG7 . In FIG8 , the diode D4 of the protection circuit is specifically BJT1 , a BJT (bipolar junction transistor) with the collector (C) connected to V DD , the emitter (E) connected to a node between T2 and the bottom electrode of the OLED stack and the base (B) connected to a power source 50 , which is a voltage source V PROTECT or a current source I PROTECT . One benefit of using a BJT in the protection circuit is that the current is amplified from the base current to the collector current. If desired, the collector of the BJT can be connected to a separate power source different from V DD . The power source V PROTECT or I PROTECT can be shared by all pixels. It should be noted that V PROTECT or I PROTECT may or may not be constant, but may vary depending on whether the OLED is desired to emit or not emit. This may be useful when used with a switching transistor to reduce the durability of the display by switching. In FIG. 8A , BJT1 is an “NPN” type BJT transistor (preferably), but may also be a “PNP” transistor with appropriate changes in design.

就一NPN型BJT而言,每當OLED之底部電極處之射極電壓V E大於基極電壓V B且V B小於集電極電壓V C(V E> V B< V C)時,BJT將處於關閉模式中且沒有電流經過。然而,每當OLED之底部電極處之電壓V E小於電壓V B且V B小於V C(V E< V B< V C)時,BJT將處於正向作用模式中。在此模式中,基極-射極接面被加正向偏壓且基極-集電極接面被加反向加偏壓,且因此集電極-射極電流將大約與基極電流成比例。 For an NPN type BJT, whenever the emitter voltage VE at the bottom electrode of the OLED is greater than the base voltage VB and VB is less than the collector voltage VC ( VE > VB < VC ), the BJT will be in the off mode and no current will flow. However, whenever the voltage VE at the bottom electrode of the OLED is less than the voltage VB and VB is less than VC ( VE < VB < VC ), the BJT will be in the forward acting mode. In this mode, the base-emitter junction is forward biased and the base-collector junction is reverse biased, and therefore the collector-emitter current will be approximately proportional to the base current.

因此,在圖8A中,若BJT1之V C係V DD且V PROTECT(其係V B)被設定為小於OLED之V th,則每當底部電極處之電壓V E高於V th+ V CATHODE時,BJT1「關斷」,但每當V E降低至低於V th+ V CATHODE時(即,每當T1或T2「關斷」時),底部電極處之電壓維持為大約V th。因此,保護電路經設計以每當需要時提供充分電流,以每當陰極電壓減小至(更負電壓)低於某一值時保護驅動電晶體及開關電晶體在其端子兩側不會具有超出其額定值之電壓。此外,藉由將基極電壓B (V PROTECT)設定為低於OLED之接通電壓(V th高於V cathode),每當遞送至OLED之底部電極之電壓大於或等於V th時功率損耗得以最小化。 Thus, in FIG8A , if VC of BJT1 is VDD and VPROTECT (which is VB ) is set to be less than Vth of the OLED, then whenever the voltage VE at the bottom electrode is above Vth + VCATHODE , BJT1 is “off”, but whenever VE decreases below Vth + VCATHODE (i.e., whenever T1 or T2 is “off”), the voltage at the bottom electrode is maintained at approximately Vth . Thus, the protection circuit is designed to provide sufficient current whenever needed to protect the drive transistor and the switching transistor from having voltages on either side of their terminals that exceed their rated values whenever the cathode voltage decreases (to a more negative voltage) below a certain value. Furthermore, by setting the base voltage B (V PROTECT ) below the turn-on voltage of the OLED (V th is higher than V cathode ), power loss is minimized whenever the voltage delivered to the bottom electrode of the OLED is greater than or equal to V th .

在利用圖8中所展示之保護電路之某些實施例中,將BJT之基極電壓(V B)與任何外部電源隔離。即,電源V PROTECT或I PROTECT與BJT之基極之間不存在電連接。BJT實體地存在圖8中所展示之現有集電極與射極連接,但仍存在之基極連接不連接至任何外部源。在此等情形中,不特意將V B維持於任何特定值,亦不特意對V B施加任何電壓或電流。允許V B獨立於電壓V C及V E「浮動」,電壓V C及V E係操作OLED之作用控制電路系統之一部分。然而,在背板內可存在寄生電流路徑,該等寄生電流路徑在內部在高阻擋條件下對基極加偏壓。注意,在此類實施例中,由於電路系統內產生寄生電流,因此V B可在OLED之操作期間變化。 In certain embodiments utilizing the protection circuit shown in FIG8, the base voltage ( VB ) of the BJT is isolated from any external power source. That is, there is no electrical connection between the power source VPROTECT or IPROTECT and the base of the BJT. The BJT physically has the existing collector and emitter connections shown in FIG8, but the base connection that remains is not connected to any external source. In these cases, VB is not intentionally maintained at any particular value, nor is any voltage or current intentionally applied to VB . VB is allowed to "float" independently of voltages VC and VE , which are part of the action control circuitry that operates the OLED. However, there may be parasitic current paths within the backplane that bias the base internally under high impedance conditions. Note that in such embodiments, VB may vary during operation of the OLED due to parasitic currents generated within the circuitry.

在其他實施例中,BJT之V B可係自偏壓的(有時被稱為具有一「基極偏壓」)。當BJT係自偏壓時,沒有外部控制輸入信號施加至BJT之基極,而是施加至BJT基極之信號由一恆定供應電壓(即,V DD)之值及與電晶體連接之任何偏壓電阻器之值設定。一種達成BJT基極自偏壓之方法形成一「固定基極偏壓電路」。在此配置中,BJT之基極連接至具有一單個限流電阻器之恆定電源供應器(即V DD)。此將允許BJT之基極電流(I B)恆定地保持為一給定值V DD,且因此BJT之操作點亦保持固定。另一選擇為,一簡單分壓器網路可提供所需偏壓電壓。注意,在此類實施例中,每一像素內之偏壓電壓及所得寄生電流將對OLED之操作做出回應。此一回應可為電晶體提供有效保護。 In other embodiments, the VB of the BJT may be self-biased (sometimes referred to as having a "base bias"). When the BJT is self-biased, no external control input signal is applied to the base of the BJT, but rather the signal applied to the base of the BJT is set by the value of a constant supply voltage (i.e., VDD ) and the value of any bias resistors connected to the transistor. One method of achieving self-biasing of the base of the BJT forms a "fixed base bias circuit." In this configuration, the base of the BJT is connected to a constant power supply (i.e., VDD ) with a single current limiting resistor. This will allow the base current (I B ) of the BJT to be kept constant at a given value V DD , and therefore the operating point of the BJT is also kept fixed. Alternatively, a simple voltage divider network can provide the required bias voltage. Note that in such embodiments, the bias voltage and resulting parasitic current within each pixel will respond to the operation of the OLED. This response can provide effective protection for the transistors.

圖9係圖8中所展示之電路之電晶體井之一示意性剖面圖示。注意,T1、T2、T3可各自位於單獨的但未隔離或浮動之n井中,該等n井連接至V DD且全部與BJT1 (一NPN BJT)之p井分隔開。為方便起見,針對T1、T2及T3標記出源(s)區、閘極(g)區及汲極(d)區。類似地,針對BJT1標記出射極(e)、基極(b)及集電極(c)區。BJT1之集電極(c)區展示為透過深n井連接至V DD,但在某些實施例中另一選擇為其可直接連接至V DDFIG9 is a schematic cross-sectional illustration of the transistor wells of the circuit shown in FIG8. Note that T1, T2, T3 may each be located in a separate but non-isolated or floating n-well connected to VDD and all separated from the p-well of BJT1 (an NPN BJT). For convenience, the source (s), gate (g) and drain (d) regions are labeled for T1, T2 and T3. Similarly, the emitter (e), base (b) and collector (c) regions are labeled for BJT1. The collector (c) region of BJT1 is shown as being connected to VDD through a deep n-well, but in some embodiments it may alternatively be connected directly to VDD .

圖9亦指示IBD5,IBD5係連接至Si基板之深n井之V DD之本徵主體二極體,Si基板中定位有所有電晶體以及IBD6,IBD6係連接至整個Si基板之接地的本徵主體二極體。應注意,保護電路中之BJT可係一NPN電晶體或PNP電晶體。若BJT係一NPN電晶體,則電晶體位於一p井中;而若BJT係一PNP電晶體,則其將位於一n井中。 Figure 9 also indicates IBD5, which is an intrinsic body diode connected to VDD of the deep n-well of the Si substrate in which all transistors are located, and IBD6, which is an intrinsic body diode connected to ground of the entire Si substrate. It should be noted that the BJT in the protection circuit can be an NPN transistor or a PNP transistor. If the BJT is an NPN transistor, the transistor is located in a p-well; if the BJT is a PNP transistor, it will be located in an n-well.

使用包括一BJT之一保護電路係較佳的。當用作包括具有其等通道串聯連接之至少兩個電晶體之一控制電路之一部分時,BJT電晶體設計之像素大小較小。另外,一正向主動模式BJT之內在放大因子意指一相對小寄生電流可產生一更大保護電流。因此,來自參考/保護電壓源之電流更小且參考電壓互連件上之電壓降極大地減小。It is preferred to use a protection circuit comprising a BJT. When used as part of a control circuit comprising at least two transistors having their equal channels connected in series, the pixel size of the BJT transistor design is smaller. In addition, the inherent amplification factor of a forward active mode BJT means that a relatively small parasitic current can produce a larger protection current. Therefore, the current from the reference/protection voltage source is smaller and the voltage drop on the reference voltage interconnect is greatly reduced.

除維持底部電極處之一最小電壓低於OLED之臨限值電壓之外,保護電路亦可經設計以藉由包含其他適當電路組件來防止其他不期望效應,例如短路保護、瞬時峰值等。然而,在某些例項中,當使用本發明之堆疊式OLED時,其仍可用於將此類已知類型之保護電路系統包含於像素電路中。In addition to maintaining a minimum voltage at the bottom electrode below the critical voltage of the OLED, the protection circuit can also be designed to prevent other undesirable effects by including other appropriate circuit components, such as short circuit protection, transient spikes, etc. However, in some examples, when the stacked OLED of the present invention is used, it can still be used to include such known types of protection circuit systems in the pixel circuit.

對於諸多OLED堆疊而言,尤其是包括三個發光單元之OLED堆疊,期望在控制電路系統中在開關電晶體之第二端子與OLED之底部電極之間的電連接中不存在介入性電晶體,如圖2至圖5中所展示。所提及之介入,意指在開關電晶體與OLED之間的電連接中,電流不直接通過另一電晶體(即,電晶體之一個端子連接至開關電晶體,而另一端子連接至OLED以使得在OLED之操作期間電流將在某些點處通過介入性電晶體)。可存在直列於開關電晶體與OLED之間的其他(非電晶體)微電子組件。For many OLED stacks, especially those including three light-emitting cells, it is desirable that there be no intervening transistor in the electrical connection between the second terminal of the switching transistor and the bottom electrode of the OLED in the control circuitry, as shown in FIGS. 2 to 5 . By intervening, it is meant that the current does not pass directly through another transistor in the electrical connection between the switching transistor and the OLED (i.e., one terminal of the transistor is connected to the switching transistor and the other terminal is connected to the OLED so that the current will pass through the intervening transistor at some point during operation of the OLED). There may be other (non-transistor) microelectronic components in series between the switching transistor and the OLED.

在開關電晶體OLED連接與一微電子組件(即,一非介入式電晶體或二極體)之一第一端子之間可存在一支線(意指不直接直列)連接,其中OLED操作電流不直接通過非介入式電晶體或二極體。舉例而言,此配置在圖4至圖6中加以圖解說明,其中一非介入式組件的一側連接至T2-OLED連接且另一側連接至一電源。There may be a spur (meaning not directly in-line) connection between the switch transistor OLED connection and a first terminal of a microelectronic component (i.e., a non-interfering transistor or diode) where the OLED operating current does not pass directly through the non-interfering transistor or diode. For example, this configuration is illustrated in Figures 4 to 6 where one side of a non-interfering component is connected to the T2-OLED connection and the other side is connected to a power source.

期望,驅動電晶體係一低電壓(LV)電晶體。即,驅動電晶體經設計且經設定大小以在5 V或低於5 V下安全且有效地操作,而無論或不考慮電路中之實際負載。此必然有助於將像素大小最小化以將微顯示器解析度最大化。應注意,具有三個或更多個OLED單元且受驅動電晶體驅動之一OLED堆疊將通常需要超過7.5 V之電壓。若需要,可使用位於單獨井中之兩個或更多個串聯連接低電壓驅動電晶體(如圖2c中所展示)以進一步減輕較高電壓之效應。Desirably, the drive transistor is a low voltage (LV) transistor. That is, the drive transistor is designed and sized to operate safely and efficiently at 5 V or less, regardless of or irrespective of the actual load in the circuit. This necessarily helps to minimize the pixel size to maximize the microdisplay resolution. It should be noted that an OLED stack having three or more OLED cells and driven by a drive transistor will typically require voltages in excess of 7.5 V. If desired, two or more series-connected low voltage drive transistors in separate wells (as shown in FIG. 2 c ) may be used to further mitigate the effects of the higher voltage.

期望驅動電晶體係一p通道薄膜電晶體(亦被稱為一p通道MOSFET (金屬氧化物半導體場效電晶體))。p通道電晶體之結構、特性及製備係眾所周知的。當驅動電晶體係一p通道電晶體時,其源極電連接至一外部電源,且其汲極電連接至開關電晶體之一第一端子。驅動電極之閘極由與電源分離之一資料線控制。The drive transistor is preferably a p-channel thin film transistor (also known as a p-channel MOSFET (metal oxide semiconductor field effect transistor)). The structure, characteristics and preparation of p-channel transistors are well known. When the drive transistor is a p-channel transistor, its source is electrically connected to an external power source and its drain is electrically connected to a first terminal of the switch transistor. The gate of the drive electrode is controlled by a data line that is separate from the power source.

當OLED堆疊包括三個OLED發光單元時,期望開關電晶體係一低電壓電晶體。即,開關電晶體經設計且經設定大小以在5 V或小於5 V下安全且有效地操作,而無論或不考慮電路中之實際負載。OLED操作所需之電流流過此電晶體以及驅動電晶體。When the OLED stack includes three OLED light-emitting units, it is desirable that the switching transistor is a low voltage transistor. That is, the switching transistor is designed and sized to operate safely and efficiently at 5 V or less, regardless of or without regard to the actual load in the circuit. The current required for OLED operation flows through this transistor and the drive transistor.

然而,若OLED堆疊包括四個或更多個OLED發光單元,則操作電壓可遠超過7.5 V且開關電晶體可視需要是中等電壓(舉例而言,設計為7.5 V至12 V)或高電壓(設計為18 V至25 V)。另一選擇為,共同或獨立選擇之兩個或更多個串聯連接開關電晶體可用於減輕較高電壓之效應。串聯連接多個開關電晶體可全部皆係LV或LV電晶體與MV電晶體之一混合。However, if the OLED stack includes four or more OLED light-emitting units, the operating voltage can be well over 7.5 V and the switching transistors can be medium voltage (designed for 7.5 V to 12 V, for example) or high voltage (designed for 18 V to 25 V) as desired. Alternatively, two or more series-connected switching transistors, selected together or independently, can be used to mitigate the effects of the higher voltages. The series-connected multiple switching transistors can all be LV or a mix of LV transistors and one of the MV transistors.

期望開關電晶體係一p通道電晶體。當開關電晶體係一p通道電晶體,其源極連接至驅動電晶體之汲極且其汲極電連接至OLED之底部電極。開關電極之閘極由一選擇線控制,該選擇線與電源以及控制驅動電晶體之資料線及選擇線分離。It is desirable that the switch transistor is a p-channel transistor. When the switch transistor is a p-channel transistor, its source is connected to the drain of the drive transistor and its drain is electrically connected to the bottom electrode of the OLED. The gate of the switch electrode is controlled by a select line that is separate from the power supply and the data line and the select line that control the drive transistor.

在某些實施例中,期望驅動電晶體及開關電晶體係p通道電晶體,其中驅動電晶體及開關電晶體兩者皆係低電壓電晶體,或者驅動電晶體係低電壓電晶體且開關電晶體係中等電壓或高電壓電晶體。在某些實施例中,亦期望控制電路系統中之所有電晶體皆係p通道電晶體。In some embodiments, it is desirable that the driver transistor and the switch transistor are p-channel transistors, wherein both the driver transistor and the switch transistor are low voltage transistors, or the driver transistor is a low voltage transistor and the switch transistor is a medium voltage or high voltage transistor. In some embodiments, it is also desirable that all transistors in the control circuit system are p-channel transistors.

儘管驅動電晶體及開關電晶體係電串聯連接的,兩個電晶體之間可存在其他介入性微電子組件。介入性組件可係直列的,其中驅動電晶體與開關電晶體之間的電流直接通過該直列組件。亦可有其他微電子組件電連接至驅動電晶體與開關電晶體之間的連接,以使得自驅動電晶體流動之電流亦流動至此額外組件以及開關電晶體。Although the driver transistor and the switch transistor are connected electrically in series, there may be other intervening microelectronic components between the two transistors. The intervening components may be in-line, where the current between the driver transistor and the switch transistor passes directly through the in-line component. There may also be other microelectronic components electrically connected to the connection between the driver transistor and the switch transistor, so that the current flowing from the driver transistor also flows to this additional component as well as the switch transistor.

在最基本形式之操作中,將一電壓自一外部電源供應至驅動電晶體。選擇線經設定以允許將正確資料電壓自資料線施加至驅動電晶體之閘極,從而允許來自電源之電流通過驅動電晶體而到達開關電晶體。開關電晶體之選擇線經設定以允許將正確電荷施加至開關電晶體,從而允許電流通過開關電晶體而到達每一個別像素中之OLED堆疊之底部陽極。此將像素「接通」且根據所接收到之電流發光。當所顯示之影像要求一個別像素不發射或減小發射時,可改變驅動電晶體之資料電壓以防止或限制電流流過驅動像素。In the most basic form of operation, a voltage is supplied to the drive transistors from an external power source. The select lines are set to allow the correct data voltage to be applied from the data lines to the gate of the drive transistors, thereby allowing current from the power source to flow through the drive transistors to the switching transistors. The select lines for the switching transistors are set to allow the correct charge to be applied to the switching transistors, thereby allowing current to flow through the switching transistors to the bottom anode of the OLED stack in each individual pixel. This turns the pixel "on" and it emits light according to the current received. When the image being displayed requires an individual pixel to not emit or reduce emission, the data voltage of the drive transistor can be changed to prevent or limit current flow through the driven pixel.

控制電路系統中之其他組件可用於控制由驅動電晶體供應之電流,控制當OLED「接通」時預計為OLED供電醉之電流或者當OLED預計「關斷」時經過驅動電晶體之電流洩漏。Other components in the control circuit system can be used to control the current supplied by the driving transistor, controlling the current that is intended to power the OLED when the OLED is "on" or the current that leaks through the driving transistor when the OLED is intended to be "off."

為藉由提供一開閉功能防止或最小化運動模糊,無論驅動電晶體(控制供應至其像素之功率)之操作如何(確切而言,當驅動電晶體「接通」(使電流通過)時),開關電晶體皆可防止電流流動至OLED。在像素之適當時間,開關電晶體可經選擇以使得即使將顯示之影像需要OLED像素係「接通」的OLED像素仍係「關斷」的。此允許顯示器中之像素之所有區段或旋轉區段「關斷」(不發射)以將微顯示器中之運動模糊之感知最小化。To prevent or minimize motion blur by providing a switching function, a switching transistor prevents current from flowing to the OLED regardless of the operation of the drive transistor (which controls the power supplied to its pixel) (specifically, when the drive transistor is "on" (allowing current to flow)). At the appropriate time for the pixel, the switching transistor can be selected so that the OLED pixel is "off" even if the image to be displayed requires the OLED pixel to be "on". This allows all segments or rotating segments of a pixel in the display to be "off" (not emitting) to minimize the perception of motion blur in the microdisplay.

在微顯示器中,可將電力以一可變電流或電壓形式自外部電源遞送至驅動電晶體,以驅動OLED堆疊從而遞送所期望照度位準。此係通常在寫入操作期間藉由給一儲存電容器充電進行儲存。功率位準可在外部電源處加以控制或若所遞送電力係恆定的,可藉由背板內之其他微電子電路將電力設定於適當位準。此被稱為「電流控制」且通常用於為大多數OLED裝置供電。另一選擇為,供應至OLED堆疊之電力可係恆定的且藉由與OLED像素「關斷」時間相較而言的OLED像素之完全「接通」時間來控制在一設定時間週期(圖框)內之光發射總量。此被稱為脈衝寬度調變或PWM控制。In a microdisplay, power can be delivered from an external power source in the form of a variable current or voltage to the driver transistors to drive the OLED stack and thereby deliver the desired illumination level. This is typically stored during write operations by charging a storage capacitor. The power level can be controlled at the external power source or if the power delivered is constant, the power can be set to the appropriate level by other microelectronic circuits in the backplane. This is called "current control" and is commonly used to power most OLED devices. Alternatively, the power supplied to the OLED stack can be constant and the total amount of light emitted within a set time period (frame) controlled by the time the OLED pixel is fully "on" compared to the time the OLED pixel is "off". This is called pulse width modulation or PWM control.

由於所闡述之控制電路能夠在無顯著洩漏或損壞之情況下應對比至少驅動電晶體之設計電壓或額定電壓高之電壓及電流需求,因此能夠使用發射量增大(且電壓較高)之OLED堆疊。具有2個發光單元且具有相對較低V th要求之串接OLED裝置所發射之光不像具有三個或更多個發光單元且具有相對較高V th要求之OLED堆疊那麼多。所闡述之電路可與一臨限值電壓(V th)大於7.5 V之一堆疊式發光OLED搭配使用;更期望,發光OLED堆疊之V th係至少10 V或大於10 V。另一選擇為,電路可與提供一光發射至少為2500尼特或較佳地至少為5000尼特之一全色彩微顯示器之一堆疊式OLED搭配使用。 Because the described control circuit can handle voltage and current requirements higher than at least the design voltage or rated voltage of the drive transistor without significant leakage or damage, an OLED stack with increased emission (and higher voltage) can be used. A tandem OLED device with two light-emitting cells and a relatively low Vth requirement does not emit as much light as an OLED stack with three or more light-emitting cells and a relatively high Vth requirement. The described circuit can be used with a stacked light-emitting OLED having a critical voltage ( Vth ) greater than 7.5 V; more desirably, the Vth of the light-emitting OLED stack is at least 10 V or greater. Alternatively, the circuit may be used with a stacked OLED that provides a full-color microdisplay having a light emission of at least 2500 nits or preferably at least 5000 nits.

有兩個基本方法來製作一像素化OLED微顯示器,其中必須經由一背板上之控制電路系統將電力供應至像素電極中之一者來控制每一個別像素之亮度。第一方法涉及使每一像素個別地產生紅色、綠色或藍色光(分別為R、G、B),或若係一單色顯示器則產生相同色彩。在此情形中,發光OLED堆疊可經配置以使得位於一個別底部電極區段上方之所有堆疊式發光單元發射相同色彩之光(自R光、G光或B光中選擇)以形成R、G及B像素。在具有此特徵之某些實施例中,每一色彩像素形成一微腔,在該微腔中區段底部電極與頂部電極之間的距離根據所發射光之色彩而定。在此情形中,微腔之長度將根據所發射色彩而定,且在像素為紅色、綠色及藍色時微腔之長度將不同。There are two basic approaches to making a pixelated OLED microdisplay, where the brightness of each individual pixel must be controlled by supplying power to one of the pixel electrodes via control circuitry on a backplane. The first approach involves having each pixel individually produce red, green, or blue light (R, G, B, respectively), or the same color if it is a monochrome display. In this case, the light-emitting OLED stack can be configured so that all stacked light-emitting units located above a respective bottom electrode segment emit the same color light (selected from R light, G light, or B light) to form R, G, and B pixels. In certain embodiments having this feature, each color pixel forms a microcavity in which the distance between the segment bottom electrode and the top electrode depends on the color of the emitted light. In this case, the length of the microcavity will depend on the color emitted, and will be different when the pixel is red, green, and blue.

第二方法係一彩色濾光器陣列(CFA)之所有像素具有一共同多模式(白色)發光OLED層以形成個別RGB像素。第二方法優於第一方法之優點係,不必針對不同方案形成個別OLED像素且因此將降低製造成本。The second method is to have all pixels of a color filter array (CFA) have a common multi-mode (white) emitting OLED layer to form individual RGB pixels. The advantage of the second method over the first method is that it is not necessary to form individual OLED pixels for different schemes and thus will reduce manufacturing costs.

堆疊式OLED內之個別OLED發光單元之數目僅受OLED之總厚度及控制電路系統處置操作OLED所需之電力之能力限制。當OLED單元之數目增大時,所發射之光總量增大,但封裝厚度、製造程序複雜性及臨限值電壓亦全部增大。具有至少三個堆疊式發光單元之一OLED將透過一串接(兩個OLED單元) OLED來增大照度。然而,較佳地OLED具有至少四個堆疊式OLED發光單元,且更佳地OLED具有至少五個堆疊式OLED發光單元。可構思具有六個甚至十個或更多個堆疊式OLED發光單元之一OLED。The number of individual OLED light cells within a stacked OLED is limited only by the overall thickness of the OLED and the ability of the control circuitry to handle the power required to operate the OLED. As the number of OLED cells increases, the total amount of light emitted increases, but the package thickness, manufacturing process complexity, and critical voltage all increase as well. An OLED having at least three stacked light cells will increase illumination over a series (two OLED cell) OLED. However, preferably the OLED has at least four stacked OLED light cells, and more preferably the OLED has at least five stacked OLED light cells. An OLED having six or even ten or more stacked OLED light cells is conceivable.

為將驅動一OLED堆疊所需之電壓之增大最小化,將電荷產生層(CGL;有時亦被稱為連接件或中間層)定位於個別OLED發光單元之間。此係由於CGL經構造以使得在施加電壓時產生電子及電洞,且將電子及電洞注入至毗鄰有機發射層。因此,使用一CGL可將一個所注入電子轉換成多個光子,以允許照度較高。確切而言,期望一CGL位於堆疊內之每一發光單元之間。然而,一光產生單元不必在兩側上具有一毗鄰CGL。堆疊之頂部及底部上之OLED光產生單元將通常僅具有一個毗鄰CGL。通常不必在一發光單元與頂部電極或底部電極中之一者之間使用一CGL,但可視需要使用一CGL。To minimize the increase in voltage required to drive an OLED stack, charge generating layers (CGLs; sometimes also called connectors or intermediate layers) are positioned between individual OLED light emitting cells. This is because the CGL is constructed so that electrons and holes are generated when voltage is applied, and the electrons and holes are injected into the adjacent organic emissive layer. Therefore, using a CGL can convert one injected electron into multiple photons, allowing higher illumination. Specifically, it is desired that a CGL is located between each light emitting cell in the stack. However, a light generating cell does not have to have an adjacent CGL on both sides. OLED light generating cells on the top and bottom of the stack will typically have only one adjacent CGL. It is generally not necessary to use a CGL between a light emitting cell and either the top electrode or the bottom electrode, but a CGL may be used if desired.

已提出諸多不同種類之CGL且可用於OLED堆疊中。舉例而言,參見US 7728517及US 2007/0046189。為形成一CGL,通常需要位於n型層與p型層的介面處之一n-p半導體異質接面以產生電荷。因此,CGL將具有兩個或更多個層。舉例而言,n摻雜有機層/透明導電層、n摻雜有機層/絕緣材料、n摻雜有機材料層/金屬氧化物層及n摻雜有機材料層/p摻雜有機材料層已全部報告。CGL之一期望金屬氧化物係MoO 3。在某些例項中,n層及p層可由一薄中間層分隔開。通常,CGL經配置以使得n層更靠近陽極且p層更靠近陰極。 Many different types of CGLs have been proposed and can be used in OLED stacks. For example, see US 7728517 and US 2007/0046189. To form a CGL, an np semiconductor heterojunction at the interface of the n-type layer and the p-type layer is usually required to generate charges. Therefore, the CGL will have two or more layers. For example, n-doped organic layer/transparent conductive layer, n-doped organic layer/insulating material, n-doped organic material layer/metal oxide layer and n-doped organic material layer/p-doped organic material layer have all been reported. One of the desired metal oxides for the CGL is MoO 3 . In some instances, the n-layer and the p-layer may be separated by a thin intermediate layer. Typically, the CGL is configured so that the n-layer is closer to the anode and the p-layer is closer to the cathode.

一CGL之一個期望方案具有三個層;具有一n摻雜物(舉例而言,Li)之一電子傳輸材料摻雜、相同(但未經摻雜)電子傳輸材料之一薄中間層及具有一p摻雜劑之一電洞傳輸材料摻雜。適合的電子傳輸及電洞傳輸材料以及適合用於一CGL中之n摻雜劑及p摻雜劑係眾所周知且常用的。材料可以是有機的或無機的。適當材料之選擇並不重要且可基於其效能而選擇任何材料。CGL之厚度應期望處於200 Å至450 Å之範圍中。在諸多例項中,CGL將在陽極側上具有一ETL且在其陰極側上具有一HTL以有助於提高電荷傳輸且有助於將充電產生摻雜劑(若存在)與發光單元中之LEL分離。One desirable embodiment of a CGL has three layers; an electron transport material doping with an n-dopant (e.g., Li), a thin intermediate layer of the same (but undoped) electron transport material, and a hole transport material doping with a p-dopant. Suitable electron transport and hole transport materials, as well as n- and p-dopant suitable for use in a CGL are well known and commonly used. The materials may be organic or inorganic. The choice of appropriate material is not critical and any material may be selected based on its performance. The thickness of the CGL should desirably be in the range of 200 Å to 450 Å. In many instances, the CGL will have an ETL on the anode side and a HTL on its cathode side to help improve charge transfer and to help separate charge generating dopants (if present) from the LEL in the light emitting cell.

儘管當OLED發光單元堆疊於彼此頂部上使用CGL有助於將電壓增大最小化,但堆疊所需之總電壓仍增大達大約每一個別單元單獨所需之電壓。預期具有至少三個堆疊式OLED發光單元之一OLED將需要超出一5 V驅動電晶體之推薦操作範圍的電壓。Although using a CGL when OLED light cells are stacked on top of each other helps minimize the voltage increase, the total voltage required for the stack still increases by approximately the voltage required for each individual cell alone. It is expected that an OLED with at least three stacked OLED light cells will require voltages outside the recommended operating range of a 5 V drive transistor.

在一項實施例中,位於一個別底部電極區段上方之OLED堆疊內之所有OLED發光單元發射相同色彩,例如紅色、綠色或藍色。此形成一像素化RGB微顯示器。圖10圖解說明使用三個不同OLED子像素堆疊來形成R像素、G像素及B像素的一微顯示器100。每一OLED子像素堆疊含有發射相同色彩之三個OLED發光單元,其中一CGL將每一單元與另一單元垂直地分隔開。In one embodiment, all OLED light emitting units within an OLED stack located above a respective bottom electrode segment emit the same color, such as red, green, or blue. This forms a pixelated RGB microdisplay. FIG. 10 illustrates a microdisplay 100 using three different OLED sub-pixel stacks to form R pixels, G pixels, and B pixels. Each OLED sub-pixel stack contains three OLED light emitting units emitting the same color, with a CGL separating each unit vertically from another unit.

在微顯示器100中存在一矽背板3,矽背板3包括例如圖2至圖8中所展示之一控制電路陣列以及將根據一輸入信號為子像素供應電力之其他必要組件。在具有電晶體及控制電路系統之層3之上,可存在一選用性平坦化層5。在層5 (若存在)之上係由電接觸件7連接之個別第一電極區段9,電接觸件7延伸穿過選用的平坦化層以形成個別底部電極區段9與層3中之控制電路系統之間的電接觸。個別底部電極區段9彼此在橫向上被一像素界定層1電隔離。不發光OLED層11(例如,電子或電洞注入(EIL或HIL)或電子或電洞傳輸(ETL或HTL)層)位於分段式底部電極區段9之上。一第一發光OLED單元13位於OLED層11之上。層15係一電荷產生層,該電荷產生層位於第一發光層13與一第二發光OLED單元17之間且將第一發光層13與一第二發光OLED單元17分隔開。在第二發光OLED單元17之上存在一第二電荷產生層19,第二電荷產生層19位於第二發光OLED單元17與一第三發光OLED單元21之間且將第二發光OLED單元17與一第三發光OLED單元21分隔開。在第三發光層21之上係不發光OLED層23,例如電子或電洞傳輸層或電子或電洞注入層及光可透射穿過之透明頂部電極25。藉由一囊封層27保護OLED微腔免受環境影響。在所展示之實施例中,一單個OLED堆疊內之所有有機層水平地與毗鄰堆疊被一像素界定層1分隔開,但頂部電極25及囊封體27係共同的且跨越整個作用區域延伸。然而,頂部電極25不需要連續且可視需要係分段式的。在微顯示器100中,位於同一底部電極區段9上方之所有OLED發光單元13、17、21發射相同色彩之光,B、G或R。此特定微顯示器不是一微腔裝置;然而,可使用使用一微腔效應之類似像素化RGB設計。In the microdisplay 100 there is a silicon backplane 3 which includes a control circuit array such as shown in FIGS. 2 to 8 and other necessary components to supply power to the sub-pixels according to an input signal. Above the layer 3 with the transistors and control circuitry there may be an optional planarization layer 5. Above the layer 5 (if present) are individual first electrode segments 9 connected by electrical contacts 7 which extend through the optional planarization layer to form electrical contacts between the individual bottom electrode segments 9 and the control circuitry in the layer 3. The individual bottom electrode segments 9 are electrically isolated from each other laterally by a pixel defining layer 1. A non-light-emitting OLED layer 11 (e.g., an electron or hole injection (EIL or HIL) or electron or hole transport (ETL or HTL) layer) is located above the segmented bottom electrode segment 9. A first light-emitting OLED unit 13 is located above the OLED layer 11. Layer 15 is a charge generation layer, which is located between the first light-emitting layer 13 and a second light-emitting OLED unit 17 and separates the first light-emitting layer 13 from the second light-emitting OLED unit 17. There is a second charge generation layer 19 above the second light-emitting OLED unit 17, which is located between the second light-emitting OLED unit 17 and a third light-emitting OLED unit 21 and separates the second light-emitting OLED unit 17 from the third light-emitting OLED unit 21. Above the third light-emitting layer 21 are non-light-emitting OLED layers 23, such as electron or hole transport layers or electron or hole injection layers and a transparent top electrode 25 through which light can be transmitted. The OLED microcavity is protected from environmental influences by an encapsulation layer 27. In the embodiment shown, all organic layers within a single OLED stack are horizontally separated from adjacent stacks by a pixel definition layer 1, but the top electrode 25 and the encapsulation body 27 are common and extend across the entire active area. However, the top electrode 25 does not need to be continuous and can be segmented as needed. In the microdisplay 100, all OLED light-emitting units 13, 17, 21 located above the same bottom electrode segment 9 emit light of the same color, B, G or R. This particular microdisplay is not a microcavity device; however, similar pixelated RGB designs using a microcavity effect can be used.

一種增大OLED發射之照度及色彩純度之眾所周知方法係利用光學微腔效應。此效應係基於在一發射表面與允許某些光通過之一半反射表面之間形成一光學共振器。兩個表面之間的多次反射會根據兩個表面之間的光學距離形成駐波,此將由於相長及相消干涉效應而加強某些波長之光且減小其他波長之光,相長及相消干涉效應將根據在駐波之波腹或波節處是否分別產生發射而發生。波腹根據反射器之間的總空間且根據被最佳化之波長而出現於不同位置處。然而,自微腔發射之光可展現出強烈的角相依性,其中當視角偏離觀察表面之垂線時時可出現色彩移位及照度損失。由於投影光學器件之進入角受限,因此此對於NED應用而言通常不會成為一問題。A well-known method of increasing the luminance and color purity of OLED emission is to exploit the optical microcavity effect. This effect is based on the formation of an optical resonator between an emitting surface and a semi-reflecting surface that allows some light to pass through. Multiple reflections between the two surfaces form resident waves, depending on the optical distance between the two surfaces, which will enhance light of certain wavelengths and reduce light of other wavelengths due to constructive and destructive interference effects, which will occur depending on whether the emission occurs at the antinodes or nodes of the resident wave, respectively. The antinodes appear at different locations depending on the total space between the reflectors and depending on the wavelength being optimized. However, the light emitted from the microcavity can exhibit strong angular dependence, where color shifts and luminance losses can occur when the viewing angle deviates from the perpendicular to the observation surface. This is usually not a problem for NED applications due to the limited entry angle of the projection optics.

將期望使用微腔效應來進一步增大OLED堆疊之照度。舉例而言,圖10中所展示之微顯示器100可經重新設計以藉由以下方式形成微腔效應:使用一反射底部電極或位於底部電極下方之一反射層,使頂部電極半透明以使得其具有某種程度之反射率且調整反射元件(底部電極9或下伏反射層)之最上部表面與頂部電極之最底部表面之間的距離以形成適合於該特定色彩之光的一微腔。It would be desirable to use the microcavity effect to further increase the illumination of the OLED stack. For example, the microdisplay 100 shown in FIG. 10 can be redesigned to form a microcavity effect by using a reflective bottom electrode or a reflective layer below the bottom electrode, making the top electrode semi-transparent so that it has a certain degree of reflectivity and adjusting the distance between the uppermost surface of the reflective element (bottom electrode 9 or underlying reflective layer) and the bottommost surface of the top electrode to form a microcavity suitable for that particular color of light.

圖11圖解說明使用多模式(白色) OLED微腔之一微顯示器200,該多模式(白色) OLED微腔由所有像素以及一彩色濾光器陣列(CFA)共用以形成R像素、G像素及B像素。多模式OLED產生一種色彩之光。理想情況下,一多模式OLED產生與R光、G光及B光之量大致相等的一白色光。通常,此將對應於大約0.33、0.33之CIE x、CIE y值。然而,根據用於形成RGB像素之彩色濾光器之特性,此等值之某些變化仍可接受或甚至期望。微顯示器200亦包含微腔效應。在此實施例中,多模式OLED堆疊含有發射不同色彩之三個OLED發光單元,其中每一單元與另一單元由一CGL垂直地分隔開,其中一反射表面與頂部電極之間的距離在作用區域之上係恆定的。 FIG. 11 illustrates a microdisplay 200 using a multi-mode (white) OLED microcavity that is shared by all pixels and a color filter array (CFA) to form R pixels, G pixels, and B pixels. The multi-mode OLED produces light of one color. Ideally, a multi-mode OLED produces a white light with approximately equal amounts of R light, G light, and B light. Typically, this will correspond to CIE x , CIE y values of approximately 0.33, 0.33. However, depending on the characteristics of the color filters used to form the RGB pixels, some variation in these values may still be acceptable or even desirable. The microdisplay 200 also includes a microcavity effect. In this embodiment, the multi-mode OLED stack contains three OLED light-emitting cells emitting different colors, where each cell is vertically separated from the other cell by a CGL, where the distance between a reflective surface and the top electrode is constant over the active area.

在微顯示器200中,存在一矽背板3,矽背板3包括例如圖2至圖8中所展示之一控制電路陣列以及將根據一輸入信號為子像素供應電力之必要組件。在具有電晶體及控制電路系統之層3之上可具有一選用平坦化層5。在層5 (若存在)之上係由電接觸件7連接之個別第一電極區段9,電接觸件7延伸穿過選用平坦化層以形成個別底部電極區段9與層3中之控制電路系統之間的電接觸。在此實施例中,底部電極區段9具有兩個層:更靠近基板1之一反射層9b及更靠近OLED層之一電極層9a。個別底部電極區段9彼此在橫向上電隔離。在分段式底部電極區段9之上係不發光OLED層11,例如電子或電洞注入或電子或電洞傳輸層。一紅色OLED光產生單元13A位於OLED層11之上。層15係一第一電荷產生層,該第一電荷產生層位於紅色OLED光產生單元13A與一綠色OLED光產生單元17A之間且將紅色OLED光產生單元13A與一綠色OLED光產生單元17A分隔開。在綠色發光層17A之上存在一第二電荷產生層19,第二電荷產生層19位於綠色OLED光產生單元17A與一藍色OLED光產生單元21A之間且將綠色OLED光產生單元17A與一藍色OLED光產生單元21A分隔開。在藍色OLED光產生單元21A之上係不發光OLED層23 (例如電子或電洞傳輸層或電子或電洞注入層)及半透明頂部電極25。此形成一OLED微腔30,OLED微腔30自反射表面9B之最上部表面延伸至半透明頂部電極25之最底部表面,半透明頂部電極25亦係一半反射電極。一囊封層27保護OLED微腔免受環境影響。在此實施例中,存在具有彩色濾光器29B、29G及29R之一彩色濾光器陣列,彩色濾光器29B、29G及29R對由OLED微腔30產生之多模式發射進行濾光以使得根據供應至下伏電極區段9之電力發射B光、G光及R光。In the microdisplay 200, there is a silicon backplane 3 including a control circuit array such as shown in Figures 2 to 8 and the necessary components to supply power to the sub-pixels according to an input signal. On top of the layer 3 with the transistors and control circuitry there may be an optional planarization layer 5. On top of the layer 5 (if present) are individual first electrode segments 9 connected by electrical contacts 7 extending through the optional planarization layer to form electrical contacts between individual bottom electrode segments 9 and the control circuitry in the layer 3. In this embodiment, the bottom electrode segment 9 has two layers: a reflective layer 9b closer to the substrate 1 and an electrode layer 9a closer to the OLED layer. The individual bottom electrode segments 9 are electrically isolated from each other in the lateral direction. Above the segmented bottom electrode segments 9 is a non-light-emitting OLED layer 11, such as an electron or hole injection or electron or hole transport layer. A red OLED light generating unit 13A is located above the OLED layer 11. Layer 15 is a first charge generating layer, which is located between the red OLED light generating unit 13A and a green OLED light generating unit 17A and separates the red OLED light generating unit 13A from the green OLED light generating unit 17A. Above the green light emitting layer 17A there is a second charge generating layer 19 which is located between and separates the green OLED light generating unit 17A and a blue OLED light generating unit 21A. Above the blue OLED light generating unit 21A is a non-light emitting OLED layer 23 (e.g. an electron or hole transport layer or an electron or hole injection layer) and a semi-transparent top electrode 25. This forms an OLED microcavity 30 which extends from the uppermost surface of the reflective surface 9B to the bottommost surface of the semi-transparent top electrode 25 which is also a semi-reflective electrode. An encapsulation layer 27 protects the OLED microcavity from the environment. In this embodiment, there is a color filter array having color filters 29B, 29G and 29R, which filter the multi-mode emission generated by the OLED microcavity 30 so that B light, G light and R light are emitted according to the power supplied to the underlying electrode segment 9.

圖12展示微顯示器300,其係微顯示器200之一變化形式,微顯示器300具有位於藍色OLED發光單元21A與OLED層23之間的一額外藍色OLED發光層22。在此實施例中,藍色OLED單元21A與額外藍色發光層22之間不存在CGL。如同微顯示器200一樣,由於藍色單元21A與藍色層22由一CGL分隔開(且因此層22不被視為一單獨發光OLED單元且應視為藍色發光單元21A之一部分),微顯示器300具有三個(而非四個) OLED光產生單元。即使藍色單元21A與藍色LEL 22由一非電荷產生夾層分隔開,但堆疊中仍將存在三個OLED單元。然而,若一中間CGL位於藍色發射單元21A與額外藍色發光層22之間,則OLED堆疊將含有四個OLED單元。12 shows a microdisplay 300, which is a variation of microdisplay 200, having an additional blue OLED light emitting layer 22 between blue OLED light emitting unit 21A and OLED layer 23. In this embodiment, there is no CGL between blue OLED unit 21A and additional blue light emitting layer 22. As with microdisplay 200, microdisplay 300 has three (rather than four) OLED light generating units because blue unit 21A and blue layer 22 are separated by a CGL (and thus layer 22 is not considered a separate light emitting OLED unit and should be considered as part of blue light emitting unit 21A). Even if the blue cell 21A is separated from the blue LEL 22 by a non-charge generating interlayer, there will still be three OLED cells in the stack. However, if an intermediate CGL is located between the blue emitting cell 21A and the additional blue light-emitting layer 22, the OLED stack will contain four OLED cells.

圖13展示具有微腔效應之一多模式OLED微顯示器400之另一實施例,多模式OLED微顯示器400類似於微顯示器200,但多模式OLED微顯示器400具有五個OLED發光單元。在此情形中,OLED單元中之某些OLED單元發射相同色彩之光且其他單元發射一不同色彩之光。確切而言,多模式微顯示器400具有兩個藍色OLED光產生單元、一個綠色OLED光產生單元、一個黃色OLED光產生單元及一個紅色OLED光產生單元,以上所有OLED光產生單元皆由CGL分隔開。FIG. 13 shows another embodiment of a multi-mode OLED microdisplay 400 with a microcavity effect, the multi-mode OLED microdisplay 400 is similar to the microdisplay 200, but the multi-mode OLED microdisplay 400 has five OLED light-emitting units. In this case, some of the OLED units emit light of the same color and other units emit light of a different color. Specifically, the multi-mode microdisplay 400 has two blue OLED light-generating units, one green OLED light-generating unit, one yellow OLED light-generating unit, and one red OLED light-generating unit, all of which are separated by CGLs.

在微顯示器400中,OLED單元13A發紅光。OLED單元13A與黃色發光OLED單元16由CGL 15分隔開。黃色發光OLED單元16與綠色發光OLED單元17A由CGL 14分隔開。綠色發光OLED單元17A與一第一藍色發光OLED單元21A由CGL 19分隔開。一第二藍色發光單元32與第一藍色發光OLED單元21A由CGL 24分隔開。另一層之所有發光OLED單元與在圖12中相同。In microdisplay 400, OLED cell 13A emits red light. OLED cell 13A is separated from yellow light-emitting OLED cell 16 by CGL 15. Yellow light-emitting OLED cell 16 is separated from green light-emitting OLED cell 17A by CGL 14. Green light-emitting OLED cell 17A is separated from a first blue light-emitting OLED cell 21A by CGL 19. A second blue light-emitting cell 32 is separated from the first blue light-emitting OLED cell 21A by CGL 24. All light-emitting OLED cells of another layer are the same as in FIG. 12.

如先前所述,OLED微顯示器構造於用作一基板之一矽背板上。通常而言,背板將係平坦的,具有一均勻厚度。由於矽背板通常係不透明的,因此OLED堆疊較佳地係頂部發射式的。然而,透明背板係已知的;在此等情形中,OLED堆疊可係頂部發射式的或底部發射式的。基板之頂部表面面向OLED。矽背板可具有各種類型之替代層(即,平坦化層、光管理層、光阻擋層等),其可被圖案化或不被圖案化且可位於頂部表面或底部表面上。As previously described, OLED microdisplays are constructed on a silicon backplane used as a substrate. Typically, the backplane will be flat, with a uniform thickness. Since silicon backplanes are typically opaque, the OLED stack is preferably top emitting. However, transparent backplanes are known; in such cases, the OLED stack can be top emitting or bottom emitting. The top surface of the substrate faces the OLED. The silicon backplane can have various types of alternative layers (i.e., planarization layers, light management layers, light blocking layers, etc.), which can be patterned or not and can be located on the top surface or the bottom surface.

底部電極區段(9或9a)可係一陽極或一陰極且可係透明的、反射的、不透明或半透明的。若OLED係頂部發射式的,則底部電極可由透明金屬氧化物或反射金屬(例如Al、Au、Ag或Mg或其合金)製成且具有至少30 nm、期望至少60 nm之一厚度。The bottom electrode segment (9 or 9a) can be an anode or a cathode and can be transparent, reflective, opaque or translucent. If the OLED is top emitting, the bottom electrode can be made of a transparent metal oxide or a reflective metal (such as Al, Au, Ag or Mg or their alloys) and have a thickness of at least 30 nm, preferably at least 60 nm.

在第一電極位於一反射層之上之微腔應用中,該第一電極應係透明的。然而,在其他應用中,第一電極層9a及9b可坍縮成一單個反射電極以使得其最上部反射表面形成光學微腔之一側(即,圖10中之30)。In microcavity applications where the first electrode is located on a reflective layer, the first electrode should be transparent. However, in other applications, the first electrode layers 9a and 9b can be collapsed into a single reflective electrode so that its uppermost reflective surface forms one side of the optical microcavity (i.e., 30 in Figure 10).

當OLED堆疊係一頂部發射微腔且底部電極係透明的時,在界定微腔30之一第一側之底部電極之下應存在一發射層。當一透明陽極位於一反射表面之上時,其係光學腔之一部分。反射層9b可係一反射金屬,例如Al、Au、Ag、Mg、Cu或Rh或其合金、一介電鏡或一高反射塗層。介電鏡係由沈積至基板上之多個薄材料(例如,氟化鎂、氟化鈣及各種金屬氧化物)層構造而成。高反射塗層由兩種材料之多個層組成,一種材料具有一高折射率(例如硫化鋅(n=2.32)或二氧化鈦(n=2.4))且一種材料具有一低折射率(例如,氟化鎂(n=1.38)或二氧化矽(n=1.49))。自所反射之光之波長角度看,層之厚度通常係四分之一波。期望反射層反射至少80%之入射光且最佳地反射至少90%。較佳反射層係Al或Ag,一厚度係300 Å至2000 Å,最佳地係800 Å至1500 Å。When the OLED stack is a top emitting microcavity and the bottom electrode is transparent, there should be an emitting layer below the bottom electrode defining a first side of the microcavity 30. When a transparent anode is located on a reflective surface, it is part of the optical cavity. The reflective layer 9b can be a reflective metal such as Al, Au, Ag, Mg, Cu or Rh or alloys thereof, a dielectric mirror or a highly reflective coating. Dielectric mirrors are constructed from multiple thin layers of materials (e.g., magnesium fluoride, calcium fluoride and various metal oxides) deposited on a substrate. Highly reflective coatings consist of multiple layers of two materials, one with a high refractive index (e.g., zinc sulfide (n=2.32) or titanium dioxide (n=2.4)) and one with a low refractive index (e.g., magnesium fluoride (n=1.38) or silicon dioxide (n=1.49)). The thickness of the layer is typically a quarter wave from the wavelength of the reflected light. It is desirable that the reflective layer reflect at least 80% of the incident light and optimally at least 90%. Preferred reflective layers are Al or Ag, with a thickness of 300 Å to 2000 Å, optimally 800 Å to 1500 Å.

期望,當OLED堆疊係底部發射式時,底部電極係一透明陽極且應透射儘可能多的可見光,較佳地具有至少70%或更期望至少80%之一透射率。雖然底部透明電極可由任何導電材料製成,但金屬氧化物(例如ITO或AZO)或薄金屬(例如Ag)層係較佳的。鑒於弱傳導材料(例如,TiN)能變得很薄,可使用弱傳導材料。Desirably, when the OLED stack is bottom emitting, the bottom electrode is a transparent anode and should transmit as much visible light as possible, preferably with a transmittance of at least 70% or more desirably at least 80%. Although the bottom transparent electrode can be made of any conductive material, metal oxides (such as ITO or AZO) or thin metal (such as Ag) layers are preferred. Weakly conductive materials (such as TiN) can be used given that they can be made very thin.

適合用於非發射層(即,圖10中之11及23) (例如電洞注入層、電洞傳輸層或電子注入層或電子傳輸層)之電子傳輸及電洞傳輸材料係眾所周知且常用的。此等層可係此等材料之混合物且可含有用於修改其性質之摻雜劑。由於其係不發光的,因此其不含有發射材料且係透明的。適當材料之選擇並不重要且可基於其效能選擇任何材料。Electron transport and hole transport materials suitable for use in non-emissive layers (i.e., 11 and 23 in FIG. 10 ) such as hole injection layers, hole transport layers or electron injection layers or electron transport layers are well known and commonly used. These layers may be mixtures of these materials and may contain dopants to modify their properties. Since they are non-luminescent, they do not contain emissive materials and are transparent. The choice of appropriate materials is not critical and any material may be selected based on its performance.

在利用微腔效應之實施例中,由於微腔內之各種OLED單元之間的間隔以及微腔之大小對於將效率最大化而言很重要,因此通常需要選擇各種不發光層之厚度以提供所期望間隔。期望,藉由使用有機非發射層(例如電洞傳輸層)之適當厚度來調整OLED單元之間的間隔以及微腔之大小。In embodiments utilizing the microcavity effect, since the spacing between various OLED units within the microcavity and the size of the microcavity are important for maximizing efficiency, the thickness of various non-luminescent layers is generally selected to provide the desired spacing. It is desirable to adjust the spacing between OLED units and the size of the microcavity by using the appropriate thickness of the organic non-emissive layer (e.g., the hole transport layer).

發光層通常具有一主材料(或主材料之一混合物)及一發光化合物,該主材料係層之主要組分。期望,由於發光化合物具有較高效率,因此發光化合物係磷光的。然而,在某些例項中,某些LEL可使用螢光或TADF (熱啟動延遲螢光)化合物作為光發射材料,而其他LEL使用磷光材料。確切而言,藍色光OLED層可使用螢光或TADF化合物或其組合,而非藍色發光層可使用綠色、黃色、橙色或紅色磷光化合物或其組合。發光層可使用發光材料之組合。LEL之適當材料之選擇係眾所周知的,並不重要,且可基於其效能及發射特性選擇任何材料。當使用磷光射極時,有時需要由磷光射極產生之激子侷限於層內。因此,可視需要使用磷光LEL之任一側或兩側上之激子阻擋層。此等材料及其應用係眾所周知的。另外,可期望在發光層(尤其是藍色發光層)周圍添加HBL (電洞阻擋層)及EBL層(電子阻擋層)以提高壽命及照度效率。The light-emitting layer typically has a host material (or a mixture of host materials) and a light-emitting compound, which is the main component of the layer. It is desirable that the light-emitting compound is phosphorescent because the light-emitting compound has a higher efficiency. However, in some examples, certain LELs may use fluorescent or TADF (thermally activated delayed fluorescence) compounds as light-emitting materials, while other LELs use phosphorescent materials. Specifically, blue light OLED layers may use fluorescent or TADF compounds or combinations thereof, while non-blue light-emitting layers may use green, yellow, orange or red phosphorescent compounds or combinations thereof. Light-emitting layers may use combinations of light-emitting materials. The selection of appropriate materials for LELs is well known and unimportant, and any material may be selected based on its performance and emission characteristics. When using phosphorescent emitters, it is sometimes desirable to confine the excitons generated by the phosphorescent emitter to the layer. Therefore, exciton blocking layers on either or both sides of the phosphorescent LEL may be used as desired. Such materials and their applications are well known. In addition, it may be desirable to add HBL (hole blocking layer) and EBL layers (electron blocking layer) around the luminescent layer (especially the blue luminescent layer) to improve lifetime and illumination efficiency.

若OLED堆疊係頂部發射式的,則頂部電極(即,圖10中之25)應係透明的;若OLED堆疊係底部發射式的,則係反射的;且在OLED堆疊係一微腔之情形中,則係半透明以及半反射:即,其反射光之一部分且透射其餘部分。在一微腔中,頂部電極之最底部內部表面界定微腔30之一第二側。期望,半透明頂部電極反射由LEL發射之光之至少5%且更期望至少10%以建立微腔效應。半透明第二電極之厚度係重要的,此乃因其控制反射光及透射光之量。然而,其不能太薄,此乃因不能夠高效地將電荷傳遞至OLED中或經受住釘紮電洞或其他缺陷。上部電極層之一厚度期望係100 Å至200 Å,且更期望係125 Å至175 Å。The top electrode (i.e., 25 in FIG. 10 ) should be transparent if the OLED stack is top emitting, reflective if the OLED stack is bottom emitting, and in the case where the OLED stack is a microcavity, semi-transparent and semi-reflective: that is, it reflects a portion of the light and transmits the rest. In a microcavity, the bottommost interior surface of the top electrode defines a second side of the microcavity 30. Desirably, the semi-transparent top electrode reflects at least 5% and more desirably at least 10% of the light emitted by the LEL to establish a microcavity effect. The thickness of the semi-transparent second electrode is important because it controls the amount of reflected and transmitted light. However, it cannot be too thin because it cannot efficiently transfer charge into the OLED or withstand pinned holes or other defects. A thickness of the upper electrode layer is desirably 100 Å to 200 Å, and more desirably 125 Å to 175 Å.

期望頂部電極係一薄金屬層或一薄金屬合金層。適合的金屬包含Ag、Mg、Al及Ca或其合金。當然,Ag係較佳的,此乃因其具有相對低藍色吸收率。為有助於電子傳輸以及穩定化,電極表面上可存在一毗鄰透明金屬氧化物(例如ITO、InZnO或MoO 3)層。另一選擇為,可使用金屬鹵化物(例如LiCl)、有機金屬氧化物(例如,喹啉鋰)或其他有機材料。 The top electrode is desirably a thin metal layer or a thin metal alloy layer. Suitable metals include Ag, Mg, Al and Ca or their alloys. Of course, Ag is preferred because of its relatively low blue absorptivity. To aid electron transport and stabilization, there may be an adjacent transparent metal oxide layer (e.g., ITO, InZnO or MoO 3 ) on the electrode surface. Alternatively, metal halides (e.g., LiCl), organometallic oxides (e.g., lithium quinolate) or other organic materials may be used.

上部電極之上可存在保護層或間隔層(圖10至圖13中未展示)以防止在囊封期間損壞。There may be a protective layer or spacer layer (not shown in FIGS. 10-13 ) over the upper electrode to prevent damage during encapsulation.

在頂部電極25及任何選用的保護層(若存在)之上沈積或放置囊封體27。在一最小值下,囊封應完全覆蓋頂部及側面上之發光區域且直接接觸基板。囊封應不被空氣及水穿透。其可係透明或不透明的。其不應導電。其可在原位形成或添加為一單獨預先形成薄片以及提供側邊緣之密封。原位形成之一實例將係薄膜囊封。薄膜囊封涉及沈積具有交替的無機材料層與聚合層之多個層,直至達成所期望程度之保護。形成薄膜囊封之方案及方法係眾所周知的且可視需要使用任一者。另一選擇為,可使用附接於至少密封區域及封圍區域之上的一預先形成薄片或蓋片提供囊封。預先形成薄片可係剛性或撓性的。其可由玻璃(包含撓性玻璃)、金屬或有機/無機障壁層製成。其應具有接近基板之一熱膨脹係數以達成一更穩健連接。可需要使用防空氣及防水黏合劑(例如,矽或環氧黏合劑)或藉由熱構件(例如,超音波焊接或玻璃熔塊焊接)將預先形成囊封薄片附接於密封區域之上,此可需要額外密封劑,例如焊料或玻璃熔塊。蓋片之側邊緣及底部邊緣可經特殊設計以與密封區域更好地配合或促進一更好密封。蓋片及密封區域可一起設計以使得其配合或在形成密封之前部分地鎖定在適當位置處。此外,蓋片可經預處置以促進與密封區域之更好黏合。An encapsulation 27 is deposited or placed over the top electrode 25 and any optional protective layer (if present). At a minimum, the encapsulation should completely cover the light emitting areas on the top and sides and directly contact the substrate. The encapsulation should be impermeable to air and water. It can be transparent or opaque. It should not be electrically conductive. It can be formed in situ or added as a separate pre-formed sheet and provide sealing of the side edges. An example of in situ formation would be thin film encapsulation. Thin film encapsulation involves depositing multiple layers with alternating layers of inorganic materials and polymeric layers until the desired degree of protection is achieved. Schemes and methods for forming thin film encapsulation are well known and any one can be used as desired. Alternatively, the encapsulation can be provided using a pre-formed sheet or cover sheet attached to at least the sealing area and the enclosure area. The preformed sheet may be rigid or flexible. It may be made of glass (including flexible glass), metal, or organic/inorganic barrier layers. It should have a thermal expansion coefficient close to that of the substrate to achieve a more stable connection. It may be necessary to attach the preformed encapsulation sheet to the sealing area using an air-proof and waterproof adhesive (e.g., silicone or epoxy adhesive) or by thermal means (e.g., ultrasonic welding or glass frit welding), which may require additional sealants such as solder or glass frit. The side and bottom edges of the cover sheet may be specially designed to better fit the sealing area or promote a better seal. The cover sheet and the sealing area may be designed together so that they fit or are partially locked in place before the seal is formed. Additionally, the cover sheet may be pre-treated to promote better bonding to the sealing area.

儘管本申請案闡述在微顯示器中使用OLED作為發光元件,但相同控制電路可用於將需要相對高電壓來發光之任何自發光顯示器技術。本發明並不僅限於OLED,而是使用將需要大於5 V、較佳地大於7.5 V、或甚至大於10 V以提供至少1000尼特或較佳地至少5000尼特之光發射的任何其他顯示器技術。Although this application describes the use of OLEDs as light emitting elements in microdisplays, the same control circuit can be used for any self-emitting display technology that would require a relatively high voltage to emit light. The invention is not limited to OLEDs, but can be used with any other display technology that would require greater than 5 V, preferably greater than 7.5 V, or even greater than 10 V to provide at least 1000 nits, or preferably at least 5000 nits of light emission.

顯示器中之串擾係一個像素所提供之所發射照度意外地受另一像素影響。此係不期望的,此乃因根據影像信號受影響像素不再提供準確照度且因此影像之品質可降級。根據串擾之量及性質,顯示器中之重要因素(例如色彩再現、對比度(最大照度與最小照度之間的差)、灰階、解析度及「重影」)皆全部可受負面影響。通常,在像素間距小之情況下,微顯示器中之串擾係特別大的問題。期望,像素之間的串擾量係15%或小於15%,較佳係5%或小於5%,且最佳係3%或小於3%。Crosstalk in a display is when the emitted illumination provided by one pixel is unexpectedly affected by another pixel. This is undesirable because the affected pixel no longer provides accurate illumination based on the image signal and therefore the quality of the image can be degraded. Depending on the amount and nature of the crosstalk, important factors in the display such as color reproduction, contrast (the difference between maximum and minimum illumination), grayscale, resolution, and "ghosting" can all be negatively affected. Typically, crosstalk in microdisplays is a particularly large problem where the pixel pitch is small. It is desirable that the amount of crosstalk between pixels is 15% or less, preferably 5% or less, and optimally 3% or less.

所闡述之堆疊式微腔OLED裝置必須係厚的,其中內部發光單元之間的間隔係界定的。此係必須提供微腔效應以在一單個微腔內增強R、G及B發射。此可使得串擾因光學及化學/電機制而增大。可增大串擾量之某些光學程序包含OLED裝置內之光散射及波導。可增大串擾之某些化學/電程序包含在同一層自一作用像素區域至一鄰近非作用像素區域之內橫向載子遷移。The stacked microcavity OLED device described must be thick, with defined spacing between internal light emitting cells. This is necessary to provide a microcavity effect to enhance R, G, and B emission within a single microcavity. This can cause crosstalk to increase due to optical and chemical/electrical mechanisms. Some optical processes that can increase the amount of crosstalk include light scattering and waveguiding within the OLED device. Some chemical/electrical processes that can increase crosstalk include lateral carrier migration from an active pixel region to a neighboring inactive pixel region in the same layer.

據信多個模式皆會導致串擾。短範圍(0.2 µm至0.7 µm)似乎係橫向電荷載子與光學機制的一組合。中等範圍(3 µm至7 µm)互動似乎主要由於橫向電荷載子遷移但可部分地由於光學機制。長範圍(50 µm至200 µm)互動似乎係主要由於自一作用像素區域至一非作用區域之光散射。亦據信,根據像素間距,基於波導存在對串擾之一更長範圍光學貢獻。It is believed that multiple modes contribute to crosstalk. Short range (0.2 µm to 0.7 µm) appears to be a combination of lateral charge carrier and optical mechanisms. Mid-range (3 µm to 7 µm) interactions appear to be primarily due to lateral charge carrier migration but may be partially due to optical mechanisms. Long range (50 µm to 200 µm) interactions appear to be primarily due to light scattering from an active pixel region to an inactive region. It is also believed that, depending on the pixel spacing, there is a longer range optical contribution to crosstalk based on the waveguide.

將由於OLED裝置中之載子遷移所致之串擾問題最小化之某些有用方法包含: -藉由改變具有高載子遷移率之層(例如HIL、HTL、CGL、ETL及EIL)的層厚度及組成(以增大「薄片電阻」)來減小橫向電荷載子遷移。確切而言,電荷載子(電洞或電子)在一作用區域內產生且可跨越照亮區域與非照亮區域之間的間隙橫向移動。此問題似乎主要出現於緊挨著或接近電極中之一者之層中。據信,位於陽極之上的共同HIL層及HTL層可係導致該問題之最大因素。似乎一旦在一個陽極接墊上HIL之照亮區域中產生電洞,則可遷移至一鄰近陽極接墊之非照亮區域,且由於電洞所得之電壓可超出OLED之V th且因此(名義上非照亮)像素無論如何會發光。另外,電洞可隨電子進入導電陽極接墊且在橫向上流過具有非常小橫向電阻之陽極。在非照亮陽極接墊之遠側處,電流可返回至HIL中(隨電洞)以跳躍至下一非照亮陽極接墊。因此,載子遷移問題不可僅限於毗鄰陽極接墊之間的一較短距離,而是亦可具有一較長距離組件。因此,應認真關注兩個電極且確切而言陽極之厚度及組成。具有較小載子遷移率之較薄有機層可有助於將此等不期望載子遷移程序最小化。 -具有高載子遷移率之有機層之材料選擇。確切而言,材料可經選擇以最小化其對串擾之促成作用。就此而言,添加至HIL之摻雜物(例如,F4-TCNQ、F6-TCNNQ或HAT-CN)之類型及水準以及HIL或HTL中HTM (例如,芳香胺化合物,例如NPB或螺環TTB)之選擇可係重要的。僅P摻雜物或非摻雜HIL亦可係有效的。在某些情形中,可使用一非摻雜HIL及一p摻雜HTL。例如MoO 3(其可與有機材料混合)等無機HIL材料亦可具有優點。 Some useful methods to minimize crosstalk problems due to carrier migration in OLED devices include: - Reducing lateral charge carrier migration by changing the layer thickness and composition of layers with high carrier mobility (such as HIL, HTL, CGL, ETL and EIL) (to increase the "sheet resistance"). Specifically, charge carriers (holes or electrons) are generated in an active area and can move laterally across the gap between the illuminated area and the non-illuminated area. This problem seems to occur mainly in layers that are next to or close to one of the electrodes. It is believed that the common HIL layer and HTL layer located above the anode may be the biggest factor causing the problem. It seems that once holes are generated in an illuminated area of the HIL on one anode pad, they can migrate to a non-illuminated area of an adjacent anode pad, and the resulting voltage due to the holes can exceed the Vth of the OLED and thus the (nominally non-illuminated) pixel will emit light anyway. Alternatively, holes can follow electrons into a conductive anode pad and flow laterally through the anode, which has very little lateral resistance. Far side of the non-illuminated anode pad, current can return to the HIL (following the holes) to jump to the next non-illuminated anode pad. Therefore, carrier migration problems cannot be limited to a shorter distance between adjacent anode pads, but can also have a longer distance component. Therefore, careful attention should be paid to the thickness and composition of both electrodes and specifically the anode. Thinner organic layers with smaller carrier mobility can help to minimize these undesired carrier migration processes. - Material selection of organic layers with high carrier mobility. Specifically, the material can be selected to minimize its contribution to crosstalk. In this regard, the type and level of dopants (e.g., F4-TCNQ, F6-TCNNQ, or HAT-CN) added to the HIL and the choice of HTM (e.g., aromatic amine compounds such as NPB or spiro-TTB) in the HIL or HTL may be important. Only p-doped or non-doped HILs may also be effective. In some cases, a non-doped HIL and a p-doped HTL may be used. Inorganic HIL materials such as MoO 3 (which may be mixed with organic materials) may also have advantages.

OLED裝置內由光學程序所致的串擾問題最小化之某些有用方法包含: -將彩色濾光器最佳化以減小空氣/玻璃介面與反射陽極之間的光波導,包含使用經特殊設計以吸收自基板法向方向以高角度行進之光之光學濾光層。 -藉由減小散射點減小光散射。確切而言,應將在陽極上或在陽極附近之小粒子碎片量最小化。亦可因陰極之粗糙度而發生散射,粗糙度可取決於用於沈積之組成及程序。(舉例而言,參見Shen等人的「Efficient Upper-Excited State Fluorescence in an Organic Hyperbolic Metamaterial」,Nano Lett. 2018,18,3,1693–1698)。 -總陽極表面在作用像素區域之上及在像素之間應儘可能平坦且光滑。確切而言,已知在像素之間形成一PDL (像素界定層)且延伸於像素區域內之陽極表面上方之突起、隆起或其他結構可用於將光散射回至像素區域中且防止光進入一鄰近(非照亮)像素。然而,當存在覆在結構上之較厚OLED層時,此方法無效。困在較厚層內之光更可能在層內發生內部反射以使得可越過結構行進至另一側。若陽極及覆疊OLED層均勻地平坦,則顯示器之層內導波之光更可能不中斷地繼續,直至其被吸收或達到顯示器之邊緣。 -針對波導光使用吸收器。 -藉由背板之介電質吸收光。 -設計HIL及陽極以形成電荷自HIL進入陽極之一障壁。 Some useful approaches to minimize crosstalk problems caused by optical processes in OLED devices include: - Optimizing color filters to reduce light waveguides between the air/glass interface and the reflective anode, including using optical filters designed to absorb light traveling at high angles from the substrate normal. - Reducing light scattering by reducing scattering points. Specifically, the amount of small particle debris on or near the anode should be minimized. Scattering can also occur due to the roughness of the cathode, which can depend on the composition and process used for deposition. (For example, see Shen et al., “Efficient Upper-Excited State Fluorescence in an Organic Hyperbolic Metamaterial,” Nano Lett. 2018, 18, 3, 1693–1698). -The overall anode surface should be as flat and smooth as possible over the active pixel area and between pixels. Specifically, it is known that a PDL (pixel definition layer) is formed between pixels and protrusions, bumps or other structures above the anode surface extending into the pixel area can be used to scatter light back into the pixel area and prevent light from entering a neighboring (non-illuminated) pixel. However, this approach does not work when there is a thicker OLED layer overlying the structure. Light trapped in the thicker layer is more likely to be internally reflected within the layer so that it can travel across the structure to the other side. If the anode and overlying OLED layer are uniformly flat, light waveguided within the layers of the display is more likely to continue uninterrupted until it is absorbed or reaches the edge of the display. -Use absorbers for waveguided light. - Absorb light through the dielectric of the backplane. - Design the HIL and anode to form a barrier for charges to enter the anode from the HIL.

為控制串擾,以下方式可有用:將一額外單獨像素控制電路添加至位於第二開關電晶體與OLED之陽極之間的一節點以在OLED被驅動時控制陽極處之電壓以使得名義上「關斷」(不供電且因此不發射)。確切而言,只有在驅動電路系統要求像素不發射或非微弱地發射時,像素控制電路才應將電壓減小至低於OLED之V th。如此一來,橫向載子遷移所形成之任何電壓可得以最小化。 實驗結果 To control crosstalk, it may be useful to add an additional separate pixel control circuit to a node between the second switching transistor and the anode of the OLED to control the voltage at the anode when the OLED is driven so that it is nominally "off" (not powered and therefore not emitting). Specifically, the pixel control circuit should reduce the voltage below the Vth of the OLED only when the drive circuitry requires the pixel to not emit or to emit at least weakly. In this way, any voltage developed by lateral carrier migration can be minimized. Experimental Results

在以下實例中,除非另有指明,在每一材料之前的數字(例如,200 HIL)係以埃為單位之實體層厚度。所有%皆係以重量計。所有裝置皆係在沈積陰極之後使用相同過程囊封。所有材料皆可買到。In the following examples, the number preceding each material (e.g., 200 HIL) is the physical layer thickness in angstroms unless otherwise specified. All % are by weight. All devices were encapsulated using the same process after cathode deposition. All materials are commercially available.

用於以下實驗裝置之背板係一基於單晶矽背板且按原樣與圖6a及圖6b中所展示之示意性控制電路系統搭配使用。背板含有:一驅動電晶體(T1)及一開關電晶體(T2),其係串聯連接低電壓(額定為5 V) p通道電晶體;及一保護電路,其具有用於每一像素之一NPN型雙極接面電晶體(BJT1)。在所有實驗實例中,BJT1之基極被隔離;即基極不連接至一外部電源以使得不特意控制BJT之基極電壓或將BJT之基極電壓設定至任何特定電壓。背板包含一反射金屬層作為底部電極/陽極。The backplane used for the following experimental setup is a single crystal silicon based backplane and is used as is with the schematic control circuitry shown in Figures 6a and 6b. The backplane contains: a drive transistor (T1) and a switch transistor (T2) which are low voltage (rated to 5 V) p-channel transistors connected in series; and a protection circuit having an NPN bipolar junction transistor (BJT1) for each pixel. In all experimental cases, the base of BJT1 is isolated; that is, the base is not connected to an external power supply so that the base voltage of the BJT is not intentionally controlled or set to any specific voltage. The backplane includes a reflective metal layer as the bottom electrode/anode.

一比較性2單元堆疊式OLED裝置A-1被製備成如下: 層1 (反射底部電極/陽極):按已交付的 層2 (電洞注入層HIL):200 電洞傳輸材料HTM1 + 6% p摻雜物PD1 層3 (電洞傳輸層HTL1):410電洞傳輸材料HTM1 層4 (HTL2):50電洞傳輸材料HTM2 層5 (綠色LEL):100綠色主GH1及3%綠色磷光摻雜劑GPD1 層6 (黃色LEL):100 GH1 + 10% GPD1 + 3%紅色磷光摻雜劑RPD1 層7 (電子傳輸層ETL1):200電子傳輸材料ETM1 層8至層10 (電荷產生層CGL1):270三層 層11A (HTL3):300 HTM1 層11B (HTL4):280 HTM1 層12 (藍色LEL2):200藍色主BH1 + 4%螢光藍色摻雜劑BFD1 層13 (ETL2):150 ETM2 層14 (電子注入層EIL):150 ETM1 + 2% Li 層15 (半透明陰極):105 75% Ag / 25% Mg A comparative 2-cell stacked OLED device A-1 was prepared as follows: Layer 1 (reflective bottom electrode/anode): as delivered Layer 2 (hole injection layer HIL): 200 hole transport material HTM1 + 6% p dopant PD1 Layer 3 (hole transport layer HTL1): 410 hole transport material HTM1 Layer 4 (HTL2): 50 hole transport material HTM2 Layer 5 (green LEL): 100 green host GH1 and 3% green phosphorescent dopant GPD1 Layer 6 (yellow LEL): 100 GH1 + 10% GPD1 + 3% red phosphorescent dopant RPD1 Layer 7 (Electron transport layer ETL1): 200 electron transport material ETM1 Layer 8 to layer 10 (charge generation layer CGL1): 270 three layers Layer 11A (HTL3): 300 HTM1 Layer 11B (HTL4): 280 HTM1 Layer 12 (blue LEL2): 200 blue main BH1 + 4% fluorescent blue dopant BFD1 Layer 13 (ETL2): 150 ETM2 Layer 14 (electron injection layer EIL): 150 ETM1 + 2% Li Layer 15 (semi-transparent cathode): 105 75% Ag / 25% Mg

以一類似方式製備一第二比較性OLED裝置A-2,但層11A及11B之厚度分別增大至1090及4090。A1及A-2兩者皆為雙單元堆疊式OLED,其中層5 (G LEL)及層6 (紅色LEL)共同表示一個單元(一G-Y堆疊)且層11 (藍色LEL)表示一第二單元(一B堆疊),該第二單元與該第一單元被一CGL分隔開。層5及層6係一單個單元,此乃因其係彼此未被一CGL (層8及層9)分隔開之毗鄰LEL。A-1及A-2兩者皆係微腔裝置,其中A-1之微腔厚度係2320A且A-2之微腔厚度係6920 A。此等雙單元堆疊式OLED裝置表示當前最高水平。A second comparative OLED device A-2 was prepared in a similar manner, but the thickness of layers 11A and 11B were increased to 1090 and 4090, respectively. Both A-1 and A-2 are two-cell stacked OLEDs, where layers 5 (G LEL) and 6 (red LEL) together represent one cell (a G-Y stack) and layer 11 (blue LEL) represents a second cell (a B stack) separated from the first cell by a CGL. Layers 5 and 6 are a single cell because they are adjacent LELs that are not separated from each other by a CGL (layers 8 and 9). Both A-1 and A-2 are microcavity devices, where the microcavity thickness of A-1 is 2320 Å and the microcavity thickness of A-2 is 6920 Å. These dual-cell stacked OLED devices represent the current state of the art.

按照與A-1相同之方式製備一發明性3單元堆疊式OLED B-1,但以下額外層插入於層11A (其厚度調整為470)與11B (係4090)之間: 層16 (BLEL1):200 BH1 + 4% BFD1 層17 (ETL3):150 ETM2 層18-20 (CGL2):270三層(與CGL1相同之方案) OLED裝置B-1係3單元堆疊式OLED,其中層5及層6係第一G-Y單元(與A-1中相同),層16係一附加第二B單元且層12 (與A-1中相同)係一第三B單元。第二單元(層16)藉由一CGL與第一單元(層5及6)及第三單元(層12)分隔開。即,B-1與A-1相比含有一額外B單元且因此將具有較高照度但電壓要求增大。OLED B-1係微腔厚度(6920 A)與裝置A-2相同之一微腔裝置。圖14展示OLED A-1、A-2 (比較性雙單元裝置)及B-1 (發明性3單元裝置)之特性I-V曲線(以mA/cm 2為單位之電流密度對電壓),其亦列示於表1中。 表1–列示OLED之I-V資料 裝置 I* V* L* A-1 臨限值 5.5       1 6.0 30.4    5 6.7 40.0    10 7.1 41.5    100 10.8 35.5 A-2 臨限值 5.3       1 6.3 29.0    5 7.3 30.3    10 8.0 30.3    100 13.5 24.5 B-1 臨限值 7.6       1 9.0 28.5    5 9.9 32.8    10 10.7 33.7    100 16.0 28.6 * I =陽極接墊上之電流密度,以mA/cm 2為單位 V = 電壓 L =照度效率,以cd/A為單位 在圖14及表1中,OLED A-1及A-2具有約相同的V th。然而,具有一額外B單元之OLED B-1具有一顯著較高V th且需要一更高電壓(約高出2.5 V)來產生與A-2相同之電流密度。 An inventive 3-unit stacked OLED B-1 is prepared in the same manner as A-1, but the following additional layers are inserted between layers 11A (whose thickness is adjusted to 470) and 11B (which is 4090): Layer 16 (BLEL1): 200 BH1 + 4% BFD1 Layer 17 (ETL3): 150 ETM2 Layers 18-20 (CGL2): 270 Three layers (same scheme as CGL1) OLED device B-1 is a 3-unit stacked OLED, in which layers 5 and 6 are the first GY unit (same as in A-1), layer 16 is an additional second B unit and layer 12 (same as in A-1) is a third B unit. The second cell (layer 16) is separated from the first cell (layers 5 and 6) and the third cell (layer 12) by a CGL. That is, B-1 contains an additional B cell compared to A-1 and will therefore have higher illumination but increased voltage requirements. OLED B-1 is a microcavity device with the same microcavity thickness (6920 Å) as device A-2. Figure 14 shows the characteristic IV curves (current density in mA/ cm2 versus voltage) for OLEDs A-1, A-2 (comparative two-cell device) and B-1 (inventive three-cell device), which are also listed in Table 1. Table 1 - IV Data for OLEDs Listed Device I* V* L* A-1 Threshold 5.5 1 6.0 30.4 5 6.7 40.0 10 7.1 41.5 100 10.8 35.5 A-2 Threshold 5.3 1 6.3 29.0 5 7.3 30.3 10 8.0 30.3 100 13.5 24.5 B-1 Threshold 7.6 1 9.0 28.5 5 9.9 32.8 10 10.7 33.7 100 16.0 28.6 * I = current density on the anode pad in mA/ cm2 V = voltage L = luminance efficiency in cd/A In Figure 14 and Table 1, OLEDs A-1 and A-2 have approximately the same Vth . However, OLED B-1, which has an additional B cell, has a significantly higher Vth and requires a higher voltage (approximately 2.5 V higher) to produce the same current density as A-2.

圖15中可看到在雙單元堆疊式OLED之上具有一微腔3單元堆疊式OLED之優點,圖15比較(強度對以nm為單位之波長)沒有A-1、A-2及B-1之彩色濾光器之情況下光譜輸出。與G發射相比,具有一較薄微腔之OLED A-1具有相對較小B發射及R發射。與G相比,具有適合於所有3種色彩之一微腔之OLED A-2具有更多B發射及R發射,但B發射仍受限制。與A-2相比,具有額外B單元之OLED B-2之藍色射極大地增大。The advantage of having a microcavity 3-cell stacked OLED over a 2-cell stacked OLED can be seen in Figure 15, which compares (intensity vs. wavelength in nm) the spectral output without the color filters of A-1, A-2, and B-1. OLED A-1, which has a thinner microcavity, has relatively less B and R emission compared to G emission. OLED A-2, which has one microcavity suitable for all 3 colors, has more B and R emission compared to G, but the B emission is still limited. OLED B-2, which has an extra B cell, has a greatly increased blue emission compared to A-2.

以上結果指代在添加將為一微顯示器形成R、G及B像素之彩色濾光器之前的白光OLED裝置。本技術中眾所周知,無論W OLED所產生之R、G及B光之相對量有任何內在不平衡,可藉由將個別色彩像素驅動至該色彩之適當照度達成顯示器中之一所期望R、G及B平衡(通常以白色照度(例如,一D65白點)指代)。舉例而言,若與綠色光相比一W OLED所產生之藍色光不足且紅色光過多,則可以較高電壓驅動B像素以產生更多藍色光,而可以較低電壓驅動R像素以使得所產生之紅色光減少。The above results refer to a white OLED device before the addition of color filters that will form the R, G, and B pixels for a microdisplay. It is well known in the art that a desired R, G, and B balance in a display (usually referred to as white luminance (e.g., a D65 white point)) can be achieved by driving individual color pixels to the appropriate luminance for that color, regardless of any inherent imbalance in the relative amounts of R, G, and B light produced by the W OLED. For example, if a W OLED produces insufficient blue light and too much red light compared to green light, the B pixels can be driven at a higher voltage to produce more blue light, while the R pixels can be driven at a lower voltage so that less red light is produced.

圖16展示在R、G及B子像素之面積相等之情況下使用彩色濾光器之OLED裝置A-1、A-2及B-1之每一色彩產生一D65白點所需之峰值電流密度的一曲線圖。雙單元裝置(A-1及A-2)所需的B中電流密度遠大於3單元裝置B-1。R及G中之電流密度與全部3裝置中之電流密度大約相同。3單元裝置B-1所需之電流密度較小且因此在相同白點處達成相同目標照度所需之功率較小。一顯示器之壽命由連續操作之一OLED之效率下降速率判定,其主要係主要電流密度與溫度之一函數。因此,顯示器B-1之一壽命將大於A-1或A-2之壽命之2倍。FIG. 16 shows a graph of the peak current density required to produce a D65 white point for each color of OLED devices A-1, A-2, and B-1 using color filters with equal areas of R, G, and B subpixels. The current density required in B for the two-cell devices (A-1 and A-2) is much greater than that for the three-cell device B-1. The current density in R and G is about the same as for all three devices. The three-cell device B-1 requires less current density and therefore requires less power to achieve the same target illumination at the same white point. The lifetime of a display is determined by the rate at which the efficiency of an OLED in continuous operation decreases, which is primarily a function of the primary current density and temperature. Therefore, the lifetime of display B-1 will be more than twice that of A-1 or A-2.

在鑒於大小較小而需要產生相對高照度之微顯示器中,期望在以最大顯示照度顯示白色時每一色彩之總電流(及電流密度)大約相同(或儘可能接近)。此將實現以下發明之若干個優點:中性褪色(其中子像素之每一色彩之照度效率在整個裝置壽命內以大約相同速率降級)、高照度(每一像素將以其最大亮度受驅動以使得提高效率)、高對比度(每一像素之全動態範圍係可用的)及壽命延長(像素之每一色彩平等地共用電流負荷)。In microdisplays that need to produce relatively high illumination given their small size, it is desirable that the total current (and current density) for each color be approximately the same (or as close as possible) when displaying white at maximum display illumination. This will achieve several of the advantages of the invention below: neutral fading (where the illumination efficiency of each color of a subpixel degrades at approximately the same rate over the lifetime of the device), high illumination (each pixel will be driven at its maximum brightness resulting in increased efficiency), high contrast (the full dynamic range of each pixel is available), and extended lifetime (each color of the pixel shares the current load equally).

然而,若所需之電壓增大,則使用具有三個或更多個單元之OLED來增大照度之優點可被抵消。在一顯示器中,針對每一像素之電力由背板中之控制電路供應並控制。然而,在面積減小但需要高數目個像素之一微顯示器中,用於電晶體及其他電路組件之實體空間係有限的。通常而言,必須藉由更大、更厚或更穩健之電子電路系統應對更高之電壓及電流要求。當前,OLED微顯示器之大小決定了電子電路系統額定設為處置5 V或小於5 V以達成所期望之像素大小及密度(像素間距)。However, the advantage of using an OLED with three or more cells to increase illumination can be offset if the required voltage increases. In a display, the power for each pixel is supplied and controlled by control circuits in the backplane. However, in a microdisplay that is decreasing in area but requires a high number of pixels, the physical space available for transistors and other circuit components is limited. Generally speaking, the higher voltage and current requirements must be addressed by larger, thicker or more robust electronic circuit systems. Currently, the size of the OLED microdisplay dictates that the electronic circuit system be rated to handle 5 V or less to achieve the desired pixel size and density (pixel pitch).

若供應至電晶體之閘極之功率長時間過大,則例如電晶體等電子電路系統可出現毀滅性故障。然而,不是所有位準或時間之過電壓皆將致使電晶體永久故障;在諸多情形中,電晶體將因洩漏而出故障。洩漏增大係一常見故障模式,其係由一半導體裝置之非毀滅性過應力導致,此時接面或閘極氧化物遭受不足以造成一毀滅性故障的永久損壞。閘極受到過應力可導致應力引發之電流洩漏。Electronic circuit systems such as transistors can fail catastrophically if the power supplied to the transistor's gate is too great for a long period of time. However, not all levels or durations of overvoltage will cause a transistor to fail permanently; in many cases, the transistor will fail due to leakage. Increased leakage is a common failure mode caused by non-destructive overstressing of a semiconductor device, when the junction or gate oxide suffers insufficient permanent damage to cause a catastrophic failure. Overstressing the gate can result in stress-induced current leakage.

解決用於虛擬實境及類似產品之微顯示器之運動模糊需要OLED在一非常短時間週期內提供非常高照度且然後在另一時間週期內關斷(接通/關斷之總週期小於人類可察覺範圍以避免閃爍)。此意味著背板中之控制電路系統必須供應一高電壓/電流以在一個週期內產生高照度且然後在另一週期內切斷去向OLED之電力。若施加至控制電路系統中之電晶體之電力在OLED接通之週期內過高,則電流可在電晶體應「關斷」時透過電晶體洩漏且OLED不會完全關斷。在接通時之OLED照度與在應關斷時之照度之間的差通常被稱為「對比度」。期望微顯示器具有高對比度,此乃因其使影像看起來銳化且鮮亮;低對比度使影像看起來暗且平。Solving motion blur in microdisplays used for virtual reality and similar products requires that the OLED provide very high illumination for a very short period of time and then be turned off for another period of time (the total on/off cycle is less than the human perceptible range to avoid flicker). This means that the control circuitry in the backplane must supply a high voltage/current to produce high illumination for one cycle and then cut power to the OLED for another cycle. If the power applied to the transistors in the control circuitry is too high during the cycle when the OLED is on, current can leak through the transistors when they should be "off" and the OLED will not shut down completely. The difference between the illumination of the OLED when it is on and the illumination when it should be off is often called the "contrast". It is desirable for a microdisplay to have a high contrast because it makes the image appear sharp and bright; low contrast makes the image appear dark and flat.

圖17展示2單元比較性裝置及一發明性3單元裝置之幾組(照度對陰極電壓)曲線。上部一組曲線係當以全照度(白色 = CV255)驅動裝置且驅動電晶體「接通」時。下部一組曲線係當以零照度(黑色 = CV0)驅動裝置且驅動電晶體標稱「關斷」時。然而,穿過驅動電晶體之電流洩漏致使產生某種程度之少量照度且陰極處之電壓係非零的。兩組曲線之間的差異表示裝置之「對比度」且期望藉由將穿過驅動電晶體之電流洩漏帶來之照度最小化來使「對比度」儘可能高。自圖17可看到,所有三個裝置之對比度大約相同(略小於10 5)且在各種陰極電壓內相對恆定。 Figure 17 shows several sets of (illuminance versus cathode voltage) curves for a 2-cell comparative device and an inventive 3-cell device. The upper set of curves is when the device is driven at full illumination (white = CV255) and the drive transistor is "on". The lower set of curves is when the device is driven at zero illumination (black = CV0) and the drive transistor is nominally "off". However, current leakage through the drive transistor causes some small amount of illumination to occur and the voltage at the cathode is non-zero. The difference between the two sets of curves represents the "contrast" of the device and it is desirable to make the "contrast" as high as possible by minimizing the illumination brought about by current leakage through the drive transistor. As can be seen in Figure 17, the contrast of all three devices is approximately the same (slightly less than 10 5 ) and is relatively constant over a wide range of cathode voltages.

注意,發明性3單元裝置維持與比較性2單元裝置大約相同之總對比度,但需要超出驅動電晶體之設計限制之較高操作電壓。儘管與圖16中所展示之A-1或A-2相比B-1達成全白色所需之電流密度較小,但B-1仍需要更大電壓(約2.5 V,參見圖14)。沒有證據表明具有本發明中所使用之背板之較高電壓OLED之洩漏增大。此外,沒有證據表明B-1中由於較高電壓要求(參見表1)而出現任何毀滅性電晶體故障,亦沒有證據表明自控制電路系統看裝置壽命似乎受影響。此等結果出乎預料,此乃因A-1、A-2及B-1之背板中電晶體經設計成適合於驅動低電壓電晶體可接受且常用之1單元OLED或雙單元OLED的電晶體。Note that the inventive 3-cell device maintains approximately the same overall contrast as the comparative 2-cell device, but requires higher operating voltages that exceed the design limits of the drive transistors. Although B-1 requires less current density to achieve full white than A-1 or A-2 shown in Figure 16, B-1 still requires a higher voltage (about 2.5 V, see Figure 14). There is no evidence of increased leakage for the higher voltage OLEDs with the backplane used in the present invention. In addition, there is no evidence of any catastrophic transistor failures in B-1 due to the higher voltage requirement (see Table 1), nor does the device lifetime appear to be affected from the control circuitry. These results are unexpected because the transistors in the backplanes of A-1, A-2 and B-1 are designed to be suitable for driving 1-cell OLED or 2-cell OLED, which are acceptable and commonly used low-voltage transistors.

如下製備使用與A-1、A-2及B-1相同之低電壓背板之另一發明性3單元OLED裝置B-2: 層1 (底部電極/陽極): 層2 (HIL):200 HTM1 + 6% PD1 層3 (HTL1):410 HTM1 層4 (HTL2):50 HTM2 層5 (綠色LEL):100 GH1及3% GPD1 層6 (黃色LEL):100 GH1 + 10% GPD1 + 3% RPD1 層7 (ETL1):200 ETM1 層8至10 (CGL1):270 三層 層11 (HTL3):570 HTM1 層12 (藍色LEL2):250 BH1 + 4% BFD1 層13 (ETL2):150 ETM2 層14至16 (CGL2):270三層(與CGL1相同之方案) 層17 (HTL4):3840 HTM1 層18 (BLEL1):250 BH1 + 4% BFD1 層19 (ETL3):150 ETM2 層20 (EIL):100 ETM2 + 2% Li 層21 (半透明陰極):105 75% Ag/25% Mg Another inventive 3-cell OLED device B-2 using the same low voltage backplane as A-1, A-2 and B-1 was prepared as follows: Layer 1 (bottom electrode/anode): Layer 2 (HIL): 200 HTM1 + 6% PD1 Layer 3 (HTL1): 410 HTM1 Layer 4 (HTL2): 50 HTM2 Layer 5 (green LEL): 100 GH1 and 3% GPD1 Layer 6 (yellow LEL): 100 GH1 + 10% GPD1 + 3% RPD1 Layer 7 (ETL1): 200 ETM1 Layers 8 to 10 (CGL1): 270 Trilayer Layer 11 (HTL3): 570 HTM1 Layer 12 (Blue LEL2): 250 BH1 + 4% BFD1 Layer 13 (ETL2): 150 ETM2 Layers 14 to 16 (CGL2): 270 triple layer (same scheme as CGL1) Layer 17 (HTL4): 3840 HTM1 Layer 18 (BLEL1): 250 BH1 + 4% BFD1 Layer 19 (ETL3): 150 ETM2 Layer 20 (EIL): 100 ETM2 + 2% Li Layer 21 (semi-transparent cathode): 105 75% Ag/25% Mg

OLED B-2係與B-1相似之一3單元裝置,此乃因其含有一G-Y單元(層5及6),該G-Y單元藉由一CGL (層8至層10)與一第二藍色單元(層12)分隔開,該第二藍色單元繼而藉由一第二CGL (層14至層16)與一第一藍色單元(層18)分隔開,(自背板開始)呈現Y-G/B/B之次序。與B-1相似,B-2係具有6910 Å之一微腔之一微腔白色光產生OLED。OLED B-2 is a 3-cell device similar to B-1 in that it contains a G-Y cell (layers 5 and 6) separated by a CGL (layers 8 to 10) from a second blue cell (layer 12), which in turn is separated from a first blue cell (layer 18) by a second CGL (layers 14 to 16), in the order Y-G/B/B (starting from the backplane). Similar to B-1, B-2 is a microcavity white light generating OLED with a microcavity of 6910 Å.

類似地,如下製備一發明性4單元OLED裝置C-1: 層1至11:與B-2中之層1-11相同 層12 (藍色LEL2):200 BH1 + 4% BFD1 (減小50 Å) 層13 (ETL2):100 ETM2 (減小50 Å) 層14至16:與B-2中之層14至16相同 層17 (HTL4):420 HTM1 (減小3420 Å) 層18 (BLEL1):200 BH1 + 4% BFD1 (減小50 Å) 層19 (ETL3):100 ETM2 (減小50 Å) 層20至22 (CGL3):270三層(與CGL1及CGL2相同之方案) 層23 (HTL5):2620 HTM1 層24 (HTL6):50 HTM2 層25 (黃色LEL):200 GH1 + 10% GPD1 + 3% RPD1 層26 (ETL4):480 ETM1 層27至28:與B-2中之層20至21相同 Similarly, an inventive 4-unit OLED device C-1 was prepared as follows: Layers 1 to 11: Same as layers 1-11 in B-2 Layer 12 (Blue LEL2): 200 BH1 + 4% BFD1 (50 Å less) Layer 13 (ETL2): 100 ETM2 (50 Å less) Layers 14 to 16: Same as layers 14 to 16 in B-2 Layer 17 (HTL4): 420 HTM1 (3420 Å less) Layer 18 (BLEL1): 200 BH1 + 4% BFD1 (50 Å less) Layer 19 (ETL3): 100 ETM2 (50 Å less) Layers 20 to 22 (CGL3): 270 three layers (same solution as CGL1 and CGL2) Layer 23 (HTL5): 2620 HTM1 Layer 24 (HTL6): 50 HTM2 Layer 25 (yellow LEL): 200 GH1 + 10% GPD1 + 3% RPD1 Layer 26 (ETL4): 480 ETM1 Layers 27 to 28: Same as layers 20 to 21 in B-2

OLED C-1係一4單元裝置此乃因其含有一額外Y單元(層25)以及與B-2中相同之G-Y單元及兩個B單元,(自背板開始)呈Y-G/B/B/Y之次序。在C-1中,額外Y單元藉由CGL3 (層20-22)與第一B單元(層18)分隔開。C-1係具有6910 Å之一微腔之一微腔白色光產生OLED。OLED C-1 is a 4-cell device because it contains an extra Y cell (layer 25) as well as the same G-Y cell and two B cells as in B-2, in the order Y-G/B/B/Y (starting from the backplane). In C-1, the extra Y cell is separated from the first B cell (layer 18) by CGL3 (layers 20-22). C-1 is a microcavity white light generating OLED with a microcavity of 6910 Å.

類似地,如下製備一發明性5單元OLED裝置D-1: 層1至10:C-1中之層1至11相同 層11 (HTL3):370 HTM1 (減小200 Å) 層12至16:與C-1中之層12至17相同 層18 (ETL2):100 ETM2 (減小50 Å) 層14至16:與C-1中之層14至16相同 層17 (HTL4):620 HTM1 (增大200 Å) 層18至層22:C-1中之層18至22相同 層23 (HTL5):610 HTM1 (減小2010 Å) 層24 (BLEL3):200 BH1 + 4% BFD1 層25 (ETL3):100 ETM2 層26至層28 (CGL4):270三層(與CGL1、CGL2及CGL3相同之方案) 層29 (HTL6):1440 HTM1 層30至層34:與C-1中之層24至28相同 Similarly, an inventive 5-unit OLED device D-1 was prepared as follows: Layers 1 to 10: Same as layers 1 to 11 in C-1 Layer 11 (HTL3): 370 HTM1 (200 Å less) Layers 12 to 16: Same as layers 12 to 17 in C-1 Layer 18 (ETL2): 100 ETM2 (50 Å less) Layers 14 to 16: Same as layers 14 to 16 in C-1 Layer 17 (HTL4): 620 HTM1 (200 Å more) Layers 18 to 22: Same as layers 18 to 22 in C-1 Layer 23 (HTL5): 610 HTM1 (2010 Å less) Layer 24 (BLEL3): 200 BH1 + 4% BFD1 Layer 25 (ETL3): 100 ETM2 Layers 26 to 28 (CGL4): 270 three layers (same solution as CGL1, CGL2 and CGL3) Layer 29 (HTL6): 1440 HTM1 Layers 30 to 34: Same as layers 24 to 28 in C-1

OLED D-1係一5單元裝置,此乃因其含有一額外B單元(層24)以及與C-1中相同之Y單元、G-Y單元及兩個B單元。其具有全部皆由一CGL分隔開的總共3個B單元、一個Y單元及一個G-Y單元,(自背板開始)呈Y-G/B/B/B/Y次序。C-1係具有6910 Å之一微腔之一微腔白色光產生OLED。OLED D-1 is a 5-cell device because it contains an additional B cell (layer 24) and the same Y cell, G-Y cell, and two B cells as in C-1. It has a total of 3 B cells, one Y cell, and one G-Y cell, all separated by a CGL, in the order Y-G/B/B/B/Y (starting from the backplane). C-1 is a microcavity white light generating OLED with a microcavity of 6910 Å.

圖18展示OLED B-2、C-1及D-1之特性I-V曲線,其亦列示於表2中。 表2 – 列示OLED之I-V資料 裝置 I* V* L* B-2 臨限值 8.2 -    1 9.1 30.9    5 10.2 35.4    10 10.9 35.8    100 15.8 30.2 C-1 臨限值 10.5 -    1 11.7 52.6    5 13.0 53.6    10 13.9 52.7    100 19.0 42.2 D-1 臨限值 12.8 -    1 14.5 50.5    5 16.0 51.9    10 17.1 51.6    100 22.1 42.1 * I = 電流,以mA/cm 2為單位 V = 電壓 L =照度,以cd/A為單位 Figure 18 shows the characteristic IV curves of OLED B-2, C-1 and D-1, which are also listed in Table 2. Table 2 - IV data of OLEDs Device I* V* L* B-2 Threshold 8.2 - 1 9.1 30.9 5 10.2 35.4 10 10.9 35.8 100 15.8 30.2 C-1 Threshold 10.5 - 1 11.7 52.6 5 13.0 53.6 10 13.9 52.7 100 19.0 42.2 D-1 Threshold 12.8 - 1 14.5 50.5 5 16.0 51.9 10 17.1 51.6 100 22.1 42.1 * I = current in mA/ cm2 V = voltage L = illuminance in cd/A

如圖18及表2所展示,在OLED內添加每一單元提供較大照度但亦將V th及操作電壓增大約2.5 V。 As shown in FIG. 18 and Table 2, adding each cell in the OLED provides greater illumination but also increases Vth and the operating voltage by approximately 2.5 V.

圖19中可看到將額外單元添加至一微腔3單元OLED之優點,圖19比較B-2 (3單元)、C-1 (4單元)及D-1 (5單元)之光譜輸出(沒有彩色濾光器)。OLED B-2具有一G/Y單元及2個B單元。添加與C-1中相同之另一Y單元相對於B-2而言會增大G及R發射量但B發射量之增大則不多。添加如D-1中相同之一第三B單元在保持較高G及R發射之情況下進一步增大藍色發射。The advantage of adding extra cells to a microcavity 3-cell OLED can be seen in Figure 19, which compares the spectral output (without color filters) of B-2 (3 cells), C-1 (4 cells), and D-1 (5 cells). OLED B-2 has a G/Y cell and 2 B cells. Adding another Y cell, like in C-1, increases G and R emission but not B emission much relative to B-2. Adding a third B cell, like in D-1, further increases blue emission while maintaining high G and R emission.

與圖16中所展示之結果類似,圖20展示OLED B-2、C-1及D-1形成1500 cd/m 2之一平衡白色照度(使用一彩色濾光器)所需的每一色彩像素之峰值電流密度之相對量。在C-1中添加一額外Y單元能使產生必需的R及G照度量所需之電流與B-2相比減小。在D-1中添加一額外B單元能使產生必需的B光量所需之電壓與C-1相比進一步減小。由於具有三個或更多個單元之此等OLED達成相同照度所需之電流密度較小,因此其操作壽命將顯著大於具有較少單元之OLED。此等裝置之LT70 (發射輸出降級達70%之時間)壽命預計為至少18,000小時之平均視訊內容。 Similar to the results shown in FIG. 16 , FIG. 20 shows the relative amounts of peak current density per color pixel required to produce a balanced white illuminance of 1500 cd/m 2 (using a color filter) for OLEDs B-2, C-1, and D-1. Adding an additional Y cell in C-1 reduces the current required to produce the necessary amounts of R and G illuminance compared to B-2. Adding an additional B cell in D-1 further reduces the voltage required to produce the necessary amount of B light compared to C-1. Because these OLEDs with three or more cells require less current density to achieve the same illuminance, their operating lifetimes will be significantly greater than OLEDs with fewer cells. The LT70 (time for emission output to degrade by 70%) lifetime of these devices is expected to be at least 18,000 hours of average video content.

圖21 (類似於圖17)展示OLED B-2、C-1及D-1之幾組(照度對陰極電壓)曲線。在所有三個此等實例中,對比度大約相同(略小於10 5)且在各種陰極電壓內相對恆定。值得注意的是,即使當此等裝置之操作電壓係驅動電晶體之設計限制之2倍或3倍時,對比度仍保持不變。 Figure 21 (similar to Figure 17) shows several sets of (illuminance vs. cathode voltage) curves for OLEDs B-2, C-1, and D-1. In all three of these examples, the contrast is about the same (slightly less than 10 5 ) and relatively constant over a wide range of cathode voltages. Notably, the contrast remains constant even when the devices are operated at voltages that are 2 or 3 times the design limit of the drive transistors.

不受任何特定理論或推測限制,關於當使用具有低電壓電晶體之背板時需要相對高V th之堆疊式OLED維持高對比度但不會造成燒壞或破壞的原因,可能與使用串聯連接電晶體相關。電晶體中之電流洩漏係一眾所周知問題且通常而言,所涉及之電壓及電流越高,則洩漏量越大。如先前所論述,此洩漏可致使OLED在大於Vth之情況下發光。由於穿過串聯連接電晶體之總洩漏將係(第一電晶體之洩漏) × (第二電晶體之洩漏),因此可能此倍增效應足以明顯足夠地減小OLED之底部電極處之洩漏,以使得OLED不因電流洩漏而發射且因此維持對比度。 Without being bound by any particular theory or speculation, the reason why a stacked OLED needs to maintain high contrast with a relatively high Vth without burning or damage when using a backplane with low voltage transistors may be related to the use of series connected transistors. Current leakage in transistors is a well known problem and generally speaking, the higher the voltages and currents involved, the greater the leakage. As previously discussed, this leakage can cause the OLED to emit light at greater than Vth. Since the total leakage through the series connected transistors will be (leakage of the first transistor) x (leakage of the second transistor), it is possible that this multiplication effect is sufficient to significantly reduce the leakage at the bottom electrode of the OLED enough so that the OLED does not emit due to current leakage and thus maintain contrast.

在操作中,位於實驗微顯示器之背板中、包括具有其等通道串聯連接之至少兩個電晶體的控制電路係一緊湊電路之一實例,其保護驅動電晶體T1不在規定範圍之外的條件(甚至當以大於LV電晶體之規定操作範圍之一開關電壓範圍驅動具有三個或更多個堆疊之一OLED時)下操作。若OLED之開關電壓範圍超過LV操作範圍,則僅開關電晶體暴露於此等條件。此對影像品質之損壞要小於其中驅動電晶體必然會在特定操作範圍之外操作的另一像素電路設計。In operation, the control circuitry in the backplane of the experimental microdisplay, including at least two transistors with their equal channels connected in series, is an example of a compact circuit that protects the drive transistor T1 from operating under conditions outside the specified range, even when driving an OLED having three or more stacks with a switching voltage range greater than the specified operating range of the LV transistor. If the switching voltage range of the OLED exceeds the LV operating range, only the switching transistor is exposed to these conditions. This is less detrimental to image quality than another pixel circuit design in which the drive transistor is bound to operate outside the specified operating range.

在操作過程中,MOSFET裝置老化,此導致如臨限值電壓、子臨限值斜坡及飽和時之跨導等特性中之某些特性緩慢轉變。此等係p通道電晶體中發現之負偏壓溫度不穩定(NBTI)及熱載子注入(HCI)之所有徵兆。藉由將一電晶體之操作限制於電晶體之規定電壓範圍內確保電晶體特性將在一長週期內(例如5年)保持於一窄規定範圍內。電晶體在規定電壓範圍之外操作會增大電晶體特性改變之速率,因而縮短特性處於規定範圍內之週期。During operation, MOSFET devices age, which causes some of the characteristics such as threshold voltage, subthreshold slope, and transconductance at saturation to slowly change. These are all symptoms of negative bias temperature instability (NBTI) and hot carrier injection (HCI) found in p-channel transistors. By limiting the operation of a transistor to the specified voltage range of the transistor, it is ensured that the transistor characteristics will remain within a narrow specified range over a long period of time (e.g., 5 years). Operating the transistor outside the specified voltage range increases the rate at which the transistor characteristics change, thereby shortening the period during which the characteristics are within the specified range.

驅動電晶體之特性保持於規定限制內係重要的,否則可導致影像降級(通常稱為不均衡)。開關電晶體之操作即使在其效能特性之改變時仍更穩健,且可以即使當電晶體特性已轉變至規定範圍之外時仍確保操作令人滿意的一足夠寬的閘極電壓來驅動。因此,圖2至圖6中所展示之電路(包含用於發明性實驗堆疊式OLED微顯示器之背板之電路在內)係一緊湊電路之實例,其經設計以在不會因超出電晶體之規定操作範圍而使顯示器品質出現預期下降之情況下應對與三個或更多個OLED單元相關聯之較高開關電壓。It is important that the characteristics of the drive transistors remain within specified limits, otherwise image degradation (commonly referred to as unbalance) may result. The operation of the switching transistors is more robust even with changes in their performance characteristics, and can be driven with a sufficiently wide gate voltage to ensure satisfactory operation even when the transistor characteristics have shifted outside of the specified range. Thus, the circuits shown in FIGS. 2 to 6 , including the circuits used in the backplane of the inventive experimental stacked OLED microdisplay, are examples of compact circuits designed to handle the higher switching voltages associated with three or more OLED cells without causing the expected degradation of the display quality due to exceeding the specified operating range of the transistors.

據信圖2至圖6中之電路藉由選擇SELECT2電壓以「接通」發射及「關斷」發射來達成此目的。為「關斷」發射,SELECT2電壓之一理想選擇係V DD,其將把T2置於操作之子臨限值區中,從而有效地停止電流。為「接通」發射,可將SELECT2電壓選擇為低至5 V,其低於V DDIt is believed that the circuits in Figures 2-6 achieve this by selecting the SELECT2 voltage to turn transmission "on" and "off". For "off" transmission, an ideal choice for the SELECT2 voltage is VDD , which will place T2 in the sub-threshold region of operation, effectively stopping the current. For "on" transmission, the SELECT2 voltage can be selected to be as low as 5 V, which is lower than VDD .

若OLED之開關電壓擺動小於約4V,則當像素顯示「黑色」時,將藉由以一正常方式驅動電晶體設定黑色位準電流且T1之汲極將高於SELECT2「接通」電壓且開關電晶體T2仍導通。然而,當OLED之開關電壓擺動大於約4V時,與在多單元堆疊式OLED具有4個以上單元之情形中相同,當形成黑色位準電流時,T1之汲極電壓(亦係T2之源極電壓)接近SELECT2「接通」電壓,且當T1之低汲極電壓將T2之過電壓(Vgs-Vth)減小至零或略負時關斷開關電晶體T2。此將T2驅動至子臨限值範圍中,從而形成黑色位準。在由多單元堆疊式OLED形成之此等條件下,驅動電晶體T1控制T2以形成黑色位準電流。If the OLED's switching voltage swing is less than about 4V, when the pixel displays "black", the black level current will be set by driving the transistors in a normal manner and the drain of T1 will be higher than the SELECT2 "on" voltage and the switching transistor T2 will still be on. However, when the OLED's switching voltage swing is greater than about 4V, as in the case of a multi-cell stacked OLED with more than 4 cells, when the black level current is formed, the drain voltage of T1 (also the source voltage of T2) is close to the SELECT2 "on" voltage, and the switching transistor T2 is turned off when the low drain voltage of T1 reduces the overvoltage of T2 (Vgs-Vth) to zero or slightly negative. This drives T2 into the sub-threshold range, thereby forming a black level. Under these conditions formed by a multi-cell stacked OLED, the driver transistor T1 controls T2 to form a black level current.

因此,據信圖2至圖6中所展示之簡單串聯連接電晶體設計能夠驅動一開關電壓範圍超過低電壓電晶體之電壓範圍的一多單元堆疊式OLED,其中與例如圖1中所展示一單個電晶體驅動電路相比老化相關不均衡減少。Therefore, it is believed that the simple series-connected transistor design shown in Figures 2 to 6 is capable of driving a multi-cell stacked OLED with a switching voltage range exceeding the voltage range of low-voltage transistors with reduced aging-related imbalance compared to a single transistor driving circuit shown in Figure 1, for example.

保護電路經設計以每當OLED旨在「關斷」或不發射時維持OLED之陽極處之電壓低於某一位準且可有助於維持高對比度。當陰極電壓減小(更負電壓)時,保護電路經設計以提供額外電流以保護驅動電晶體及開關電晶體以使電壓位準不違反裝置之最大額定值。The protection circuit is designed to maintain the voltage at the anode of the OLED below a certain level whenever the OLED is intended to be "off" or not emitting and can help maintain a high contrast ratio. When the cathode voltage decreases (more negative), the protection circuit is designed to provide additional current to protect the drive transistors and the switching transistors so that the voltage level does not violate the maximum rating of the device.

然而,在BJT之基極被隔離且未連接至一外部電源之實驗實例中仍能觀察到保護效果,因此無需特意控制基極電壓。已觀察到,在沒有堆疊式OLED之裝置中OLED顯示器之黑電流對電壓(0.75十位/伏特)之指數斜坡類似於存在OLED之實例。此表明當BJT之基極被隔離時保護電路仍在OLED之陽極處提供某些電流及電壓控制。不受任何特定理論或推測限制,可能一鄰近n井(例如,開關電晶體T2之n井)可係遷移至BJT BJT1之p井(基極)之電洞之一來源。一旦此等電洞處於基極中,其將跨越空乏區擴散至n型射極觸點(OLED陽極接墊),從而在正向方向上行進穿過基極射極二極體。此將藉由熱激發電子自射極擴散至基極中及其穿過基極及空乏區傳輸至集電極中補充,擴散及傳輸係由基極與集電極之間的大電場電位促成。在此情形中,來自(驅動電晶體或開關電晶體之)鄰近n井之電洞將電荷(電洞)提供至將通常來自於外部基極連接之基極中。當OLED陽極電壓下降至非常低位準(例如,以利用三個或更多個OLED單元展示黑色)時,則驅動電路電晶體中之一者(將處於V DD)之一鄰近n井與BJT基極(處於OLED陽極電壓)之間的電位差非常大,從而增大自驅動電晶體井至BJT基極中之電洞流。基極電流之此增大由於BJT之放大而增大射極電流。 However, the protection effect was still observed in experimental examples where the base of the BJT was isolated and not connected to an external power source, so there was no need to specifically control the base voltage. It was observed that the exponential slope of the black current versus voltage (0.75 decibels/volt) of the OLED display in the device without the stacked OLED was similar to the example with the OLED present. This suggests that the protection circuitry still provides some current and voltage control at the anode of the OLED when the base of the BJT is isolated. Without being bound by any particular theory or speculation, it is possible that a neighboring n-well (e.g., the n-well of the switching transistor T2) may be a source of holes that migrate to the p-well (base) of the BJT BJT1. Once these holes are in the base, they will diffuse across the depletion region to the n-type emitter contact (OLED anode pad), thereby traveling through the base emitter diode in the forward direction. This will be replenished by the diffusion of thermally excited electrons from the emitter into the base and their transport through the base and depletion region to the collector, the diffusion and transport being facilitated by the large electric field potential between the base and collector. In this case, holes from the neighboring n-well (of the drive transistor or the switching transistor) provide charge (holes) to the base which will usually come from the external base connection. When the OLED anode voltage drops to a very low level (e.g., to display black with three or more OLED cells), the potential difference between a neighboring n-well of one of the driver circuit transistors (which will be at V DD ) and the BJT base (at the OLED anode voltage) is very large, increasing the hole flow from the driver transistor well into the BJT base. This increase in base current increases the emitter current due to amplification of the BJT.

然而,保護電路所提供之保護效應對於每一圖框而言皆不同且必須針對影像之每一新圖框恰當地重設。當BJT之基極連接至一外部電源且針對每一訊框加以主動控制時,此不會成為一問題。針對BJT之基極被隔離且未特意連接之實施例,由於開關電晶體提供開閉效應,因此當開關電晶體關斷像素時可提供每一圖框之重設。因此,保護效應控制運動之此態樣取決於具有串聯連接的驅動電晶體與開關電晶體,此乃因 其必須在資料載入期間(或在圖框時間之某些部分)關斷發射以進行重設。However, the protection effect provided by the protection circuit is different for each frame and must be reset appropriately for each new frame of the image. This is not a problem when the base of the BJT is connected to an external power supply and actively controlled for each frame. For embodiments where the base of the BJT is isolated and not intentionally connected, since the switching transistor provides the switching effect, a reset for each frame can be provided when the switching transistor turns off the pixel. Therefore, this aspect of the protection effect control movement depends on having a drive transistor and a switching transistor connected in series, because they must turn off the transmission during data loading (or some part of the frame time) to reset.

具有三個或更多個單元之OLED方案可經設計 以使得自黑色位準(低於Vth;例如2uA/cm2)至白色位準(20mA/cm2)之電壓範圍相對恆定且小於約6V。如圖17及圖21中所展示,此可使得對比度係約10,000:1且可略較小,此乃因在電流密度之高端處電流效率下降。僅在當驅動電晶體及/或開關電晶體停止電流時的電流範圍底端處保護電路發揮作用時,此電壓範圍才大約處於LV電晶體之容許操作範圍內。因此,在範圍之低電流端,保護電路另外亦防止通過OLED之電流密度降低至低於約2 uA/cm 2。雖然此效應係藉由具有上文所論述之至少兩個串聯連接電晶體提供之額外保護,但其限制了達成較高對比度之能力。以此略高黑色位準及減小對比度為交換,保護電路允許藉由降低陰極電壓推動像素驅動電路達成較高峰值亮度或補償由於OLED老化所致之效率損失,以確保LV電晶體在其規定電壓範圍內操作。 OLED schemes with three or more cells can be designed so that the voltage range from black level (below Vth; e.g. 2uA/cm2) to white level (20mA/cm2) is relatively constant and less than about 6V. As shown in Figures 17 and 21, this can result in a contrast ratio of about 10,000:1 and can be slightly less, since the current efficiency drops at the high end of the current density. This voltage range is approximately within the permissible operating range of the LV transistors only when the protection circuitry comes into play at the bottom of the current range when the drive transistors and/or the switch transistors stop the current. Thus, at the low current end of the range, the protection circuitry additionally prevents the current density through the OLED from dropping below about 2 uA/ cm2 . Although this effect is provided with additional protection by having at least two series connected transistors as discussed above, it limits the ability to achieve higher contrast. In exchange for this slightly higher black level and reduced contrast, the protection circuit allows the pixel driver circuit to achieve higher peak brightness or compensate for efficiency loss due to OLED aging by reducing the cathode voltage to ensure that the LV transistor operates within its specified voltage range.

以上說明闡述若干個不同實施例,該若干個不同實施例可涉及不同個別特徵之不同組合。任何實施例之個別特徵可視需要不受限制地以任何次序或程度組合,但惟當不相容時時除外。The above description describes several different embodiments, which may involve different combinations of different individual features. The individual features of any embodiment may be combined in any order or degree as desired without restriction, except when incompatible.

在以上說明中,參考附圖,附圖形成以上說明之一部分且在附圖中藉由圖解說明展示可實踐之特定實施例。詳細地闡述此等實施例以使熟習此項技術者能夠實踐本發明,且應理解,可利用其他實施例且可做出結構改變、邏輯改變及電改變,此並不背離本發明之範疇。因此,不應在限制意義上理解對任何實例性實施例之說明。儘管已出於圖解說明目的闡述本發明,但應理解,此細節僅出於圖解說明目的且熟習此項技術者可做出變化,而此並不背離本發明之精神及範疇。In the above description, reference is made to the accompanying drawings, which form a part thereof and in which specific embodiments that may be practiced are shown by way of illustration. These embodiments are described in detail to enable one skilled in the art to practice the invention, and it is understood that other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. Therefore, the description of any exemplary embodiment should not be understood in a limiting sense. Although the invention has been described for illustrative purposes, it is understood that such details are for illustrative purposes only and that variations may be made by one skilled in the art without departing from the spirit and scope of the invention.

1:像素界定層 3:矽背板 5:選用性平坦化層 7:電觸點 9:第一電極區段 9A:第一電極層 9B:反射層 11:非發光有機發光二極體層 13:第一發光有機發光二極體單元 13A:紅色發光有機發光二極體單元 15:電荷產生層 16:黃色發光OLED單元 17:第二發光有機發光二極體單元 17A:綠色發光有機發光二極體單元 19:電荷產生層 21:第三發光有機發光二極體單元 21A:藍色發光有機發光二極體單元 22:藍色發光層 23:非發光有機發光二極體層 24:電荷產生層 25:頂部電極 27:囊層體 29:彩色濾光器陣列 29B:藍色濾光器 29G:綠色濾光器 29R:紅色濾光器 30:微腔 32:第二藍色發光單元 45:電源 50:電源 100:RGB微顯示器/微顯示器 200:多模式微腔有機發光二極體堆疊之微顯示器/微顯示器 300:多模式微腔有機發光二極體堆疊之微顯示器/微顯示器 400:多模式微腔有機發光二極體堆疊之微顯示器/多模式有機發光二極體微顯示器/微顯示器 A-1:2單元堆疊式有機發光二極體裝置/有機發光二極體 A-2:第二比較性有機發光二極體裝置/裝置/有機發光二極體 B-1:發明性3單元堆疊式有機發光二極體/有機發光二極體裝置/顯示器/有機發光二極體 B-2:發明性3單元有機發光二極體裝置/有機發光二極體 BJT1:雙極接面電晶體 C1:儲存電容器 C-1:發明性4單元有機發光二極體裝置/有機發光二極體 D-1:發明性5單元有機發光二極體裝置/有機發光二極體 D4:二極體 GND:接地 IBD1:本徵主體二極體 IBD2:本徵主體二極體 IBD3:本徵主體二極體 IBD5:本徵主體二極體 IBD6:本徵主體二極體 LSC:位準移位電路 MP1:電晶體 MP2:電流驅動電晶體/電晶體 SELECT1:選擇線 SELECT2:選擇線 SELECT3:選擇線 T1:p通道驅動電晶體/驅動電晶體 T2:開關電晶體 T3:直排選擇電晶體/掃描電晶體 T4:第三電晶體/驅動電晶體 T5:直排選擇電晶體 T6:保護電路p通道電晶體 V B:基極電壓 V C:集電極電壓 V CATHODE:陰極電壓 V DD:外部電源/電壓源/恆定供應電壓 V DD2:電壓源 V E:射極電壓/電壓 V REF:電壓參考/參考電壓 1: Pixel definition layer 3: Silicon backplane 5: Optional planarization layer 7: Electrical contact 9: First electrode segment 9A: First electrode layer 9B: Reflection layer 11: Non-luminescent organic light-emitting diode layer 13: First light-emitting organic light-emitting diode unit 13A: Red light-emitting organic light-emitting diode unit 15: Charge generation layer 16: Yellow light-emitting organic light-emitting diode unit 17: Second light-emitting organic light-emitting diode unit 17A: Green light-emitting organic light-emitting diode unit 19: Charge generation layer 21: Third light-emitting organic light-emitting diode unit 21A: Blue light-emitting organic light-emitting diode unit 22: Blue light-emitting layer 23: Non-luminescent organic light-emitting diode unit LED layer 24: charge generation layer 25: top electrode 27: capsule layer 29: color filter array 29B: blue filter 29G: green filter 29R: red filter 30: microcavity 32: second blue light emitting unit 45: power supply 50: power supply 100: RGB microdisplay/microdisplay 200: multi-mode microcavity organic light emitting diode stacked microdisplay/microdisplay 300: multi-mode microcavity organic light emitting diode stacked microdisplay/microdisplay 400: multi-mode microcavity organic light emitting diode stacked microdisplay/multi-mode organic light emitting diode microdisplay/microdisplay A- 1: 2-unit stacked organic light-emitting diode device/organic light-emitting diode A-2: second comparative organic light-emitting diode device/device/organic light-emitting diode B-1: inventive 3-unit stacked organic light-emitting diode/organic light-emitting diode device/display/organic light-emitting diode B-2: inventive 3-unit organic light-emitting diode device/organic light-emitting diode BJT1: bipolar junction transistor C1: storage capacitor C-1: inventive 4-unit organic light-emitting diode device/organic light-emitting diode D-1: inventive 5-unit organic light-emitting diode device/organic light-emitting diode D4: diode GND : Ground IBD1: Intrinsic body diode IBD2: Intrinsic body diode IBD3: Intrinsic body diode IBD5: Intrinsic body diode IBD6: Intrinsic body diode LSC: Level shift circuit MP1: Transistor MP2: Current drive transistor/transistor SELECT1: Select line SELECT2: Select line SELECT3: Select line T1: p-channel drive transistor/drive transistor T2: Switching transistor T3: DC select transistor/scan transistor T4: Third transistor/drive transistor T5: DC select transistor T6: Protection circuit p-channel transistor V B : Base voltage V C : Collector voltage V CATHODE : Cathode voltage V DD : External power supply/voltage source/constant supply voltage V DD2 : Voltage source VE : Emitter voltage/voltage V REF : Voltage reference/reference voltage

圖1展示一OLED之一簡單先前技術控制電路。 圖2展示具有具有其等通道串聯連接之兩個電晶體之一基本控制電路,該基本控制電路適合於具有至少三個OLED單元之一OLED堆疊。 圖3展示圖2之本徵主體二極體連接之一項實施例。 圖4展示圖2之本徵主體二極體連接之另一實施例。 圖5A展示具有具有其等通道串聯連接之三個電晶體之一基本控制電路,該基本控制電路適合於具有至少三個OLED單元之一OLED堆疊。圖5B類似於圖5A,唯驅動電晶體係經由一位準位移電路控制除外。 圖6展示適合於具有至少三個OLED單元及一額外保護電路之一OLED堆疊之一基本控制電路,該額外保護電路包括二極體連接p通道MOSFET電晶體。 圖7展示包括二極體之一類似保護電路。 圖8展示適合於具有至少三個OLED單元及一保護電路之一OLED堆疊之一基本控制電路,該保護電路具有一雙極接面電晶體(BJT)。 圖9展示貫穿Si背板之一示意性剖面,該示意性剖面圖解說明圖8中所展示之電路之連接位置、連接及電晶體井。 圖10展示具有三個毗鄰單色RGB OLED堆疊之一RGB微顯示器100之一剖面圖,每一個別堆疊具有三個OLED發光單元。 圖11展示具有一多模式微腔OLED堆疊之微顯示器200之一剖面圖,該多模式微腔OLED堆疊具有三個OLED發光單元及一RGB彩色濾光器陣列。 圖12展示具有一多模式微腔OLED堆疊之微顯示器300之一剖面圖,該多模式微腔OLED堆疊具有包括一額外藍色發光層之三個OLED發光單元及一RGB彩色濾光器陣列。 圖13展示具有一多模式微腔OLED堆疊之微顯示器400之一剖面圖,該多模式微腔OLED堆疊具有五個OLED發光單元及一RGB彩色濾光器陣列。 圖14展示某些比較性OLED裝置及發明性OLED裝置之電流密度對電壓之一曲線圖。 圖15展示某些比較性OLED裝置及發明性OLED裝置之光譜(繪示為強度對波長)。 圖16展示具有彩色濾光器之比較性OLED裝置及發明性OLED裝置之每一色彩為產生一D65白點所需之峰值電流密度之一圖表。 圖17展示當比較性OLED裝置及發明性OLED裝置經驅動以產生黑色時且在峰值白色照度下比較性OLED裝置及發明性OLED裝置之照度對電壓之一曲線圖。 圖18展示某些發明性OLED裝置之電流密度對電壓之一曲線圖。 圖19展示某些發明性OLED裝置之光譜(繪示為強度對波長)。 圖20展示具有彩色濾光器之某些發明性OLED裝置之每一色彩為產生一D65白點所需之峰值電流密度之一圖表。 圖21展示當某些發明性OLED裝置經驅動以產生黑色時且在峰值白色照度下該等發明性OLED裝置之照度對電壓之一曲線圖。 FIG. 1 shows a simple prior art control circuit for an OLED. FIG. 2 shows a basic control circuit having two transistors with their equal channel series connection, the basic control circuit being suitable for an OLED stack having at least three OLED cells. FIG. 3 shows an embodiment of the intrinsic body diode connection of FIG. 2. FIG. 4 shows another embodiment of the intrinsic body diode connection of FIG. 2. FIG. 5A shows a basic control circuit having three transistors with their equal channel series connection, the basic control circuit being suitable for an OLED stack having at least three OLED cells. FIG. 5B is similar to FIG. 5A, except that the drive transistors are controlled via a level shift circuit. FIG. 6 shows a basic control circuit suitable for an OLED stack having at least three OLED cells and an additional protection circuit comprising a diode connected p-channel MOSFET transistor. FIG. 7 shows a similar protection circuit comprising a diode. FIG. 8 shows a basic control circuit suitable for an OLED stack having at least three OLED cells and a protection circuit having a bipolar junction transistor (BJT). FIG. 9 shows a schematic cross-section through a Si backplane illustrating connection locations, connections and transistor wells for the circuit shown in FIG. 8. FIG. 10 shows a cross-section of an RGB microdisplay 100 having three adjacent single color RGB OLED stacks, each individual stack having three OLED light emitting cells. FIG. 11 shows a cross-sectional view of a microdisplay 200 having a multi-mode microcavity OLED stack with three OLED light-emitting cells and an RGB color filter array. FIG. 12 shows a cross-sectional view of a microdisplay 300 having a multi-mode microcavity OLED stack with three OLED light-emitting cells including an additional blue light-emitting layer and an RGB color filter array. FIG. 13 shows a cross-sectional view of a microdisplay 400 having a multi-mode microcavity OLED stack with five OLED light-emitting cells and an RGB color filter array. FIG. 14 shows a graph of current density versus voltage for certain comparative OLED devices and inventive OLED devices. FIG. 15 shows the spectra of certain comparative OLED devices and inventive OLED devices (plotted as intensity versus wavelength). FIG. 16 shows a graph of the peak current density required to produce a D65 white point for each color of the comparative OLED devices and inventive OLED devices with color filters. FIG. 17 shows a graph of illumination versus voltage for the comparative OLED devices and inventive OLED devices when the comparative OLED devices and inventive OLED devices are driven to produce black and at peak white illumination. FIG. 18 shows a graph of current density versus voltage for certain inventive OLED devices. FIG. 19 shows the spectra of certain inventive OLED devices (plotted as intensity versus wavelength). FIG. 20 shows a graph of the peak current density required for each color to produce a D65 white point for certain inventive OLED devices with color filters. FIG. 21 shows a graph of illumination versus voltage for certain inventive OLED devices when they are driven to produce black and at peak white illumination.

SELECT1:選擇線 SELECT1: Select line

SELECT2:選擇線 SELECT2: Select line

T1:p通道驅動電晶體/驅動電晶體 T1: p-channel driver transistor/driver transistor

T2:開關電晶體 T2: Switching transistor

T3:直排選擇電晶體/掃描電晶體 T3: In-line selection transistor/scanning transistor

VCATHODE:陰極電壓 V CATHODE : cathode voltage

VDD:外部電源/電壓源/恆定供應電壓 V DD : External power supply/voltage source/constant supply voltage

Claims (19)

一種包括位於一矽基背板之頂部上之一發光OLED堆疊之微顯示器,該矽基背板具有可個別定址像素及控制電路系統(circuitry),其中:該發光OLED堆疊具有位於一頂部電極與一底部電極之間的三個或更多個OLED單元;且該矽基背板之該控制電路系統包括用於每一可個別定址像素之至少兩個電晶體,該至少兩個電晶體之通道串聯連接於一外部電源(VDD)與該發光OLED堆疊之該底部電極之間,其中具有其等通道串聯連接之該至少兩個電晶體皆額定為5V或低於5V。 A microdisplay includes a light-emitting OLED stack located on top of a silicon-based backplane, the silicon-based backplane having individually addressable pixels and control circuitry, wherein: the light-emitting OLED stack has three or more OLED units located between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane includes at least two transistors for each individually addressable pixel, the channels of the at least two transistors are connected in series between an external power supply ( VDD ) and the bottom electrode of the light-emitting OLED stack, wherein the at least two transistors with their equal channel series connection are rated at 5V or less. 如請求項1之微顯示器,其中該發光OLED堆疊之一臨限值電壓(Vth)係至少7.5V或大於7.5V。 A microdisplay as in claim 1, wherein a threshold voltage (V th ) of the light-emitting OLED stack is at least 7.5V or greater than 7.5V. 如請求項1之微顯示器,其中該發光OLED堆疊之一臨限值電壓(Vth)係至少10V或大於10V。 A microdisplay as in claim 1, wherein a threshold voltage (V th ) of the light-emitting OLED stack is at least 10V or greater than 10V. 如請求項1至3中任一項之微顯示器,其中該發光OLED堆疊包括四個或更多個OLED單元。 A microdisplay as claimed in any one of claims 1 to 3, wherein the light-emitting OLED stack comprises four or more OLED units. 如請求項1至3中任一項之微顯示器,其中該等OLED單元各自被一電荷產生層(CGL)彼此分隔開。 A microdisplay as claimed in any one of claims 1 to 3, wherein the OLED units are each separated from each other by a charge generation layer (CGL). 如請求項5之微顯示器,其中該底部電極係分段式的,且每一區段與該矽基背板中之該控制電路系統電接觸。 A microdisplay as claimed in claim 5, wherein the bottom electrode is segmented and each segment is electrically connected to the control circuit system in the silicon-based backplane. 如請求項6之微顯示器,其中該發光OLED堆疊係頂部發射式的(top-emitting)。 A microdisplay as claimed in claim 6, wherein the light-emitting OLED stack is top-emitting. 如請求項7之微顯示器,其中該發光OLED堆疊形成一微腔(microcavity),在該微腔中該分段式底部電極與該頂部電極之間的實體距離跨越所有像素恆定。 A microdisplay as claimed in claim 7, wherein the light-emitting OLED stack forms a microcavity in which the physical distance between the segmented bottom electrode and the top electrode is constant across all pixels. 如請求項1至3中任一項之微顯示器,其中最靠近該外部電源之該至少兩個電晶體中之一者係一驅動電晶體且額定為5V或低於5V,並且最靠近該發光OLED堆疊之該底部電極之該至少兩個電晶體中之另一者係一開關電晶體(switch transistor)且額定為大於5V。 A microdisplay as claimed in any one of claims 1 to 3, wherein one of the at least two transistors closest to the external power source is a drive transistor and is rated at 5V or less, and another of the at least two transistors closest to the bottom electrode of the light-emitting OLED stack is a switch transistor and is rated at greater than 5V. 如請求項1至3中任一項之微顯示器,其中具有其等通道串聯連接之該至少兩個電晶體兩者皆係p通道電晶體。 A microdisplay as claimed in any one of claims 1 to 3, wherein the at least two transistors having their equal-channel series connection are both p-channel transistors. 如請求項10之微顯示器,其中具有其等通道串聯連接之該至少兩個電晶體各自位於單獨井中。 A microdisplay as claimed in claim 10, wherein the at least two transistors having their equal-channel series connections are each located in a separate well. 如請求項1至3中任一項之微顯示器,其中該控制電路系統另外包括 一保護電路,該保護電路包括一p通道電晶體。 A microdisplay as claimed in any one of claims 1 to 3, wherein the control circuit system further comprises a protection circuit comprising a p-channel transistor. 如請求項1至3中任一項之微顯示器,其中該控制電路系統另外包括一保護電路,該保護電路包括一p-n二極體。 A microdisplay as claimed in any one of claims 1 to 3, wherein the control circuit system further comprises a protection circuit, the protection circuit comprising a p-n diode. 如請求項13之微顯示器,其中該p-n二極體之陰極連接至該發光OLED堆疊之該底部電極之節點,且陽極連接至一電壓參考(VREF)或一電流參考。 A microdisplay as in claim 13, wherein the cathode of the pn diode is connected to the node of the bottom electrode of the light emitting OLED stack, and the anode is connected to a voltage reference (V REF ) or a current reference. 如請求項1至3中任一項之微顯示器,其中該控制電路系統另外包括一保護電路,該保護電路包括一雙極接面電晶體。 A microdisplay as claimed in any one of claims 1 to 3, wherein the control circuit system further comprises a protection circuit, the protection circuit comprising a bipolar junction transistor. 如請求項15之微顯示器,其中該雙極接面電晶體係一NPN電晶體,在該NPN電晶體中基極連接至一電壓源(VPROTECT)或一電流源,射極連接至與該發光OLED堆疊之該底部電極連接之一節點且集電極連接至該外部電源(VDD)。 A microdisplay as in claim 15, wherein the bipolar junction transistor is an NPN transistor, in which the base is connected to a voltage source (V PROTECT ) or a current source, the emitter is connected to a node connected to the bottom electrode of the light-emitting OLED stack, and the collector is connected to the external power supply (V DD ). 如請求項15之微顯示器,其中該雙極接面電晶體之基極係與外部之電源隔離,射極連接至與該發光OLED堆疊之該底部電極連接之一節點且集電極連接至該外部電源(VDD)。 A microdisplay as in claim 15, wherein the base of the bipolar junction transistor is isolated from an external power source, the emitter is connected to a node connected to the bottom electrode of the light-emitting OLED stack and the collector is connected to the external power source (V DD ). 如請求項15之微顯示器,其中該雙極接面電晶體位於與具有其等通道串聯連接之該至少兩個電晶體分離之一井中。 A microdisplay as claimed in claim 15, wherein the bipolar junction transistor is located in a well separated from the at least two transistors having equal channel series connection therewith. 如請求項18之微顯示器,其中具有其等通道串聯連接之該至少兩個電晶體兩者皆係p通道電晶體且各自位於單獨n井中,並且該雙極接面電晶體係位於一單獨p井中之一NPN電晶體。 A microdisplay as claimed in claim 18, wherein the at least two transistors having their equal-channel series connection are both p-channel transistors and are each located in a separate n-well, and the bipolar junction transistor is an NPN transistor located in a separate p-well.
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* Cited by examiner, † Cited by third party
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Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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