TWI852520B - Chip package and manufacturing method thereof - Google Patents

Abstract

A chip package includes a chip, a support element, a first light transmissive sheet, a second light transmissive sheet, a first redistribution layer, and a second redistribution layer. A top surface of the chip has a conductive pad and a sensing area. The support element is located on the top surface of the chip and surrounds the sensing area. The first light transmissive sheet is located on the support element and covers the sensing area. The second light transmissive sheet is located on a bottom surface of the chip, and the first and second light transmissive sheets have the same material. The first redistribution layer is electrically connected to the conductive pad and extends to the bottom surface of the chip. The second redistribution layer is electrically connected to the first redistribution layer that is on the bottom surface of the chip, and extends to a bottom surface of the second light transmissive sheet.

Description

Chip package and manufacturing method thereof

The present disclosure relates to a chip package and a method for manufacturing the chip package.

Generally speaking, a chip package for image sensing may include a chip and a light-transmitting sheet on the chip. The light-transmitting sheet may cover the image sensing area of the chip to protect the image sensing area from contamination or external damage. Since the thickness of the chip affects the strength of the chip package, when the chip is thin, the support provided by the light-transmitting sheet above the chip may be insufficient. In addition, when the chip is thicker, although the strength of the chip itself is sufficient, the thicker chip will be unfavorable for the formation of through silicon vias (TSV).

One technical aspect of the present disclosure is a chip package.

According to some embodiments of the present disclosure, a chip package includes a chip, a support, a first light-transmitting sheet, a second light-transmitting sheet, a first redistribution layer, and a second redistribution layer. The top surface of the chip has a conductive pad and a sensing area. The support is located on the top surface of the chip and surrounds the sensing area. The first light-transmitting sheet is located on the support and covers the sensing area. The second light-transmitting sheet is located on the bottom surface of the chip, and the second light-transmitting sheet and the first light-transmitting sheet have the same material. The first redistribution layer is electrically connected to the conductive pad and extends to the bottom surface of the chip. The second redistribution layer is electrically connected to the first redistribution layer on the bottom surface of the chip, and the second redistribution layer extends to the bottom surface of the second light-transmitting sheet.

In some embodiments, the chip package further includes a bonding layer located between the chip and the second light-transmitting sheet.

In some embodiments, a portion of the bonding layer is located in the chip.

In some embodiments, the chip package further includes an insulating layer located between the bonding layer and the chip, and between the chip and the first redistribution layer.

In some implementations, the chip package further includes a buffer layer located between the insulating layer and the bonding layer.

In some implementations, the second redistribution layer passes through the first redistribution layer on the bottom surface of the chip.

In some implementations, the chip package further includes a barrier layer that covers the bottom surface of the second light-transmitting sheet and the second redistribution layer.

In some implementations, a portion of the barrier layer is located in the second light-transmitting sheet.

In some embodiments, the chip package further includes a conductive structure which is electrically connected to the second redistribution layer on the bottom surface of the second light-transmitting sheet and protrudes from the barrier layer.

One technical aspect of the present disclosure is a chip package.

According to some embodiments of the present disclosure, a chip package includes a chip, a support, a first light-transmitting sheet, a second light-transmitting sheet, and a redistribution layer. The top surface of the chip has a conductive pad and a sensing area, wherein the conductive pad protrudes from the side wall of the chip. The support is located on the top surface of the chip and surrounds the sensing area. The first light-transmitting sheet is located on the support and covers the sensing area. The second light-transmitting sheet is located on the bottom surface of the chip, and the second light-transmitting sheet and the first light-transmitting sheet have the same material. The redistribution layer extends from the bottom surface of the support to the bottom surface of the second light-transmitting sheet, and is electrically connected to the conductive pad protruding from the side wall of the chip.

In some implementations, the sidewall of the chip and the bottom surface of the chip are blunt.

In some embodiments, the chip package further includes a bonding layer, which covers the bottom surface and side walls of the chip and extends to the bottom surface of the conductive pad, wherein the side surface of the bonding layer contacts the redistribution layer.

In some implementations, the second light-transmitting sheet has a side wall, the side wall of the second light-transmitting sheet and the bottom surface form a blunt angle, and the side wall of the second light-transmitting sheet contacts the redistribution wiring layer.

In some implementations, the top of the redistribution layer is higher than the top surface of the chip.

In some embodiments, the chip package further includes a first barrier layer, a second barrier layer and a conductive structure. The first barrier layer is located on the bottom surface of the second light-transmitting sheet, wherein a portion of the redistribution wiring layer covers the first barrier layer. The second barrier layer covers the bottom surface of the second light-transmitting sheet and the redistribution wiring layer. The conductive structure is electrically connected to the redistribution wiring layer and protrudes from the second barrier layer.

A technical aspect of the present disclosure is a method for manufacturing a chip package.

According to some embodiments of the present disclosure, a method for manufacturing a chip package includes bonding a first light-transmitting sheet to the top surface of a wafer so that a support is located between the first light-transmitting sheet and the wafer, wherein the top surface of the wafer has a conductive pad and a sensing area, and the first light-transmitting sheet covers the sensing area; etching the bottom surface of the wafer to form a through hole exposing the conductive pad; forming a first redistribution layer electrically connected to the exposed conductive pad and extending to the bottom surface of the wafer; bonding a second light-transmitting sheet to the bottom surface of the wafer, wherein the second light-transmitting sheet and the first light-transmitting sheet have the same material; forming an opening in the second light-transmitting sheet to expose the first redistribution layer; and forming a second redistribution layer electrically connected to the first redistribution layer exposed from the opening, wherein the second redistribution layer extends to the bottom surface of the second light-transmitting sheet.

In some implementations, the manufacturing method of the chip package further includes forming an insulating layer on the bottom surface of the wafer and the wall surface of the through hole.

In some embodiments, the manufacturing method of the chip package further includes forming a buffer layer on the insulating layer on the bottom surface of the wafer.

In some embodiments, the opening formed in the second light-transmitting sheet to expose the first redistribution layer passes through the first redistribution layer on the bottom surface of the chip and extends into the buffer layer.

In some embodiments, the manufacturing method of the chip package further includes forming a bonding layer to cover the bottom surface of the wafer and fill the through hole.

In the above-mentioned embodiment of the present disclosure, since the chip package has the first light-transmitting sheet and the second light-transmitting sheet respectively on the top and bottom surfaces of the chip, the chip package can be strengthened and the strength can be improved. When the thickness of the chip is customized or thin, a second light-transmitting sheet of appropriate thickness can be selected or ground to provide chip support. In this way, the thickness selection of the chip will be flexible, and a thinner chip can be used to make the chip package, which makes it easier to form silicon through-holes. In addition, the first light-transmitting sheet, the chip and the second light-transmitting sheet are a sandwich structure, and the first light-transmitting sheet and the second light-transmitting sheet have the same material, which can balance the stress caused by the difference in the coefficient of thermal expansion (CTE).

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a chip package 100 according to an embodiment of the present disclosure. As shown in the figure, the chip package 100 includes a chip 110, a support 120, a first light-transmitting sheet 130, a second light-transmitting sheet 140, a first redistribution layer 150a, and a second redistribution layer 150b. The top surface 111 of the chip 110 has a conductive pad 112 and a sensing area 114. The support 120 is located on the top surface 111 of the chip 110 and surrounds the sensing area 114. The first light-transmitting sheet 130 is located on the support 120 and covers the sensing area 114. The second light-transmitting sheet 140 is located on the bottom surface 113 of the chip 110, and the second light-transmitting sheet 140 and the first light-transmitting sheet 130 have the same material. The first redistribution wiring layer 150a is electrically connected to the conductive pad 112 and extends to the bottom surface 113 of the chip 110. The second redistribution wiring layer 150b is electrically connected to the first redistribution wiring layer 150a on the bottom surface 113 of the chip 110, and the second redistribution wiring layer 150b extends to the bottom surface 141 of the second transparent sheet 140.

In the present embodiment, the chip 110 may be an image sensing chip, and its material includes silicon. The sensing area 114 is used to sense images, but this is not intended to limit the present disclosure. The material of the support member 120 may be epoxy, but is not limited thereto. In addition, the materials of the first light-transmitting sheet 130 and the second light-transmitting sheet 140 may be glass. The first light-transmitting sheet 130 allows light to pass through so that the sensing area 114 receives the image. The second light-transmitting sheet 140 allows light to pass through for alignment, so as to form an opening 143 corresponding to the position of the first redistribution layer 150a, and then in the subsequent process, a second redistribution layer 150b electrically connected to the first redistribution layer 150a can be formed.

Specifically, since the chip package 100 has the first light-transmitting sheet 130 and the second light-transmitting sheet 140 on the top surface 111 and the bottom surface 113 of the chip 110, respectively, the chip package 100 can be strengthened and the strength can be improved. When the thickness of the chip 110 is customized or thin, the second light-transmitting sheet 140 of appropriate thickness can be selected or ground to provide support for the chip 110. In this way, the thickness of the chip 110 will be flexible, and a thinner chip 110 can be used to make the chip package 100, which makes it easier to form a through-silicon via (such as the through hole 115). In addition, the first light-transmitting sheet 130, the chip 110 and the second light-transmitting sheet 140 are a sandwich structure, and the first light-transmitting sheet 130 and the second light-transmitting sheet 140 have the same material, which can balance the stress generated by the difference in the coefficient of thermal expansion (CTE).

In the present embodiment, the chip package 100 further includes a bonding layer 160. The bonding layer 160 is located between the chip 110 and the second light-transmitting sheet 140. A portion of the bonding layer 160 is located in the chip 110. As shown in FIG. 1 , the bonding layer 160 fills the through-hole 115 of the chip 110. The chip package 100 may also include an insulating layer 170. The insulating layer 170 is located on the bottom surface 113 of the chip 110 and the wall surface of the through-hole 115, that is, the insulating layer 170 is located between the bonding layer 160 and the chip 110, and between the chip 110 and the first redistribution layer 150a.

In addition, the chip package 100 may further include a barrier layer 180 and a conductive structure 190. The barrier layer 180 covers the bottom surface 141 of the second light-transmitting sheet 140 and the second redistribution layer 150b. The conductive structure 190 is electrically connected to the second redistribution layer 150b on the bottom surface 141 of the second light-transmitting sheet 140 and protrudes from the barrier layer 180. The conductive structure 190 can be electrically connected to an external device (e.g., a circuit board) and transmit electrical signals through the conductive pad 112, the first redistribution layer 150a, and the second redistribution layer 150b.

It should be understood that the connection relationship, materials and functions of the components that have been described will not be repeated, and it is better to explain them first. In the following description, the manufacturing method of the chip package will be explained. The manufacturing method of the chip package adopts wafer level packaging, which can improve the yield and production efficiency.

Figures 2 to 6 show cross-sectional views of the manufacturing method of the chip package 100 of Figure 1 at different stages. Referring to Figure 2, the first light-transmitting sheet 130 is bonded to the top surface 111 of the wafer 110a, so that the support member 120 is located between the first light-transmitting sheet 130 and the wafer 110a. The wafer 110a is a semiconductor structure that has not yet been cut into the chip 110 of Figure 1. The support member 120 covers the conductive pad 112. Before this step, the support member 120 can be formed on the bottom surface of the first light-transmitting sheet 130 or the top surface 111 of the wafer 110a, and is not intended to limit the present disclosure. In some embodiments, the bottom surface 113 of the wafer 110a can be ground to reduce the thickness of the wafer 110a.

3 , the bottom surface 113 of the wafer 110a may then be etched to form a through hole 115 exposing the conductive pad 112. After the through hole 115 is formed, an insulating layer 170 may be formed on the bottom surface 113 of the wafer 110a and the wall surface of the through hole 115.

Referring to FIG. 4 , after the insulating layer 170 is formed, the first redistribution layer 150a can be formed to electrically connect the exposed conductive pads 112 and extend to the bottom surface 113 of the wafer 110a. The insulating layer 170 is located between the first redistribution layer 150a and the wafer 110a. Then, the second light-transmitting sheet 140 can be bonded to the bottom surface 113 of the wafer 110a via the bonding layer 160, wherein the second light-transmitting sheet 140 and the first light-transmitting sheet 130 have the same material (e.g., glass). Before bonding the second light-transmitting sheet 140, the bonding layer 160 can be formed to cover the bottom surface 113 of the wafer 110a and fill the through-hole 115.

Referring to FIG. 5 , after bonding the second light-transmitting sheet 140 to the bottom surface 113 of the wafer 110a, an opening 143 exposing the first redistribution layer 150a may be formed in the second light-transmitting sheet 140. The opening 143 may be formed by laser drilling, and the opening 143 passes through the second light-transmitting sheet 140 and extends into the bonding layer 160. Then, a second redistribution layer 150b may be formed to electrically connect the first redistribution layer 150a exposed from the opening 143, and the second redistribution layer 150b extends to the bottom surface 141 of the second light-transmitting sheet 140.

Referring to FIG. 6 and FIG. 1 simultaneously, after the second redistribution wiring layer 150b is formed, a barrier layer 180 may be formed to cover the bottom surface 141 of the second light-transmitting sheet 140 and the second redistribution wiring layer 150b, and the barrier layer 180 may be patterned to form an opening 181. Then, a conductive structure 190 may be formed in the opening 181 of the barrier layer 180, so that the conductive structure 190 is electrically connected to the second redistribution wiring layer 150b on the bottom surface 141 of the second light-transmitting sheet 140, and the conductive structure 190 protrudes from the barrier layer 180. In a subsequent process, the top surface 131 of the first light-transmitting sheet 130 may be ground to reduce the thickness of the first light-transmitting sheet 130. Then, a dicing process may be performed to obtain the chip package 100 shown in FIG. 1 .

FIG. 7 shows a cross-sectional view of a chip package 100a according to another embodiment of the present disclosure. The chip package 100a includes a chip 110, a support member 120, a first light-transmitting sheet 130, a second light-transmitting sheet 140, a first redistribution layer 150c, and a second redistribution layer 150d. This embodiment differs from the embodiment of FIG. 1 in that the chip package 100a further includes a buffer layer 210 located below the chip 110. In addition, the buffer layer 210 is located between the insulating layer 170 and the bonding layer 160. In this embodiment, the second redistribution layer 150d passes through the first redistribution layer 150c on the bottom surface 113 of the chip 110. A portion of the barrier layer 180 of the chip package 100a is located in the second light-transmitting sheet 140 and the bonding layer 160, and extends into the first redistribution layer 150c and the buffer layer 210.

Figures 8 to 12 show cross-sectional views of the manufacturing method of the chip package 100a of Figure 7 at different stages. Referring to Figures 8 and 9 at the same time, the first light-transmitting sheet 130 is bonded to the top surface 111 of the wafer 110a so that the support member 120 is located between the first light-transmitting sheet 130 and the wafer 110a. In some embodiments, the bottom surface 113 of the wafer 110a can be ground to reduce the thickness of the wafer 110a. Then, the bottom surface 113 of the wafer 110a can be etched to form a through hole 115 that exposes the conductive pad 112. After the through hole 115 is formed, an insulating layer 170 can be formed on the bottom surface 113 of the wafer 110a and the wall surface of the through hole 115. Next, a buffer layer 210 may be formed on the insulating layer 170 on the bottom surface 113 of the wafer 110a.

Referring to FIG. 10 , after the buffer layer 210 is formed, a first redistribution layer 150c may be formed to electrically connect the exposed conductive pad 112 and extend to the bottom surface 113 of the wafer 110a. The buffer layer 210 is located between the first redistribution layer 150c and the wafer 110a. Next, the second light-transmitting sheet 140 may be bonded to the bottom surface 113 of the wafer 110a via a bonding layer 160, wherein the second light-transmitting sheet 140 and the first light-transmitting sheet 130 have the same material (e.g., glass). Before bonding the second light-transmitting sheet 140, a bonding layer 160 may be formed to cover the bottom surface 113 of the wafer 110a and fill the through hole 115.

Referring to FIG. 11 , after bonding the second light-transmitting sheet 140 to the bottom surface 113 of the wafer 110a, an opening 143a passing through the first redistribution wiring layer 150c may be formed in the second light-transmitting sheet 140, so that the inner wall of the first redistribution wiring layer 150c is exposed from the opening 143a. The opening 143a may be a notch formed by a tool, and the opening 143a extends into the buffer layer 210. Then, a second redistribution wiring layer 150d may be formed to electrically connect the first redistribution wiring layer 150c exposed from the opening 143a, and the second redistribution wiring layer 150d extends to the bottom surface 141 of the second light-transmitting sheet 140.

Referring to FIG. 11 and FIG. 7 at the same time, after the second redistribution wiring layer 150d is formed, a barrier layer 180 may be formed to cover the bottom surface 141 of the second light-transmitting sheet 140 and the second redistribution wiring layer 150d, and the barrier layer 180 may be patterned to form an opening 181. Then, a conductive structure 190 may be formed in the opening 181 of the barrier layer 180, so that the conductive structure 190 is electrically connected to the second redistribution wiring layer 150d on the bottom surface 141 of the second light-transmitting sheet 140, and the conductive structure 190 protrudes from the barrier layer 180. In a subsequent process, the top surface 131 of the first light-transmitting sheet 130 may be polished to reduce the thickness of the first light-transmitting sheet 130. Then, a dicing process may be performed to obtain the chip package 100a shown in FIG. 7 .

FIG. 13 shows a cross-sectional view of a chip package 100b according to another embodiment of the present disclosure. As shown in the figure, the chip package 100b includes a chip 110, a support member 120, a first light-transmitting sheet 130, a second light-transmitting sheet 140, and a redistribution layer 150e. The top surface 111 of the chip 110 has a conductive pad 112 and a sensing area 114, wherein the conductive pad 112 protrudes from the side wall 117 of the chip 110. The support member 120 is located on the top surface 111 of the chip 110 and surrounds the sensing area 114. The first light-transmitting sheet 130 is located on the support member 120 and covers the sensing area 114. The second transparent sheet 140 is located on the bottom surface 113 of the chip 110 and is made of the same material as the first transparent sheet 130, such as glass. The redistribution layer 150e extends from the bottom surface of the support 120 to the bottom surface 141 of the second transparent sheet 140 and is electrically connected to the conductive pad 112 protruding from the side wall 117 of the chip 110.

In the present embodiment, the side wall 117 of the chip 110 and the bottom surface 113 of the chip 110 form a blunt angle θ1. The chip package 100b further includes a bonding layer 160. The bonding layer 160 covers the bottom surface 113 and the side wall 117 of the chip 110, and extends to the bottom surface of the conductive pad 112. The bonding layer 160 is located between the bottom surface 113 of the chip 110 and the second light-transmitting sheet 140, and between the side wall 117 of the chip 110 and the redistribution layer 150e. The side surface of the bonding layer 160 contacts the redistribution layer 150e. In addition, the side wall 142 of the second light-transmitting sheet 140 and the bottom surface 141 form a blunt angle θ2, and the side wall 142 of the second light-transmitting sheet 140 contacts the redistribution wiring layer 150 e. The top of the redistribution wiring layer 150 e is higher than the top surface 111 of the chip 110.

The chip package 100b further includes a first barrier layer 180a, a second barrier layer 180b and a conductive structure 190. The first barrier layer 180a is located on the bottom surface 141 of the second light-transmitting sheet 140, wherein a portion of the redistribution wiring layer 150e covers the first barrier layer 180a. In other words, the first barrier layer 180a is located between the bottom surface 141 of the second light-transmitting sheet 140 and the redistribution wiring layer 150e. The second barrier layer 180b covers the bottom surface 141 of the second light-transmitting sheet 140 and the redistribution wiring layer 150e. The conductive structure 190 is electrically connected to the redistribution wiring layer 150e and protrudes from the second barrier layer 180b. The second barrier layer 180b can prevent the second light-transmitting sheet 140 from being broken due to thermal stress during the manufacturing process, such as when forming the redistribution wiring layer 150e and the conductive structure 190.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100,100a,100b: chip package 110a: wafer 110: chip 111: top surface 112: conductive pad 113: bottom surface 114: sensing area 115: through hole 117: side wall 120: support member 130: first light-transmitting sheet 131: top surface 140: second light-transmitting sheet 141: bottom surface 142: side wall 143,143a: opening 150a,150c: first redistribution layer 150b,150d: second redistribution layer 150e: redistribution layer 160: bonding layer 170: insulation layer 180: barrier layer 180a: first barrier layer 180b: second barrier layer 181: opening 190: conductive structure 210: buffer layer θ1, θ2: blunt angle

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a chip package according to an embodiment of the disclosure. FIGS. 2 to 6 illustrate cross-sectional views of a method for manufacturing the chip package of FIG. 1 at different stages. FIG. 7 illustrates a cross-sectional view of a chip package according to another embodiment of the disclosure. FIGS. 8 to 12 illustrate cross-sectional views of a method for manufacturing the chip package of FIG. 7 at different stages. FIG. 13 illustrates a cross-sectional view of a chip package according to yet another embodiment of the disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Chip package

110: Chip

111: Top

112: Conductive pad

113: Bottom

114: Sensing area

115:Piercing

120: Support parts

130: First light-transmitting sheet

131: Top

140: Second light-transmitting sheet

141: Bottom

143: Open mouth

150a: First redistribution layer

150b: Second redistribution layer

160:Joint layer

170: Insulation layer

180: Barrier layer

190: Conductive structure

Claims (20)

A chip package includes: a chip having a conductive pad and a sensing area on a top surface; a support member located on the top surface of the chip and surrounding the sensing area; a first light-transmitting sheet located on the support member and covering the sensing area; a second light-transmitting sheet located on a bottom surface of the chip, and the second light-transmitting sheet and the first light-transmitting sheet have the same material; a first redistribution wiring layer electrically connected to the conductive pad and extending to the bottom surface of the chip; and a second redistribution wiring layer electrically connected to the first redistribution wiring layer on the bottom surface of the chip and extending to a bottom surface of the second light-transmitting sheet, wherein a lower horizontal portion of the redistribution wiring layer directly contacts the second light-transmitting sheet, and the entire bottom surface of the second light-transmitting sheet is higher than the lower horizontal portion of the redistribution wiring layer. The chip package as described in claim 1 further includes: a bonding layer located between the chip and the second light-transmitting sheet. A chip package as described in claim 2, wherein a portion of the bonding layer is located in the chip. The chip package as described in claim 2 further includes: an insulating layer located between the bonding layer and the chip, and between the chip and the first redistribution layer. The chip package as described in claim 4 further includes: a buffer layer located between the insulating layer and the bonding layer. A chip package as described in claim 1, wherein the second redistribution layer passes through the first redistribution layer on the bottom surface of the chip. The chip package as described in claim 1 further includes: a barrier layer covering the bottom surface of the second light-transmitting sheet and the second redistribution layer. A chip package as described in claim 7, wherein a portion of the barrier layer is located in the second light-transmitting sheet. The chip package as described in claim 7 further includes: a conductive structure electrically connected to the second redistribution layer on the bottom surface of the second light-transmitting sheet and protruding from the barrier layer. A chip package comprises: a chip having a conductive pad and a sensing area on a top surface thereof, wherein the conductive pad protrudes from a side wall of the chip; a support member located on the top surface of the chip and surrounding the sensing area; a first light-transmitting sheet located on the support member and covering the sensing area; a second light-transmitting sheet located on a bottom surface of the chip, and the second light-transmitting sheet and the first light-transmitting sheet have the same material; and a redistribution layer extending from the bottom surface of the support member to a bottom surface of the second light-transmitting sheet and electrically connected to the conductive pad protruding from the side wall of the chip, wherein a lower horizontal portion of the redistribution layer directly contacts the second light-transmitting sheet, and the entire bottom surface of the second light-transmitting sheet is higher than the lower horizontal portion of the redistribution layer. A chip package as described in claim 10, wherein the side wall of the chip and the bottom surface of the chip are blunt. The chip package as described in claim 10 further includes: a bonding layer covering the bottom surface and the side wall of the chip and extending to the bottom surface of the conductive pad, wherein the side surface of the bonding layer contacts the redistribution layer. The chip package as described in claim 10, wherein the second light-transmitting sheet has a side wall, the side wall of the second light-transmitting sheet is blunt with the bottom surface, and the side wall of the second light-transmitting sheet is in contact with the redistribution layer. A chip package as described in claim 10, wherein the top of the redistribution layer is higher than the top surface of the chip. The chip package as described in claim 10 further comprises: a first barrier layer located on the bottom surface of the second light-transmitting sheet, wherein a portion of the redistribution wiring layer covers the first barrier layer; a second barrier layer covering the bottom surface of the second light-transmitting sheet and the redistribution wiring layer; and a conductive structure electrically connected to the redistribution wiring layer and protruding from the second barrier layer. A method for manufacturing a chip package includes: bonding a first light-transmitting sheet to a top surface of a wafer, so that a support is located between the first light-transmitting sheet and the wafer, wherein the top surface of the wafer has a conductive pad and a sensing area, and the first light-transmitting sheet covers the sensing area; etching a bottom surface of the wafer to form a through hole exposing the conductive pad; forming a first redistribution layer electrically connected to the exposed conductive pad and extending to the bottom surface of the wafer; bonding a second light-transmitting sheet to the wafer A bottom surface of the second light-transmitting sheet is formed, wherein the second light-transmitting sheet and the first light-transmitting sheet are made of the same material; an opening is formed in the second light-transmitting sheet to expose the first redistribution wiring layer; and a second redistribution wiring layer is formed to be electrically connected to the first redistribution wiring layer exposed from the opening, wherein the second redistribution wiring layer extends to a bottom surface of the second light-transmitting sheet, wherein a lower horizontal portion of the redistribution wiring layer directly contacts the second light-transmitting sheet, and the entire bottom surface of the second light-transmitting sheet is higher than the lower horizontal portion of the redistribution wiring layer. The manufacturing method of the chip package as described in claim 16 further includes: forming an insulating layer on the bottom surface of the wafer and the wall surface of the through hole. The manufacturing method of the chip package as described in claim 17 further includes: forming a buffer layer on the insulating layer on the bottom surface of the wafer. A method for manufacturing a chip package as described in claim 18, wherein the opening exposing the first redistribution layer is formed in the second light-transmitting sheet so that the opening passes through the first redistribution layer on the bottom surface of the wafer and extends into the buffer layer. The manufacturing method of the chip package as described in claim 16 further includes: forming a bonding layer to cover the bottom surface of the wafer and fill the through hole.

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