TWI735034B - Interconnect substrate with stiffener and warp balancer and semiconductor assembly using the same - Google Patents

Abstract

The interconnect substrate mainly includes a stiffener, a core layer, a warp balancer and a routing circuitry. The stiffener has an elastic modulus higher than 100 GPa and is laterally surrounded by the core layer. The warp balancer is disposed over the top surface of the core layer and laterally surrounds a cavity aligned with the stiffener. The routing circuitry is disposed under the bottom surfaces of the stiffener and the core layer and electrically connected to the stiffener. By the high modulus of the stiffener, local thermo-mechanical stress induced by un-even thickness can be counterbalanced. Furthermore, adjusting the ratio of the stiffener thickness to the cavity dimension can maintain the cavity area stiffness and modulate the global flatness.

Description

Interconnect substrate with reinforcing layer and warp balancer and its semiconductor assembly

The present invention relates to an interconnection substrate, in particular to an interconnection substrate and its semiconductor assembly in which a reinforcing layer and a warp balancer are incorporated.

The market trend of electronic devices (such as multimedia devices) is toward faster and thinner design requirements. One of the methods is to stack semiconductor chips on top of each other through the cavity substrate, so that the assembled device can be small and thin. U.S. Patent No. 8,446,736 to Kita et al. and U.S. Patent No. 8,400,776 to Sahara et al. disclose a circuit board in which the top of the board is removed to form a cavity in the board. Using this platform, one semiconductor wafer can be placed in the cavity, and another semiconductor wafer can be placed on it to form a stacked structure. This vertical stacking structure can save space and minimize the size, thereby achieving the purpose of thinning and miniaturization of the mobile device.

However, conventional resin-based cavity substrates (as shown in FIGS. 1A and 1B, usually composed of multiple resin layers 11 and multiple circuit layers 13) tend to warp during repeated heating and cooling during the manufacturing process. This is mainly due to the uneven thickness of the cavity substrate, and the thermal expansion of the lower part does not match the thermal expansion of the top. For example, at a high temperature such as 260°C, the lower resin material tends to expand to a degree Larger, thus causing the plate to bend upwards, as shown in Figure 1A. When it is lowered to room temperature, the resin material in the lower part tends to shrink more than the top part, thus bending the board downward, as shown in Figure 1B. In addition, the size of the cavity can also affect the degree of bending. For example, the general rule is that the wider the cavity, the greater the mismatch, and the worse the warping. Although the conventional method of adding a reinforcing layer around the peripheral edge of the substrate can partially improve the overall rigidity problem, it still fails to fundamentally solve the local bending problem (especially in the component connection area).

In view of the various development stages and limitations of substrates, there is an urgent need to develop a new substrate to achieve high packaging density and thinness requirements, while ensuring that it is not prone to warping during assembly and operation.

An object of the present invention is to provide an interconnection substrate with a high modulus reinforcement layer below the cavity area where the component is connected, so that the local thermo-mechanical stress caused by the uneven thickness can be offset. In addition, by adjusting the ratio of the thickness of the reinforcing layer to the specific size of the upper cavity, the rigidity of the central area can be maintained and the overall flatness can be adjusted.

According to the above and other objectives, the present invention provides an interconnection substrate comprising: a reinforcement layer having top contact pads on its top surface and bottom contact pads on its bottom surface, the top contact pads are electrically connected to the bottom surfaces Contact pad; a core layer, which laterally surrounds the peripheral side wall of the reinforcement layer; a routing circuit, which is arranged under the bottom surface of the reinforcement layer, and extends laterally to the bottom surface of the core layer, and is electrically coupled To the bottom contact pads of the reinforcing layer; and a warped balance piece, which is arranged above the top surface of the core layer and has an inner side wall laterally surrounding a cavity, and the top contact pads of the reinforcing layer are paired Quasi the cavity, and a part of the warping balance piece overlaps the top surface of the reinforcing layer, wherein the elastic modulus of the reinforcing layer is higher than the elastic modulus of the core layer and the routing circuit, and the reinforcing layer The ratio between the thickness and the size of the cavity in a millimeter unit thickness to the upper square millimeter unit size is 1×10 ^-5 or more.

In addition, the present invention also provides a semiconductor assembly, which includes a first semiconductor element disposed in the cavity of the above-mentioned interconnect substrate and electrically connected to the top contact pad of the reinforcing layer.

The above and other features and advantages of the present invention can be more clearly understood by the detailed description of the following preferred embodiments.

100, 110, 120, 130, 200, 210, 300, 310, 400, 410, 500, 510, 600, 610: interconnect substrate

20: Reinforcement layer

201: Top contact pad

203: bottom contact pad

205: Through hole

21: Support base

211: base plate

213: top wiring layer

215: bottom wiring layer

217: Metallized through hole

23: Top re-distribution circuit

231: Top insulating layer

233: Top routing layer

237, 257, 337, 77: metalized vias

25: Redistribute the circuit at the bottom

251: bottom insulating layer

253: bottom routing layer

31: Sacrifice Carrier Board

33: build-up circuit

331: Insulation layer

335: routing layer

338: Top terminal pad

35: Solder ball

38: primer

40: core layer

401: open

45: Patterned metal at the bottom

47: The first vertical connector

50: Modified bonding matrix

51: Resin adhesive

53: Adjusting parts

60: Bending balance piece

605: dent

61: Top conductive pad

67: second vertical connector

70: routing circuit

71: Dielectric layer

72: Metal pad

73: Wire layer

81: The first semiconductor component

83: The second semiconductor element

91: bump

92: The first bump

93: second bump

With reference to the accompanying drawings, the present invention can be more clearly understood by the detailed description of the following preferred embodiments, in which: Fig. 1A is a cross-sectional view of a conventional cavity substrate under high temperature treatment; Fig. 1B is a conventional cavity substrate heat treatment Figure 2 is a cross-sectional view of the reinforcing layer in the first embodiment of the present invention; Figure 3 is a cross-sectional view of the core layer provided in the structure of Figure 2 in the first embodiment of the present invention; Figure 4 is the first embodiment of the present invention 3 provides a cross-sectional view of the bending balancer and the routing circuit; FIG. 5 is a cross-sectional view of the first embodiment of the present invention, the cavity is formed in the structure of FIG. 4 to complete the interconnection substrate manufacturing; FIG. 6 is the first embodiment of the present invention In one embodiment, the first semiconductor element is electrically connected to a cross-sectional view of the semiconductor assembly of the interconnect substrate shown in FIG. 5; FIG. 7 is a cross-sectional view of another aspect of the interconnect substrate in the first embodiment of the present invention; 8 is a cross-sectional view of another aspect of the interconnect substrate in the first embodiment of the present invention; FIG. 9 is a cross-sectional view of another aspect of the interconnect substrate in the first embodiment of the present invention; FIG. 10 is a second embodiment of the present invention In the example, the cross-sectional view of the interconnect substrate; FIG. 11 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element is electrically connected to the interconnect substrate shown in FIG. 10 in the second embodiment of the present invention; FIG. 12 is the second embodiment of the present invention FIG. 13 is a cross-sectional view of the interconnect substrate in the third embodiment of the present invention; FIG. 14 is a cross-sectional view of the interconnect substrate in the third embodiment of the present invention, where the first semiconductor element is electrically connected to FIG. 13 Fig. 15 is a cross-sectional view of another aspect of the interconnect substrate in the third embodiment of the present invention; Fig. 16 is a cross-sectional view of the interconnect substrate in the fourth embodiment of the present invention; 17 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element is electrically connected to the interconnect substrate shown in FIG. 16 in the fourth embodiment of the present invention; FIG. 18 is another aspect of the interconnect substrate in the fourth embodiment of the present invention 19 is a cross-sectional view of the interconnect substrate in the fifth embodiment of the present invention; FIG. 20 is a cross-sectional view of the semiconductor assembly in the fifth embodiment of the present invention where the first semiconductor element is electrically connected to the interconnect substrate shown in FIG. 19 21 is a cross-sectional view of another aspect of the interconnect substrate in the fifth embodiment of the present invention; FIG. 22 is a cross-sectional view of the build-up circuit attached to the sacrificial carrier and soldered to the reinforcement layer in the sixth embodiment of the present invention Figure 23 is a cross-sectional view of the core layer provided in the structure of Figure 22 in the sixth embodiment of the present invention; 24 is a cross-sectional view of the structure of FIG. 23 in the sixth embodiment of the present invention, which provides a bending balancer and routing circuit; FIG. 25 is a sixth embodiment of the present invention, in which a cavity is formed in the structure of FIG. 24 to complete the interconnection substrate fabrication FIG. 26 is a cross-sectional view of the semiconductor assembly in the sixth embodiment of the present invention, the first semiconductor element is electrically connected to the interconnect substrate shown in FIG. 25; and FIG. 27 is another aspect of the sixth embodiment of the present invention Cross-sectional view of such interconnect substrate.

Hereinafter, an example will be provided to illustrate the implementation aspects of the present invention in detail. The advantages and effects of the present invention will be more obvious through the content disclosed by the present invention. The drawings attached to this description are simplified and used as examples. The number, shape, and size of the components shown in the drawings can be modified according to actual conditions, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

2-5 is a cross-sectional view of a manufacturing method of an interconnect substrate in the first embodiment of the present invention. The interconnect substrate includes a reinforcement layer, a core layer, a warp balancer, and a routing circuit.

2 is a cross-sectional view of the reinforcing layer 20 with a top contact pad 201 and a bottom contact pad 203 on the top surface and the bottom surface, respectively. In this embodiment, the reinforcement layer 20 includes a supporting base 21 and a bottom redistribution circuit 25 disposed under the bottom surface of the supporting base 21. Preferably, the reinforcing layer 20 has an elastic modulus higher than 100 GPa to maintain the flatness of the component connection area. To achieve the required rigidity, support The substrate 21 is generally made of a high modulus material. More specifically, the supporting substrate 21 may include a base board 211 made of a high-modulus inorganic material, a top wiring layer 213 on the top surface of the base board 211, and a bottom wiring layer on the bottom surface of the base board 211. 215, and metallized through vias 217 passing through the base plate 211. The top wiring layer 213 at the top surface of the supporting substrate 21 provides a top contact pad 201 for subsequent device connection, and is electrically connected to the bottom surface of the base board 21 through the metallized through holes 217 connecting the top wiring layer 213 and the bottom wiring layer 215 At the bottom wiring layer 215. In this embodiment, the bottom redistribution circuit 25 is shown as a multilayer build-up circuit, which includes a bottom insulating layer 251 and a bottom routing layer 253 alternately formed. The bottom insulating layer 251 contacts, covers, and extends laterally on the bottom surface of the support base 21 from below. The bottom routing layer 253 extends laterally on the bottom insulating layer 251 to provide a bottom contact pad 203 for the next level of electrical connection, and includes a metalized via 257 that directly contacts the bottom wiring layer 215 of the support substrate 21 ( metallized vias). Therefore, the top contact pad 201 and the bottom contact pad 203 of the reinforcement layer 20 are electrically connected to each other through the metalized via 257 and the metalized through hole 217.

FIG. 3 is a cross-sectional view of using a resin adhesive 51 to attach the reinforcing layer 20 to the opening 401 of the core layer 40. The reinforcing layer 20 is separated from the inner side wall of the opening 401 of the core layer 40, and the resin adhesive 51 in the gap between the outer side wall of the reinforcing layer 20 and the inner side wall of the opening 401 is used to make the reinforcing layer 20 adhere to the inside of the opening 401 of the core layer 40 Side wall. The material of the core layer 40 is not particularly limited, and it can be any organic or inorganic material.

4 is a cross-sectional view of a bending balance 60 and a routing circuit 70 provided on opposite sides of the reinforcement layer 20 and the core layer 40. The bending balance 60 is disposed on the top surface of the reinforcing layer 20 and the core layer 40 and above the resin adhesive 51, and the routing circuit 70 is disposed on the bottom surface of the reinforcing layer 20 and the core layer 40 and below the resin adhesive 51. The warping balance 60 (usually containing resin materials) is used to suppress Since the structure is bent or warped, the coefficient of thermal expansion (CTE) of the warping balancer 60 is preferably substantially equal to or close to the coefficient of thermal expansion of the routing circuit 70. More specifically, in order to effectively maintain the required flatness of the structure, the CTE difference between the warping balance 60 and the routing circuit 70 is preferably controlled to be less than 20 ppm/°C. In addition, in some examples, the thickness of the warp balancer 60 is also controlled to be substantially equal to or close to the thickness of the routing circuit 70 to meet strict flatness requirements. In this embodiment, the routing circuit 70 is shown as a multilayer build-up circuit, and includes a plurality of dielectric layers 71 and a plurality of wire layers 73 formed alternately. Each wire layer 73 extends laterally on its corresponding dielectric layer 71 and includes a metalized via 77 located in the dielectric layer 71. Therefore, the wire layers 73 can be electrically coupled to each other through the metalized via 77. Similarly, the innermost wire layer 73 can be electrically coupled to the bottom contact pad 203 of the reinforcement layer 20 through the metalized via 77.

FIG. 5 is a cross-sectional view of a part of the bending balance member 60 removed. The selected part of the bending balance member 60 is removed to form a cavity 605 overlapping the top surface of the reinforcing layer 20. Therefore, the top contact pad 201 of the reinforcing layer 20 is aligned with the cavity 605 and is exposed from the cavity 605 from above. Preferably, the ratio of the thickness (in millimeters) of the reinforcing layer 20 to the opening area (in square millimeters) of the upper cavity 605 is 1×10 ^-5 or more. By adjusting the ratio of the thickness of the reinforcing layer to the size of the upper cavity, the rigidity of the cavity area can be maintained to prevent bending or deformation of the cavity area. In this embodiment, the reinforcing layer 20 extends laterally beyond the periphery of the cavity 605, and the outer periphery of the reinforcing layer 20 is located under the bending balance piece 60 to provide support for the inner edge portion of the bending balance piece 60, thereby strengthening the entire The mechanical reliability of the structure.

Accordingly, the completed interconnect substrate 100 includes the reinforcement layer 20, the core layer 40, the resin adhesive 51, the warp balancer 60 and the routing circuit 70. The reinforcement layer 20 can offset the local thermal-mechanical stress caused by the uneven thickness, and provide a high modulus for the chip assembled in the cavity 605, reliable and reliable Flat interface. In this embodiment, the elastic modulus of the reinforcing layer 20 is greater than the elastic modulus of the core layer 40, the bending balance 60 and the routing circuit 70. In addition, in some heat dissipation gain type examples, the thermal conductivity of the reinforcing layer 20 is preferably higher than the thermal conductivity of the core layer 40, the warp balancer 60, and the routing circuit 70. Therefore, the reinforcing layer 20 can not only solve the warpage problem, but also serve as a heat sink to enhance heat dissipation. The core layer 40 is bonded to the periphery of the reinforcing layer 20 by the resin adhesive 51 and is located between the warping balance 60 and the routing circuit 70. The CTE of the warp balancer 60 is matched with the routing circuit 70 to prevent the interconnect substrate 100 from being bent or deformed due to CTE mismatch. The routing circuit 70 is electrically coupled to the reinforcement layer 20, and provides fan-out routing/interconnection with the next level of connection.

6 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element 81 is electrically connected to the interconnect substrate 100 shown in FIG. 5. The first semiconductor element 81 (shown as a wafer) is disposed in the cavity 605, and is mounted on the top contact pad 201 of the reinforcement layer 20 through bumps 91 face down. Since the cavity area is completely covered by the high modulus reinforcement layer 20 from the bottom of the cavity, and the ratio between the thickness of the reinforcement layer and the size of the cavity is well controlled, bending or deformation of the interconnect substrate 100 can be effectively suppressed to avoid An electrical disconnection occurs between the first semiconductor element 81 and the reinforcement layer 20.

FIG. 7 is a cross-sectional view of another interconnection substrate in the first embodiment of the present invention. The interconnection substrate 110 is similar to the structure shown in FIG. 5, except that the core layer 40 surrounds laterally, covers the same shape and directly contacts the peripheral sidewalls of the reinforcement layer 20, and there is no resin adhesive between the reinforcement layer 20 and the core layer 30 .

FIG. 8 is a cross-sectional view of another interconnection substrate in the first embodiment of the present invention. The interconnection substrate 120 is similar to the structure shown in FIG. 5, except that (i) a plurality of adjusting members 53 are distributed in the resin adhesive 51 so as to be between the peripheral sidewalls of the reinforcing layer 20 and the inner sidewalls of the opening 401 of the core layer 40 A modified bonding matrix 50 is formed in the gap, (ii) the core layer 40 has a first vertical connecting member 47, And (iii) the bending balance member 60 has a second vertical connecting member 67. The CTE of the adjusting member 53 is generally lower than the CTE of the resin adhesive 51 to effectively reduce the risk of resin cracking. In order to achieve a significant effect, the CTE of the adjusting member 53 is lower than the CTE of the resin adhesive 51 by at least 10 ppm/°C. In this embodiment, based on the total volume of the gap 316, the modified bonding substrate 50 contains at least 30% (volume percentage) of the adjusting member 53, and the thermal expansion coefficient of the modified bonding substrate 50 is preferably less than 50 ppm/°C. Therefore, during the thermal cycle, the internal expansion and contraction of the modified bonding matrix 50 can be slowed down to prevent cracking. In addition, in order to effectively release the thermal-mechanical stress, the modified bonding matrix 50 preferably has a sufficient width greater than 10 microns (more preferably 25 microns or more) in the gap to absorb the stress. The first vertical connector 47 provides an electrical connection channel between the top surface and the bottom surface of the core layer 40, and contacts the patterned metal 45 on the bottom of the core layer 40 through the additional metalized via 77 of the routing circuit 70 to be electrically coupled To routing circuit 70. The second vertical connection member 67 provides an electrical connection channel between the top surface and the bottom surface of the bending balance member 60 and is electrically connected to the first vertical connection member 47. Therefore, the top conductive pad 61 provided on the top surface of the bending balance member 60 can be electrically connected to the routing circuit 70 through the first vertical connection member 47 and the second vertical connection member 67.

FIG. 9 is a cross-sectional view of another interconnection substrate in the first embodiment of the present invention. The interconnect substrate 130 is similar to the structure shown in FIG. 8, except that the modified bonding matrix 50 extends beyond the gap and further covers the bottom surface of the reinforcing layer 20 and the bottom surface of the core layer 40, and the innermost wire layer of the routing circuit 70 73 extends laterally on the modified bonding substrate 50 and includes a metalized via 77 located in the modified bonding substrate 50 for electrically connecting with the reinforcing layer 20 and the core layer 40. In this aspect, based on the total volume of the modified bonding matrix 50, the modified bonding matrix 50 contains at least 30% (volume percentage) of the adjusting member 53.

[Example 2]

FIG. 10 is a cross-sectional view of the interconnect substrate according to the second embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated here, and the same description is not required to be repeated.

The structure of the interconnect substrate 200 is similar to that shown in FIG. In this embodiment, the top redistribution circuit 25 is shown as a multilayer build-up circuit, which includes a top insulating layer 231 and a top routing layer 233 formed alternately. The top insulating layer 231 contacts, covers, and extends laterally on the top surface of the support base 21 from above. The top routing layer 233 extends laterally on the top insulating layer 231 to provide a top contact pad 201 for subsequent device connection, and includes a metalized via 237 that directly contacts the top wiring layer 213 of the supporting substrate 21. Therefore, the top redistribution circuit 23 is exposed from the cavity 605 and is partially covered by the warp balancer 60, and is electrically connected to the routing circuit 70 through the support base 21 and the bottom redistribution circuit 25.

FIG. 11 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element 81 is electrically connected to the interconnect substrate 200 shown in FIG. 10. The first semiconductor element 81 is disposed in the cavity 605 and is mounted on the top contact pad 201 of the reinforcement layer 20 through the bump 91 face down. Therefore, the first semiconductor element 81 is electrically connected to the routing circuit 70 through the reinforcement layer 20, where the reinforcement layer 20 provides a high modulus and flat platform to ensure a reliable connection between the first semiconductor element 81 and the interconnect substrate 200.

12 is a cross-sectional view of another interconnection substrate in the second embodiment of the present invention. The interconnect substrate 210 is similar to the structure shown in FIG. 10, except that the resin adhesive 51 is further mixed with a low-CTE adjusting member 53, and the core layer 40 and the warping balance member 60 each have a first vertical connecting member 47 and the second vertical connecting member 67. The adjusting member 53 with low CTE is dispersed in the resin adhesive 51 to reduce the risk of resin cracking. The first vertical connector 47 provides the routing circuit 70 and the second vertical The electrical connection between the straight connectors 67. Therefore, the top conductive pad 61 provided on the top surface of the warp balancer 60 can be electrically connected to the routing circuit 70 through the first vertical connection member 47 and the second vertical connection member 67.

[Example 3]

Fig. 13 is a cross-sectional view of an interconnect substrate according to a third embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

The interconnect substrate 300 is similar to the structure shown in FIG. 10, except that the reinforcement layer 20 does not include a bottom redistribution circuit between the supporting base 21 and the routing circuit 70. In this embodiment, the supporting substrate 21 is electrically coupled to the routing circuit 70 through the metalized via 77 contacting the wiring layer 215 at the bottom of the supporting substrate 21. Therefore, the top contact pad 201 and the bottom contact pad 203 of the reinforcement layer 20 are electrically connected to each other through the metalized via 237 of the top redistribution circuit 23 and the metalized through hole 217 of the support substrate 21.

FIG. 14 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element 81 is electrically connected to the interconnect substrate 300 shown in FIG. 13. The first semiconductor element 81 is disposed in the cavity 605 and is mounted on the reinforcement layer 20 in a flip-chip manner through bumps 91. Therefore, the first semiconductor element 81 is laterally surrounded by the warp balancer 60 and is electrically connected to the routing circuit 70 through the bump 91 contacting the top contact pad 201 of the reinforcement layer 20.

15 is a cross-sectional view of another interconnection substrate in the third embodiment of the present invention. The interconnect substrate 310 is similar to the structure shown in FIG. 13 except that the resin adhesive 51 is further mixed with a low-CTE adjusting member 53 to reduce the risk of resin cracking, and the warping balance member 60 includes The top conductive pads 61 on the top surface of the top conductive pads 61 are provided by the core layer 40 The second vertical connecting member 67 of a vertical connecting piece 47 and the bending balance piece 60 is electrically connected to the routing circuit 70.

[Example 4]

Fig. 16 is a cross-sectional view of an interconnect substrate according to a fourth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

The interconnect substrate 400 is similar to the structure shown in FIG. 13, except that the low-CTE adjustment member 53 is distributed in the resin adhesive 51 to form a modified bonding matrix 50, and the reinforcing layer 20 only includes a supporting base 21 on which There is no top re-distribution circuit. In this embodiment, the supporting base 21 is exposed from the recess 605, and the inner edge of the warping balance member 60 partially overlaps and contacts the top surface of the supporting base 21 of the reinforcing layer 20.

FIG. 17 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element 81 is electrically connected to the interconnect substrate 400 shown in FIG. 16. The first semiconductor element 81 is disposed in the cavity 605 facing down, and is electrically connected to the top contact pad 201 of the reinforcement layer 20 through the bump 91. Therefore, the first semiconductor element 81 is electrically connected to the interconnect substrate 400 through the high modulus reinforcement layer 20 at the bottom of the cavity 605, where the cavity 605 is laterally surrounded by the inner sidewall of the warping balance 60.

18 is a cross-sectional view of another interconnection substrate in the fourth embodiment of the present invention. The interconnect substrate 410 is similar to the structure shown in FIG. 16, except that the modified bonding matrix 50 extends beyond the gap and further covers the bottom surface of the support base 21 and the bottom surface of the core layer 40, and the core layer 40 and the warping balance 60 Each has a first vertical connection piece 47 and a second vertical connection piece 67. The top conductive pad 61 provided on the top surface of the warp balancer 60 can be electrically connected to the routing circuit 70 via the first vertical connection member 47 and the second vertical connection member 67.

[Example 5]

Fig. 19 is a cross-sectional view of an interconnect substrate according to a fifth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

The interconnect substrate 500 is similar to the structure shown in FIG. 16, except that the reinforcement layer 20 further has a through hole 205 aligned with the cavity 605, and the routing circuit 70 includes metal exposed from the through hole 205 and the cavity 605垫72. A part of the reinforcement 20 and optionally a part of the routing circuit 70 may be removed to form a through hole 205, wherein the size of the through hole 205 is smaller than the size of the cavity 605. In this embodiment, the through hole 205 extends through the reinforcement layer 20 and further extends into the innermost dielectric layer 71 of the routing circuit 70.

20 is a cross-sectional view of a semiconductor assembly in which the first semiconductor element 81 and the second semiconductor element 83 are packaged on the interconnect substrate 500 shown in FIG. 19. The first semiconductor element 81 is disposed in the cavity 605 facing down, and is electrically connected to the top contact pad 201 of the reinforcement layer 20 through the first bump 92. The second semiconductor element 83 is disposed in the through hole 205 facing upward, and is electrically connected to the first semiconductor element 81 via the second bump 93 and attached to the metal pad 72.

FIG. 21 is a cross-sectional view of another interconnection substrate in the fifth embodiment of the present invention. The interconnect substrate 510 is similar to the structure shown in FIG. 19, except that the modified bonding matrix 50 extends beyond the gap and further covers the bottom surface of the reinforcing layer 20 and the bottom surface of the core layer 40, and the warping balance 60 includes a top conductive The pad 61 is located on the top surface of the warp balancer 60 and is electrically connected to the routing circuit 70 through the first vertical connector 47 in the core layer 40 and the second vertical connector 67 of the warp balancer 60. In this aspect, the through hole 205 extends through the reinforcement layer 20 and further extends into the modified bonding matrix 50.

[Example 6]

22-25 are cross-sectional views of another method of manufacturing an interconnect substrate in the sixth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

FIG. 22 is a cross-sectional view of the build-up circuit 33 attached to the sacrificial carrier board 31 and soldered to the reinforcement layer 20. The build-up circuit 33 can be directly formed on the sacrificial carrier 31 through a build-up process, and then connected to the top surface of the reinforcement layer 20. The reinforcement layer 20 includes a top contact pad 201, a bottom contact pad 203, and a metalized through hole 217. In this figure, the build-up circuit 33 includes a plurality of insulating layers 331 and a plurality of routing layers 335 alternately formed on the sacrificial carrier 31. The routing layers 335 are electrically coupled to each other through the metalized vias 337 in the insulating layer 331, and the lowest routing layer 335 is electrically coupled to the reinforcement layer through the solder balls 35 between the reinforcement layer 20 and the build-up circuit 33 The top of 20 touches the pad 201. Therefore, the routing layer 335 of the build-up circuit 33 can be electrically connected to the bottom contact pad 203 of the reinforcement layer 20 through the solder balls 35, the top contact pad 201, and the metalized through hole 217. Optionally, a primer 38 may be coated between the build-up circuit 33 and the reinforcement layer 20.

FIG. 23 is a cross-sectional view of the reinforcing layer 20 inserted into the opening 401 of the core layer 40. The peripheral side wall of the reinforcing layer 20 is separated from the inner side wall of the opening 401 of the core layer 40 and is laterally surrounded by the inner side wall of the opening 401 of the core layer 40. The build-up circuit 33 and the sacrificial carrier board 31 are located outside the opening 401 of the core layer 40.

24 is a cross-sectional view of the reinforcing layer 20 and the core layer 40 on opposite sides of the bending balance 60 and the routing circuit 70. The warping balance 60 is arranged on the core layer 40 and part of the reinforcement layer 20 from above, and surrounds laterally and covers the peripheral edges of the sacrificial carrier 31 and the build-up circuit 33 in the same shape. It further extends into the gap between the peripheral sidewall of the reinforcing layer 20 and the inner sidewall of the opening 401 of the core layer 40. The routing circuit 70 covers the bottom surface of the reinforcement layer 20 and the core layer 40 and is electrically coupled to the bottom contact pad 203 of the reinforcement layer 20 through the metalized via 77.

FIG. 25 is a cross-sectional view of the sacrificial carrier plate 31 removed. By removing the sacrificial carrier plate 31, a cavity 605 is formed by the inner sidewall of the warped balancer 60 and the top surface of the build-up circuit 33, and the top terminal pad 338 provided by the topmost routing layer 335 on the top surface of the build-up circuit 33 It is revealed by the recess 605.

Accordingly, the completed interconnect substrate 600 includes the reinforcement layer 200, the build-up circuit 33, the solder balls 35, the core layer 40, the warp balancer 60 and the routing circuit 70. The reinforcement layer 20 is aligned with the cavity 605 and is located below the cavity 605 to provide sufficient rigidity at the cavity area, thereby suppressing bending or deformation of the component interface. As mentioned above, the ratio of the thickness of the reinforcing layer 20 (in millimeters) to the opening area of the upper cavity 605 (in square millimeters) is preferably controlled to be 1×10 ^-5 or more to resist bending and warping. Produce significant beneficial effects. The build-up circuit 33 is disposed on the reinforcement layer 20 and supported by the reinforcement layer 20, and a top terminal pad 338 is provided for the chip to be assembled in the cavity 605. The CTE of the warp balancer 60 is preferably substantially equal to or close to the CTE of the routing circuit 70 to effectively maintain the required flatness of the interconnect substrate 600. The routing circuit 70 is electrically connected to the bottom contact pad 203 of the reinforcement layer 20 and provides electrical contacts from the bottom of the interconnect substrate 600 for the next level of connection.

FIG. 26 is a cross-sectional view of the semiconductor assembly in which the first semiconductor element 81 is electrically connected to the interconnect substrate 600 shown in FIG. 25. The first semiconductor element 81 is disposed in the cavity 605 and is mounted on the top terminal pad 338 of the build-up circuit 33 at the bottom of the cavity 605 through the bump 91 facing down. Therefore, the first semiconductor element 81 can be electrically connected to the routing circuit 70 through the build-up circuit 33 and the reinforcement layer 20.

FIG. 27 is a cross-sectional view of another interconnection substrate in the sixth embodiment of the present invention. The interconnect substrate 610 is similar to the structure shown in FIG. 25, except that before providing the warp balancer 60 and the routing circuit 70, the gap between the reinforcement layer 20 and the core layer 40 is filled with a modified bonding matrix 50. As described above, the modified bonding matrix 50 may include a low-CTE adjusting member 53 dispersed in the resin adhesive 51 to reduce the risk of resin cracking.

As shown in the above embodiments, the present invention constructs a unique interconnect substrate with better reliability, which mainly includes a reinforcement layer, a core layer, a warp balancer, a routing circuit, and an optional build-up circuit. The above-mentioned interconnection substrate and assembly are only illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments based on considerations of design and reliability.

The interconnection substrate has a cavity, which is laterally surrounded by the inner side wall of the warping balancer, and is completely covered by the reinforcing layer from the bottom of the cavity. In order to connect the components in the cavity, the interconnection substrate is provided with electrical contacts exposed from the cavity. Specifically, the cavity can be formed by the inner sidewall of the warped balancer and the top surface of the reinforcement layer, wherein the reinforcement layer includes a top contact pad exposed from the bottom of the cavity as an electrical contact for device connection. Alternatively, the cavity can be formed by the inner sidewall of the warped balancer and the top surface of the build-up circuit, wherein the build-up circuit includes a top terminal pad exposed from the bottom of the cavity as an electrical contact for device connection. By specifically controlling the ratio between the thickness of the reinforcement layer and the size of the cavity (that is, the area of the exposed top surface of the reinforcement layer or build-up circuit), it is possible to ensure that the reinforcement layer has sufficient rigidity to compensate for the formation of the cavity. Structural weaknesses, thereby inhibiting bending or deformation of the cavity area. Preferably, the ratio of the thickness of the reinforcement layer (in millimeters) to the size of the upper cavity (in square millimeters) is controlled to be 1×10 ^-5 or more.

The reinforcement layer is a non-electronic component exposed from the bottom of the cavity or located below the bottom of the cavity. Its elastic modulus is higher than that of the core layer and the routing circuit, and preferably higher than 100 GPa, to maintain the interconnect substrate and its The flatness of the semiconductor assembly. Specifically, the reinforcement layer may include a supporting substrate, optionally a top rerouted circuit, and optionally a bottom rerouted circuit to provide a top contact pad at its top surface and a bottom contact pad at its bottom surface. The supporting substrate exposed from the bottom of the cavity or located below the bottom of the cavity is used to provide the required rigidity, and therefore usually includes a high-modulus inorganic substrate plate that completely covers the bottom of the cavity. In a preferred embodiment, the supporting substrate includes a top wiring layer on its top surface, a bottom wiring layer on its bottom surface, and metallized through holes penetrating the base plate, wherein the metalized through holes are used for the top wiring layer and Vertical electrical connections between the bottom wiring layers. To redistribute routing (routing redistribution), the top and bottom redistribution circuits can be respectively arranged above the top surface and below the bottom surface of the supporting substrate as appropriate. The top and bottom redistribution circuits usually each include at least one insulating layer and at least one routing layer alternately formed. For example, the top redistributed circuit may include a top insulating layer on the top surface of the supporting substrate and a top routing layer on the top insulating layer, the top routing layer is electrically coupled to the top wiring layer of the supporting substrate, and the bottom redistributed circuit It may include a bottom insulating layer on the bottom surface of the supporting substrate and a bottom wiring layer on the bottom insulating layer, and the bottom routing layer is electrically coupled to the bottom wiring layer of the supporting substrate. Therefore, the top routing layer of the top redistribution circuit can provide the top contact pads of the reinforcement layer, and the bottom routing layer of the bottom redistribution circuit can provide the bottom contact pads of the reinforcement layer. Optionally, the reinforcement layer may further have a through hole aligned with the cavity. More specifically, the size of the through hole of the reinforcement layer is smaller than the size of the cavity, and the through hole of the reinforcement layer communicates with the cavity and can further extend into the routing circuit. Accordingly, the through hole of the reinforcement layer can provide a space for accommodating the semiconductor device. In addition, since the core layer and routing circuit usually contain resin dielectric materials and glass fibers with very low thermal conductivity, the heat generated by the chip flows through these areas. The domain will experience very high thermal resistance. In this case, if the thermal conductivity of the strengthening layer is higher than the thermal conductivity of the core layer and the routing circuit, the strengthening layer can be used as a heat sink.

The core layer is arranged around the peripheral side wall of the reinforcement layer and can directly contact the peripheral side wall of the reinforcement layer, or the core layer has an inner side wall separated from the peripheral side wall of the reinforcement layer. In a preferred embodiment, the core layer has an opening, and the reinforcing layer provided in the opening of the core layer can be adhered to the inner side wall of the opening by using a resin adhesive or a part of the bending balance member. Generally, the CTE of the resin adhesive may be very high compared to the CTE of the reinforcing layer and the core layer, and therefore, it is easy to cause cracks due to internal expansion and contraction during thermal cycling in a confined area. In order to reduce the risk of adhesive cracking, a plurality of adjusting elements (with CTE lower than the CTE of the resin adhesive) can be further distributed in the resin adhesive to form a modified joint in the gap between the outer side wall of the reinforcing layer and the inner side wall of the opening Matrix. Preferably, the content of the adjusting element is at least 30% (volume percentage) of the total volume of the gap, more preferably 50% or more, and the CTE difference between the resin adhesive and the adjusting element may be 10 ppm/°C or higher, To show a significant effect. Therefore, the CTE of the modified bonding matrix can be lower than 50ppm/°C, which can slow down the internal expansion and contraction of the modified bonding matrix during thermal cycling to prevent cracking. In addition, in order to effectively release the thermal-mechanical stress, the modified bonding matrix preferably has a sufficient width of more than 10 microns (more preferably more than 25 microns) in the gap to absorb the stress. Furthermore, the modified bonding matrix can extend beyond the gap and further cover the bottom surface of the reinforcing layer and the core layer. By extending the modified bonding matrix laterally below the reinforcing layer and the core layer, the interface stress between the modified bonding matrix and the reinforcing layer and between the modified bonding matrix and the core layer can be dispersed, thereby helping to further reduce the risk of cracking. Optionally, the core layer may include at least one first vertical connector electrically coupled to the routing circuit. Therefore, the core layer can provide a signal vertical conduction path or/and an energy transmission and return path between the routing circuit and the warp balancer.

The warping balancer arranged above the top surface of the core layer usually contains resin-like materials, and can further extend into the gap between the peripheral side wall of the reinforcing layer and the inner side wall of the core layer. In order to suppress the bending or warpage of the interconnect substrate, the CTE and thickness of the warping balancer are preferably substantially equal to or close to the CTE and thickness of the routing circuit. For example, the CTE difference between the warp balancer and the routing circuit can be controlled to be less than 20 ppm/°C, so as to effectively maintain the required flatness of the interconnect substrate. In a preferred embodiment, the inner edge part of the warping balance piece overlaps the top surface of the reinforcement layer, so that the edge portion of the reinforcement layer below the warpage balance piece can provide support to the inner edge portion of the warpage balance piece, thereby Enhance the mechanical reliability of the interconnect substrate. Optionally, the warping balance member may include at least one second vertical connecting member electrically coupled to the first vertical connecting member of the core layer. Therefore, the top conductive pad provided at the top surface of the warping balance member can be electrically connected to the routing circuit through the first and second vertical connecting members.

The routing circuit disposed under the bottom surface of the reinforcing layer and the core layer includes a wire layer, wherein the wire layer can be electrically connected to the bottom contact pad of the reinforcing layer through its metallized vias, and may be connected to the first layer of the core layer as appropriate. The vertical connector is electrically connected. For example, the routing circuit can be a multi-layer build-up circuit without a core board, which includes at least one dielectric layer and at least one wire layer. On the electrical layer. The dielectric layer and the wire layer can be alternately formed, and can be formed repeatedly if more signal routing is required. Therefore, the routing circuit can be electrically connected to the bottom contact pad of the reinforcement layer through the metalized vias, and can be electrically connected to the first vertical connector of the core layer as appropriate. In the aspect where the reinforcement layer has a through hole, a part of the routing circuit can be exposed from the through hole and the cavity, and the through hole is preferably covered by at least one dielectric layer of the routing circuit from below.

The optional build-up circuit arranged on the top surface of the reinforcement layer can be electrically coupled to the top contact pad of the reinforcement layer through solder balls, and the top surface has a top terminal pad exposed from the cavity. The build-up circuit usually includes at least one insulating layer and at least one routing layer. The routing layer includes metalized vias located in the insulating layer and extending laterally on the insulating layer. The insulating layer and the routing layer can be alternately formed, and can be formed repeatedly if more signal routing is required. Through the reinforcement layer, the build-up circuit can be electrically connected to the routing circuit.

The present invention also provides a semiconductor assembly, in which a first semiconductor element such as a chip is disposed in the cavity of the above-mentioned interconnection substrate and is electrically connected to the top contact pad of the reinforcing layer. Specifically, the first semiconductor device may be electrically connected to the interconnect substrate through bumps (such as gold or solder bumps). For example, in the state where the top contact pad of the reinforcement layer is exposed from the cavity, the first semiconductor element can be disposed in the cavity and mounted and electrically connected to the reinforcement layer by bumps contacting the top contact pad Top surface. Therefore, the first semiconductor element can be electrically connected to the routing circuit through the reinforcing layer. Alternatively, in another aspect in which the top terminal pad of the build-up circuit is exposed from the cavity, the first semiconductor element can be placed in the cavity and mounted and electrically connected to the bump by the bump contacting the top terminal pad On the top surface of the build-up circuit. In this other aspect, the first semiconductor element can be electrically connected to the routing circuit through the reinforcement layer and the build-up circuit. In addition, when the reinforcement layer has the through hole as described above, the semiconductor assembly may further include a second semiconductor element (such as a wafer) disposed in the through hole and electrically connected to the first semiconductor element through bumps.

The assembly can be a first-stage or a second-stage single crystal or polycrystalline device. For example, the assembly may be a first-level package including a single chip or multiple chips. Alternatively, the assembly may be a second-level module including a single package or multiple packages, wherein each package may include a single or multiple chips. The semiconductor element can be a packaged chip or an unpackaged chip. In addition, the semiconductor device can be a bare chip, or a wafer-level package die.

The term "covering" means incomplete and complete coverage in the vertical and/or lateral directions. For example, in a preferred embodiment, the reinforcement layer completely covers the cavity from below, regardless of whether another component (such as a build-up circuit) is located between the reinforcement layer and the cavity.

The term "surround" refers to the relative position of components, regardless of whether there is another component between them. For example, in a preferred embodiment, the core layer laterally surrounds the reinforcing layer, regardless of whether there is another element (such as a resin adhesive) between the reinforcing layer and the core layer.

"Install on...above", "Attach to", "Extend...", "Set on...above/above/below", "Locate on... .. "Above" semantically includes contact and non-contact between components. For example, in a preferred embodiment, the routing circuit is disposed under the bottom surface of the reinforcement layer and further extends to the bottom surface of the core layer, regardless of whether the routing circuit contacts the core layer and the reinforcement layer or is modified by the bonding matrix and the core layer and the reinforcement layer Separate.

The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, in a preferred embodiment, the routing circuit can be electrically connected to the build-up circuit through the reinforcement layer, but not in contact with the build-up circuit.

The interconnect substrate prepared by this method has high reliability, low price, and is very suitable for mass production. The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this manufacturing method can greatly improve the yield, yield, performance and cost-effectiveness.

The embodiments described here are for illustrative purposes, and these embodiments may simplify or omit elements or steps that are well known in the art so as not to obscure the characteristics of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or unnecessary components and component symbols.

100: Interconnect substrate

20: Reinforcement layer

201: Top contact pad

203: bottom contact pad

21: Support base

40: core layer

51: Resin adhesive

60: Bending balance piece

605: dent

70: routing circuit

71: Dielectric layer

73: Wire layer

77: Metallized vias

Claims (18)

An interconnection substrate includes: a reinforcement layer with top contact pads on its top surface and bottom contact pads on its bottom surface, the top contact pads are electrically connected to the bottom contact pads; a core layer, the side of which is Surrounding the peripheral side wall of the reinforcing layer and having an opening, wherein the reinforcing layer is disposed in the opening of the core layer and is adhered to the inner side wall of the opening through a resin adhesive; a routing circuit is disposed on the reinforcing layer Below the bottom surface, extending laterally to the bottom surface of the core layer, and electrically coupled to the bottom contact pads of the reinforcing layer; and a bending balance piece, which is disposed above the top surface of the core layer , And has an inner side wall laterally surrounding a cavity, the top contact pads of the reinforcement layer are aligned with the cavity, and a part of the warping balance piece overlaps the top surface of the reinforcement layer, wherein the reinforcement layer The modulus of elasticity is higher than the modulus of elasticity of the core layer and the routing circuit, and the ratio between the thickness of the reinforcement layer and the size of the cavity in millimeter unit thickness to square millimeter unit size is 1×10 ^-5 or more . An interconnection substrate includes: a reinforcement layer with top contact pads on its top surface and bottom contact pads on its bottom surface, the top contact pads are electrically connected to the bottom contact pads; a core layer, the side of which is Surrounding the peripheral side wall of the reinforcing layer and having an opening, wherein the reinforcing layer is disposed in the opening of the core layer; a routing circuit is disposed below the bottom surface of the reinforcing layer and extending laterally to the core layer On the bottom surface, and electrically coupled to the bottom contact pads of the reinforcing layer; and a warping balance member disposed above the top surface of the core layer and extending into the peripheral sidewall and the opening of the reinforcing layer In the gap between the inner side walls, the inner side wall laterally surrounds a cavity, the top contact pads of the reinforcing layer are aligned with the cavity, and a part of the warping balance piece overlaps the reinforcing layer Above the top surface, the elastic modulus of the reinforcing layer is higher than the elastic modulus of the core layer and the routing circuit, and the ratio of the thickness of the reinforcing layer to the size of the cavity between the unit thickness in millimeters and the unit size in square millimeters is 1×10 ^-5 or larger. The interconnect substrate described in item 1 or item 2 of the scope of patent application, wherein the elastic modulus of the reinforcing layer is higher than 100 GPa. For the interconnect substrate described in item 1 or item 2 of the scope of the patent application, wherein the reinforcement layer further has a through hole aligned with the cavity, and a part of the routing circuit is composed of the cavity and the through hole Revealed. The interconnection substrate described in item 1 or item 2 of the scope of patent application, wherein the interconnection substrate further includes a build-up circuit, which is disposed above the top surface of the reinforcement layer and is electrically conductive through solder balls The top contact pads coupled to the reinforcement layer, and the build-up circuit has a top terminal pad exposed from the cavity on the top surface of the build-up circuit. The interconnection substrate as described in item 1 or item 2 of the scope of patent application, wherein the reinforcement layer includes a support base and a bottom redistributed circuit, the bottom redistributed circuit is disposed under the bottom surface of the support base, and The top contact pads at the top surface of the supporting substrate are exposed from the cavity, and are electrically connected to the routing circuit through the bottom contact pads at the bottom surface of the bottom redistribution circuit. According to the interconnection substrate described in item 1 or item 2 of the scope of patent application, the reinforcement layer includes a supporting base and a top redistributed circuit, and the top redistributed circuit is arranged above the top surface of the supporting base, The top contact pads on the top surface of the top redistribution circuit are exposed from the cavity, and are electrically connected to the routing circuit through the bottom contact pads at the bottom surface of the supporting substrate. The interconnection substrate as described in item 1 of the scope of the patent application further includes: a plurality of adjustment members distributed in the resin adhesive to form a modified bonding matrix on the peripheral side wall of the reinforcing layer and the opening In the gap between the inner side walls, the thermal expansion coefficient of the adjusting members is lower than the thermal expansion coefficient of the resin adhesive. The interconnect substrate according to claim 8, wherein the modified bonding matrix extends beyond the gap and further covers the bottom surface of the reinforcing layer and the bottom surface of the core layer. According to the interconnection substrate described in item 1 or item 2 of the scope of patent application, the core layer has a first vertical connector electrically coupled to the routing circuit. According to the interconnection substrate described in claim 10, the warping balance member is electrically coupled to a second vertical connection member of the first vertical connection member. According to the interconnection substrate described in item 1 or item 2 of the scope of patent application, the difference in thermal expansion coefficient between the warping balancer and the routing circuit is less than 20 ppm/°C. The interconnect substrate described in item 1 or item 2 of the scope of patent application, wherein the thermal conductivity of the reinforcing layer is higher than the thermal conductivity of the core layer and the thermal conductivity of the routing circuit. A semiconductor assembly comprising: the interconnection substrate as described in any one of items 1 to 3 and items 8 to 13 in the scope of the patent application; and A first semiconductor element is arranged in the cavity and electrically connected to the top contact pads of the reinforcing layer. The semiconductor assembly described in claim 14, wherein the reinforcement layer further has a through hole aligned with the cavity, and the semiconductor assembly further includes a second semiconductor element disposed on the through hole In the hole and electrically connected to the first semiconductor element. The semiconductor assembly described in claim 14, wherein the interconnect substrate further includes a build-up circuit, which is disposed above the top surface of the reinforcement layer and is electrically coupled to the The top contact pads of the reinforcing layer, and the build-up circuit has a top terminal pad located at the bottom of the cavity and electrically connected to the first semiconductor element through bumps. The semiconductor assembly according to claim 14, wherein the reinforcement layer includes a supporting substrate and a bottom redistributed circuit, and the bottom redistributed circuit is disposed under the bottom surface of the supporting substrate and located on the supporting substrate The top contact pads at the top surface are electrically connected to the first semiconductor element through bumps, and the bottom contact pads at the bottom surface of the bottom redistribution circuit are electrically connected to the routing circuit. The semiconductor assembly according to claim 14, wherein the reinforcement layer includes a support base and a top redistributed circuit, and the top redistributed circuit is disposed above the top surface of the support base and located on the top The top contact pads on the top surface of the redistribution circuit are electrically connected to the first semiconductor element by bumps, and the bottom contact pads on the bottom surface of the supporting substrate are electrically connected to the routing circuit.

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