TWI848301B - Electronic device with cable interface and manufacturing method thereof - Google Patents
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本揭示有關於一種具備纜線介面的電子裝置,且特別是有關一種電子裝置其能夠降低纜線介面上的共模雜訊。 The present disclosure relates to an electronic device having a cable interface, and in particular to an electronic device capable of reducing common mode noise on the cable interface.
對於具備通訊功能的電子產品而言,數位電子產品經常包含天線電路以及高速連接器介面,例如通用序列匯流排(universal serial bus,USB)、高解析度多媒體介面(high definition multimedia interface,HDMI)埠或顯示連接埠。 For electronic products with communication functions, digital electronic products often include antenna circuits and high-speed connector interfaces, such as universal serial bus (USB), high definition multimedia interface (HDMI) port or display connection port.
電子產品的設計人員需要避免天線電路與高速連接器介面之間的可能發生的射頻干擾(radio frequency interference,RFI)及/或電磁干擾(electromagnetic interference,EMI)等問題。近代電子產品設計通常趨向於小型化。因此,在一些情況下,電子產品中的天線電路與高速連接器介面被迫設置在距離較近的位置上,這將導致更難以降低兩者間的射頻干擾或電磁干擾。 Designers of electronic products need to avoid possible radio frequency interference (RFI) and/or electromagnetic interference (EMI) between antenna circuits and high-speed connector interfaces. Modern electronic product designs generally tend to be miniaturized. Therefore, in some cases, the antenna circuits and high-speed connector interfaces in electronic products are forced to be placed at a closer distance, which will make it more difficult to reduce the radio frequency interference or electromagnetic interference between the two.
本揭示的一態樣揭露一種電子裝置,包含印刷電路板、積體電路、連接器、扼流圈模組以及補償模組。積體電路設置於該印刷電路板上。連接器設置於該印刷電路板上。扼流圈模組設置於該印刷電路板上,並耦接於該積體電路以及該連接器之間。補償模組設置於該印刷電路板上,並耦接於該扼流圈模組以及該連接器之間。 One embodiment of the present disclosure discloses an electronic device, including a printed circuit board, an integrated circuit, a connector, a choke module, and a compensation module. The integrated circuit is disposed on the printed circuit board. The connector is disposed on the printed circuit board. The choke module is disposed on the printed circuit board and coupled between the integrated circuit and the connector. The compensation module is disposed on the printed circuit board and coupled between the choke module and the connector.
本揭示的另一態樣揭露一種製造方法用以製造一電子裝置,製造方法包含:提供印刷電路板,印刷電路板包含第一佈局線路以及第二佈局線路;附接積體電路至印刷電路板上,並將積體電路連接至第一佈局線路以及第二佈局線路;附接連接器至印刷電路板上,並將連接器連接至第一佈局線路以及第二佈局線路;附接扼流圈模組至印刷電路板上且在積體電路與連接器之間,並將扼流圈模組連接至第一佈局線路以及第二佈局線路;以及,附接補償模組至印刷電路板上且在扼流圈模組與連接器之間,並將補償模組連接至第一佈局線路以及第二佈局線路。 Another aspect of the present disclosure discloses a manufacturing method for manufacturing an electronic device, the manufacturing method comprising: providing a printed circuit board, the printed circuit board comprising a first layout line and a second layout line; attaching an integrated circuit to the printed circuit board, and connecting the integrated circuit to the first layout line and the second layout line; attaching a connector to the printed circuit board, and connecting the connector to the first layout line and the second layout line; attaching a choke module to the printed circuit board between the integrated circuit and the connector, and connecting the choke module to the first layout line and the second layout line; and attaching a compensation module to the printed circuit board between the choke module and the connector, and connecting the compensation module to the first layout line and the second layout line.
須說明的是,上述說明以及後續詳細描述是以實施例方式例示性說明本案,並用以輔助本案所請求之發明內容的解釋與理解。 It should be noted that the above explanation and subsequent detailed description are illustrative examples of this case and are used to assist in the explanation and understanding of the invention content claimed in this case.
100:電子裝置 100: Electronic devices
110:印刷電路板 110: Printed circuit board
120:積體電路 120: Integrated circuits
140:扼流圈模組 140: Choke module
160:補償模組 160: Compensation module
160a,160b,160c,160d,160e:補償模組 160a,160b,160c,160d,160e: Compensation module
180:連接器 180: Connector
200:纜線 200: Cable
210:第一端 210: First end
220:第二端 220: Second end
500:製造方法 500: Manufacturing method
W1:第一佈局線路 W1: First layout line
W2:第二佈局線路 W2: Second layout line
X-X:剖面線 X-X: hatch line
DIF:差動訊號 DIF: Differential signal
DIF+:正向訊號 DIF+: Positive signal
DIF-:負向訊號 DIF-: Negative signal
PORT1,PORT2,PORT3,PORT4:連接埠 PORT1,PORT2,PORT3,PORT4:Port
P1:第一部分 P1: Part 1
P2:第二部分 P2: Part 2
CMN1:第一共模雜訊 CMN1: First common mode noise
CMN2:第二共模雜訊 CMN2: Second common mode noise
IOp:正輸入輸出端 IOp: positive input output port
IOn:負輸入輸出端 IOn: negative input and output terminal
mPORT1,mPORT2:連接埠 mPORT1, mPORT2: port
PC1:第一被動元件 PC1: First passive element
PC2:第二被動元件 PC2: Second passive element
PC3:第三被動元件 PC3: The third passive element
PC4:第四被動元件 PC4: Fourth passive element
PC5:第五被動元件 PC5: The fifth passive element
PC6:第六被動元件 PC6: Sixth passive element
S510,S520,S530,S540,S550:步驟 S510, S520, S530, S540, S550: Steps
為讓本揭示內容之上述和其他目的、特徵與實施例 能更明顯易懂,所附圖式之說明如下:第1圖繪示根據本揭示之一些實施例中一種電子裝置的俯視示意圖;第2圖繪示根據一些實施例中第1圖所示之電子裝置沿著剖面線X-X的剖面示意圖;第3A圖至第3E圖繪示根據一些實施例中具有不同配置的各種補償模組的示意圖;第4圖繪示補償模組、連接器以及纜線在S參數量測當中連接埠定義的示意圖;以及第5圖繪示根據本揭示文件的一些實施例中一種製造方法的方法流程示意圖。 In order to make the above and other purposes, features and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a schematic diagram of a top view of an electronic device according to some embodiments of the present disclosure; FIG. 2 is a schematic diagram of a cross-section of the electronic device shown in FIG. 1 along the section line X-X according to some embodiments; FIG. 3A to FIG. 3E are schematic diagrams of various compensation modules with different configurations according to some embodiments; FIG. 4 is a schematic diagram of the connection port definition of the compensation module, connector and cable in S parameter measurement; and FIG. 5 is a schematic diagram of a method flow of a manufacturing method according to some embodiments of the present disclosure.
以下揭示提供許多不同實施例或例證用以實施本揭示文件的不同特徵。特殊例證中的元件及配置在以下討論中被用來簡化本揭示。所討論的任何例證只用來作解說的用途,並不會以任何方式限制本揭示文件或其例證之範圍和意義。在適當的情況下,在圖式之間及相應文字說明中採用相同的標號以代表相同或是相似的元件。 The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. The components and configurations in the specific examples are used to simplify the present disclosure in the following discussion. Any examples discussed are used for illustrative purposes only and do not limit the scope and meaning of the present disclosure or its examples in any way. Where appropriate, the same reference numerals are used between the drawings and in the corresponding text description to represent the same or similar components.
請參閱第1圖,其繪示根據本揭示之一些實施例中一種電子裝置100的俯視示意圖。如第1圖所示,電子裝置100包含印刷電路板110、積體電路(integrated circuit,IC)120、扼流圈模組140、補償模組160以及連接器180。其中,積體電路120、扼流圈模組140、補
償模組160以及連接器180分別設置於印刷電路板110的表面上。
Please refer to FIG. 1, which shows a schematic top view of an
在一些實施例中,連接器180用以與纜線200的第一端210連接。纜線200用以乘載一對差動訊號DIF。與纜線200相連接的連接器180用以從纜線200接收差動訊號DIF,或者連接器180用以將電子裝置100產生的差動訊號DIF傳送至纜線200。
In some embodiments, the
在一例子中,連接器180為通用序列匯流排(universal serial bus,USB)連接器;纜線200為USB纜線用以與USB連接器相連接;而差動訊號DIF包含適合由USB纜線傳遞的數位資料(例如檔案、文件、命令、指令或封包)。於另一例子中,連接器180為高解析度多媒體介面(high definition multimedia interface,HDMI)連接埠;纜線200為HDMI纜線用以與HDMI連接埠相連接;而差動訊號DIF包含顯示資訊(例如照片、影像、圖框或串流資料)。
In one example,
如第1圖所示,印刷電路板110包含第一佈局線路W1以及第二佈局線路W2,其分別耦接在積體電路120與連接器180之間。第一佈局線路W1以及第二佈局線路W2用以在積體電路120與連接器180之間傳遞差動訊號DIF(並由連接器180進一步傳輸至纜線200)。
As shown in FIG. 1 , the
在一些實施例中,第一佈局線路W1用以在積體電路120與纜線200之間傳輸差動訊號DIF當中的正向訊號DIF+。在一些實施例中,第二佈局線路W2用以在積
體電路120與纜線200之間傳輸差動訊號DIF當中的負向訊號DIF-。
In some embodiments, the first layout line W1 is used to transmit the positive signal DIF+ in the differential signal DIF between the integrated
在一些實施例中,差動訊號DIF為輸入方向的訊號由纜線200傳輸往電子裝置100上的積體電路120。在此情況下,積體電路120用以經過扼流圈模組140、補償模組160及連接器180由纜線200接收差動訊號DIF。
In some embodiments, the differential signal DIF is an input direction signal transmitted from the
在一些實施例中,差動訊號DIF為輸出方向的訊號由電子裝置100產生並傳輸往纜線200。在此情況下,積體電路120產生差動訊號DIF並經過扼流圈模組140、補償模組160及連接器180發送至纜線200。在一些實施例中,積體電路120產生的差動訊號DIF可以通過纜線200傳輸至與外部裝置(例如電腦、螢幕、電視等,圖中未繪示),此外部裝置與纜線200的第二端220相連接。
In some embodiments, the differential signal DIF is an output signal generated by the
請進一步參閱第2圖,其繪示根據一些實施例中第1圖所示之電子裝置100沿著剖面線X-X的剖面示意圖。
Please further refer to FIG. 2, which shows a schematic cross-sectional view of the
如第1圖以及第2圖所示,當沿著纜線200與連接器180傳輸差動訊號DIF時,經纜線200傳輸的差動訊號DIF將感應(induce)產生第一共模雜訊CMN1累積在連接器180的多個連接接腳,這是因為連接器180中與纜線200相連的多個連接接腳彼此之間可能存在不匹配的阻抗及/或具備不一致的對地參照準位。換句話說,第一共模雜訊CMN1是由差動訊號DIF的差模至共模轉換所導致。此第一共模雜訊CMN1可能會干擾到設置在印刷電路
板上且位在連接器180附近的其他組件(例如天線、射頻電路等,圖中未繪示)。
As shown in FIG. 1 and FIG. 2, when the differential signal DIF is transmitted along the
在一些實際例子中,累積在連接器180的多個連接接腳之間的第一共模雜訊CMN1可能會感應產生一電流。此感應產生的電流可以會流過連接器及纜線的屏蔽表面,這會對其他元件(例如天線、射頻電路等,圖中未繪示)造成雜訊電波干擾,其中這個雜訊電波無法被忽略。舉例來說,當電子裝置100(例如行動裝置或筆記型電腦)連接USB纜線,而此USB纜線感應產生的雜訊電波可能會干擾到與電子裝置100通訊連接的一個無線滑鼠、或者導致電子裝置100上無線網路的頻寬吞吐量降低。相似的雜訊電波問題也會發生在當電子裝置100連接到其他訊號纜線時,例如快速週邊組件互連(Peripheral Component Interconnect Express,PCIE)纜線、序列先進技術附件(Serial Advanced Technology Attachment,SATA)纜線、高解析度多媒體介面(high definition multimedia interface,HDMI)纜線、顯示埠(Display Port,DP)纜線、數位視覺介面(Digital Visual Interface,DVI)纜線或影像圖樣陣列(Video Graphics Array,VGA)纜線。
In some practical examples, the first common mode noise CMN1 accumulated between the multiple connection pins of the
在一些例子中,如第1圖及第2圖所示,積體電路120的正輸入輸出端IOp與負輸入輸出端IOn之間可能存在不平衡。在一例子中,積體電路120的正訊號驅動電路(圖中未示)的驅動功率不同於積體電路120的負訊號
驅動電路(圖中未示)的驅動功率,而此差異會導致不平衡並進而產生第二共模雜訊CMN2。在另一例子中,第一佈局線路W1的阻抗可能會不同於第二佈局線路W2的阻抗。當積體電路120產生(或接收)差動訊號DIF時,將在積體電路120的正輸入輸出端IOp與負輸入輸出端IOn上累積第二共模雜訊CMN2。
In some examples, as shown in FIG. 1 and FIG. 2, there may be an imbalance between the positive input/output terminal IOp and the negative input/output terminal IOn of the
如第1圖以及第2圖所示,扼流圈模組140設置於印刷電路板110上並耦接在積體電路120以及連接器180之間。更精確地說,在一些實施例中,扼流圈模組140是耦接於積體電路120與補償模組160之間。在一些實施例中,扼流圈模組140與第一佈局線路W1及第二佈局線路W2連接,並設置鄰近於積體電路120。扼流圈模組140於一些實施例中包含共模扼流線圈(common mode choke coil),其可用來補償或降低累積在積體電路120的正輸入輸出端IOp與負輸入輸出端IOn上的第二共模雜訊CMN2。
As shown in FIG. 1 and FIG. 2 , the
在一些實施例中,共模扼流線圈(即扼流圈模組140)是設置鄰近於積體電路120,並可作為雜訊濾波器的設計用以補償或降低第1圖所示之第二部分P2(包含積體電路120以及扼流圈模組140)上的第二共模雜訊CMN2。在一些實施例中,扼流圈模組140通常無法用來補償或降低第1圖所示之第一部分P1(包含補償模組160、連接器180以及纜線200)上的第一共模雜訊CMN1,因為扼流圈模組140與連接器180的距離相對較遠,且在扼流圈模
組140的設計時並不會考慮纜線200帶來的影響。
In some embodiments, the common mode choke (i.e., the choke module 140) is disposed adjacent to the
如第1圖及第2圖所示,補償模組160設置在印刷電路板110上並耦接在扼流圈模組140以及連接器180之間。在一些實施例中,補償模組160用以補償或降低第一部分P1中連接器180上的第一共模雜訊CMN1。於一些實施例中,補償模組160用以降低在第一部分P1(包含補償模組160、連接器180以及纜線200)的差模至共模轉換(differential to common mode conversion,SCD21)所具有的散射參數(scattering parameter,又稱為S參數)。關於補償模組160如何降低差模至共模轉換(SCD21)中的S參數的詳細作法將在後續段落中進一步說明。
As shown in FIG. 1 and FIG. 2 , the
請一併參閱第3A圖至第3E圖,其繪示根據一些實施例中具有不同配置的各種補償模組160a~160e的示意圖。補償模組160a~160e中每一者可以用來實現第1圖及第2圖中所示的補償模組160。
Please refer to FIGS. 3A to 3E, which illustrate schematic diagrams of
如第3A圖所示,補償模組160a包含第一被動元件PC1以及第二被動元件PC2。第一被動元件PC1與第一佈局線路W1串聯耦接並位於扼流圈模組140與連接器180之間。第二被動元件PC2與第二佈局線路W2串聯耦接並位於扼流圈模組140與連接器180之間。第一被動元件PC1以及第二被動元件PC2各自包含電阻(R)、電感(L)及電容(C)當中至少一者。
As shown in FIG. 3A , the
如第3B圖所示,補償模組160b包含第一被動元
件PC1以及第二被動元件PC2。第一被動元件PC1的第一端耦接至第一佈局線路W1且耦接位置位於扼流圈模組140與連接器180之間,第一被動元件PC1的第二端接地。第二被動元件PC2的第一端耦接至第二佈局線路W2且耦接位置位於扼流圈模組140與連接器180之間,第二被動元件PC2的第二端接地。第一被動元件PC1以及第二被動元件PC2各自包含電阻(R)、電感(L)及電容(C)當中至少一者。
As shown in FIG. 3B , the
如第3C圖所示,補償模組160c包含第一被動元件PC1、第二被動元件PC2、第三被動元件PC3以及第四被動元件PC4。第一被動元件PC1與第一佈局線路W1串聯耦接並且位於扼流圈模組140與連接器180之間。第二被動元件PC2與第二佈局線路W2串聯耦接並且位於扼流圈模組140與連接器180之間。第三被動元件PC3的第一端耦接至第一佈局線路W1且耦接位置位於扼流圈模組140與第一被動元件PC1之間,第三被動元件PC3的第二端接地。第四被動元件PC4的第一端耦接至第二佈局線路W2且耦接位置位於扼流圈模組140與第二被動元件PC2之間,第四被動元件PC4的第二端接地。第一被動元件PC1、第二被動元件PC2、第三被動元件PC3以及第四被動元件PC4各自包含電阻(R)、電感(L)及電容(C)當中至少一者。
As shown in FIG. 3C , the compensation module 160c includes a first passive element PC1, a second passive element PC2, a third passive element PC3, and a fourth passive element PC4. The first passive element PC1 is coupled in series with the first layout line W1 and is located between the
如第3D圖所示,補償模組160d包含第一被動元件PC1、第二被動元件PC2、第三被動元件PC3以及第
四被動元件PC4。相較於第3C圖,第3D圖所示的實施例中,第三被動元件PC3的第一端耦接至第一佈局線路W1且耦接位置位於第一被動元件PC1與連接器180之間,第四被動元件PC4的第一端耦接至第二佈局線路W2且耦接位置位於第二被動元件PC2與連接器180之間。第3D圖所示的補償模組160d的其他結構特徵與第3C圖中所示的補償模組160c相似。
As shown in FIG. 3D, the compensation module 160d includes a first passive component PC1, a second passive component PC2, a third passive component PC3, and a fourth passive component PC4. Compared with FIG. 3C, in the embodiment shown in FIG. 3D, the first end of the third passive component PC3 is coupled to the first layout line W1 and the coupling position is located between the first passive component PC1 and the
如第3E圖所示,補償模組160e包含第一被動元件PC1、第二被動元件PC2、第三被動元件PC3、第四被動元件PC4、第五被動元件PC5以及第六被動元件PC6。相較於第3C圖,第3E圖所示的實施例中增加了第五被動元件PC5以及第六被動元件PC6。第五被動元件PC5的第一端耦接至第一佈局線路W1且耦接位置位於第一被動元件PC1與連接器180之間,第六被動元件PC6的第一端耦接至第二佈局線路W2且耦接位置位於第二被動元件PC2與連接器180之間。第三被動元件PC3與第五被動元件PC5耦接至第一被動元件PC1的不同端。第四被動元件PC4與第六被動元件PC6耦接至第二被動元件PC2的不同端。第3E圖所示的補償模組160e的其他結構特徵與第3C圖中所示的補償模組160c相似。
As shown in FIG. 3E , the
需特別注意的是,第3A圖至第3E圖中所示的多個補償模組160a~160e的一者可被選作為第1圖及第2圖之實施例中的補償模組160。關於補償模組160a~160e的各種不同配置的選擇以及其中多個被動元件的電阻、電
感或電容數值的設定是根據第2圖中第一部分P1進行S參數量測的結果而定。
It should be noted that one of the
請一併參閱第4圖,其繪示補償模組160、連接器180以及纜線200在S參數量測當中連接埠定義的示意圖。
Please also refer to Figure 4, which shows a schematic diagram of the
如第1圖以及第4圖所示,連接埠PORT1定義在纜線200上並對應正向訊號DIF+以及第一佈局線路W1,另一連接埠PORT3定義在纜線200上並對應負向訊號DIF-以及第二佈局線路W2。連接埠PORT2定義在補償模組160上並耦接至第一佈局線路W1(朝向扼流圈模組140)對應正向訊號DIF+。連接埠PORT4定義在補償模組160上並耦接至第二佈局線路W2(朝向扼流圈模組140)對應負向訊號DIF-。
As shown in Figures 1 and 4, port PORT1 is defined on
上述四個連接埠PORT1~PORT4可以連接至一網路分析儀,藉以在四埠單端模型下進行散射參數(S參數)分析。此S參數分析的結果會產生單端S參數矩陣如下所示:
在這個單端S參數的矩陣,S參數SXY代表在連接埠PORTX位置輸入觸發訊號時在連接埠PORTY所量測到的響應準位。舉例來說,S參數S12代表由連接埠PORT2位置輸入激發訊號時在連接埠PORT1上的響應;S參數S23代表由連接埠PORT3位置輸入激發訊號時在 連接埠PORT2上的響應;S參數S11代表由連接埠PORT1位置輸入激發訊號時在連接埠PORT1上的響應。若一對傳輸線是由兩個訊號分別進行單端驅動,此單端S參數的矩陣通常用來分析這一對傳輸線以得到兩傳輸線之間的串擾量,或者分析得到通過這一對傳輸線之差動訊號的反射功率和入射功率。 In this single-ended S parameter matrix, S parameter S XY represents the response level measured at port PORTY when a trigger signal is input at port PORTX. For example, S parameter S 12 represents the response at port PORT1 when a trigger signal is input at port PORT2; S parameter S 23 represents the response at port PORT2 when a trigger signal is input at port PORT3; S parameter S 11 represents the response at port PORT1 when a trigger signal is input at port PORT1. If a pair of transmission lines is driven by two signals in a single-ended manner, the single-ended S-parameter matrix is usually used to analyze the pair of transmission lines to obtain the crosstalk between the two transmission lines, or to analyze the reflected power and incident power of the differential signal passing through the pair of transmission lines.
在一些例子中,如第4圖所示,兩連接埠PORT1與PORT3可共同被定義為邏輯連接埠mPORT1,而兩連接埠PORT2與PORT4可共同被定義為邏輯連接埠mPORT2。則單端S參數的矩陣可以轉換為混和模式S參數矩陣,如下所示:
在混和模式S參數矩陣中,S參數SCD21代表代表由連接埠mPORT1位置輸入差模激發訊號時在連接埠mPORT2上的共模響應。換句話說,S參數SCD21代表了差動訊號DIF經由纜線200傳輸至連接埠mPORT2(即補償模組上的連接埠PORT2與PORT4)時的差模至共模轉換。
In the mixed mode S parameter matrix, the S parameter S CD21 represents the common mode response on the port mPORT2 when the differential mode excitation signal is input from the port mPORT1. In other words, the S parameter S CD21 represents the differential mode to common mode conversion when the differential signal DIF is transmitted through the
在一些實施例中,根據單端S參數矩陣中已知的S參數經計算可得到混和模式S參數矩陣中的S參數SCD21,計算方式如下:S CD21=(S 21+S 41-S 23-S 43)/2 In some embodiments, the S parameter S CD21 in the mixed mode S parameter matrix can be obtained by calculation based on the known S parameters in the single-ended S parameter matrix. The calculation method is as follows: S CD 21 =( S 21 + S 41 - S 23 - S 43 )/2
相似地,混和模式S參數矩陣中的其他S參數同樣可以根據單端S參數矩陣當中已量測到的S參數計算獲得。 Similarly, other S parameters in the mixed-mode S parameter matrix can also be calculated based on the measured S parameters in the single-ended S parameter matrix.
在一些實施例中,當基於四個連接埠PORT1~PORT4的S參數分析完成後,便可以進行S參數SCD21的監控與量測。補償模組160經調整(透過選擇第3A圖至第3E圖當中的不同配置,或改變被動元件的電阻值、電感值或電容值)以降低或最小化上述混和模式S參數矩陣當中S參數SCD21的數值大小。
In some embodiments, after the S parameter analysis based on the four connection ports PORT1-PORT4 is completed, the S parameter S CD21 can be monitored and measured. The
在選擇補償模組160的最佳化配置後,補償模組160能夠使整個第一部分P1(包含補償模組160、連接器180以及纜線200)所量測到的S參數SCD21降低或達到最小化。在此例子中,補償模組160可以用來降低連接器180上的第一共模雜訊CMN1。
After selecting the optimal configuration of the
請一併參閱第5圖,其繪示根據本揭示文件的一些實施例中一種製造方法500的方法流程示意圖。製造方法500用以生產上述第1圖及第2圖所示實施例中的電子裝置100。如第1圖、第2圖以及第5圖所示,執行步驟S510以提供印刷電路板110,印刷電路板110包含第一佈局線路W1以及第二佈局線路W2。由粘合機器及/或焊接機器,執行步驟S520,將積體電路120附接至印刷電路板110上,並將積體電路120連接至第一佈局線路W1以及第二佈局線路W2。由粘合機器及/或焊接機器,執行步驟S530,將連接器180附接至印刷電路板110上,並
將連接器180連接至第一佈局線路W1以及第二佈局線路W2。由粘合機器及/或焊接機器,執行步驟S540,將扼流圈模組140附接至印刷電路板110上並位在積體電路120與連接器180之間,並將扼流圈模組140連接至第一佈局線路W1以及第二佈局線路W2。
Please refer to FIG. 5, which is a schematic diagram of a method flow of a manufacturing method 500 according to some embodiments of the present disclosure. The manufacturing method 500 is used to produce the
由粘合機器及/或焊接機器,執行步驟S550,將補償模組160附接至印刷電路板110上並位在扼流圈模組140以及連接器180之間,並將補償模組160連接至第一佈局線路W1以及第二佈局線路W2。其中步驟S550所設置的補償模組160可以是第3A圖至第3E圖等實施例所討論的補償模組160a~160e其中一者。補償模組160的配置以及補償模組160當中的被動元件的電阻、電感或電容數值可由上述實施例所討論中S參數分析而加以決定,在此不另贅述。
The step S550 is performed by a bonding machine and/or a welding machine to attach the
需特別說明的是,步驟S520至步驟S550的順序並不以第5圖所示的順序為限。在一些其他實施例中,步驟S520至步驟S550也可以採用相異於第5圖實施例的不同順序加以進行。 It should be noted that the order of steps S520 to S550 is not limited to the order shown in FIG. 5. In some other embodiments, steps S520 to S550 may also be performed in a different order than the embodiment shown in FIG. 5.
雖然上述實施例已揭露本揭示文件的相關具體內容,其他實施方式也是有可能的。本揭示文件的請求項的意義與範圍並不僅限於上述實施例的文字。 Although the above embodiments have disclosed the relevant specific contents of this disclosure document, other implementation methods are also possible. The meaning and scope of the claims of this disclosure document are not limited to the text of the above embodiments.
一般技術人員在沒有背離本揭示文件的原理及精神的情況下,可能對上述提出之架構進行各種替代及改良方式。進一步而言,本揭示文件的保護範圍由所附申請專 利範圍確定,並涵蓋申請專利範圍所指涉之做法與架構的各種修改與變化。 A person skilled in the art may make various substitutions and improvements to the above-mentioned framework without departing from the principles and spirit of this disclosure document. Furthermore, the scope of protection of this disclosure document is determined by the scope of the attached patent application and covers various modifications and changes of the practices and frameworks referred to in the scope of the patent application.
100: 電子裝置 110: 印刷電路板 120: 積體電路 140: 扼流圈模組 160: 補償模組 180: 連接器 200: 纜線 210: 第一端 220: 第二端 W1: 第一佈局線路 W2: 第二佈局線路 X-X: 剖面線 DIF: 差動訊號 DIF+: 正向訊號 DIF-: 負向訊號 PORT1, PORT2, PORT3, PORT4: 連接埠 IOp: 正輸入輸出端 IOn: 負輸入輸出端 100: electronic device 110: printed circuit board 120: integrated circuit 140: choke module 160: compensation module 180: connector 200: cable 210: first end 220: second end W1: first layout line W2: second layout line X-X: cross section line DIF: differential signal DIF+: positive signal DIF-: negative signal PORT1, PORT2, PORT3, PORT4: connection port IOp: positive input/output port IOn: negative input/output port
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