TWI847309B - Semiconductor device with programmable structure - Google Patents

Abstract

The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Description

Semiconductor device with programmable structure

This application claims priority to U.S. Patent Application Nos. 17/678,212 and 17/678,407 (i.e., priority date is February 23, 2022), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device with a programmable structure.

Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is constantly shrinking to meet the growing demand for computing power. However, various problems arise in the process of size reduction, and these problems are increasing. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, as well as reduced complexity.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a semiconductor device, including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure disposed on the transistor portion; a drain region disposed in the programmable portion and the transistor portion and adjacent to the gate structure; a source region disposed in the transistor portion, adjacent to the gate structure and opposite to the drain region, with the gate structure interposed therebetween; an intermediate insulating layer disposed on the programmable portion; and an upper conductive layer disposed on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Another aspect of the present disclosure provides a semiconductor device, comprising a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure disposed in the transistor portion; a drain region disposed in the programmable The programmable design part and the transistor part are adjacent to the buried gate structure; a source region is arranged in the transistor part, adjacent to the buried gate structure and opposite to the drain region, and the buried gate structure is between the two; an intermediate insulating layer is arranged on the programmable design part; and an upper conductive layer is arranged on the intermediate insulating layer. The drain region, the intermediate insulating layer and the upper conductive layer of the programmable design part jointly configure a programmable design structure.

Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; forming a gate structure on the transistor portion; forming a drain region in the programmable portion and the transistor portion, adjacent to the gate structure; forming a source region in the transistor portion, adjacent to the gate structure and opposite to the drain region; forming an intermediate insulating layer on the programmable portion; and forming an upper conductive layer on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; forming a buried gate structure in the transistor portion; forming a drain region in the programmable portion and the transistor portion, adjacent to the buried gate structure; forming a source region in the transistor portion, adjacent to the buried gate structure and opposite to the drain region; forming an intermediate insulating layer on the programmable portion; and forming an upper conductive layer on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Due to the design of the semiconductor element disclosed in the present invention, the programmable structure integrates the drain region associated with the gate structure into the lower conductor of the programmable structure, so the area occupied by the programmable structure can be reduced. Therefore, more area can be used for other complex functional units or more programmable structures. Therefore, the performance of the semiconductor element can be improved. In addition, the gate structure associated with the programmable structure can also be used as an isolation transistor to isolate the high-programmed voltage from the adjacent components. Therefore, the damage of the high-programmed voltage to the adjacent components (for example, the leakage current from the high-programmed voltage) can be reduced. Therefore, the reliability of the semiconductor element can be improved.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. In order to simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which an additional feature can be formed between the first and second features, so that the first and second features are not in direct contact. In addition, the disclosure may repeatedly refer to numbers and/or letters in various embodiments. This repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "lower", "below", "beneath", "upper", "above", etc., may be used herein to describe the relationship of one element or feature to another element or features shown in the figure for ease of description. Spatially relative terms are intended to encompass different orientations of the element in use or operation, in addition to the orientation depicted in the figure. The element may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It should be understood that although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms such as "same," "equal," "planar," or "coplanar" used herein when referring to orientation, layout, position, shape, size, quantity, or other measures do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measures, but rather mean nearly the same orientation, layout, position, shape, size, quantity, or other measures within an acceptable range of variation that may occur, such as due to manufacturing processes. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or they may be the same, equal, or planar within an acceptable range of variation that may occur, such as due to manufacturing processes.

In the present disclosure, semiconductor elements generally refer to elements that can function by utilizing semiconductor properties. Optoelectronic elements, light-emitting display elements, semiconductor circuits, and electronic components are all included in the scope of semiconductor elements.

It should be noted that in the description of the present disclosure, up (or above) corresponds to the direction of the arrow in direction Z, and down (or below) corresponds to the opposite direction of the arrow in direction Z.

FIG. 1 is a flow chart illustrating a method 10 for preparing a semiconductor element 1A according to an embodiment of the present disclosure. FIG. 2 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. FIG. 3 to FIG. 6 are cross-sectional views along line A-A' and line B-B' of FIG. 2, illustrating a portion of the preparation process of a semiconductor element 1A according to an embodiment of the present disclosure. FIG. 7 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. FIG. 8 and FIG. 9 are cross-sectional views along line A-A' and line B-B' of FIG. 7, illustrating a portion of the preparation process of a semiconductor element 1A according to an embodiment of the present disclosure.

1 to 9 , in step S11 , a substrate 101 may be provided, and an isolation layer 103 may be formed in the substrate 101 to define a plurality of active areas AA1 , AA2 , AA3 , AA4 , and AA5 of the substrate 101 .

2 to 4 , substrate 101 may include a silicon-containing material. Illustrative examples of silicon-containing materials suitable for substrate 101 may include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, silicon germanium carbide, carbon-doped silicon, silicon carbide, and multiple layers thereof. Although silicon is the primary semiconductor material used in wafer preparation, in some embodiments, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, germanium tin, and the like.

2 to 4 , a series of deposition processes may be performed to deposit a pad oxide layer 601 and a pad nitride layer 603 on the substrate 101. A lithography process may be performed to define the configuration of the isolation layer 103 by forming a first mask layer 607 on the pad nitride layer 603.

5 and 6 , after the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a first trench 101TR penetrating along the pad nitride layer 603 and the pad oxide layer 601 and extending to the substrate 101 .

7 to 9 , an insulating material may be deposited into the first trench 101TR, and a planarization process, such as chemical mechanical polishing, may then be performed to remove excess filling material until the top surface of the substrate 101 is exposed to form an isolation layer 103. The top surface of the isolation layer 103 may be substantially coplanar with the top surface of the substrate 101. The insulating material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorinated silicate. It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxide nitride refers to a substance containing silicon, oxygen and nitrogen, in which the proportion of nitrogen is greater than that of oxygen.

7 to 9, the portion of the substrate 101 surrounded by the isolation layer 103 may be referred to as an active area AA1, an active area AA2, an active area AA3, an active area AA4, and an active area AA5. In some embodiments, the active areas AA1, AA2, AA3, AA4, and AA5 may be arranged along a Y direction in a top view. For simplicity, clarity, and convenience of description, only one active area AA1 is described. The active area AA1 may include a transistor portion TP and a programmable portion PP.

In some embodiments, from a top view, the transistor portion TP may have a rectangular outline, and the transistor portion TP may extend along the X direction. A width W1 of the transistor portion TP is greater than a width W2 of the programmable portion PP.

In some embodiments, from a top view angle, the upper side of the programmable portion PP and the upper side of the transistor portion TP are aligned with each other, but not limited thereto.

In some embodiments, from a top view perspective, a length L1 of the transistor portion TP is greater than or equal to a length L2 of the programmable portion PP.

FIG. 10 and FIG. 11 are cross-sectional views along the line A-A' and the line BB' of FIG. 7, illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure. FIG. 12 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 13 and FIG. 14 are cross-sectional views along the line A-A' and the line BB' of FIG. 12, illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure.

FIG. 15 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 16 to FIG. 21 are cross-sectional views along line A-A' and line BB' of FIG. 15, illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure. FIG. 22 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 23 and FIG. 24 are cross-sectional views along line A-A' and line BB' of FIG. 22, illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure.

1 and 10 to 24 , in step S13 , a plurality of well regions 113 may be formed in a plurality of active regions AA1 , AA2 , AA3 , AA4 , AA5 , a plurality of gate structures 200 may be formed on the plurality of active regions AA1 , AA2 , AA3 , AA4 , AA5 , and a plurality of source regions 117 and a plurality of drain regions 119 may be formed in the plurality of well regions 113 .

10 and 11, in some embodiments, a p-type impurity implantation process may be performed to form well regions 113 in active regions AA1, AA2, AA3, AA4, and AA5, respectively and correspondingly. The p-type impurity implantation process may add impurities to an intrinsic semiconductor, thereby generating defects in valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium, or indium. In some embodiments, well region 113 may have a first electrical type (i.e., p-type).

For the sake of brevity, clarity and convenience of description, only one gate structure 200 is described.

12 to 14 , the gate structure 200 may be formed on the transistor portion TP of the active area AA1. It should be noted that the gate structure 200 does not overlap the programmable portion PP of the active area AA1 in a top view. In some embodiments, the length L3 of the gate structure 200 may be greater than or equal to the length L1 of the transistor portion TP of the active area AA1 in a top view.

In some embodiments, from a top view, the gate structure 200 may extend along the X direction and divide the transistor portion TP of the active area AA1 into an upper portion and a lower portion. In this embodiment, the programmable portion PP may extend from the upper portion of the transistor portion TP.

12 to 14 , the gate structure 200 may include a gate insulating layer 201 and a gate conductive layer 203. The gate insulating layer 201 may be formed on the transistor portion TP of the active area AA1. In some embodiments, the thickness of the gate insulating layer 201 may be about 50 angstroms or less.

In some embodiments, the gate insulating layer 201 may be formed using, for example, silicon oxide. In some embodiments, the gate insulating layer 201 may be formed using, for example, a high-k dielectric material such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate, or a combination thereof.

Illustrative examples of high-k dielectric materials may include, but are not limited to, bismuth oxide, bismuth silicon oxide, bismuth silicon oxynitride, bismuth tantalum oxide, bismuth titanium oxide, bismuth zirconium oxide, bismuth tantalum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, titanium strontium oxide, titanium barium oxide, zirconium barium oxide, silicon tantalum oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, the gate insulation layer 201 may be a multi-layer structure including, for example, a layer of silicon oxide and another layer of high-k dielectric material.

12 to 14 , a gate conductive layer 203 may be formed on the gate insulating layer 201. In some embodiments, the gate conductive layer 203 may be made of, for example, (doped) polysilicon, (doped) polycrystalline germanium, (doped) polysilicon germanium or other suitable conductive materials.

15 to 17, an n-type impurity implantation process may be performed using the gate structure 200 as a mask to form a plurality of lightly doped regions 115 in the upper and lower portions of the transistor portions TP of the active regions AA1, AA2, AA3, AA4, AA5. The n-type impurity implantation process may add impurities that contribute free electrons to an intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic, or phosphorus. In some embodiments, the lightly doped regions 115 may have a second electrical type (i.e., n-type) opposite to the first electrical type.

18 and 19, a layer of spacer material 605 may be conformally formed to cover the middle semiconductor device illustrated in FIG15 to FIG17. In some embodiments, the spacer material 605 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or other suitable insulating materials.

In some embodiments, the interstitial material 605 may include an energy removable material. The energy removable material may include a material such as a thermally decomposable material, a photon decomposable material, an electron beam decomposable material, or a combination thereof. For example, the energy removable material may include a base material and a decomposable porogenic material that is sacrificed when exposed to an energy source. The base material may include a silyldioxane-based material. The decomposable porogenic material may include a porogenic organic compound that provides porosity to the energy removable base material.

20 and 21 , an etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the spacer material 605 and simultaneously form a gate spacer 205 on the sidewall 200SW of the gate structure 200. The gate spacer 205 may also cover a portion of the upper and lower lightly doped regions 115 of the transistor portions TP of the active regions AA1, AA2, AA3, AA4, and AA5.

In some embodiments, when the gap material 605 includes the energy-removable material, an energy treatment can be performed by applying an energy source after the etching process. The energy source can include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment can be between about 800° C. and about 900° C. When light is used as the energy source, an ultraviolet ray can be used. The energy treatment can remove the decomposable porogen from the energy-removable material to produce voids (pores), while the base material remains in place. The voids (pores) can reduce the dielectric constant of the two gate spacers 205. Therefore, the effect of the gate structure 200 on the parasitic capacitance of adjacent components may be reduced.

22 to 24, the gate structure 200 and the gate spacer 205 may be used as a mask to form a plurality of source regions 117 at the bottom of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, AA5 and a plurality of drain regions 119 and a programmable portion PP of the active regions AA1, AA2, AA3, AA4, AA5 may be formed at the top of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, AA5. The n-type impurity implantation process may be similar to the process shown in FIGS. 15 to 17, and its description will not be repeated here.

For the sake of simplicity, clarity and convenience of description, only one source region 117 and one drain region 119 are described.

In some embodiments, the source region 117 and the drain region 119 may have the second electrical type (i.e., n-type) opposite to the first electrical type. The dopant concentration of the source region 117 and the drain region 119 may be greater than the dopant concentration of the lightly doped region 115. In some embodiments, the dopant concentration of the source region 117 and the drain region 119 may be about 1E19 atoms/cm^3 to about 1E21/cm^3. In some embodiments, from a top view angle, the length L4 of the source region 117 may be less than the length L5 of the drain region 119. In some embodiments, in a top view, the length L3 of the gate structure 200 may be greater than the length L4 of the source region 117 .

FIG. 25 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 26 is a cross-sectional view along line A-A' of FIG. 25 illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure. FIG. 27 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 28 and FIG. 29 are cross-sectional views along line A-A' and line B-B' of FIG. 27 illustrating a partial preparation process of a semiconductor element 1A of an embodiment of the present disclosure.

1 , 25 and 26 , in step S15 , a middle insulating layer 401 may be formed on the plurality of drain regions 119 , and an upper conductive layer 403 may be formed on the middle insulating layer 401 , wherein the plurality of drain regions 119 , the middle insulating layer 401 and the upper conductive layer 403 together configure a plurality of programmable structures 400 .

25 and 26 , the middle insulating layer 401 may extend along the Y direction and may be formed on the drain region 119. The middle insulating layer 401 may be orthogonal to the drain region 119. It should be noted that the middle insulating layer 401 does not overlap with the gate structure 200 in a top view.

In some embodiments, the manufacturing technology of the middle insulating layer 401 can be, for example, silicon oxide. In some embodiments, the manufacturing technology of the middle insulating layer 401 can be, for example, a high-K dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate or a combination thereof.

Illustrative examples of high-k dielectric materials may include, but are not limited to, bismuth oxide, bismuth silicon oxide, bismuth silicon oxynitride, bismuth tantalum oxide, bismuth titanium oxide, bismuth zirconium oxide, bismuth tantalum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, titanium strontium oxide, titanium barium oxide, zirconium barium oxide, silicon tantalum oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, the intermediate insulating layer 401 may be a multi-layer structure including, for example, a layer of silicon oxide and another layer of high-k dielectric material.

25 and 26 , the upper conductive layer 403 may be formed on the middle insulating layer 401. In some embodiments, the upper conductive layer 403 may be made of, for example, (doped) polysilicon, (doped) polycrystalline germanium, (doped) polysilicon germanium or other suitable conductive materials.

In some embodiments, the middle insulating layer 401 and the upper conductive layer 403 can be formed at the same time as the gate structure 200 is covered. In some embodiments, the middle insulating layer 401 and the upper conductive layer 403 can be formed at the same time as the gate structure 200 is formed.

25 and 26, the middle insulating layer 401, the upper conductive layer 403 and the corresponding drain region 119 together configure the programmable structure 400. The programmable structure 400 can be, for example, an anti-fuse. The anti-fuse is non-conductive in the native unprogrammed state and becomes conductive when programmed. For example, the anti-fuse can be composed of a thin dielectric layer sandwiched between two conductors. In this embodiment, the drain region 119 can serve as a lower conductor of the programmable structure 400. The upper conductive layer 403 can serve as an upper conductor of the programmable structure 400. The middle insulating layer 401 may serve as a dielectric layer sandwiched between the lower and upper conductors.

1 and 27 to 29 , in step S17 , a plurality of first contacts 107 may be formed to be electrically connected to a plurality of source regions 117 , and a second contact 109 may be formed to be electrically connected to the upper conductive layer 403 .

27 to 29, an interlayer dielectric layer 105 may be formed to cover the substrate 101, the gate structure 200, and the programmable structure 400. The fabrication technology of the interlayer dielectric layer 105 may include, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a chemical vapor deposition low-k dielectric layer, or a combination thereof. The term "low-k" used in the present disclosure refers to a dielectric material having a dielectric constant less than that of silicon dioxide. In some embodiments, the interlayer dielectric layer 105 may include a self-planarizing material, such as a spin-on glass or a spin-on low-k dielectric material, such as SiLK™. Using a self-planarizing dielectric material can avoid the need to perform a subsequent planarization step. In some embodiments, the interlayer dielectric layer 105 can be formed by a deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps.

27 to 29, a plurality of first contacts 107 and a second contact 109 may be formed in the interlayer dielectric layer 105. For simplicity, clarity and convenience of description, only one first contact 107 is described. The first contact 107 may be formed on and electrically connected to the source region 117. The second contact 109 may be formed on and electrically connected to the upper conductive layer 403. The manufacturing technology of the first contact 107 and the second contact 109 may include, for example, a damascene process.

Typically, in the damascene process, one or more dielectric materials (i.e., interlayer dielectric layer 105) may be deposited and pattern etched to form vertical interconnects, or vias or contacts. Conductive materials, such as copper-containing materials, and other materials, such as barrier materials used to prevent the copper-containing materials from diffusing into the surrounding low-k dielectric, are then damascened into the etched pattern. Any excess copper-containing material and excess barrier material - outside the etched pattern, such as on the substrate area, may then be removed by a planarization process such as chemical mechanical polishing.

In some embodiments, the manufacturing technology of the first contact 107 and the second contact 109 can be, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminum, or a combination thereof.

When programming the programmable structure 400, a high voltage (e.g., +6.0 volts) can be applied to the upper conductive layer 403 through the second contact 109, a selection voltage (e.g., +1.5 volts) can be applied to the gate structure 200, and the first contact 107 can be grounded. The middle insulating layer 401 sandwiched by the upper conductive layer 403 and the drain region 119 can be stressed under the programming voltage. Therefore, the sandwiched portion of the middle insulating layer 401 will be broken, forming a continuous path to connect the upper conductive layer 403 and the drain region 119. In other words, the interlayer portion of the middle insulating layer 401 can be burned off and the programmable structure 400 can be programmed.

It should be noted that all drain regions 119 can be combined with the middle insulating layer 401 and the upper conductive layer 403, respectively, to configure a plurality of programmable structures 400. The plurality of programmable structures 400 can configure a programmable array having a common upper conductor (i.e., the upper conductive layer 403). The selection of the programmable structure 400 to be programmed can be achieved by controlling the gate structure 200 associated with the corresponding drain region 119.

Conventionally, a programmable structure can be electrically coupled to other conductive features through, for example, M0 traces, which requires additional wafer area and a more complex design.

In contrast, the programmable structure 400 integrates the drain region 119 associated with the gate structure 200 into a lower conductor, so the area occupied by the programmable structure 400 can be reduced. Therefore, more area can be used for other complex functional units or more programmable structures 400. Therefore, the performance of the semiconductor device 1A can be improved. In addition, the gate structure 200 associated with the programmable structure 400 can also be used as an isolation transistor to isolate the high-programmed voltage from the adjacent components. Therefore, the damage of the high-programmed voltage to the adjacent components (for example, the leakage current from the high-programmed voltage) can be reduced. Therefore, the reliability of the semiconductor device 1A can be improved.

30 to 33 are cross-sectional views illustrating a partial manufacturing process of a semiconductor device 1B according to another embodiment of the present disclosure.

30 and 31, an intermediate semiconductor element may be prepared using a process similar to that described in FIG. 2 to FIG. 24. A layer of conductive material (not shown) may be conformally formed to cover the intermediate semiconductor element. The conductive material may include, for example, titanium, nickel, platinum, tantalum, or cobalt. Subsequently, a heat treatment may be performed. During the heat treatment, metal atoms of the conductive material layer may chemically react with silicon atoms of the source region 117, the drain region 119, and the gate conductive layer 203 to form a plurality of intermediate layers 111. The plurality of intermediate layers 111 may include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The heat treatment may be a dynamic surface annealing process. After the heat treatment, a cleaning process may be performed to remove unreacted conductive material. The cleaning process may use an etchant such as hydrogen peroxide and SC-1 solution.

In some embodiments, the thickness of the plurality of intermediate layers 111 may be between about 2 nm and about 20 nm.

32 and 33, the manufacturing techniques of the middle insulating layer 401, the upper conductive layer 403, the interlayer dielectric layer 105, the first contact 107 and the second contact 109 can be similar to the process described in FIG. 25 to FIG. 29, and the description thereof will not be repeated here. The plurality of middle layers 111 can reduce the contact resistance of the source region 117, the drain region 119 and the gate conductive layer 203 to reduce the power consumption of the semiconductor device 1B.

Fig. 34 is a top view illustrating a semiconductor device 1C according to another embodiment of the present disclosure. Fig. 35 is a cross-sectional view taken along line A-A' of Fig. 34.

34 and 35 , the first connection pad 405 may be connected to one end of the programmable structure 400 and may be electrically connected to the programmable structure 400. The first connection pad 405 may include a bottom insulating layer 405-1 and a top conductive layer 405-3. The bottom insulating layer 405-1 may be disposed on the isolation layer 103 and connected to the middle insulating layer 401. The top conductive layer 405-3 may be disposed on the bottom insulating layer 405-1 and connected to the upper conductive layer 403. The second contact 109 may be disposed on the top conductive layer 405-3. The programming voltage may be applied to the programmable structure 400 through the second contact 109 and the first connection pad 405. In some embodiments, the width W3 of the first connection pad 405 may be greater than the width W4 of the programmable structure 400.

In some embodiments, the first connection pad 405 can be formed simultaneously with the middle insulating layer 401 and the upper conductive layer 403. In some embodiments, the manufacturing technology of the bottom insulating layer 405-1 can be the same material as the middle insulating layer 401. In some embodiments, the manufacturing technology of the top conductive layer 405-3 can be the same material as the upper conductive layer 403.

FIG. 36 is a flow chart illustrating a method 20 for preparing a semiconductor device 1D according to another embodiment of the present disclosure. FIG. 37 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 38 is a cross-sectional view along line BB' of FIG. 37 illustrating a partial preparation process of a semiconductor device 1D according to another embodiment of the present disclosure.

36 to 38 , in step S21, a substrate 101 may be provided, an isolation layer 103 may be formed in the substrate 101 to define a plurality of active areas AA1, AA2, AA3, AA4, AA5, a plurality of well areas 113 may be formed in the plurality of active areas AA1, AA2, AA3, AA4, AA5, and a plurality of gate trenches 300TR may be formed in the substrate 101.

Referring to FIG. 37 and FIG. 38 , the substrate 101, the isolation layer 103, the active regions AA1, AA2, AA3, AA4, AA5 and the well region 113 can be formed by a process similar to that described in FIG. 2 to FIG. 11 , and the description thereof will not be repeated here. For the sake of simplicity, clarity and convenience of description, only one gate trench 300TR is described. In a top view, the gate trench 300TR can extend along the X direction and can divide the transistor portion TP of the active region AA1 into an upper portion and a lower portion.

Fig. 39 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. Fig. 40 is a cross-sectional view along line BB' of Fig. 39 illustrating a partial preparation process of a semiconductor device 1D according to another embodiment of the present disclosure.

36 , 39 and 40 , in step S23 , a plurality of buried gate structures 300 may be formed in a plurality of gate trenches 300TR.

For the sake of brevity, clarity and convenience of description, only one buried gate structure 300 is described.

39 and 40 , the buried gate structure 300 may include a buried gate insulating layer 301, a buried gate conductive layer 303, and a buried gate capping layer 305. The buried gate insulating layer 301 may be conformally formed in the gate trench 300TR and may have a U-shaped cross-sectional profile. In some embodiments, the buried gate insulating layer 301 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material may include tantalum oxide, tantalum oxide silicon, tantalum oxide, zirconia, zirconia silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead tantalum oxide, lead zinc niobate, or a combination thereof.

The buried gate conductive layer 303 may be formed on the buried gate insulating layer 301. In some embodiments, the buried gate conductive layer 303 may include, for example, one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). The buried gate capping layer 305 may be formed on the buried gate insulating layer 301 and the buried gate conductive layer 303. In some embodiments, the buried gate capping layer 305 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The top surface of the buried gate capping layer 305 and the top surface of the isolation layer 103 may be substantially coplanar.

Fig. 41 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. Fig. 42 is a cross-sectional view along line BB' of Fig. 41 illustrating a partial preparation process of a semiconductor device 1D according to another embodiment of the present disclosure.

36 , 41 and 42 , in step S25 , a plurality of source regions 117 and a plurality of drain regions 119 may be formed in a plurality of well regions 113 .

41 and 42, an n-type impurity implantation process may be performed using the buried gate structure 300 as a mask to form a plurality of source regions 117 in the lower portion of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, AA5, a plurality of drain regions 119 in the upper portion of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, AA5, and a programmable portion PP of the active regions AA1, AA2, AA3, AA4, AA5. The n-type impurity implantation process may be similar to the process shown in FIGS. 15 to 17, and its description will not be repeated here.

For the sake of simplicity, clarity and convenience of description, only one source region 117 and one drain region 119 are described.

In some embodiments, the source region 117 and the drain region 119 may have the second electrical type (i.e., n-type). The dopant concentration of the source region 117 and the drain region 119 may be about 1E19 atoms/cm^3 to about 1E21 atoms/cm^3. In some embodiments, from a top view, the length L4 of the source region 117 may be less than the length L5 of the drain region 119.

Fig. 43 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. Fig. 44 to Fig. 47 are cross-sectional views along lines AA', BB' and CC' of Fig. 43, illustrating a partial preparation process of a semiconductor element 1D of another embodiment of the present disclosure.

36 and 43 to 46 , in step S27 , a middle insulating layer 401 may be formed on a plurality of active regions AA1, AA2, AA3, AA4, AA5, and an upper conductive layer 403 may be formed on the middle insulating layer 401 , wherein the middle insulating layer 401 , the upper conductive layer 403 , and a plurality of drain regions 119 together configure a plurality of programmable structures 400 .

43 to 46 , the middle insulating layer 401 may extend along the Y direction and may be formed on the drain region 119. The middle insulating layer 401 may be orthogonal to the drain region 119. It should be noted that the middle insulating layer 401 does not overlap the buried gate structure 300 in a top view.

In some embodiments, the manufacturing technology of the middle insulating layer 401 can be, for example, silicon oxide. In some embodiments, the manufacturing technology of the middle insulating layer 401 can be, for example, a high-k dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate or a combination thereof.

Illustrative examples of high-k dielectric materials may include, but are not limited to, bismuth oxide, bismuth silicon oxide, bismuth silicon oxynitride, bismuth tantalum oxide, bismuth titanium oxide, bismuth zirconium oxide, bismuth tantalum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, titanium strontium oxide, titanium barium oxide, zirconium barium oxide, silicon tantalum oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, the intermediate insulating layer 401 may be a multi-layer structure including, for example, a layer of silicon oxide and another layer of high-k dielectric material.

43 to 46 , an upper conductive layer 403 may be formed on the middle insulating layer 401. In some embodiments, the upper conductive layer 403 may be made of, for example, (doped) polysilicon, (doped) polygermanium, (doped) polysilicon germanium or other suitable conductive materials.

43 to 46, the middle insulating layer 401, the upper conductive layer 403 and the corresponding drain region 119 together configure the programmable structure 400. The programmable structure 400 can be, for example, an anti-fuse. In this embodiment, the drain region 119 can serve as the lower conductor of the programmable structure 400. The upper conductive layer 403 can serve as the upper conductor of the programmable structure 400. The middle insulating layer 401 can serve as a dielectric layer sandwiched between the lower and upper conductors.

36 and 47 , in step S29 , two spacers 407 may be formed on the side walls 401SW and 403SW of the middle insulating layer 401 and the upper conductive layer 403 .

Referring to FIG. 47 , a layer of spacer material (not shown) may be conformally formed to cover the middle semiconductor element shown in FIG. 46 . In some embodiments, the spacer material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable insulating materials. In some embodiments, the spacer material may include an energy removable material. The energy removable material may include a material such as a thermally decomposable material, a photon decomposable material, an electron beam decomposable material, or a combination thereof. For example, the energy removable material may include a base material and a decomposable porogenic material that is sacrificed when exposed to an energy source. The base material may include a silyldioxane-based material. The decomposable porogenic material may include a porogenic organic compound that provides porosity to the energy removable base material.

47 , an etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the spacer material and simultaneously form two spacers 407 on the sidewalls 401SW, 403SW of the middle insulating layer 401 and the upper conductive layer 403. In some embodiments, when the spacer material 605 includes the energy-removable material, an energy treatment may be performed by applying an energy source after the etching process. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment may be between about 800° C. and about 900° C. When light is used as the energy source, an ultraviolet ray may be used. The energy treatment may remove the decomposable porogen from the energy-removable material to produce voids (pores), while the base material remains in place. The voids (voids) may reduce the dielectric constant of the two gate spacers 407. Therefore, the effect of the programmable structure 400 on the parasitic capacitance of the adjacent devices may be reduced.

Fig. 48 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. Fig. 49 to Fig. 51 are cross-sectional views along lines AA', BB' and CC' of Fig. 48, illustrating a partial preparation process of a semiconductor element 1D of another embodiment of the present disclosure.

36 and 48 to 51 , in step S31 , a plurality of first contacts 107 may be formed to be electrically connected to a plurality of source regions 117 , and a second contact 109 may be formed to be electrically connected to the upper conductive layer 403 .

48 to 51, the interlayer dielectric layer 105, the first contact 107 and the second contact 109 may be formed by a process similar to that shown in FIGS. 27 to 29, and the description thereof will not be repeated here.

When programming the programmable structure 400, a high voltage (e.g., +6.0 volts) can be applied to the upper conductive layer 403 through the second contact 109, a selected voltage (e.g., +1.5 volts) can be applied to the buried gate structure 300, and the first contact 107 can be grounded, and the middle insulating layer 401 sandwiched by the upper conductive layer 403 and the drain region 119 can be stressed under the programming voltage. Therefore, the sandwiched portion of the middle insulating layer 401 will be broken, forming a continuous path to connect the upper conductive layer 403 and the drain region 119. In other words, the interlayer portion of the middle insulating layer 401 can be burned off, and the programmable structure 400 is programmed.

It should be noted that all drain regions 119 can be combined with the middle insulating layer 401 and the upper conductive layer 403, respectively, to configure a plurality of programmable structures 400. The plurality of programmable structures 400 can configure a programmable array having a common upper conductor (i.e., the upper conductive layer 403). The selection of the programmable structure 400 to be programmed can be achieved by controlling the buried gate structure 300 associated with the corresponding drain region 119.

The programmable structure 400 integrates the drain region 119 associated with the buried gate structure 300 into a lower conductor, so the area occupied by the programmable structure 400 can be reduced. Therefore, more area can be used for other complex functional units or more programmable structures 400. Therefore, the performance of the semiconductor device 1D can be improved. In addition, the buried gate structure 300 associated with the programmable structure 400 can also be used as an isolation transistor to isolate the high-programmed voltage from the adjacent components. Therefore, the damage of the high-programmed voltage to the adjacent components (for example, the leakage current from the high-programmed voltage) can be reduced. Therefore, the reliability of the semiconductor device 1D can be improved.

52 and 53 are cross-sectional views illustrating a semiconductor device 1E according to another embodiment of the present disclosure.

52 and 53, a plurality of intermediate layers 111 may be disposed between the source region 117 and the first contact 107, between the drain region 119 and the intermediate insulating layer 401, and between the drain region 119 and the interlayer dielectric layer 105. The plurality of intermediate layers 111 may include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. In some embodiments, the thickness of the plurality of intermediate layers 111 may be between about 2 nanometers and about 20 nanometers.

One aspect of the present disclosure provides a semiconductor device, including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure disposed on the transistor portion; a drain region disposed in the programmable portion and the transistor portion and adjacent to the gate structure; a source region disposed in the transistor portion, adjacent to the gate structure and opposite to the drain region, with the gate structure interposed therebetween; an intermediate insulating layer disposed on the programmable portion; and an upper conductive layer disposed on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Another aspect of the present disclosure provides a semiconductor device, comprising a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure disposed in the transistor portion; a drain region disposed in the programmable The programmable design part and the transistor part are adjacent to the buried gate structure; a source region is arranged in the transistor part, adjacent to the buried gate structure and opposite to the drain region, and the buried gate structure is located between the two; an intermediate insulating layer is arranged on the programmable design part; an upper conductive layer is arranged on the intermediate insulating layer. The drain region, the intermediate insulating layer and the upper conductive layer of the programmable design part jointly configure a programmable structure.

Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; forming a gate structure on the transistor portion; forming a drain region in the programmable portion and the transistor portion, adjacent to the gate structure; forming a source region in the transistor portion, adjacent to the gate structure and opposite to the drain region; forming an intermediate insulating layer on the programmable portion; and forming an upper conductive layer on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; forming a buried gate structure in the transistor portion; forming a drain region in the programmable portion and the transistor portion, adjacent to the buried gate structure; forming a source region in the transistor portion, adjacent to the buried gate structure and opposite to the drain region; forming an intermediate insulating layer on the programmable portion; and forming an upper conductive layer on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part together configure a programmable structure.

Due to the design of the semiconductor element disclosed in the present invention, the programmable structure integrates the drain region associated with the gate structure into the lower conductor of the programmable structure, so the area occupied by the programmable structure can be reduced. Therefore, more area can be used for other complex functional units or more programmable structures. Therefore, the performance of the semiconductor element can be improved. In addition, the gate structure associated with the programmable structure can also be used as an isolation transistor to isolate the high-programmed voltage from adjacent components. Therefore, the damage of the high-programmed voltage to the adjacent components (for example, the leakage current from the high-programmed voltage) can be reduced. Therefore, the reliability of the semiconductor element can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

1A: semiconductor element 1B: semiconductor element 1C: semiconductor element 1D: semiconductor element 1E: semiconductor element 10: preparation method 20: preparation method 101: substrate 101TR: first trench 103: isolation layer 105: interlayer dielectric layer 107: first contact 109: second contact 111: intermediate layer 113: well region 115: lightly doped region 117: source region 119: drain region 200: gate structure 200SW: sidewall 201: gate insulating layer 203: Gate conductive layer 205: Gate spacer 300: Buried gate structure 300TR: Gate trench 301: Buried gate insulating layer 303: Buried gate conductive layer 305: Buried gate capping layer 400: Programmable structure 401: Middle insulating layer 401SW: Sidewall 403: Upper conductive layer 403SW: Sidewall 405: First connection pad 405-1: Bottom insulating layer 405-3: Top conductive layer 407: spacer 601: pad oxide layer 603: pad nitride layer 605: spacer material 607: first mask layer A-A': line AA1: active area AA2: active area AA3: active area AA4: active area AA5: active area B-B': line C-C': line L1: length L2: length L3: length L4: length L5: length PP: programmable part S11: step S13: step S15: step S17: step S21: step S23: step S25: step S27: step S29: step S31: Step TP: Transistor part W1: Width W2: Width W3: Width W4: Width X: Direction Y: Direction Z: Direction

When referring to the embodiments and the scope of the patent application together with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow chart illustrating a method for preparing a semiconductor element of an embodiment of the present disclosure. FIG. 2 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 3 to FIG. 6 are cross-sectional views along line A-A' and line B-B' of FIG. 2, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 7 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 8 to FIG. 11 are cross-sectional views along line A-A' and line B-B' of FIG. 7, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 12 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 13 and FIG. 14 are cross-sectional views along line A-A’ and line B-B’ of FIG. 12, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 15 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 16 to FIG. 21 are cross-sectional views along line A-A’ and line B-B’ of FIG. 15, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 22 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 23 and FIG. 24 are cross-sectional views along line A-A’ and line B-B’ of FIG. 22, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 25 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 26 is a cross-sectional view along line A-A’ of FIG. 25, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 27 is a top view illustrating an intermediate semiconductor element of an embodiment of the present disclosure. FIG. 28 and FIG. 29 are cross-sectional views along line A-A’ and line B-B’ of FIG. 27, illustrating a partial preparation process of a semiconductor element of an embodiment of the present disclosure. FIG. 30 to FIG. 33 are cross-sectional views illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 34 is a top view illustrating a semiconductor element of another embodiment of the present disclosure. FIG. 35 is a cross-sectional view along line A-A’ of FIG. 34. FIG. 36 is a flow chart illustrating a method for preparing a semiconductor element of another embodiment of the present disclosure. FIG. 37 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. FIG. 38 is a cross-sectional view along line BB' of FIG. 37 illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 39 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. FIG. 40 is a cross-sectional view along line BB' of FIG. 39 illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 41 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. FIG. 42 is a cross-sectional view along line BB' of FIG. 41 illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 43 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. FIG. 44 to FIG. 47 are cross-sectional views along lines A-A', B-B', and CC' of FIG. 43, illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 48 is a top view illustrating an intermediate semiconductor element of another embodiment of the present disclosure. FIG. 49 to FIG. 51 are cross-sectional views along lines A-A', B-B', and CC' of FIG. 48, illustrating a partial preparation process of a semiconductor element of another embodiment of the present disclosure. FIG. 52 and FIG. 53 are cross-sectional views illustrating a semiconductor element of another embodiment of the present disclosure.

1A: Semiconductor components

101: Base

101TR: First groove

103: Isolation layer

105: Interlayer dielectric layer

107: First contact

113: Well area

115: Lightly mixed area

117: Source region

119: Drain area

200: Gate structure

201: Gate insulation layer

203: Gate conductive layer

205: Gate gap

AA1: Active area

B-B': line

TP: Transistor part

Z: Direction

Claims (26)

A semiconductor element comprises: a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region comprises a transistor portion and a programmable portion extending from the transistor portion; a gate structure disposed on the transistor portion; a drain region disposed in the programmable portion and the transistor portion and adjacent to the gate structure; a source region disposed in the transistor portion, adjacent to the gate structure and opposite to the drain region, the gate structure being between the two; an intermediate insulating layer disposed on the programmable portion; and An upper conductive layer is disposed on the middle insulating layer; wherein the drain region, the middle insulating layer and the upper conductive layer in the programmable part together configure a programmable structure. The semiconductor device as described in claim 1 further includes a first contact disposed on the source region and electrically connected to the source region. The semiconductor device as described in claim 2 further includes a second contact disposed on the upper conductive layer and electrically connected to the upper conductive layer. A semiconductor device as described in claim 3, wherein the gate structure includes: a gate insulating layer disposed on the transistor portion and between the source region and the drain region; and a gate conductive layer disposed on the gate insulating layer. The semiconductor device as described in claim 4 further includes two gate spacers, which are respectively arranged on the source region and the drain region and cover the side walls of the gate structure. The semiconductor device as described in claim 5 further includes a lightly doped region disposed in the substrate, below one of the two gate spacers, and adjacent to the drain region. A semiconductor device as described in claim 6, wherein the drain region and the lightly doped region comprise the same electrical type. The semiconductor device as described in claim 7 further includes a well region disposed in the transistor portion and the programmable portion; wherein the lightly doped region, the source region and the drain region are disposed in the well region. A semiconductor device as described in claim 8, wherein the well region and the drain region comprise different electrical types. The semiconductor device as described in claim 9 further includes an intermediate layer disposed between the first contact and the source region; wherein the intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device as described in claim 9 further includes an intermediate layer disposed on the drain region; wherein the intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device as described in claim 9 further includes an intermediate layer disposed between the intermediate insulating layer and the drain region; wherein the intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device as described in claim 9 further includes an intermediate layer disposed on the gate conductive layer; wherein the intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. A semiconductor device as described in claim 1, wherein a length of the source region is smaller than a length of the drain region when viewed from a top view angle. A semiconductor device as described in claim 1, wherein the programmable portion extends along a first direction, and the programmable structure extends along a second direction perpendicular to the first direction. A semiconductor device as described in claim 2, wherein the gate structure extends along the first direction. A semiconductor device as described in claim 1, wherein a length of the gate structure is greater than or equal to a length of the source region. A semiconductor device as described in claim 1, wherein a width of the programmable portion is smaller than a width of the transistor portion. The semiconductor device as described in claim 1 further includes a first connection pad connected to one end of the programmable structure; wherein the first connection pad includes: a bottom insulating layer extending from the middle insulating layer and disposed on the substrate; and a top conductive layer extending from the upper conductive layer disposed on the bottom insulating layer. A semiconductor device as described in claim 19, wherein a width of the first connection pad is greater than a width of the programmable structure. A semiconductor element comprises: a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region comprises a transistor portion and a programmable portion extending from the transistor portion; an embedded gate structure disposed in the transistor portion; a drain region disposed in the programmable portion and the transistor portion and adjacent to the embedded gate structure; a source region disposed in the transistor portion, adjacent to the embedded gate structure and opposite to the drain region, the embedded gate structure being between the two; an intermediate insulating layer disposed on the programmable portion; and An upper conductive layer is disposed on the middle insulating layer; wherein the drain region, the middle insulating layer and the upper conductive layer in the programmable part together configure a programmable structure. A semiconductor device as described in claim 21, wherein a length of the source region is smaller than a length of the drain region when viewed from a top-down angle. A semiconductor device as described in claim 22, wherein the programmable portion extends along a first direction and the programmable structure extends along a second direction perpendicular to the first direction. A semiconductor device as described in claim 21, wherein a width of the programmable portion is smaller than a width of the transistor portion. A semiconductor element as described in claim 21, wherein the buried gate structure comprises: a buried gate insulating layer disposed inwardly in the transistor portion and having a U-shaped cross-sectional profile; a buried gate conductive layer disposed on the buried gate insulating layer; and a buried gate capping layer disposed on the buried gate insulating layer and the buried gate conductive layer. The semiconductor device as described in claim 21 further includes two spacers disposed on the side walls of the middle insulating layer and the upper conductive layer.

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