TW202341490A - Semiconductor device with programmable structure - Google Patents

Abstract

The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Description

Semiconductor components with programmable structures

This application claims priority to U.S. Patent Application Nos. 17/678,212 and 17/678,407 (that is, the priority date is "February 23, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device with a programmable structure.

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor components are continuously shrinking in size to meet growing demands for computing power. However, various problems arise during the downsizing process, and such problems are increasing. Therefore, challenges remain in achieving improvements in quality, throughput, performance and reliability, and in reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and extends from the transistor portion a programmable part; a gate structure disposed on the transistor part; a drain region disposed in the programmable part and the transistor part and adjacent to the gate structure; a source A pole region is disposed in the transistor part, adjacent to the gate structure and opposite to the drain region, with the gate structure being between the two; an intermediate insulating layer is disposed on the programmable part; and an upper conductive layer disposed on the middle insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a semiconductor device including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and extends from the transistor portion a programmable design part; a buried gate structure, disposed in the transistor part; a drain region, disposed in the programmable design part and the transistor part, and connected with the buried gate adjacent to the gate structure; a source region is disposed in the transistor portion, adjacent to the buried gate structure, and opposite to the drain region, with the buried gate structure being between the two between; an intermediate insulating layer, arranged on the programmable part; an upper conductive layer, arranged on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a portion formed from the transistor. a partially extended programmable portion; forming a gate structure on the transistor portion; forming a drain region in the programmable portion and the transistor portion and adjacent to the gate structure; A source region is formed in the transistor part, adjacent to the gate structure and opposite to the drain region; an intermediate insulating layer is formed on the programmable part; and an upper part is formed on the intermediate insulating layer conductive layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a transistor portion formed from the transistor; A programmable design part extends from the crystal part; a buried gate structure is formed in the transistor part; a drain region is formed in the programmable design part and the transistor part, and is connected with the buried gate structure. The gate structure is adjacent; a source region is formed in the transistor portion, adjacent to the buried gate structure, and opposite to the drain region; an intermediate insulating layer is formed on the programmable portion; and forming an upper conductive layer on the middle insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Due to the design of the semiconductor device of the present disclosure, the programmable structure integrates the drain region associated with the gate structure as the lower conductor of the programmable structure, thereby reducing the area occupied by the programmable structure. Therefore, more area is available for other complex functional units or more programmable design structures. Therefore, the performance of the semiconductor element can be improved. In addition, the gate structure associated with the programmable structure can also be used as an isolation transistor to isolate high-programmable voltages from adjacent components. Therefore, damage to adjacent components caused by high-program design voltages (eg, leakage currents originating from high-program design voltages) can be reduced. Therefore, the reliability of the semiconductor element can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are examples only and are not meant to be limiting. For example, in the following description, the formation of the first feature on the second feature may include an embodiment in which the first and second features are formed in direct contact, or may include an embodiment in which additional features may be formed between the first and second features. embodiment so that the first and second features may not be in direct contact. Additionally, reference numbers and/or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not by itself determine the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "under", "below", "below", "on", "above", etc., for ease of description, may be used herein to describe one element or feature relative to another as shown in the figure. The relationship between (some) elements or characteristics. Spatially relative terms are intended to encompass various orientations of elements in use or operation, as well as the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when an element or layer is said to be "connected" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer, or intervening elements or layers may be present .

It will be understood that, although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are only used to distinguish one element from another. Thus, for example, a first element, element or section discussed below could be termed a second element, element or section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms such as "same", "equal", "planar" or "coplanar" are used herein when referring to orientation, arrangement, location, shape, size, quantity or other measures, and not necessarily means exactly the same orientation, layout, position, shape, size, quantity or other measures, but means almost the same orientation, layout, position within acceptable variations that may occur, for example due to the manufacturing process , shape, size, quantity or other measures. The term "substantially" may be used here to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or they may be the same, equal, or planar within acceptable variations, such as due to changes that may occur due to the manufacturing process.

In this disclosure, semiconductor components generally refer to components that utilize semiconductor characteristics to function. Optoelectronic components, light-emitting display components, semiconductor circuits and electronic components are all included in the category of semiconductor components.

It should be noted that in the description of the present disclosure, upper (or upper) corresponds to the direction of the arrow of direction Z, and lower (or lower) corresponds to the opposite direction of the arrow of direction Z.

FIG. 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 2 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 3 to 6 are cross-sectional views along line AA' and line BB' of FIG. 2 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure. FIG. 7 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 8 and 9 are cross-sectional views along line AA' and line BB' of FIG. 7 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure.

Referring to FIGS. 1 to 9 , in step S11 , a substrate 101 may be provided, and an isolation layer 103 may be formed in the substrate 101 to define a plurality of active areas AA1 , AA2 , AA3 , AA4 , AA5 of the substrate 101 .

Referring to FIGS. 2 to 4 , the substrate 101 may include a silicon-containing material. Illustrative examples of silicon-containing materials suitable for substrate 101 may include, but are not limited to, silicon, silicon germanium, carbon doped silicon germanium, silicon germanium carbide, carbon doped silicon, silicon carbide, and multilayers thereof. Although silicon is the main semiconductor material used in wafer preparation, in some embodiments, alternative semiconductor materials can be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, Cadmium telluride, zinc selenide, germanium tin, etc.

Referring to FIGS. 2 to 4 , a series of deposition processes may be performed to deposit a pad oxide layer 601 and a pad nitride layer 603 on the substrate 101 . A photolithography process may be performed to define the arrangement of the isolation layer 103 by forming a first mask layer 607 on the pad nitride layer 603 .

Referring to FIGS. 5 and 6 , after the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a lithography process that penetrates along the pad nitride layer 603 and the pad oxide layer 601 and extends to the substrate 101 First trench 101TR.

Referring to FIGS. 7 to 9 , an insulating material may be deposited into the first trench 101TR, and then a planarization process, such as chemical mechanical polishing, may be performed to remove excess filling material until the top surface of the substrate 101 is exposed. , to form the isolation layer 103. The top surface of the isolation layer 103 and the top surface of the substrate 101 may be substantially coplanar. The insulating material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate. It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen and nitrogen, in which the proportion of nitrogen is greater than the proportion of oxygen.

Referring to FIGS. 7 to 9 , the portions of the substrate 101 surrounded by the isolation layer 103 may be referred to as active areas AA1 , AA2 , AA3 , AA4 , and AA5 . In some embodiments, the active areas AA1, AA2, AA3, AA4, and AA5 may be arranged along the Y direction from a top view. For simplicity, clarity and convenience of description, only one active area AA1 is described. The active area AA1 may include a transistor part TP and a programmable part PP.

In some embodiments, from a top view, the transistor portion TP may have a rectangular outline, and the transistor portion TP may extend along the X direction. The width W1 of the transistor part TP is greater than the width W2 of the programmable part PP.

In some embodiments, from a top view, the upper side of the programmable part PP and the upper side of the transistor part TP are aligned with each other, but are not limited thereto.

In some embodiments, from a top view, the length L1 of the transistor portion TP is greater than or equal to the length L2 of the programmable portion PP.

10 and 11 are cross-sectional views along line AA' and line BB' of FIG. 7 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure. FIG. 12 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 13 and 14 are cross-sectional views along line AA' and line BB' of FIG. 12 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure.

FIG. 15 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 16 to 21 are cross-sectional views along line AA' and line BB' of FIG. 15 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure. FIG. 22 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 23 and 24 are cross-sectional views along lines AA′ and BB′ of FIG. 22 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure.

Referring to Figure 1 and Figures 10 to 24, in step S13, a plurality of well areas 113 can be formed in a plurality of active areas AA1, AA2, AA3, AA4, and AA5. A plurality of gate structures 200 are formed on AA5, and a plurality of source regions 117 and a plurality of drain regions 119 are formed in a plurality of well regions 113.

Referring to FIGS. 10 and 11 , in some embodiments, a p-type impurity implantation process may be performed to form well regions 113 in the active regions AA1 , AA2 , AA3 , AA4 , and AA5 respectively and accordingly. This p-type impurity implantation process can add impurities to an intrinsic semiconductor, thus creating defects in valence electrons. In a silicon-containing substrate, examples of p-type dopants, ie, impurities, include, but are not limited to, boron, aluminum, gallium, or indium. In some embodiments, well region 113 may be of a first electrical type (ie, p-type).

For simplicity, clarity and convenience of description, only one gate structure 200 is described.

Referring to FIGS. 12 to 14 , the gate structure 200 may be formed on the transistor portion TP of the active region AA1. It should be noted that, in a top view, the gate structure 200 does not overlap with the programmable portion PP of the active area AA1. In some embodiments, from a top view, the length L3 of the gate structure 200 may be greater than or equal to the length L1 of the transistor portion TP of the active region AA1.

In some embodiments, from a top view, the gate structure 200 may extend along the X direction and divide the transistor portion TP of the active area AA1 into an upper part and a lower part. In this embodiment, the programmable part PP may extend from the upper part of the transistor part TP.

Referring to FIGS. 12 to 14 , the gate structure 200 may include a gate insulating layer 201 and a gate conductive layer 203 . The gate insulation layer 201 may be formed on the transistor portion TP of the active region AA1. In some embodiments, the thickness of gate insulating layer 201 may be about 50 Angstroms or less.

In some embodiments, the manufacturing technology of the gate insulating layer 201 may be, for example, silicon oxide. In some embodiments, the manufacturing technology of the gate insulating layer 201 may be, for example, a high-k dielectric material such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal nitride, etc. Metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate or combinations thereof, etc.

Illustrative examples of high-k dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, Titanium, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, silicon aluminum oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, gate insulating layer 201 may be a multi-layer structure including, for example, one layer of silicon oxide and another layer of high-k dielectric material.

Referring to FIGS. 12 to 14 , a gate conductive layer 203 may be formed on the gate insulating layer 201 . In some embodiments, the manufacturing technology of the gate conductive layer 203 may be, for example, (doped) polycrystalline silicon, (doped) polycrystalline germanium, (doped) polycrystalline silicon germanium or other suitable conductive materials.

Referring to FIGS. 15 to 17 , the gate structure 200 can be used as a mask to perform an n-type impurity implantation process, so that the upper portion and the transistor portion TP of the active regions AA1 , AA2 , AA3 , AA4 , and AA5 A plurality of lightly doped regions 115 are formed in the lower part. This n-type impurity implantation process can add impurities that contribute free electrons to intrinsic semiconductors. In a silicon-containing substrate, examples of n-type dopants, ie, impurities, include, but are not limited to, antimony, arsenic, or phosphorus. In some embodiments, the lightly doped region 115 may have a second electrical type opposite to the first electrical type (ie, n-type).

Referring to FIGS. 18 and 19 , a layer of gap material 605 may be conformally formed to cover the intermediate semiconductor element illustrated in FIGS. 15 to 17 . In some embodiments, gap material 605 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable insulating material.

In some embodiments, gap material 605 may include an energy-removable material. The energy-removable material may include a material such as a thermally decomposable material, a photon decomposable material, an electron beam decomposable material, or a combination thereof. For example, the energy-removable material may include a base material and a decomposable porogen material that is sacrificed upon exposure to an energy source. The base material may include a silyldioxane-based material. The decomposable porogenic material may include a porogenic organic compound that provides porosity to the energy-removable base material.

Referring to FIGS. 20 and 21 , an etching process, such as an anisotropic dry etching process, may be performed to remove portions of the gap material 605 and simultaneously form the gate spacers 205 on the sidewalls 200SW of the gate structure 200 . The gate spacer 205 may also cover the upper and lower lightly doped regions 115 of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, AA5.

In some embodiments, when gap material 605 includes the energy-removable material, an energy process may be performed by applying an energy source after the etching process. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment may be between about 800°C and about 900°C. When light is used as the energy source, an ultraviolet ray can be used. The energy treatment can remove the decomposable porogenic material from the energy-removable material to create voids (pores), while the base material remains in place. The voids (pores) can reduce the dielectric constant of the two gate spacers 205 . Therefore, the influence of the gate structure 200 on the parasitic capacitance of adjacent components may be reduced.

Referring to FIGS. 22 to 24 , the gate structure 200 and the gate spacer 205 can be used as masks to form a plurality of source regions at the lower portion of the transistor portion TP of the active regions AA1, AA2, AA3, AA4, and AA5. 117 and a plurality of drain regions 119 and a programmable part PP of the active regions AA1, AA2, AA3, AA4, AA5 are formed on the upper part of the transistor part TP of the active regions AA1, AA2, AA3, AA4, AA5. The n-type impurity implantation process may be similar to the process shown in FIGS. 15 to 17 , and its description will not be repeated here.

For simplicity, clarity and convenience of description, only one source region 117 and one drain region 119 are described.

In some embodiments, source region 117 and drain region 119 may have the second electrical type opposite to the first electrical type (ie, n-type). The dopant concentration of the source region 117 and the drain region 119 may be greater than the dopant concentration of the lightly doped region 115 . In some embodiments, the dopant concentration of the source region 117 and the drain region 119 may be about 1E19 atoms/cm^3 to about 1E21/cm^3. In some embodiments, from a top view, the length L4 of the source region 117 may be smaller than the length L5 of the drain region 119 . In some embodiments, from a top view, the length L3 of the gate structure 200 may be greater than the length L4 of the source region 117 .

FIG. 25 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 26 is a cross-sectional view along line A-A' of FIG. 25 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure. FIG. 27 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 28 and 29 are cross-sectional views along lines A-A' and B-B' of FIG. 27 , illustrating part of the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure.

Referring to Figures 1, 25 and 26, in step S15, an intermediate insulating layer 401 can be formed on the plurality of drain regions 119, and an upper conductive layer 403 can be formed on the intermediate insulating layer 401, wherein the plurality of drain regions 119, The middle insulating layer 401 and the upper conductive layer 403 jointly configure a plurality of programmable structures 400.

Referring to FIGS. 25 and 26 , the intermediate insulating layer 401 may extend along the Y direction and may be formed on the drain region 119 . The intermediate insulating layer 401 may be orthogonal to the drain region 119 . It should be noted that the middle insulating layer 401 does not overlap the gate structure 200 in a top view.

In some embodiments, the manufacturing technology of the middle insulating layer 401 may be, for example, silicon oxide. In some embodiments, the manufacturing technology of the intermediate insulating layer 401 may be, for example, a high-K dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal nitride, etc. Metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate or combinations thereof.

Illustrative examples of high-k dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide. Titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, zirconium barium oxide, lanthanum silicon oxide, silicon aluminum oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, the intermediate insulating layer 401 may be a multi-layer structure including, for example, one layer of silicon oxide and another layer of high-k dielectric material.

Referring to FIGS. 25 and 26 , the upper conductive layer 403 may be formed on the middle insulating layer 401 . In some embodiments, the manufacturing technology of the upper conductive layer 403 may be, for example, (doped) polycrystalline silicon, (doped) polycrystalline germanium, (doped) polycrystalline silicon germanium or other suitable conductive materials.

In some embodiments, the middle insulating layer 401 and the upper conductive layer 403 may be formed while covering the gate structure 200 . In some embodiments, the middle insulating layer 401 and the upper conductive layer 403 may be formed simultaneously with the gate structure 200 .

Referring to FIGS. 25 and 26 , the middle insulating layer 401 , the upper conductive layer 403 and the corresponding drain region 119 jointly configure the programmable structure 400 . Programmable structure 400 may be, for example, an antifuse. Antifuses are non-conductive in their native unprogrammed state and become conductive when programmed. For example, the antifuse may consist of a thin dielectric layer sandwiched between two conductors. In this embodiment, the drain region 119 can be used as a lower conductor of the programmable structure 400 . The upper conductive layer 403 can serve as an upper conductor of the programmable structure 400 . The intermediate insulating layer 401 may serve as a dielectric layer sandwiched between the lower and upper conductors.

Referring to FIG. 1 and FIGS. 27 to 29 , in step S17 , a plurality of first contacts 107 may be formed to be electrically connected to a plurality of source regions 117 , and second contacts 109 may be formed to be electrically connected to the upper conductive layer 403 .

Referring to FIGS. 27 to 29 , an interlayer dielectric layer 105 may be formed to cover the substrate 101 , the gate structure 200 and the programmable structure 400 . The fabrication technology of the interlayer dielectric layer 105 may include, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a Chemical vapor deposition of low-k dielectric layers or combinations thereof. The term "low-k" as used in this disclosure refers to a dielectric material with a lower dielectric constant than silicon dioxide. In some embodiments, interlayer dielectric layer 105 may include a self-planarizing material, such as a spun glass or a spun low-k dielectric material, such as SiLK™. Using a self-planarizing dielectric material can avoid the need to perform a subsequent planarization step. In some embodiments, the manufacturing technique of the interlayer dielectric layer 105 may include a deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent process steps.

Referring to FIGS. 27 to 29 , a plurality of first contacts 107 and second contacts 109 may be formed in the interlayer dielectric layer 105 . For simplicity, clarity and convenience of description, only one first contact point 107 is described. The first contact 107 may be formed on the source region 117 and be electrically connected to the source region 117 . The second contact 109 may be formed on and electrically connected to the upper conductive layer 403 . The manufacturing technology of the first contact 107 and the second contact 109 may include, for example, a damascene process.

Typically, during this damascene process, one or more dielectric materials (ie, interlayer dielectric layer 105) may be deposited and patterned to form vertical interconnects, also known as vias or contacts. Conductive materials, such as copper-containing materials, and other materials, such as barrier materials used to prevent copper-containing materials from diffusing into the surrounding low-k dielectric, are then embedded into the etched pattern. Any excess copper-containing material and excess barrier material - outside the etched pattern, such as on the substrate area, can then be removed by a planarization process such as chemical mechanical polishing.

In some embodiments, the manufacturing technology of the first contact 107 and the second contact 109 may be, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, Metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, titanium nitride), transition metal aluminides, or combinations thereof.

When programming the programmable structure 400, a high voltage (for example, +6.0 volts) can be applied to the upper conductive layer 403 through the second contact 109, and a selection voltage (for example, +1.5 volts) can be applied to the gate structure 200. ), and the first contact 107 can be grounded, and the middle insulating layer 401 sandwiched by the upper conductive layer 403 and the drain region 119 can be stressed under the programmed voltage. Therefore, the interlayer portion of the middle insulating layer 401 will be broken, forming a continuous path to connect the upper conductive layer 403 and the drain region 119 . In other words, the interlayer portion of the middle insulating layer 401 can be burned, and the programmable structure 400 can be programmed.

It should be noted that all drain regions 119 can be combined with the middle insulating layer 401 and the upper conductive layer 403 respectively to configure multiple programmable structures 400. The plurality of programmable structures 400 may be configured as a programmable array having a common upper conductor (ie, upper conductive layer 403). Selection of the programmable structure 400 to be programmed may be accomplished by controlling the gate structure 200 associated with the corresponding drain region 119 .

Conventionally, a programmable structure can be electrically coupled to other conductive features through, for example, M0 routing, which requires additional wafer area and more complex design.

In contrast, the programmable structure 400 integrates the drain region 119 associated with the gate structure 200 as a lower conductor, so the area occupied by the programmable structure 400 can be reduced. Therefore, more area is available for other complex functional units or more programmable design structures 400 . Therefore, the performance of the semiconductor element 1A can be improved. In addition, the gate structure 200 associated with the programmable structure 400 can also be used as an isolation transistor to isolate the high-programmable voltage from adjacent components. Therefore, damage to adjacent components caused by high-program design voltages (eg, leakage currents originating from high-program design voltages) can be reduced. Therefore, the reliability of the semiconductor element 1A can be improved.

30 to 33 are cross-sectional views illustrating part of the manufacturing process of the semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIGS. 30 and 31 , a process similar to that illustrated in FIGS. 2 to 24 can be used to prepare an intermediate semiconductor device. A layer of conductive material (not shown) may be conformally formed to cover the intermediate semiconductor element. The conductive material may include, for example, titanium, nickel, platinum, tantalum or cobalt. Subsequently, a heat treatment can be performed. During the heat treatment, metal atoms in the conductive material layer may chemically react with silicon atoms in the source region 117 , the drain region 119 and the gate conductive layer 203 to form a plurality of intermediate layers 111 . The plurality of intermediate layers 111 may include titanium silicide, nickel silicide, platinum nickel silicide, tantalum silicide, or cobalt silicide. The heat treatment may be a dynamic surface annealing process. After the heat treatment, a cleaning process may be performed to remove unreacted conductive material. This cleaning process can use etchants such as hydrogen peroxide and SC-1 solution.

In some embodiments, the thickness of the plurality of intermediate layers 111 may be between about 2 nanometers and about 20 nanometers.

Referring to FIGS. 32 and 33 , the manufacturing technology of the middle insulating layer 401 , the upper conductive layer 403 , the interlayer dielectric layer 105 , the first contact 107 and the second contact 109 can be similar to the procedures illustrated in FIGS. 25 to 29 . Its description will not be repeated here. The plurality of intermediate layers 111 can reduce the contact resistance of the source region 117, the drain region 119 and the gate conductive layer 203, thereby reducing the power consumption of the semiconductor device 1B.

FIG. 34 is a top view illustrating a semiconductor device 1C according to another embodiment of the present disclosure. Fig. 35 is a cross-sectional view along line A-A' of Fig. 34.

Referring to FIGS. 34 and 35 , the first connection pad 405 may be connected to one end of the programmable structure 400 and may be electrically connected to the programmable structure 400 . The first connection pad 405 may include a bottom insulating layer 405-1 and a top conductive layer 405-3. The bottom insulation layer 405-1 may be disposed on the isolation layer 103 and connected to the middle insulation layer 401. The top conductive layer 405-3 may be disposed on the bottom insulating layer 405-1 and connected to the upper conductive layer 403. The second contact 109 may be disposed on the top conductive layer 405-3. The programming voltage may be applied to the programmable structure 400 through the second contact 109 and the first connection pad 405 . In some embodiments, the width W3 of the first connection pad 405 may be greater than the width W4 of the programmable structure 400 .

In some embodiments, the first connection pad 405 may be formed simultaneously with the middle insulating layer 401 and the upper conductive layer 403 . In some embodiments, the bottom insulating layer 405-1 may be made of the same material as the middle insulating layer 401. In some embodiments, the top conductive layer 405-3 may be made of the same material as the upper conductive layer 403.

FIG. 36 is a flowchart illustrating a method 20 for manufacturing a semiconductor device 1D according to another embodiment of the present disclosure. 37 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 38 is a cross-sectional view along line BB′ of FIG. 37 , illustrating part of the manufacturing process of the semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIGS. 36 to 38 , in step S21 , a substrate 101 may be provided, and an isolation layer 103 may be formed in the substrate 101 to define a plurality of active areas AA1, AA2, AA3, AA4, and AA5. The plurality of active areas AA1, AA2 may be A plurality of well regions 113 are formed in AA3, AA4, and AA5, and a plurality of gate trenches 300TR can be formed in the substrate 101.

Referring to Figures 37 and 38, the substrate 101, the isolation layer 103, the active areas AA1, AA2, AA3, AA4, AA5 and the well area 113 can be formed using procedures similar to those illustrated in Figures 2 to 11, which will not be repeated here. Repeat its description. For simplicity, clarity and convenience of description, only one gate trench 300TR is described. From a top view, the gate trench 300TR can extend along the X direction, and can divide the transistor part TP of the active area AA1 into an upper part and a lower part.

39 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 40 is a cross-sectional view along line BB′ of FIG. 39 , illustrating part of the manufacturing process of the semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIGS. 36 , 39 and 40 , in step S23 , a plurality of buried gate structures 300 may be formed in a plurality of gate trenches 300TR.

For simplicity, clarity and convenience of description, only one buried gate structure 300 is described.

Referring to FIGS. 39 and 40 , the buried gate structure 300 may include a buried gate insulating layer 301 , a buried gate conductive layer 303 and a buried gate capping layer 305 . The buried gate insulating layer 301 may be conformally formed in the gate trench 300TR and may have a U-shaped cross-sectional profile. In some embodiments, the buried gate insulating layer 301 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, Aluminum, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

The buried gate conductive layer 303 may be formed on the buried gate insulating layer 301 . In some embodiments, the buried gate conductive layer 303 may include, for example, one of a conductive metal nitride (such as titanium nitride or tantalum nitride) and a metal (such as titanium, tantalum, tungsten, copper, or aluminum) or more. The buried gate capping layer 305 may be formed on the buried gate insulating layer 301 and the buried gate conductive layer 303 . In some embodiments, the buried gate cap layer 305 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The top surface of the buried gate capping layer 305 and the top surface of the isolation layer 103 may be substantially coplanar.

FIG. 41 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 42 is a cross-sectional view along line BB′ of FIG. 41 , illustrating part of the manufacturing process of the semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIG. 36 , FIG. 41 and FIG. 42 , in step S25 , a plurality of source regions 117 and a plurality of drain regions 119 may be formed in a plurality of well regions 113 .

Referring to FIGS. 41 and 42 , the buried gate structure 300 can be used as a mask to perform an n-type impurity implantation process to form the transistor portion TP of the active regions AA1, AA2, AA3, AA4, and AA5. The plurality of source regions 117 in the lower part and the transistor part TP of the active regions AA1, AA2, AA3, AA4, AA5. The plurality of drain regions 119 in the upper part and the active regions AA1, AA2, AA3, AA4, AA5. Programmable part of PP. The n-type impurity implantation process may be similar to the process shown in FIGS. 15 to 17 , and its description will not be repeated here.

For simplicity, clarity and convenience of description, only one source region 117 and one drain region 119 are described.

In some embodiments, source region 117 and drain region 119 may be of the second electrical type (ie, n-type). The dopant concentration of the source region 117 and the drain region 119 may be about 1E19 atoms/cm^3 to about 1E21 atoms/cm^3. In some embodiments, from a top view, the length L4 of the source region 117 may be smaller than the length L5 of the drain region 119 .

43 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. 44 to 47 are cross-sectional views along lines AA′, BB′ and CC′ of FIG. 43 , illustrating part of the manufacturing process of the semiconductor device 1D according to another embodiment of the present disclosure.

Referring to Figure 36 and Figures 43 to 46, in step S27, an intermediate insulating layer 401 can be formed on the plurality of active areas AA1, AA2, AA3, AA4, and AA5, and an upper conductive layer 403 can be formed on the intermediate insulating layer 401, where The middle insulating layer 401, the upper conductive layer 403 and the plurality of drain regions 119 jointly configure a plurality of programmable structures 400.

Referring to FIGS. 43 to 46 , the intermediate insulating layer 401 may extend along the Y direction and may be formed on the drain region 119 . The intermediate insulating layer 401 may be orthogonal to the drain region 119 . It should be noted that in a top view, the middle insulating layer 401 does not overlap the buried gate structure 300 .

In some embodiments, the manufacturing technology of the middle insulating layer 401 may be, for example, silicon oxide. In some embodiments, the manufacturing technology of the intermediate insulating layer 401 may be, for example, a high-k dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal nitride, etc. Metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate or combinations thereof.

Illustrative examples of high-k dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide. Titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, zirconium barium oxide, lanthanum silicon oxide, silicon aluminum oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

In some embodiments, the intermediate insulating layer 401 may be a multi-layer structure including, for example, a layer of silicon oxide and another layer of high-k dielectric material.

Referring to FIGS. 43 to 46 , an upper conductive layer 403 may be formed on the middle insulating layer 401 . In some embodiments, the manufacturing technology of the upper conductive layer 403 may be, for example, (doped) polycrystalline silicon, (doped) polycrystalline germanium, (doped) polycrystalline silicon germanium or other suitable conductive materials.

Referring to FIGS. 43 to 46 , the middle insulating layer 401 , the upper conductive layer 403 and the corresponding drain region 119 jointly configure the programmable structure 400 . Programmable structure 400 may be, for example, an antifuse. In this embodiment, the drain region 119 can be used as the lower conductor of the programmable structure 400 . The upper conductive layer 403 can serve as the upper conductor of the programmable structure 400 . The intermediate insulating layer 401 may serve as a dielectric layer sandwiched between the lower and upper conductors.

Referring to FIGS. 36 and 47 , in step S29 , two spacers 407 may be formed on the sidewalls 401SW and 403SW of the middle insulating layer 401 and the upper conductive layer 403 .

Referring to FIG. 47 , a layer of gap material (not shown) may be conformally formed to cover the middle semiconductor element shown in FIG. 46 . In some embodiments, the gap material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable insulating material. In some embodiments, the gap material may include an energy-removable material. The energy-removable material may include a material such as a thermal decomposition material, a photon decomposition material, an electron beam decomposition material, or a combination thereof. For example, the energy-removable material may include a base material and a decomposable porogen material that is sacrificed upon exposure to an energy source. The base material may include a silyldioxane-based material. The decomposable porogenic material may include a porogenic organic compound that provides porosity to the energy-removable base material.

Referring to FIG. 47 , an etching process, such as an anisotropic dry etching process, may be performed to remove part of the gap material and simultaneously form two spacers 407 on the sidewalls 401SW and 403SW of the middle insulating layer 401 and the upper conductive layer 403 . In some embodiments, when gap material 605 includes the energy-removable material, an energy process may be performed by applying an energy source after the etching process. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment may be between about 800°C and about 900°C. When light is used as the energy source, an ultraviolet ray can be used. The energy treatment can remove the decomposable porogenic material from the energy-removable material to create voids (pores), while the base material remains in place. The voids (pores) can reduce the dielectric constant of the two gate spacers 407 . Therefore, the influence of the programmable structure 400 on the parasitic capacitance of adjacent components may be reduced.

FIG. 48 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. 49 to 51 are cross-sectional views along lines AA′, BB′ and CC′ of FIG. 48 , illustrating part of the manufacturing process of the semiconductor device 1D according to another embodiment of the present disclosure.

Referring to FIG. 36 and FIG. 48 to FIG. 51 , in step S31 , a plurality of first contacts 107 may be formed to be electrically connected to a plurality of source regions 117 , and second contacts 109 may be formed to be electrically connected to the upper conductive layer 403 .

Referring to FIGS. 48 to 51 , the interlayer dielectric layer 105 , the first contact 107 and the second contact 109 may be formed using a process similar to that shown in FIGS. 27 to 29 , and the description thereof will not be repeated here.

When programming the programmable structure 400, a high voltage (for example, +6.0 volts) can be applied to the upper conductive layer 403 through the second contact 109, and a selection voltage (for example, +6.0 volts) can be applied to the buried gate structure 300. 1.5 volts), and the first contact 107 can be grounded, and the middle insulating layer 401 sandwiched by the upper conductive layer 403 and the drain region 119 can be stressed under the programmed voltage. Therefore, the interlayer portion of the middle insulating layer 401 will be broken, forming a continuous path to connect the upper conductive layer 403 and the drain region 119 . In other words, the interlayer portion of the intermediate insulating layer 401 can be burned, and the programmable structure 400 can be programmed.

It should be noted that all drain regions 119 can be combined with the middle insulating layer 401 and the upper conductive layer 403 respectively to configure multiple programmable structures 400. The plurality of programmable structures 400 may be configured as a programmable array having a common upper conductor (ie, upper conductive layer 403). Selection of the programmable structure 400 to be programmed may be accomplished by controlling the buried gate structure 300 associated with the corresponding drain region 119 .

The programmable structure 400 integrates the drain region 119 associated with the buried gate structure 300 as a lower conductor, so the area occupied by the programmable structure 400 can be reduced. Therefore, more area is available for other complex functional units or more programmable design structures 400 . Therefore, the performance of the semiconductor element 1D can be improved. In addition, the buried gate structure 300 associated with the programmable structure 400 can also be used as an isolation transistor to isolate the high-programmable voltage from adjacent components. Therefore, damage to adjacent components caused by high-program design voltages (eg, leakage currents originating from high-program design voltages) can be reduced. Therefore, the reliability of the semiconductor element 1D can be improved.

52 and 53 are cross-sectional views illustrating a semiconductor device 1E according to another embodiment of the present disclosure.

Referring to FIGS. 52 and 53 , a plurality of intermediate layers 111 may be disposed between the source region 117 and the first contact 107 , between the drain region 119 and the intermediate insulating layer 401 , and between the drain region 119 and the interlayer dielectric layer. between 105. The plurality of intermediate layers 111 may include titanium silicide, nickel silicide, platinum nickel silicide, tantalum silicide, or cobalt silicide. In some embodiments, the thickness of the plurality of intermediate layers 111 may be between about 2 nanometers and about 20 nanometers.

One aspect of the present disclosure provides a semiconductor device including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and extends from the transistor portion A programmable design part; a gate structure disposed on the transistor part. a drain region, disposed in the programmable part and the transistor part, and adjacent to the gate structure; a source region, disposed in the transistor part, adjacent to the gate structure, and Opposite to the drain region, the gate structure is between the two; an intermediate insulating layer is provided on the programmable part; and an upper conductive layer is provided on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a semiconductor device including a substrate; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and extends from the transistor portion a programmable design part; a buried gate structure, disposed in the transistor part; a drain region, disposed in the programmable design part and the transistor part, and connected with the buried gate adjacent to the gate structure; a source region is disposed in the transistor part, adjacent to the buried gate structure, and opposite to the drain region, with the buried gate structure being between the two ; An intermediate insulating layer is provided on the programmable part; an upper conductive layer is provided on the intermediate insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a portion formed from the transistor. a partially extended programmable portion; forming a gate structure on the transistor portion; forming a drain region in the programmable portion and the transistor portion and adjacent to the gate structure; A source region is formed in the transistor part, adjacent to the gate structure and opposite to the drain region; an intermediate insulating layer is formed on the programmable part; and an upper part is formed on the intermediate insulating layer conductive layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming an isolation layer in the substrate to define an active region of the substrate, wherein the active region includes a transistor portion and a transistor portion formed from the transistor; A programmable design part extends from the crystal part; a buried gate structure is formed in the transistor part; a drain region is formed in the programmable design part and the transistor part, and is connected with the buried gate structure. The gate structure is adjacent; a source region is formed in the transistor portion, adjacent to the buried gate structure, and opposite to the drain region; an intermediate insulating layer is formed on the programmable portion; and forming an upper conductive layer on the middle insulating layer. The drain region, the middle insulating layer and the upper conductive layer of the programmable part jointly configure a programmable structure.

Due to the design of the semiconductor device of the present disclosure, the programmable structure integrates the drain region associated with the gate structure as the lower conductor of the programmable structure, thereby reducing the area occupied by the programmable structure. Therefore, more area is available for other complex functional units or more programmable design structures. Therefore, the performance of the semiconductor element can be improved. In addition, the gate structure associated with the programmable structure can also be used as an isolation transistor to isolate high-programmable voltages from adjacent components. Therefore, damage to adjacent components caused by high-program design voltages (eg, leakage currents originating from high-program design voltages) can be reduced. Therefore, the reliability of the semiconductor element can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 1C: Semiconductor components 1D: Semiconductor components 1E: Semiconductor components 10:Preparation method 20:Preparation method 101: Base 101TR: First trench 103:Isolation layer 105: Interlayer dielectric layer 107:First point of contact 109: Second contact point 111:Middle layer 113:Well area 115:Lightly doped area 117: Source area 119: Drainage area 200: Gate structure 200SW: Side wall 201: Gate insulation layer 203: Gate conductive layer 205: Gate spacer 300: Buried gate structure 300TR: Gate trench 301: Buried gate insulation layer 303: Buried gate conductive layer 305: Buried gate capping layer 400: Programmable structure 401: Intermediate insulation layer 401SW: Side wall 403: Upper conductive layer 403SW: Side wall 405: First connection pad 405-1: Bottom insulation layer 405-3:Top conductive layer 407:Gap 601: Pad oxide layer 603: Nitride layer 605: Gap material 607: First mask layer A-A': line AA1: Active area AA2: Active area AA3: Active area AA4: Active area AA5: Active area B-B':line C-C':line L1:Length L2: length L3: length L4:Length L5:Length PP: Programmable part S11: Steps S13: Steps S15: Steps S17: Steps S21: Steps S23: Steps S25: Steps S27: Steps S29: Steps S31: Steps TP: transistor part W1: Width W2: Width W3: Width W4: Width X: direction Y: direction Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 3 to 6 are cross-sectional views along line AA' and line BB' of FIG. 2 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 8 to 11 are cross-sectional views along lines AA′ and BB′ of FIG. 7 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 12 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 13 and 14 are cross-sectional views along lines A-A' and B-B' of FIG. 12 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 15 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 16 to 21 are cross-sectional views along lines A-A' and B-B' of FIG. 15 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 22 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 23 and 24 are cross-sectional views along lines A-A' and B-B' of FIG. 22 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 25 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 26 is a cross-sectional view along line A-A' of FIG. 25 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 27 is a top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 28 and 29 are cross-sectional views along lines A-A' and B-B' of FIG. 27 , illustrating part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 30 to 33 are cross-sectional views illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 34 is a top view illustrating a semiconductor device according to another embodiment of the present disclosure. Fig. 35 is a cross-sectional view along line A-A' of Fig. 34. FIG. 36 is a flow chart illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. 37 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 38 is a cross-sectional view along line BB′ of FIG. 37 , illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 39 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 40 is a cross-sectional view along line BB′ of FIG. 39 , illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. FIG. 41 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. FIG. 42 is a cross-sectional view along line BB′ of FIG. 41 , illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 43 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. 44 to 47 are cross-sectional views along lines AA′, BB′ and CC′ of FIG. 43 , illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 48 is a top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. 49 to 51 are cross-sectional views along lines AA′, BB′ and CC′ of FIG. 48 , illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. 52 and 53 are cross-sectional views illustrating a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components

101: Base

101TR: First trench

103:Isolation layer

105: Interlayer dielectric layer

107:First point of contact

113:Well area

115:Lightly doped area

117: Source area

119: Drainage area

200: Gate structure

201: Gate insulation layer

203: Gate conductive layer

205: Gate spacer

AA1: Active area

B-B': line

TP: transistor part

Z: direction

Claims (26)

A semiconductor component including: a base; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure disposed on the transistor part; a drain region disposed in the programmable part and the transistor part and adjacent to the gate structure; a source region disposed in the transistor portion adjacent to the gate structure and opposite to the drain region, with the gate structure being between the two; An intermediate insulating layer is provided on the programmable part; and An upper conductive layer is provided on the middle insulating layer; The drain region, the middle insulating layer and the upper conductive layer in the programmable part jointly configure a programmable structure. The semiconductor device of claim 1 further includes a first contact disposed on the source region and electrically connected to the source region. The semiconductor device of claim 2 further includes a second contact disposed on the upper conductive layer and electrically connected to the upper conductive layer. The semiconductor device according to claim 3, wherein the gate structure includes: a gate insulating layer disposed on the transistor portion and between the source region and the drain region; and A gate conductive layer is provided on the gate insulating layer. The semiconductor device of claim 4 further includes two gate spacers, which are respectively disposed on the source region and the drain region and cover the sidewalls of the gate structure. The semiconductor device according to claim 5, further comprising a lightly doped region disposed in the substrate under one of the two gate spacers and adjacent to the drain region. The semiconductor device of claim 6, wherein the drain region and the lightly doped region include the same electrical type. The semiconductor device according to claim 7, further comprising a well region disposed in the transistor part and the programmable part; The lightly doped region, the source region and the drain region are disposed in the well region. The semiconductor device of claim 8, wherein the well region and the drain region include different electrical types. The semiconductor device according to claim 9, further comprising an intermediate layer disposed between the first contact and the source region; The intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device according to claim 9, further comprising an intermediate layer disposed on the drain region; The intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device according to claim 9, further comprising an intermediate layer disposed between the intermediate insulating layer and the drain region; The intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device according to claim 9, further comprising an intermediate layer disposed on the gate conductive layer; The intermediate layer includes titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The semiconductor device of claim 1, wherein a length of the source region is smaller than a length of the drain region in a top view. The semiconductor device of claim 1, wherein the programmable portion extends along a first direction, and the programmable structure extends along a second direction perpendicular to the first direction. The semiconductor device of claim 2, wherein the gate structure extends along the first direction. The semiconductor device of claim 1, wherein the length of the gate structure is greater than or equal to a length of the source region. The semiconductor device of claim 1, wherein a width of the programmable portion is smaller than a width of the transistor portion. The semiconductor device as claimed in claim 1, further comprising a first connection pad connected to one end of the programmable structure; wherein the first connection pad includes: A bottom insulating layer extends from the middle insulating layer and is disposed on the substrate; and A top conductive layer extends from the upper conductive layer disposed on the bottom insulating layer. The semiconductor device of claim 19, wherein a width of the first connection pad is greater than a width of the programmable structure. A semiconductor component including: a base; an isolation layer disposed in the substrate and defining an active region of the substrate, wherein the active region includes a transistor portion and a programmable portion extending from the transistor portion; An embedded gate structure is provided in the transistor part; a drain region disposed in the programmable part and the transistor part and adjacent to the buried gate structure; a source region disposed in the transistor portion adjacent to the buried gate structure and opposite to the drain region, with the buried gate structure between the two; An intermediate insulating layer is provided on the programmable part; and An upper conductive layer is provided on the middle insulating layer; The drain region, the middle insulating layer and the upper conductive layer in the programmable part jointly configure a programmable structure. The semiconductor device of claim 21, wherein a length of the source region is smaller than a length of the drain region in a top view. The semiconductor device of claim 22, wherein the programmable portion extends along a first direction, and the programmable structure extends along a second direction perpendicular to the first direction. The semiconductor device of claim 21, wherein a width of the programmable portion is smaller than a width of the transistor portion. The semiconductor device as claimed in claim 21, wherein the buried gate structure includes: a buried gate insulating layer disposed inwardly in the transistor portion and having a U-shaped cross-sectional profile; a buried gate conductive layer disposed on the buried gate insulating layer; and An embedded gate capping layer is provided on the embedded gate insulating layer and the embedded gate conductive layer. The semiconductor device according to claim 21, further comprising two spacers disposed on the sidewalls of the middle insulating layer and the upper conductive layer.

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