TWI846427B - Semiconductor Devices - Google Patents
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- TWI846427B TWI846427B TW112113969A TW112113969A TWI846427B TW I846427 B TWI846427 B TW I846427B TW 112113969 A TW112113969 A TW 112113969A TW 112113969 A TW112113969 A TW 112113969A TW I846427 B TWI846427 B TW I846427B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000002347 injection Methods 0.000 claims abstract description 30
- 239000007924 injection Substances 0.000 claims abstract description 30
- 230000001629 suppression Effects 0.000 claims abstract description 15
- 230000005764 inhibitory process Effects 0.000 claims 8
- 239000010410 layer Substances 0.000 description 45
- 239000000969 carrier Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 6
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 4
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 2
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 2
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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Abstract
本發明之課題在於提供一種可抑制閘極共通配線區域及閘極墊區域之附近之主動區域中之載子集中、確保關斷耐量之半導體裝置。 本發明之半導體裝置具有：複數個開關元件、共通連接於複數個開關元件之閘極之閘極共通配線1、及向閘極共通配線1進行饋電之閘極墊，其特徵在於在重疊於閘極共通配線1之閘極共通配線區域6、及重疊於閘極墊之閘極墊區域具有載子注入抑制區域18。 The subject of the present invention is to provide a semiconductor device that can suppress carrier concentration in the active region near the gate common wiring region and the gate pad region and ensure turn-off tolerance. The semiconductor device of the present invention has: a plurality of switching elements, a gate common wiring 1 commonly connected to the gates of the plurality of switching elements, and a gate pad that feeds the gate common wiring 1, and is characterized in that a carrier injection suppression region 18 is provided in the gate common wiring region 6 overlapping the gate common wiring 1 and the gate pad region overlapping the gate pad.
Description
本發明係關於一種半導體裝置。The present invention relates to a semiconductor device.
於IGBT等之功率半導體中，必須充分確保關斷耐量(RBSOA(Reverse Bias Safe Operating Area，反向偏壓安全操作區域)耐量)。In power semiconductors such as IGBTs, the turn-off tolerance (RBSOA (Reverse Bias Safe Operating Area) tolerance) must be fully ensured.
作為提高IGBT之關斷時之截斷能力之技術，例如存在專利文獻1。專利文獻1之段落0120～0123、圖32A、圖32B所示之構造為抑制IGBT之中間區域(2)至終端區域(5)之自集極側之載子之注入之構造，於圖32A中顯示在有效單元區域(1)中集極層(16)與金屬(29)相接，在中間區域(2)與終端區域(5)中n緩衝層(15)與金屬(29)相接之IGBT，於圖32B中顯示在有效單元區域(1)中p集極層(16)與金屬(29)相接，於中間區域(2)與終端區域(5)中雜質濃度較p集極層(16)為低之低濃度p集極層(16’)與金屬(29)相接之IGBT，其結果，曾記載存在以下作用，即：緩和於關斷動作時位於中間區域(2)之主接合pn接面部之電場強度，抑制局部的電場強度之上升，抑制由以碰撞電離化所致之電流集中為起因之局部的溫度上升所致的熱破壞。 [先前技術文獻] [專利文獻] As a technology for improving the cutoff capability of an IGBT when it is turned off, there is, for example, patent document 1. The structure shown in paragraphs 0120 to 0123, Figure 32A, and Figure 32B of patent document 1 is a structure for suppressing the injection of carriers from the collector side from the middle region (2) to the terminal region (5) of the IGBT. Figure 32A shows an IGBT in which the collector layer (16) is connected to the metal (29) in the active cell region (1), and the n buffer layer (15) is connected to the metal (29) in the middle region (2) and the terminal region (5). Figure 32B shows an IGBT in which the p collector layer (16) is connected to the metal (29) in the active cell region (1). (16) is connected to the metal (29), and the low-concentration p-collector layer (16') in the middle region (2) and the terminal region (5) is connected to the metal (29). As a result, it has been described that the following functions exist, namely, to mitigate the electric field intensity of the main junction pn junction portion located in the middle region (2) during the shutdown operation, to suppress the increase of the local electric field intensity, and to suppress the thermal damage caused by the local temperature increase caused by the current concentration due to collision ionization. [Prior technical literature] [Patent literature]
[專利文獻1]國際公開第2017/115434號[Patent Document 1] International Publication No. 2017/115434
[發明所欲解決之問題][The problem the invention is trying to solve]
作為IGBT於關斷時破壞之一個要因，認為係由於在關斷時自終端區域注入大量之電洞等載子，故於主動區域之周邊部(尤其是轉角區域)產生載子集中，因電場集中，而導致破壞。One of the main reasons for IGBT damage when turned off is that a large amount of holes and other carriers are injected from the terminal region when turned off, which causes carrier concentration in the periphery of the active region (especially the corner region), resulting in electric field concentration and thus causing damage.
根據專利文獻1之技術，由於抑制自終端區域之載子之注入，故可抑制主動區域之周邊部中之關斷時之破壞。According to the technology of Patent Document 1, since the injection of carriers from the terminal region is suppressed, the damage during the shutdown in the peripheral portion of the active region can be suppressed.
然而，根據本發明申請案之發明者之探討，可知自亦被稱為閘極指狀物之閘極共通配線與閘極墊之下部亦產生載子之注入，於閘極共通配線區域及閘極墊區域之附近之主動區域產生載子集中，而導致破壞。However, according to the research of the inventors of the present invention application, it is known that carrier injection also occurs from the lower part of the gate common wiring and the gate pad, which is also called a gate finger, and carriers are concentrated in the active region near the gate common wiring region and the gate pad region, resulting in damage.
於專利文獻1中，於相當於閘極共通配線之專利文獻1之圖1之表面閘極配線部(3)未採用抑制自集極側之載子之注入之構造，而無法解決該問題。In Patent Document 1, a structure for suppressing the injection of carriers from the collector side is not adopted in the surface gate wiring portion (3) of FIG. 1 of Patent Document 1 corresponding to the gate common wiring, and the problem cannot be solved.
又，本根據本發明申請案之發明者之探討，可知無論於終端區域有無抑制載子之注入之構造，均於例如開關速度快時，較主動區域之周邊部先於閘極共通配線區域及閘極墊區域之附近之主動區域產生載子集中，而導致破壞。Furthermore, according to the research of the inventors of the present invention application, it is known that regardless of whether there is a structure to suppress carrier injection in the terminal region, when the switching speed is fast, for example, carriers concentrate in the active region near the periphery of the active region before the gate common wiring region and the gate pad region, resulting in damage.
使用圖1、圖2、圖10至圖12說明該理由。This reason will be described using FIG. 1 , FIG. 2 , and FIG. 10 to FIG. 12 .
圖1係半導體裝置之俯視圖，圖2係圖1之半導體裝置之A部放大圖，圖10係先前之半導體裝置之B-B’剖視圖，圖11係先前之半導體裝置之D-D’剖視圖，圖12係先前之半導體裝置之B-B’剖視圖。FIG1 is a top view of a semiconductor device, FIG2 is an enlarged view of portion A of the semiconductor device of FIG1 , FIG10 is a B-B’ cross-sectional view of the previous semiconductor device, FIG11 is a D-D’ cross-sectional view of the previous semiconductor device, and FIG12 is a B-B’ cross-sectional view of the previous semiconductor device.
如圖10所示，於開關速度慢時，重疊於閘極共通配線1之閘極共通配線區域6與終端區域4中之電洞20注入主動區域3，於主動區域3之周邊部產生載子集中。如圖11所示，於夾在主動區域3之間之閘極共通配線區域6中亦然，電洞20注入主動區域3，於閘極共通配線區域6之附近之主動區域3產生載子集中。然而，如圖10所示，於開關速度慢時，由於主動區域3之周邊部之注入電洞20之量更多，故於主動區域3之周邊部更容易導致破壞。As shown in FIG10 , when the switching speed is slow, the holes 20 overlapped in the gate common wiring region 6 and the terminal region 4 of the gate common wiring 1 are injected into the active region 3, and carriers are concentrated in the peripheral portion of the active region 3. As shown in FIG11 , the holes 20 are injected into the active region 3 in the gate common wiring region 6 sandwiched between the active regions 3, and carriers are concentrated in the active region 3 near the gate common wiring region 6. However, as shown in FIG10 , when the switching speed is slow, since the amount of the injected holes 20 in the peripheral portion of the active region 3 is greater, the peripheral portion of the active region 3 is more likely to be damaged.
另一方面，如圖12所示，於開關速度快時，在閘極共通配線區域6與終端區域4中之電洞20之一部分到達之前，如圖11所示，有時來自夾在主動區域3之間之閘極共通配線區域6之電洞20所注入之量佔支配性地位，於閘極共通配線區域6之附近之主動區域3更有可能導致破壞。又，未圖示之閘極墊區域之構造由於與閘極共通配線區域6同樣，故同樣於閘極墊區域之附近之主動區域3更有可能導致破壞。On the other hand, as shown in FIG12, when the switching speed is fast, before a part of the holes 20 in the gate common wiring region 6 and the terminal region 4 arrive, as shown in FIG11, the amount of holes 20 injected from the gate common wiring region 6 sandwiched between the active regions 3 is sometimes dominant, and the active region 3 near the gate common wiring region 6 is more likely to be damaged. In addition, since the structure of the gate pad region not shown is the same as that of the gate common wiring region 6, the active region 3 near the gate pad region is more likely to be damaged.
因此，可知為了確保關斷耐量，而於閘極共通配線區域6及閘極墊區域中亦必須要有抑制載子之注入之構造。Therefore, it can be seen that in order to ensure the turn-off tolerance, a structure for suppressing the injection of carriers is necessary in the gate common wiring region 6 and the gate pad region.
本發明所欲解決之問題在於提供一種可抑制閘極共通配線區域及閘極墊區域之附近之主動區域中之載子集中、確保關斷耐量之半導體裝置。 [解決問題之技術手段] The problem that the present invention aims to solve is to provide a semiconductor device that can suppress carrier concentration in the active region near the gate common wiring region and the gate pad region and ensure turn-off tolerance. [Technical means for solving the problem]
為了解決上述問題，本發明之半導體裝置例如具有：複數個開關元件、共通連接於前述複數個開關元件之閘極之閘極共通配線、及向前述閘極共通配線進行饋電之閘極墊，其特徵在於在重疊於前述閘極共通配線之閘極共通配線區域、與重疊於閘極墊之閘極墊區域具有載子注入抑制區域。 [發明之效果] In order to solve the above problems, the semiconductor device of the present invention has, for example: a plurality of switching elements, a gate common wiring commonly connected to the gates of the plurality of switching elements, and a gate pad for feeding the gate common wiring, and is characterized in that a carrier injection suppression region is provided in a gate common wiring region overlapping the gate common wiring and a gate pad region overlapping the gate pad. [Effect of the invention]
根據本發明之半導體裝置，可抑制閘極共通配線區域及閘極墊區域之附近之主動區域中之載子集中，確保關斷耐量。According to the semiconductor device of the present invention, carrier concentration in the active region near the gate common wiring region and the gate pad region can be suppressed, thereby ensuring turn-off tolerance.
以下，使用圖式說明本發明之實施例。各圖於各實施例中，針對同一或類似之構成要素賦予相同之符號，且省略重複之說明。 [實施例1] The following is an illustration of an embodiment of the present invention. In each embodiment, the same or similar components are given the same symbols, and repeated descriptions are omitted. [Example 1]
圖1係半導體裝置之俯視圖，圖2係圖1之半導體裝置之A部放大圖，圖3係實施例1之半導體裝置之B-B’剖視圖，圖4係實施例1之半導體裝置之C-C’剖視圖，圖5係實施例1之半導體裝置之D-D’剖視圖。FIG1 is a top view of the semiconductor device, FIG2 is an enlarged view of portion A of the semiconductor device of FIG1, FIG3 is a B-B’ cross-sectional view of the semiconductor device of Example 1, FIG4 is a C-C’ cross-sectional view of the semiconductor device of Example 1, and FIG5 is a D-D’ cross-sectional view of the semiconductor device of Example 1.
如圖1及圖2所示，半導體裝置100具有：形成有複數個開關元件之主動區域3、共通連接於複數個開關元件之閘極5之閘極共通配線1、及對閘極共通配線1進行饋電之閘極墊2。閘極共通配線1具有：將主動區域3分割之部分、及形成於主動區域3與終端區域4之邊界之部分。As shown in FIG. 1 and FIG. 2 , the semiconductor device 100 includes an active region 3 in which a plurality of switch elements are formed, a gate common wiring 1 commonly connected to gates 5 of the plurality of switch elements, and a gate pad 2 for feeding the gate common wiring 1. The gate common wiring 1 includes a portion that divides the active region 3 and a portion formed at a boundary between the active region 3 and the terminal region 4.
此外，於圖1中省略閘極5之圖示，於圖1及圖2中省略閘極電極13、射極電極14、場板15之圖示。In addition, the gate 5 is omitted in FIG. 1 , and the gate electrode 13 , the emitter electrode 14 , and the field plate 15 are omitted in FIG. 1 and FIG. 2 .
實施例1之半導體裝置如圖3所示般於主動區域3具有IGBT作為開關元件。具體而言，實施例1之半導體裝置具有：第1導電型(圖3中為n型)之漂移層7、設置於漂移層7之表面側之第2導電型(圖3中為p型)之主體層8、形成於溝渠內之閘極5及閘極絕緣膜10、設置於主體層8之表面側之第1導電型之射極層9、及設置於較漂移層7更靠背面側之第2導電型之集極層17。As shown in FIG3 , the semiconductor device of Example 1 has an IGBT as a switching element in the active region 3. Specifically, the semiconductor device of Example 1 has a drift layer 7 of the first conductivity type (n-type in FIG3 ), a main layer 8 of the second conductivity type (p-type in FIG3 ) disposed on the surface side of the drift layer 7, a gate 5 and a gate insulating film 10 formed in the trench, an emitter layer 9 of the first conductivity type disposed on the surface side of the main layer 8, and a collector layer 17 of the second conductivity type disposed on the back side of the drift layer 7.
此處，將第1導電型設為n型、將第2導電型設為p型而進行說明，但可將第1導電型設為p型、將第2導電型設為n型。該情形下，載子為電子而非電洞20。Here, the first conductivity type is n-type and the second conductivity type is p-type for explanation, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the carriers are electrons instead of holes 20.
又，實施例1之半導體裝置具有：設置於漂移層7與集極層17之間之第1導電型之緩衝層16、設置於集極層17之背面側之集極電極19、設置於主體層8及射極層9之表面側之層間絕緣膜12、及經由設置於層間絕緣膜12之接觸孔與射極層9及主體層8接觸之射極電極14。Furthermore, the semiconductor device of Embodiment 1 has: a buffer layer 16 of the first conductivity type disposed between the drift layer 7 and the collector layer 17, a collector electrode 19 disposed on the back side of the collector layer 17, an interlayer insulating film 12 disposed on the surface side of the main layer 8 and the emitter layer 9, and an emitter electrode 14 in contact with the emitter layer 9 and the main layer 8 via a contact hole disposed in the interlayer insulating film 12.
實施例1之半導體裝置於終端區域4中具有：設置於漂移層7之表面側之第2導電型之井層11、及經由設置於層間絕緣膜12之接觸孔與井層11接觸之場板15。The semiconductor device of Example 1 has, in the terminal region 4, a well layer 11 of the second conductivity type disposed on the surface side of the drift layer 7, and a field plate 15 in contact with the well layer 11 via a contact hole disposed in the interlayer insulating film 12.
實施例1之半導體裝置在重疊於閘極共通配線1之閘極共通配線區域6中具有：井層11、閘極共通配線1、及經由設置於層間絕緣膜12之接觸孔與閘極共通配線1接觸之閘極電極13。雖未圖示，但重疊於閘極墊2之閘極墊區域之構造亦為與閘極共通配線區域6大致同樣之構成。The semiconductor device of the first embodiment has a well layer 11, a gate common wiring 1, and a gate electrode 13 in contact with the gate common wiring 1 via a contact hole provided in an interlayer insulating film 12 in a gate common wiring region 6 overlapping the gate common wiring 1. Although not shown, the structure of the gate pad region overlapping the gate pad 2 is also substantially the same as that of the gate common wiring region 6.
如圖4所示，閘極共通配線1與閘極5連接，閘極共通配線1與閘極5及閘極墊2係由例如多晶矽形成。As shown in FIG. 4 , the gate common wiring 1 is connected to the gate 5 , and the gate common wiring 1 , the gate 5 , and the gate pad 2 are formed of, for example, polysilicon.
此處，實施例1之半導體裝置如圖3至圖5所示般於閘極共通配線區域6、及未圖示之閘極墊區域具有載子注入抑制區域18。藉此，可抑制閘極共通配線區域6及閘極墊區域之附近之主動區域3中之載子集中，確保關斷耐量。Here, the semiconductor device of Example 1 has a carrier injection suppression region 18 in the gate common wiring region 6 and the gate pad region (not shown) as shown in Figures 3 to 5. This can suppress carrier concentration in the active region 3 near the gate common wiring region 6 and the gate pad region, thereby ensuring turn-off tolerance.
如圖4及圖5所示， 載子注入抑制區域18較理想為亦形成於夾在經分割之主動區域3之間之閘極共通配線區域6中。藉此，可抑制夾在經分割之主動區域3之間之閘極共通配線區域6之附近之主動區域3中之載子集中，確保關斷耐量。As shown in FIG4 and FIG5, the carrier injection suppression region 18 is preferably formed also in the gate common wiring region 6 sandwiched between the divided active regions 3. In this way, carrier concentration in the active region 3 near the gate common wiring region 6 sandwiched between the divided active regions 3 can be suppressed, and the turn-off tolerance can be ensured.
又，如圖3所示，載子注入抑制區域18較理想為亦形成於終端區域4中。藉此，可抑制主動區域3之周邊部中之載子集中，確保關斷耐量。此外，於例如開關速度快時等、來自終端區域4之電洞注入不佔支配性地位時，可針對終端區域4不設置載子注入抑制區域18。As shown in FIG3 , the carrier injection suppression region 18 is preferably formed in the terminal region 4 as well. This can suppress the concentration of carriers in the peripheral portion of the active region 3 and ensure the turn-off tolerance. In addition, when the hole injection from the terminal region 4 is not dominant, for example, when the switching speed is fast, the carrier injection suppression region 18 may not be provided for the terminal region 4.
於實施例1中，顯示使用與集極層17為相同之導電型且較集極層17為低濃度之層作為載子注入抑制區域18之例。In Example 1, an example is shown in which a layer having the same conductivity type as the collector layer 17 and a lower concentration than the collector layer 17 is used as the carrier injection suppression region 18.
此外，各半導體層之雜質濃度例如為漂移層為低濃度之n-型、射極層9為高濃度之n+型、載子注入抑制區域18為低濃度之p-型。 [實施例2] In addition, the impurity concentration of each semiconductor layer is, for example, a low-concentration n-type for the drift layer, a high-concentration n+ type for the emitter layer 9, and a low-concentration p-type for the carrier injection suppression region 18. [Example 2]
實施例2係實施例1之變化例，與實施例1不同之點為載子注入抑制區域18之構造。其以外由於與實施例1相同，故省略重複之說明。Embodiment 2 is a variation of Embodiment 1, and is different from Embodiment 1 in the structure of the carrier injection suppression region 18. Since the rest is the same as Embodiment 1, repeated description is omitted.
圖6係實施例2之半導體裝置之B-B’剖視圖，圖7係實施例2之半導體裝置之D-D’剖視圖。FIG6 is a B-B’ cross-sectional view of the semiconductor device of Example 2, and FIG7 is a D-D’ cross-sectional view of the semiconductor device of Example 2.
實施例2之載子注入抑制區域18係無集極層17、且導電型與集極層17不同之層(此處為緩衝層16)與集極電極19直接相接之區域。The carrier injection suppression region 18 of Example 2 is a region without the collector layer 17, and a layer having a conductivity type different from that of the collector layer 17 (here, the buffer layer 16) is directly connected to the collector electrode 19.
與實施例1進行比較，由於無須於背面側形成低濃度之p-型之層，故有容易製造之優點。其以外可獲得與實施例1同樣之效果。 [實施例3] Compared with Example 1, since there is no need to form a low-concentration p-type layer on the back side, it has the advantage of being easy to manufacture. Other than that, the same effects as Example 1 can be obtained. [Example 3]
實施例3係實施例1之變化例，與實施例1不同之點為載子注入抑制區域18之構造。其以外由於與實施例1相同，故省略重複之說明。Embodiment 3 is a variation of Embodiment 1, and is different from Embodiment 1 in the structure of the carrier injection suppression region 18. Since the rest is the same as Embodiment 1, repeated description is omitted.
圖8係實施例3之半導體裝置之B-B’剖視圖，圖9係實施例3之半導體裝置之D-D’剖視圖。FIG8 is a B-B’ cross-sectional view of the semiconductor device of Example 3, and FIG9 is a D-D’ cross-sectional view of the semiconductor device of Example 3.
實施例3之載子注入抑制區域18係藉由輕離子照射而形成之低壽命區域。作為輕離子，可使用例如質子或氦等。The carrier injection suppression region 18 of Embodiment 3 is a low-life region formed by light ion irradiation. As the light ions, for example, protons or helium can be used.
於實施例3中，亦可獲得與實施例1同樣之效果。In Example 3, the same effect as that of Example 1 can also be obtained.
以上，說明了本發明之實施例，但本發明不限定於實施例所記載之構成，可於本發明之技術性思想之範圍內進行各種變更。又，可將各實施例所說明之構成之一部分或全部組合而應用。The embodiments of the present invention are described above, but the present invention is not limited to the configurations described in the embodiments, and various modifications can be made within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiments can be combined and applied.
1:閘極共通配線 2:閘極墊 3:主動區域 4:終端區域 5:閘極 6:閘極共通配線區域 7:漂移層 8:主體層 9:射極層 10:閘極絕緣膜 11:井層 12:層間絕緣膜 13:閘極電極 14:射極電極 15:場板 16:緩衝層 17:集極層 18:載子注入抑制區域 19:集極電極 20:電洞 100:半導體裝置 1: Gate common wiring 2: Gate pad 3: Active region 4: Terminal region 5: Gate 6: Gate common wiring region 7: Drift layer 8: Body layer 9: Emitter layer 10: Gate insulating film 11: Well layer 12: Interlayer insulating film 13: Gate electrode 14: Emitter electrode 15: Field plate 16: Buffer layer 17: Collector layer 18: Carrier injection suppression region 19: Collector electrode 20: Holes 100: Semiconductor device
圖1係半導體裝置之俯視圖。 圖2係圖1之半導體裝置之A部放大圖。 圖3係實施例1之半導體裝置之B-B’剖視圖。 圖4係實施例1之半導體裝置之C-C’剖視圖。 圖5係實施例1之半導體裝置之D-D’剖視圖。 圖6係實施例2之半導體裝置之B-B’剖視圖。 圖7係實施例2之半導體裝置之D-D’剖視圖。 圖8係實施例3之半導體裝置之B-B’剖視圖。 圖9係實施例3之半導體裝置之D-D’剖視圖。 圖10係先前之半導體裝置之B-B’剖視圖。 圖11係先前之半導體裝置之D-D’剖視圖。 圖12係先前之半導體裝置之B-B’剖視圖。 FIG. 1 is a top view of a semiconductor device. FIG. 2 is an enlarged view of the A portion of the semiconductor device of FIG. 1. FIG. 3 is a B-B’ cross-sectional view of the semiconductor device of Example 1. FIG. 4 is a C-C’ cross-sectional view of the semiconductor device of Example 1. FIG. 5 is a D-D’ cross-sectional view of the semiconductor device of Example 1. FIG. 6 is a B-B’ cross-sectional view of the semiconductor device of Example 2. FIG. 7 is a D-D’ cross-sectional view of the semiconductor device of Example 2. FIG. 8 is a B-B’ cross-sectional view of the semiconductor device of Example 3. FIG. 9 is a D-D’ cross-sectional view of the semiconductor device of Example 3. FIG. 10 is a B-B’ cross-sectional view of the previous semiconductor device. FIG. 11 is a D-D’ cross-sectional view of the previous semiconductor device. Figure 12 is a B-B’ cross-sectional view of a previous semiconductor device.
1:閘極共通配線 3:主動區域 6:閘極共通配線區域 7:漂移層 8:主體層 11:井層 12:層間絕緣膜 13:閘極電極 14:射極電極 16:緩衝層 17:集極層 18:載子注入抑制區域 19:集極電極 1: Gate common wiring 3: Active region 6: Gate common wiring region 7: Drift layer 8: Body layer 11: Well layer 12: Interlayer insulation film 13: Gate electrode 14: Emitter electrode 16: Buffer layer 17: Collector layer 18: Carrier injection suppression region 19: Collector electrode
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| CN105940496A (en) * | 2014-01-29 | 2016-09-14 | 三菱电机株式会社 | Power semiconductor device |
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