TWI844326B - Direct memory access (dma) circuit and operation method thereof - Google Patents

Abstract

A direct memory access (DMA) circuit and an operation method thereof are provided. The DMA circuit includes a buffer circuit, a first channel, and a second channel. The operation method includes: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of the first and second channels that correspond to a first data and a second data, respectively; determining a read address according to the first start address and a read count value; reading a first part of the first data from the buffer circuit according to the read address and updating the read count value; reading at least a part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count value; and reading a second part of the first data from the buffer circuit according to the updated read address.

Description

Direct memory access circuit and operation method thereof

The present invention relates to direct memory access (DMA), and more particularly to a direct memory access circuit and an operating method thereof.

The delay of the data source end (such as memory) or the data destination end (such as processing circuit) of the direct memory access circuit is usually not fixed, and the read and write speeds of the data source end and the data destination end are not necessarily matched. In addition, when the number of data source ends or the number of data destination ends is greater than one, the data transmission between multiple channels may be blocked due to the above delay, resulting in reduced performance of the direct memory access circuit.

In view of the deficiencies of the prior art, one purpose of the present invention is to provide a direct memory access circuit and a method for operating the direct memory access circuit to improve the deficiencies of the prior art.

An embodiment of the present invention provides an operation method of a direct memory access circuit. The direct memory access circuit includes a buffer circuit, a first channel and a second channel. The method includes: determining a first starting address from the buffer circuit according to a first read request of the first channel, the first read request corresponding to a first data; determining a second starting address from the buffer circuit according to a second read request of the second channel, the second read request corresponding to a second data; determining a read address according to the first starting address and a first read count value; and determining a read address from the buffer circuit according to the read address. The circuit reads a first portion of the first data and updates the first read count value; after reading the first portion of the first data, reads at least a portion of the second data from the buffer circuit according to the second starting address; updates the read address according to the first starting address and the updated first read count value; and reads a second portion of the first data from the buffer circuit according to the updated read address.

Another embodiment of the present invention provides a direct memory access circuit, comprising: a buffer circuit, a first channel, a second channel, a write state determination circuit, a read address generation circuit and a control circuit. The first channel is used to generate a first read request. The second channel is used to generate a second read request. The write state determination circuit is used to determine a first starting address from the buffer circuit according to the first read request, and to determine a second starting address from the buffer circuit according to the second read request, the first read request corresponds to a first data, and the second read request corresponds to a second data. The read address generation circuit is used to determine a read address according to the first starting address and a first read count value. The control circuit is used to read a first part of the first data from the buffer circuit according to the read address, control the read address generation circuit to update the first read count value, and after reading the first part of the first data, read at least a part of the second data from the buffer circuit according to the second start address. The read address generation circuit further updates the read address according to the first start address and the updated first read count value, and the control circuit further reads a second part of the first data from the buffer circuit according to the updated read address.

The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art, so the present invention can improve the performance of the direct memory access circuit compared to the prior art.

The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings.

100: Direct memory access circuit

110: Write status judgment circuit

120: Write address generation circuit

130: Read address generation circuit

140: Control circuit

150: Buffer circuit

160,170: Channel

162,172: register

122,124: Write counter

132,134: Read counter

buff_sec0~buff_sec31: buffer segment

buff0~buff127: buffer block

210: Buffer status table

wr_flg: write status flag

rd_flg: read status flag

220: Write status table

Req, Req0, Req1: Read request

addr_start, Sa0, Sa1: starting address

wr_cnt,wr_cnt0,wr_cnt1: write count value

230: Read status table

Ln, Ln0, Ln1: data length

rd_cnt,rd_cnt0,rd_cnt1: read count value

Axi_ID, ID0, ID1: Axi identification code

ptr0,ptr1:pointer

Din: Data

wr_addr: write address

wr_data: data to be written

rd_cmd0,rd_cmd1: read command

rd_cmd: target read command

rd_addr: target read address

310,S315,S320,S330,S340,S350,S360,S370,S380,S390,S510,S520,S530,S540,S550,S560,S910,S915,S920,S925,S930,S935,S940,S945,S950,S960,S1810,S1820,S1830,S1840,S1850,S1855,S1860,S1870: Steps

FIG1 is a functional block diagram of an embodiment of the direct memory access circuit of the present invention; FIG2, FIG4, FIG6~FIG8, FIG10~FIG17 and FIG20 show the contents of the buffer circuit and some control values of the direct memory access circuit; FIG3 is a flow chart of an embodiment of configuring the buffer circuit in response to a read request; FIG5 is a flow chart of a write address generation circuit writing data into the buffer circuit; FIG9 is a flow chart of a control circuit reading data from the buffer circuit; and FIG18~FIG19 are flow charts of an embodiment of an operation method of the direct memory access circuit of the present invention.

The technical terms used in the following descriptions refer to the customary terms in this technical field. If this manual explains or defines some of the terms, the interpretation of those terms shall be based on the explanation or definition in this manual.

The disclosure of the present invention includes a direct memory access circuit and an operating method thereof. Since some components included in the direct memory access circuit of the present invention may be known components individually, the following description will omit the details of the known components without affecting the full disclosure and feasibility of the device invention. In addition, part or all of the process of the operating method of the direct memory access circuit of the present invention may be in the form of software and/or firmware, and may be executed by the direct memory access circuit of the present invention or its equivalent device. Without affecting the full disclosure and feasibility of the method invention, the following description of the method invention will focus on the step content rather than the hardware.

FIG1 is a functional block diagram of an embodiment of a direct memory access circuit 100 of the present invention. The direct memory access circuit 100 includes a write state determination circuit 110, a write address generation circuit 120, a read address generation circuit 130, a control circuit 140, and a buffer circuit 150. The write state determination circuit 110 includes a plurality of channels (including but not limited to channels 160 and 170) and a plurality of registers corresponding to the channels (including but not limited to registers 162 and 172 corresponding to channels 160 and 170, respectively). The write address generation circuit 120 includes a plurality of write counters (including but not limited to write counter 122 and write counter 124). The read address generation circuit 130 includes a plurality of read counters (including but not limited to the read counter 132 and the read counter 134).

FIG2 shows the details of the buffer circuit 150 and some control values of the direct memory access circuit 100. The buffer circuit 150 includes N buffer segments buff_sec (in the example of FIG2, N=32 (buff_sec0~buff_sec31)), and one buffer segment buff_sec includes X buffer blocks (in the example of FIG2, X=4) (in other words, X is the granularity of the buffer segment buff_sec); therefore, the buffer circuit 150 has a total of N*X buffer blocks (buff0~buff127).

When X is equal to 1, one buffer buff_sec is equivalent to one buffer chunk buff.

The buffer status table 210 records the write status flag wr_flg and the read status flag rd_flg of each buffer buff_sec. The write status table 220 records the corresponding Axi identification code Axi_ID, the start address addr_start and the write count value wr_cnt of each read request Req. The Axi identification code Axi_ID can also be used as a channel number. The read status table 230 records the start address addr_start, the data length Ln and the read count value rd_cnt of each channel. The start address Sa0 and the start address Sa1 of the write status table 220 are determined by the write status judgment circuit 110 and can be stored in the write status judgment circuit 110 (for example, stored in the register 162 and the register 172 respectively). The write count value wr_cnt0 and the write count value wr_cnt1 of the write status table 220 are the count values of the write counter 122 and the write counter 124 respectively. The read count value rd_cnt0 and the read count value rd_cnt1 of the read status table 230 are the count values of the read counter 132 and the read counter 134 respectively. The data length Ln0 and the data length Ln1 can be stored in the register 162 and the register 172 respectively.

FIG3 is a flow chart of an embodiment of configuring the buffer circuit 150 in response to a read request Req, including the following steps.

Step S310: Channel 160 issues a read request Req0 (corresponding to the first data with a data length of Ln0).

Step S315: Channel 170 issues a read request Req1 (corresponding to the second data with a data length of Ln1).

For example, the read request Req0 and the read request Req1 may be read requests for reading data from a target device (e.g., an external memory (e.g., a double data rate (DDR) memory) of an electronic device (e.g., a chip) in which the direct memory access circuit 100 is located). In some embodiments, the read request Req0 and the read request Req1 correspond to different target devices.

Step S320: The write state determination circuit 110 arbitrates to generate a target read request. The write state determination circuit 110 may include an arbitrator (not shown) for arbitrating between the read request Req0 and the read request Req1 to generate a target read request according to a predetermined arbitration rule (e.g., round-robin).

個未被使用的緩衝段。在一些實施例中，粒度X可以是2的冪次方(即，X=1,2,4,8,...)。以圖2為例(X=4)，假設Ln=6(即，需要

個緩衝段buff_sec)，因為至少有5個緩衝段buff_sec(緩衝段buff_sec0、緩衝段buff_sec1、緩衝段buff_sec2、緩衝段buff_sec3及緩衝段buff_sec31)的寫狀態標誌位wr_flg皆為第一數值(例如1，代表未被使用)，所以步驟S330的判斷結果為是。 Step S330: The write status determination circuit 110 determines whether the buffer circuit 150 has sufficient unused space (e.g., buffer block). More specifically, the write status determination circuit 110 finds out the buffer circuit 150 based on the write status flag wr_flg of the buffer segment, the amount of data to be processed (i.e., the data length Ln0 of the first data or the data length Ln1 of the second data) and the granularity X.

unused buffers. In some embodiments, the granularity X may be a power of 2 (i.e., X=1, 2, 4, 8, ...). Taking FIG. 2 as an example (X=4), assuming Ln=6 (i.e.,

Buffers buff_sec), because the write status flags wr_flg of at least five buffers buff_sec (buffer buff_sec0, buffer buff_sec1, buffer buff_sec2, buffer buff_sec3, and buffer buff_sec31) are all the first value (for example, 1, representing that they are not used), the determination result of step S330 is yes.

When the judgment result of step S330 is yes, the write status judgment circuit 110 further selects one of the idle Axi identification codes Axi_ID of the direct memory access circuit 100. In the following discussion, it is assumed that the write status judgment circuit 110 assigns the Axi identification code ID0 to the channel 160 (i.e., the channel 160 is numbered as ID0), and assigns the Axi identification code ID1 to the channel 170 (i.e., the channel 170 is numbered as ID1).

In some embodiments, multiple buffer segments buff_sec or multiple buffer blocks allocated to a read request Req must be contiguous.

Step S340: The write status judgment circuit 110 judges whether the target read request is a read request Req0 or a read request Req1. If the target read request is judged to be a read request Req0, step S350 is executed. If the target read request is judged to be a read request Req1, step S360 is executed.

Step S350: The write status determination circuit 110 determines whether the register 162 of the channel 160 is full. If yes, the write status determination circuit 110 returns to step S320 to arbitrate and generate another target read request; if not, the write status determination circuit 110 executes steps S370 and S390.

Step S360: The write status determination circuit 110 determines whether the register 172 of the channel 170 is full. If yes, the write status determination circuit 110 returns to step S320 to arbitrate and generate another target read request; if no, the write status determination circuit 110 executes steps S380 and S390.

Step S370: The write status determination circuit 110 updates the write status flag wr_flg, and writes the determined start address addr_start of the buffer segment buff_sec and the data length Ln0 of the read request Req0 into the register 162 of the channel 160. Please refer to FIG. 2. Assuming that Ln=Ln0=6 and the write status determination circuit 110 assigns the buffer segments buff_sec0 and buff_sec1 to the channel 160, the write status determination circuit 110 updates the write status flag wr_flg of the buffer segments buff_sec0 and buff_sec1 to a second value (e.g., 0, indicating that they have been used), and writes the data length Ln0 and the starting address addr_start of the buffer segment buff_sec0 (hereinafter referred to as the starting address Sa0) into the register 162.

Step S380: The write status determination circuit 110 updates the write status flag wr_flg, and writes the determined start address addr_start of the buffer segment buff_sec and the data length Ln1 of the read request Req1 into the register 172 of the channel 170. Please refer to FIG. 2. Assuming that Ln=Ln1=5 and the write status determination circuit 110 assigns the buffer segments buff_sec2 and buff_sec3 to the channel 170, the write status determination circuit 110 updates the write status flag wr_flg of the buffer segments buff_sec2 and buff_sec3 to the second value, and writes the data length Ln1 and the starting address addr_start of the buffer segment buff_sec2 (hereinafter referred to as the starting address Sa1) into the register 172.

Step S390: The write status determination circuit 110 sets the correspondence between the target read request and the channel number (ID0 or ID1) of the channel (channel 160 or channel 170) (as shown in the write status table 220) to confirm the correlation between the data and the channel. More specifically, if step S350 is no, the write status determination circuit 110 sets the read request Req0 and the Axi identification code ID0 to be mutually correlated. If step S360 is no, the write status determination circuit 110 sets the read request Req1 and the Axi identification code ID1 to be mutually correlated.

Continuing with the above example, after the process of FIG. 3 is completed, the contents of the buffer circuit 150, the buffer segment status table 210, the write status table 220 and the read status table 230 are shown in FIG. 4. Because no data has been written into or read from the buffer circuit 150, the values of the write count value wr_cnt0, the write count value wr_cnt1, the read count value rd_cnt0, the read count value rd_cnt1 and the read status flag bit rd_flg are all 0. The read status flag bit rd_flg is used to record the number of unread data in the corresponding buffer segment buff_sec. Taking FIG. 4 as an example, if all four buffer blocks of a buffer segment buff_sec have data but only three of them have not been read, the read status flag bit rd_flg corresponding to the buffer segment buff_sec is 3. In some embodiments, the number of bits of the read status flag bit rd_flg can be log ₂ X +1. Pointer ptr0 corresponds to the read request Req0 and channel 160 (ID0). Pointer ptr1 corresponds to the read request Req1 and channel 170 (ID1). Pointer ptr0 and pointer ptr1 are used to indicate the address of the read operation or the write operation, which will be described in detail below.

In some embodiments, the number of the buffer segment buff_sec may be used as the starting address (e.g., Sa0=0, Sa1=2). In subsequent operations, the direct memory access circuit 100 obtains the corresponding buffer block number (e.g., Sa0=0 corresponds to buffer block buff0, Sa1=2 corresponds to buffer block buff8) by shifting the starting address Sa0 and the starting address Sa1 left by log ₂ X bits. Compared to storing the number of the buffer block, storing the number of the buffer segment buff_sec can save memory.

Please refer to FIG. 5, which is a flow chart of the write address generation circuit 120 writing the data Din into the buffer circuit 150, including the following steps.

Step S510: The write address generation circuit 120 obtains data Din from the target device, that is, reads the corresponding first data or second data from the target device according to the read request Req0 or the read request Req1.

Step S520: The write address generation circuit 120 determines whether the current write operation is the first burst write, that is, whether the data corresponding to a read request Req is written into the buffer circuit 150 for the first time. If yes, execute step S530; if not, execute step S540.

Step S530: The write address generation circuit 120 resets the write count value wr_cnt (for example, sets the write count value wr_cnt to 0). More specifically, the write address generation circuit 120 obtains the corresponding write count value wr_cnt from the write status table 220 according to whether the data Din belongs to the read request Req0 or the read request Req1, and resets the corresponding write count value wr_cnt.

Step S540: Determine the write address wr_addr according to the start address addr_start and the write count value wr_cnt. More specifically, the write address wr_addr is equal to the start address addr_start plus the write count value wr_cnt.

Step S550: The write address generation circuit 120 writes the data to be written wr_data (i.e., data Din or a part of data Din) into the write address wr_addr of the buffer circuit 150, and controls the read address generation circuit 130 to update the corresponding read status flag rd_flg. More specifically, the read address generation circuit 130 updates the read status flag rd_flg corresponding to the write address wr_addr according to the write address wr_addr. For example, if the write address wr_addr corresponds to the buffer segment buff_sec1 (i.e., the write address wr_addr is one of the buffer blocks buff4 to buff7), the read address generation circuit 130 updates the read status flag bit rd_flg of the buffer segment buff_sec1 to 1.

Step S560: The write address generation circuit 120 updates the write count value wr_cnt, that is, adds 1 to the write count value wr_cnt0 or the write count value wr_cnt1.

Please refer to Figures 6 to 8, which show an example of the buffer circuit 150, the buffer segment status table 210, the write status table 220 and the read status table 230 according to the process of Figure 5.

FIG6 (continued from FIG4) shows that the write address generation circuit 120 writes the first data corresponding to the read request Req0 into the buffer block buff0 (equivalent to executing the process of FIG5 once). Because at this time, the buffer segment buff_sec0 has written one data, so the value of the read status flag bit rd_flg of the buffer segment buff_sec0 is 1 (step S550), and the write count value wr_cnt0 is 1 (step S560).

FIG7 (continued from FIG6) shows that the write address generation circuit 120 writes the first data corresponding to the read request Req1 into the buffer block buff8. Because one data has been written into the buffer block buff8 at this time, the value of the read status flag bit rd_flg of the buffer segment buff_sec2 is 1 (step S550), and the write count value wr_cnt1 is 1 (step S560).

FIG8 (following FIG7) shows that the write address generation circuit 120 writes the 2nd to 5th data corresponding to the read request Req1 into the buffer blocks buff9 to buff12 (equivalent to executing the process of FIG5 4 times in a row). Because at this time, 4 data have been written into the buffer segment buff_sec2 and 1 data has been written into the buffer segment buff12, the value of the read status flag bit rd_flg of the buffer segment buff_sec2 is 4, the value of the read status flag bit rd_flg of the buffer segment buff_sec3 is 1, and the write count value wr_cnt1 is 5.

FIG6 to FIG8 show that the direct memory access circuit 100 can process the read request Req0 and the read request Req1 in a disordered manner, because the write address generation circuit 120 does not process all the first data before processing the second data.

FIG9 is a flow chart of the control circuit 140 reading data from the buffer circuit 150, including the following steps.

Step S910: The read address generation circuit 130 obtains the read count value rd_cnt0 of the channel 160 according to the starting address Sa0 of the channel 160.

(0為讀取 地址，4為前述的粒度X)。 Step S920: The read address generation circuit 130 determines the read address according to the start address Sa0 and the read count value rd_cnt0, and determines the target buffer corresponding to the read address. Please refer to FIG. 10 (continued from FIG. 8), at this time, the read address corresponding to the channel 160 is Sa0+rd_cnt0=0+0=0 (i.e., the address pointed to by the pointer ptr0), and the target buffer corresponding to the pointer ptr0 is

(0 is the read address, 4 is the aforementioned granularity X).

Step S930: The read address generation circuit 130 determines whether the read status flag bit rd_flg of the target buffer is greater than 0. If yes (indicating that there is unread data in the target buffer), step S940 is executed; if no, steps S910 to S930 are repeated until there is unread data in the target buffer. In the example of FIG10 , because the read status flag bit rd_flg of the target buffer (i.e., buffer buff_sec0) is 1, the judgment result of step S930 is yes.

Step S940: The read address generation circuit 130 generates a read command rd_cmd0 to read the data in the target buffer buff_sec0.

。因為目標緩衝段(即，緩衝段buff_sec2)的讀狀態標誌位rd_flg為4，所以步驟S935的判斷結果為是，且讀地址生成電路130產生讀取命令rd_cmd1以讀取目標緩衝段buff_sec2中的資料(步驟S945)。 Steps S915 to S945 correspond to the operation of the second channel, and the contents are similar or identical to steps S910 to S940. For example, in FIG. 10 , the read address of channel 170 is Sa1+rd_cnt1=8+0=8 (i.e., the address pointed to by pointer ptr1), and the target buffer is

Since the read status flag rd_flg of the target buffer (ie, buffer buff_sec2) is 4, the determination result of step S935 is yes, and the read address generation circuit 130 generates a read command rd_cmd1 to read the data in the target buffer buff_sec2 (step S945).

Step S950: The control circuit 140 arbitrates between the read command rd_cmd0 and the read command rd_cmd1 according to a predetermined arbitration rule (e.g., a round-robin system) to generate a target read command rd_cmd. Continuing with the above example, if the target read command rd_cmd is the read command rd_cmd0 (rd_cmd1), the target read address rd_addr is the address pointed to by the pointer ptr0 (ptr1).

Step S960: The control circuit 140 issues a target read command rd_cmd to read data from the buffer circuit 150, and controls the read address generation circuit 130 to update the corresponding read count value rd_cnt and the read status flag bit rd_flg (equivalent to the read address generation circuit 130 updating the corresponding read count value rd_cnt and updating the read status flag bit rd_flg according to the target read address rd_addr). Please refer to Figure 11 (Continued from Figure 10), assuming that the target read command rd_cmd is the read command rd_cmd0, the control circuit 140 reads the data of the buffer block buff0, and the read address generation circuit 130 adds 1 to the read count value rd_cnt0 (i.e., rd_cnt0 changes from 0 to 1) and reduces 1 to the read status flag rd_flg of the target buffer segment buff_sec0 (i.e., rd_flg changes from 1 to 0).

As shown in FIG11 , since the first data currently only has data in the buffer block buff0 and has been read (i.e., the read status flag bit rd_flg of the buffer segment buff_sec0 is 0), the judgment result of the next step S930 is always negative until the direct memory access circuit 100 receives more first data from the target device. At this time, since the channel 160 does not generate a read command temporarily, the control circuit 140 continues to use the read command rd_cmd1 generated by the channel 170 as the target read command rd_cmd (step S950) until the channel 160 generates a read command rd_cmd0 again or the second data has been read.

FIG. 12 and FIG. 13 show that the control circuit 140 continuously reads the second data. FIG. 12 (continued from FIG. 11) shows that the four data of the buffer segment buff_sec2 have been read; therefore, the read status flag bit rd_flg of the buffer segment buff_sec2 changes from 4 to 0, and the read count value rd_cnt1 changes from 0 to 4. FIG. 13 (continued from FIG. 12) shows that the control circuit 140 further reads one data of the buffer segment buff_sec3; therefore, the read status flag bit rd_flg of the buffer segment buff_sec3 changes from 1 to 0, and the read count value rd_cnt1 changes from 4 to 5. At this time, because the read count value rd_cnt1 and the data length Ln1 are both equal to 5, the control circuit 140 knows that the second data has been read.

It should be noted that after the control circuit 140 has read the last data of a buffer buff_sec, the control circuit 140 updates the write status flag wr_flg corresponding to the buffer buff_sec (i.e., resets the write status flag wr_flg to 1). More specifically, because the buffer buff_sec2 has 4 data to be read, the control circuit 140 can reset the write status flag wr_flg corresponding to the buffer buff_sec2 to 1 only after the control circuit 140 has read the data of the buffer block buff11 (Figure 12). Next, because there is only one piece of data to be read in the buffer segment buff_sec3, after the control circuit 140 finishes reading the data in the buffer block buff12, the control circuit 140 resets the write status flag wr_flg corresponding to the buffer segment buff_sec3 to 1 (Figure 13).

After the second data is read (FIG. 13), the write address generation circuit 120 receives the first data corresponding to the read request Req0 and writes it into the buffer circuit 150, as shown in FIG. 14 and FIG. 15 (please refer to the flow chart of FIG. 5). FIG. 14 (following FIG. 13) shows that the write address generation circuit 120 writes the second data of the first data into the buffer block buff1, so the read status flag bit rd_flg of the buffer segment buff_sec0 changes from 0 to 1, and the write count value wr_cnt0 changes from 1 to 2. FIG15 (continued from FIG14) shows that the write address generation circuit 120 continues to write 2 data in the buffer buff_sec0, and then writes another 2 data in the buffer buff_sec1, so the read status flag rd_flg of the buffer buff_sec0 changes from 1 to 3, the read status flag rd_flg of the buffer buff_sec1 changes from 0 to 2, and the write count value wr_cnt0 changes from 2 to 6.

As shown in FIG15 , because the read status flag bit rd_flg of the buffer segment buff_sec0 is greater than 0 (i.e., the judgment result of step S930 in FIG9 is yes), the subsequent control circuit 140 will read the first data. As shown in FIG16 (following FIG15 ), because the read count value rd_cnt0=1, the control circuit 140 will start to read data in sequence from the buffer block buff1 (i.e., Sa0+rd_cnt0=0+1=1) (i.e., repeatedly execute the process of FIG9 ). Figure 17 (continued from Figure 16) shows the state after the first data is read. At this time, the write status flag wr_flg of buffer buff_sec0 and buffer buff_sec1 becomes 1, the read status flag rd_flg of buffer buff_sec0 and buffer buff_sec1 becomes 0, and the read count value rd_cnt0 becomes 6.

In summary, the present invention can improve the performance of direct memory access circuits. More specifically, even if a channel encounters data delay (for example, FIG. 6 to FIG. 8, the first data is delayed), the writing and reading of the data of the other channel will not be affected (as shown in FIG. 11 to FIG. 13, when the first data is delayed, the second data can still be smoothly written and read). In addition, the writing of the first data can be interrupted (as shown in the above implementation, the first part (for example, buffer block buff0) and the second part (for example, buffer block buff1 to buffer block buff5) of the first data are not continuously written), and the reading of the first data can also be interrupted (as shown in the above implementation, the first data is not continuously read out).

FIG18 is a flow chart showing an embodiment of the operation method of the direct memory access circuit of the present invention, which includes the following steps.

Step S1810: The write state determination circuit 110 determines the first starting address (e.g., starting address Sa0) from the buffer circuit 150 according to the first read request (e.g., read request Req0) of the first channel (e.g., channel 160), and the first read request corresponds to the first data.

Step S1820: The write state determination circuit 110 determines the second starting address (e.g., starting address Sa1) from the buffer circuit 150 according to the second read request (e.g., read request Req1) of the second channel (e.g., channel 170), and the second read request corresponds to the second data. For details of step S1810 and step S1820, please refer to the description of Figures 2 to 4.

Step S1830: The read address generation circuit 130 determines the read address according to the first start address and the first read count value (e.g., read count value rd_cnt0). Please refer to FIG. 9 for details of step S1830.

Step S1840: The control circuit 140 reads the first part of the first data from the buffer circuit 150 according to the read address, and updates the first read count value. Step S1840 may correspond to FIG. 10 to FIG. 11.

Step S1850: After reading the first part of the first data, the control circuit 140 reads at least a part of the second data from the buffer circuit 150. Step S1840 may correspond to FIG. 11 to FIG. 12 or FIG. 11 to FIG. 13.

Step S1860: After at least a portion of the second data is read, the read address generation circuit 130 updates the read address according to the first start address and the updated first read count value. Please refer to FIG. 9 for details of step S1860.

Step S1870: The control circuit 140 reads a second part of the first data from the buffer circuit according to the updated read address. Step S1870 may correspond to FIG. 16 to FIG. 17.

The operation method of the direct memory access circuit of the present invention may also include step S1855 of FIG. 19: after the at least a portion of the second data is read (i.e., step S1850) and before the second portion of the first data is read (i.e., step S1870), the write address generation circuit 120 writes the second portion of the first data into the buffer circuit. Step S1855 may correspond to FIG. 14 to FIG. 15.

It should be noted that step S1855 is not necessary (i.e., the writing of the first data may not be interrupted). More specifically, in some embodiments, even if the first data is read only after it is written into the buffer circuit 150, the reading of the first data by the control circuit 140 may be interrupted due to step S950 of FIG. 9 (i.e., corresponding to step S1840 to step S1870 of FIG. 18). For example, assuming that both the first data and the second data have been written into the buffer circuit 150 but have not been read (as shown in FIG. 20 ), the target read command rd_cmd generated by arbitration in step S950 may be in the following order: read command rd_cmd0 (read buffer segment buff_sec0) → read command rd_cmd1 (read buffer segment buff_sec2) → read command rd_cmd0 (read buffer segment buff_sec1) → read command rd_cmd1 (read buffer segment buff_sec3); in other words, the first data is not read continuously.

A person with ordinary knowledge in this technical field can implement the write state determination circuit 110, the write address generation circuit 120, the read address generation circuit 130 and the control circuit 140 with a logic circuit according to the above discussion.

Although the above-mentioned embodiment uses two channels as an example, this is not a limitation of the present invention. People skilled in the art can appropriately apply the present invention to more channels based on the disclosure of the present invention.

In addition, those with ordinary knowledge in the art can also apply the present invention to the case where at least one of the read operation and write operation of a single channel is out of order based on the above discussion. In other words, the write operation (or read operation) of channel 160 and the write operation (or read operation) of channel 170 are regarded as write operations (or read operations) of different data parts of the same channel.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field may make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

S1810,S1820,S1830,S1840,S1850,S1860,S1870: Steps

Claims (18)

A method for operating a direct memory access circuit includes a buffer circuit, a first channel and a second channel. The method includes: determining a first starting address from the buffer circuit according to a first read request of the first channel, wherein the first read request corresponds to a first data; determining a second starting address from the buffer circuit according to a second read request of the second channel, wherein the second read request corresponds to a second data; determining a read address according to the first starting address and a first read count value; and reading the first data from the buffer circuit according to the read address. a first portion of the data and updates the first read count value; after reading the first portion of the first data, read at least a portion of the second data from the buffer circuit according to the second start address; update the read address according to the first start address and the updated first read count value; and read a second portion of the first data from the buffer circuit according to the updated read address; wherein the direct memory access circuit further includes a second read count value, the second read count value corresponds to the second start address, and the second read count value is not equal to the first read count value. The method of claim 1 further comprises: after reading the at least a portion of the second data and before reading the second portion of the first data, writing the second portion of the first data into the buffer circuit. As in the method of claim 1, the buffer circuit includes a plurality of buffer segments, each buffer segment corresponds to a write status flag bit, and the write status flag bit is used to indicate whether the buffer segment corresponding to the write status flag bit is not used. The method further includes: determining a first buffer segment from the buffer segments according to a data amount of the first data and the write status flag bits; wherein the first starting address is a starting address of the first buffer segment, and the first buffer segment is used to store the first data. The method of claim 3 further includes: after determining the first buffer segment, updating the write status flag corresponding to the first buffer segment. As in the method of claim 1, the buffer circuit includes a first buffer segment for storing the first part of the first data, the first buffer segment has a read status flag bit, and the read status flag bit is used to indicate whether there is any unread data in the first buffer segment. The method further includes: before reading the first part of the first data, determining whether to read the first part of the first data from the first buffer segment according to the read status flag bit. The method of claim 5 further comprises: writing the first part of the first data into the first buffer; and updating the read status flag when the data is written into the first buffer. The method of claim 5 further includes: after reading the first part of the first data, updating the read status flag. The method of claim 1 further includes: after reading the first part of the first data, updating the first read count value. The method of claim 1 further comprises: writing the first part of the first data into the buffer circuit according to the first starting address and a write count value; and updating the write count value after writing the first part of the first data. A direct memory access circuit includes: a buffer circuit; a first channel for generating a first read request; a second channel for generating a second read request; a write state determination circuit for determining a first starting address from the buffer circuit according to the first read request, and a second starting address from the buffer circuit according to the second read request, wherein the first read request corresponds to a first data, and the second read request corresponds to a second data; a read address generation circuit for determining a read address according to the first starting address and a first read count value; and a control circuit for reading the first data from the buffer circuit according to the read address. a first part of the first data, controlling the read address generation circuit to update the first read count value, and after reading the first part of the first data, reading at least a part of the second data from the buffer circuit according to the second starting address; Wherein, the read address generation circuit further updates the read address according to the first starting address and the updated first read count value, and the control circuit further reads a second part of the first data from the buffer circuit according to the updated read address; wherein, the read address generation circuit further stores a second read count value, the second read count value corresponds to the second starting address, and the second read count value is not equal to the first read count value. The direct memory access circuit of claim 10 further comprises: a write address generation circuit for writing the second portion of the first data into the buffer circuit after the at least a portion of the second data is read and before the second portion of the first data is read. As in claim 10, the direct memory access circuit includes a plurality of buffer segments, each buffer segment corresponds to a write status flag bit, and the write status flag bit is used to indicate whether the buffer segment corresponding to the write status flag bit is not used. The write status determination circuit further determines a first buffer segment from the buffer segments for storing the first data according to a data amount of the first data and the write status flag bits, and the first starting address is a starting address of the first buffer segment. A direct memory access circuit as claimed in claim 12, wherein the write status determination circuit further updates the write status flag corresponding to the first buffer segment after determining the first buffer segment. A direct memory access circuit as claimed in claim 10, wherein the buffer circuit includes a first buffer segment for storing the first part of the first data, the first buffer segment has a read status flag bit, the read status flag bit is used to indicate whether there is any unread data in the first buffer segment, and the read address generation circuit is before the control circuit reads the first part of the first data, and determines whether to read the first part of the first data from the first buffer segment according to the read status flag bit. A direct memory access circuit as claimed in claim 14, wherein the direct memory access circuit further comprises a write address generation circuit, the write address generation circuit is used to write the first part of the first data into the first buffer, and the read address generation circuit further updates the read status flag bit when the data is written into the first buffer. A direct memory access circuit as claimed in claim 14, wherein the read address generation circuit further updates the read status flag after the first portion of the first data is read. A direct memory access circuit as claimed in claim 10, wherein the read address generation circuit further updates the first read count value after the first portion of the first data is read. The direct memory access circuit of claim 10 further comprises: a write address generation circuit for writing the first part of the first data into the buffer circuit according to the first starting address and a write count value, and updating the write count value.

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