TWI840189B - Pixel structure - Google Patents

Abstract

A pixel structure includes a substrate, a first metal pattern, a gate insulating layer, a semiconductor pattern, a second metal pattern and a pixel electrode. The first metal pattern includes a scan line, a gate and a common electrode. The gate insulating layer covers the first metal pattern. The semiconductor pattern is located on the gate insulating layer, and includes a semiconductor channel, a data line carrier part, a capacitor electrode, a first connection line and a second connection line. The second metal pattern is directly located on the semiconductor pattern and includes a data line, a source and a drain. The total capacitance of the pixel structure is C _total, and the capacitance value of the metal-insulator-semiconductor (MIS) capacitor generated by a stack of the common electrode, the gate insulating layer, the semiconductor pattern and the drain is C _MIS, and the ratio of C _MISto C _totalis R, 10% ＞R＞0%.

Description

Pixel structure

The present invention relates to a pixel structure.

With the advancement of technology, display devices have been widely used in people's lives. Generally speaking, a display device includes many pixel structures, and the thin film transistor (TFT) in the pixel structure is used to control light-emitting elements, liquid crystals, electrophoretic particles, etc., so that the display device can display various images.

In the existing technology, lithography and etching processes are used to form each film layer in a thin film transistor. For example, after depositing a conductive material or a semiconductor material, a lithography process is used to form a patterned photoresist layer on the conductive material or the semiconductor material, and then the conductive material or the semiconductor material located below is etched using the patterned photoresist layer as a mask to obtain a patterned conductive layer or a patterned semiconductor layer. Generally speaking, the lithography process requires the use of a mask. However, the design and production of the mask often takes a lot of time and money. Therefore, in order to save the manufacturing cost of thin film transistors, many manufacturers are committed to reducing the number of masks required to manufacture thin film transistors.

The present invention provides a pixel structure that can save production costs and reduce the Just Noticeable Difference (JND) of a display device by adjusting the ratio of C _MIS to C _total .

At least one embodiment of the present invention provides a pixel structure, which includes a substrate, a first metal pattern, a gate insulating layer, a semiconductor pattern, a second metal pattern and a pixel electrode. The first metal pattern is located on the substrate and includes a scan line, a gate connecting the scan line and a common electrode. The gate insulating layer covers the first metal pattern. The semiconductor pattern is located on the gate insulating layer and includes a semiconductor channel, a data line carrying part, a capacitor electrode, a first connecting line connecting the data line carrying part and the semiconductor channel, and a second connecting line connecting the semiconductor channel and the capacitor electrode. The semiconductor channel overlaps the gate. The second metal pattern is directly located on the semiconductor pattern and includes a data line, a source and a drain. The data line is directly located on the data line carrier. The source is connected to the data line and is directly located on the semiconductor channel. The drain is directly located on the semiconductor channel, the first connection line and the capacitor electrode. The pixel electrode is electrically connected to the drain. The total capacitance of the pixel structure is C _total , and the capacitance value of the metal-insulator-semiconductor (MIS) capacitor generated by the stacking of the common electrode, the gate insulation layer, the semiconductor pattern and the drain is C _MIS , and the ratio of C _MIS to C _total is R, 10%>R>0%.

1: Display device

10,20,30,40,50: Pixel structure

100: Substrate

110: The first metal pattern

112: Scan line

114: Gate

116: Shared electrode

116a: Electrode part

116b: Main Branch

116c: First branch

116d: Second branch

116h: Opening

120: Gate insulation layer

130: Semiconductor pattern

132: Data line carrier

133: First connection line

134: Semiconductor channel

135: Second connection line

136: Capacitor electrode

140: Second metal pattern

142: Data line

144: Source

146: Drainage

146a: Extension

146b: Connection part

150: Dielectric layer

151:Through hole

160: Pixel electrode

B: Black Zone

D1: First direction

D2: Second direction

ND: Normal direction

W: White area

FIG1A is a top view schematic diagram of a pixel structure according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

Figure 2A is a top view schematic diagram of a pixel structure according to an embodiment of the present invention.

FIG2B is a schematic cross-sectional view along line A-A’ of FIG2A .

FIG3A is a top view schematic diagram of a pixel structure according to a comparative example of the present invention.

FIG3B is a schematic cross-sectional view along line A-A’ of FIG3A .

FIG4A is a top view schematic diagram of a pixel structure according to an embodiment of the present invention.

FIG4B is a schematic cross-sectional view along line A-A’ of FIG4A .

Figure 5A is a top view schematic diagram of a pixel structure according to an embodiment of the present invention.

FIG5B is a schematic cross-sectional view along line A-A’ of FIG5A .

Figures 6A and 6B are top-view schematic diagrams of a display device testing method according to the present invention.

Figures 7A, 7B and 8 are data graphs of the brightness of the display screen and the voltage of the common electrode (Vcom) of the display device including the pixel structure.

FIG. 1A is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line A-A' of FIG. 1A. Referring to FIG. 1A and FIG. 1B, the pixel structure 10 includes a substrate 100, a first metal pattern 110, a gate insulating layer 120, a semiconductor pattern 130, a second metal pattern 140, and a pixel electrode 160. In this embodiment, the pixel structure 10 further includes a dielectric layer 150.

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems.

The first metal pattern 110 is located on the substrate 100. The first metal pattern 110 is a single-layer or multi-layer structure. In some embodiments, the material of the first metal pattern 110 includes metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, etc., the above alloys or other suitable metal materials. In some embodiments, the method of forming the first metal pattern 110 includes: depositing one or more layers of metal material on the substrate 100; using a lithography process to form a patterned photoresist layer on the aforementioned one or more layers of metal material, and then using the patterned photoresist layer as a mask to etch one or more layers of metal material located thereunder, thereby obtaining the first metal pattern 110.

The first metal pattern 110 includes a scan line 112, a gate 114 connected to the scan line 112, and a common electrode 116. The scan line 112 and the common electrode 116 are separated from each other, and both extend along the first direction D1. In this embodiment, the common electrode 116 includes an electrode portion 116a, a main trunk 116b, two first branch portions 116c, and two second branch portions 116d. The electrode portion 116a is located on a side of the common electrode 116 close to the gate 114. One end of the main trunk 116b is connected to the electrode portion 116a, and extends from the electrode portion 116a along the second direction D2. In some embodiments, the first direction D1 is substantially perpendicular to the second direction D2. The two first branches 116c extend outward from both sides of the main trunk 116b, and the two first branches 116c are substantially parallel to the first direction D1. The two second branches 116d are respectively connected to the two first branches 116c, and the two first branches 116c respectively connect the two second branches 116d to the main trunk 116b. The two second branches 116d are substantially parallel to the second direction D2.

In some embodiments, the first branch portion 116c extends beyond the second branch portion 116d and is connected to a common electrode (not shown) of other adjacent pixel structures (not shown).

The gate insulating layer 120 covers the first metal pattern 110. In some embodiments, the material of the gate insulating layer 120 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material or other suitable materials or a combination thereof. In some embodiments, the thickness of the gate insulating layer 120 is 0.2 microns to 0.3 microns.

The semiconductor pattern 130 is located on the gate insulating layer 120. The semiconductor pattern 130 is a single-layer or multi-layer structure. In some embodiments, the material of the semiconductor pattern 130 includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials.

The semiconductor pattern 130 includes a data line carrier 132, a first connection line 133, a semiconductor channel 134, a second connection line 135, and a capacitor electrode 136. The data line carrier 132 extends along the second direction D2. The semiconductor channel 134 overlaps the gate 114 in the normal direction ND of the surface of the substrate 100. The first connection line 133 extends outward from one side of the data line carrier 132 and connects the data line carrier 132 and the semiconductor channel 134. In some embodiments, the width of the first connection line 133 is less than or equal to the width of the data line carrier 132, but the present invention is not limited thereto. The capacitor electrode 136 completely overlaps or partially overlaps the electrode portion 116a of the common electrode 116 in the normal direction ND of the surface of the substrate 100. In this embodiment, the capacitor electrode 136 completely overlaps the electrode portion 116a. The second connection line 135 connects the semiconductor channel 134 and the capacitor electrode 136. In some embodiments, the width of the second connection line 135 is smaller than the width of the semiconductor channel 134 and the width of the capacitor electrode 136, but the present invention is not limited thereto.

The second metal pattern 140 is directly located on the semiconductor pattern 130. The second metal pattern 140 is a single-layer or multi-layer structure. In some embodiments, the material of the second metal pattern 140 includes metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, etc., the above alloys or other suitable metal materials.

The second metal pattern 140 includes a data line 142, a source 144, and a drain 146. The data line 142 is directly located on the data line carrier 132 and extends along the second direction D2. The width of the data line 142 is less than or equal to the width of the data line carrier 132.

The source 144 is connected to the data line 142 and is directly located on the semiconductor channel 134 and the first connection line 133. The drain 146 is directly located on the semiconductor channel 134, the second connection line 135 and the capacitor electrode 136. The source 144 and the drain 146 are separated from each other. In this embodiment, the drain 146 includes an extension 146a directly located on the semiconductor channel 134 and the second connection line 135 and a connection portion 146b directly located on the capacitor electrode 136. The width of the connection portion 146b is greater than the width of the extension portion 146a, and the connection portion 146b completely overlaps or partially overlaps the common electrode 116 in the normal direction ND of the surface of the substrate 100.

In some embodiments, the method of forming the semiconductor pattern 130 and the second metal pattern 140 includes: depositing one or more layers of semiconductor material on the gate insulation layer 120; depositing one or more layers of metal material on the aforementioned one or more layers of semiconductor material; using a lithography process to form a patterned photoresist layer on the aforementioned one or more layers of metal material, and then using the patterned photoresist layer as a mask to etch one or more layers of metal material and one or more layers of semiconductor material located therebelow, thereby obtaining the second metal pattern 140 and the semiconductor pattern 130. In some embodiments, a portion of the photoresist layer is formed at the gap between the source 144 and the drain 146. By making the thickness of the photoresist layer at the gap between the source 144 and the drain 146 smaller than the thickness of other portions of the photoresist layer, the etching process can be controlled to remove the metal material between the source 144 and the drain 146 while retaining the semiconductor channel 134 between the source 144 and the drain 146.

In this embodiment, since the number of masks required for the process of forming the semiconductor pattern 130 and the second metal pattern 140 is only one, the manufacturing cost of the pixel structure 10 can be greatly saved.

In some embodiments, due to the difference in etching rate, the outer sidewall of the semiconductor pattern 130 of the pixel structure 10 exceeds the outer sidewall of the second metal pattern 140.

The dielectric layer 150 is located on the second metal pattern 140. The dielectric layer 150 has a through hole 151 overlapping the drain 146 and the capacitor electrode 136. In some embodiments, the material of the dielectric layer 150 includes an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, uranium oxide, aluminum oxide, other suitable materials, or a stacking layer of at least two of the above materials), an organic material or other suitable materials or a combination of the above. In some embodiments, the thickness of the dielectric layer 150 is 0.2 microns to 0.3 microns, but the present invention is not limited thereto. In other embodiments, in order to prevent capacitive coupling, the thickness of the dielectric layer 150 can be increased to 3 microns.

The pixel electrode 160 is located on the dielectric layer 150 and is electrically connected to the drain 146 through the through hole 151 of the dielectric layer 150. The pixel electrode 160 includes a transparent material or a reflective material. In some embodiments, the pixel electrode 160 includes a metal material, a metal oxide material (such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, etc.), a metal nitride material, a combination of the foregoing materials, or other suitable materials.

In this embodiment, the total capacitance of the pixel structure 10 is C _total . More specifically, the total capacitance generated by the first metal pattern 110 , the gate insulating layer 120 , the semiconductor pattern 130 , the second metal pattern 140 , the dielectric layer 150 and the pixel electrode 160 is C _total . The total capacitance value formed by the dielectric layer/insulating layer between each conductive layer in the pixel structure 10 is C _total .

In the present embodiment, the capacitance value of the metal-insulator-semiconductor capacitor generated by the stacking of the common electrode 116, the gate insulating layer 120, the semiconductor pattern 130 and the drain 146 is C _MIS . In the present embodiment, C _MIS includes the capacitance in the region where the common electrode 116, the gate insulating layer 120, the capacitor electrode 136 and the drain 146 overlap each other. In some embodiments, a ground voltage or other constant voltage is applied to the common electrode, and a gate voltage is applied to the scanning line 112. Since the voltage on the scan line 112 is not constant, the capacitance generated by the stack of the scan line 112, the data line carrier 132 and the data line 142 can be ignored. In addition, since the overlapping area of the common electrode 116, the data line carrier 132 and the data line 142 is very small, the capacitance generated by the stack of the common electrode 116, the data line carrier 132 and the data line 142 can be ignored.

Since the semiconductor pattern 130 may change in electrical properties due to long-term use, thereby changing _CMIS . Generally speaking, _CMIS can be reduced to avoid the change in _CMIS affecting the storage capacitor of the pixel, thereby avoiding the problem of the screen caused by the offset of the storage capacitor. However, if _CMIS is completely removed, the storage capacitor will be insufficient, making the signal on the pixel electrode 160 susceptible to crosstalk, and the display screen may easily show uneven brightness marks (or, for example, image sticking problems) after long-term use.

In some embodiments of the present invention, _CMIS can be adjusted by replacing different materials or changing the thickness of the film layer. In addition, _CMIS can also be changed and adjusted by changing the overlapping area of the common electrode 116, the gate insulating layer 120, the capacitor electrode 136 and the drain 146. The smaller the overlapping area of the common electrode 116, the gate insulating layer 120, the capacitor electrode 136 and the drain 146, the smaller the _CMIS .

By adjusting the ratio R of C _MIS to C _total , the problem of uneven brightness of the display device after long-term use can be improved, and the Just Noticeable Difference (JND) of the display device can be reduced. In some embodiments, 10%>R>0%, preferably 10%>R>5%.

FIG2A is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG2B is a schematic cross-sectional view along line A-A' of FIG2A. It must be noted that the embodiments of FIG2A and FIG2B use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the pixel structure 20 of FIG. 2A and FIG. 2B and the pixel structure 10 of FIG. 1A and FIG. 1B is that the capacitor electrode 136 of the pixel structure 10 completely overlaps the electrode portion 116a of the common electrode 116, while the capacitor electrode 136 of the pixel structure 20 partially overlaps the electrode portion 116a of the common electrode 116.

In this embodiment, by reducing the overlapping area between the capacitor electrode 136 and the common electrode 116, C _MIS can be reduced, thereby reducing the ratio R of C _MIS to C _total .

FIG3A is a schematic top view of a pixel structure according to a comparative example of the present invention. FIG3B is a schematic cross-sectional view along line A-A' of FIG3A. It must be noted that the comparative examples of FIG3A and FIG3B use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the pixel structure 30 of FIG. 3A and FIG. 3B and the pixel structure 10 of FIG. 1A and FIG. 1B is that the capacitor electrode 136 of the pixel structure 10 completely overlaps the electrode portion 116a of the common electrode 116, while the capacitor electrode 136 of the pixel structure 30 does not overlap the common electrode 116 at all.

In the comparative example, the capacitor electrode 136 does not overlap the common electrode 116 at all, and C _MIS is substantially 0. Since C _MIS is 0, the pixel electrode 160 of the pixel structure 30 is easily affected by cross talk, and the display screen of the display device including the pixel structure 30 is prone to uneven brightness after long-term use.

FIG4A is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG4B is a schematic cross-sectional view along line A-A' of FIG4A. It must be noted that the embodiments of FIG4A and FIG4B use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the pixel structure 40 of FIG. 4A and FIG. 4B and the pixel structure 10 of FIG. 1A and FIG. 1B is that the capacitor electrode 136 of the pixel structure 10 completely overlaps the electrode portion 116a of the common electrode 116, while the capacitor electrode 136 of the pixel structure 40 partially overlaps the common electrode 116.

4A and 4B , in this embodiment, the connection portion 146b of the drain 146 and the capacitor electrode 136 of the semiconductor pattern 130 partially overlap the electrode portion 116a of the common electrode 116. The electrode portion 116a of the common electrode 116 has an opening 116h that overlaps the connection portion 146b and the capacitor electrode 136. In this embodiment, the design of the opening 116h can reduce the overlapping area of the capacitor electrode 136 and the common electrode 116, thereby reducing C _MIS and the ratio R of C _MIS to C _total .

FIG5A is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG5B is a schematic cross-sectional view along line A-A' of FIG5A. It must be noted that the embodiments of FIG5A and FIG5B use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the pixel structure 50 of FIG. 5A and FIG. 5B and the pixel structure 10 of FIG. 1A and FIG. 1B is that the outer sidewall of the semiconductor pattern 130 of the pixel structure 10 exceeds the outer sidewall of the second metal pattern 140, while the outer sidewall of the semiconductor pattern 130 of the pixel structure 50 is aligned with the outer sidewall of the second metal pattern 140.

6A and 6B are top views of a method for testing a display device according to the present invention. Specifically, a plurality of pixel structures disclosed in any of the aforementioned embodiments or comparative examples are combined with a backlight module (not shown), a liquid crystal layer (not shown), an opposing substrate (not shown), and an object electrode (not shown) on the opposing substrate to form a display device 1. Referring to FIG. 6A , the display device 1 is used to display a screen including a plurality of white areas W and a plurality of black areas B. The white area W is, for example, an area with a brightness of L255, and the black area B is, for example, an area with a brightness of L0. When the display device 1 is made to display a screen including a plurality of white areas W and a plurality of black areas B, the white areas W and the black areas B of the display device 1 are subjected to a high temperature treatment for a long time (for example, at a temperature of 50 to 60 degrees Celsius for 96 hours). Next, all white areas W and all black areas B of the display device 1 are switched to a grayscale screen, as shown in FIG6B . Then, the effect of the high temperature treatment on the brightness of the white areas W and the black areas B is measured.

FIG. 7A and FIG. 7B are data diagrams of the brightness (unit: Nit) of the display screen of the display device including the pixel structure and the voltage (Vcom) of the common electrode. The pixel structure in the display device corresponding to FIG. 7A is similar to the pixel structure in the comparative example of FIG. 3A and FIG. 3B, and C _MIS is approximately 0. The pixel structure in the display device corresponding to FIG. 7B is similar to the pixel structure in the embodiment of FIG. 1A and FIG. 1B, and the difference is only that the ratio R of C _MIS to C _total is adjusted to 60%.

As can be seen from FIG7A, if the display device has a C _MIS of approximately 0 (or a ratio R of C _MIS to C _total of 0), after undergoing the test method illustrated in FIGS. 6A and 6B, the black area will become relatively darker (darker) and the white area will become relatively whiter (brighter), causing traces of uneven brightness to appear on the display screen.

As can be seen from FIG. 7B , if a display device with a higher ratio R of C _MIS to C _total is used, after the test method illustrated in FIGS. 6A and 6B , the black area can become relatively whiter (brighter) and the white area can become relatively blacker (darker).

Combining FIG. 7A and FIG. 7B , it can be reasonably predicted that by adjusting the ratio R of C _MIS to C _total , the black area and the white area of the display device will not have uneven brightness after the test method shown in FIG. 6A and FIG. 6B . In some embodiments of the present invention, when 10%>R>0% (preferably 10%>R>5%), the aforementioned uneven brightness problem of the display screen can be improved.

FIG8 is a data graph of the brightness of the display screen of a display device including a pixel structure and the voltage of the common electrode (Vcom). FIG8 is similar to FIG7B, except that FIG8 is tested on a display screen with lower brightness in the test step of FIG6B. FIG8 shows that after the test method of the display device shown in FIG6A and FIG6B, the black area becomes white and the white area becomes black gradually converges as the voltage of the common electrode is increased, and even reverses to the black area becoming darker and the white area becoming whiter. Based on the results of FIG8, it can be seen that the appropriate voltage of the common electrode can be selected to make the black area and the white area have the same brightness.

Tables 1 to 3 provide the JND values of the display screen obtained after different high temperature treatment times (such as the high temperature treatment described in the relevant description of FIG _{. 6A} and FIG. 6B) of the display device having a pixel structure with different R values (ratio of C MIS to C total). Table 1 is operated in a manner that the display device after high temperature treatment will produce a picture with a grayscale brightness of L40 before the high temperature treatment, Table 2 is operated in a manner that the display device after high temperature treatment will produce a picture with a grayscale brightness of L128 before the high temperature treatment, and Table 3 is operated in a manner that the display device after high temperature treatment will produce a picture with a grayscale brightness of L180 before the high temperature treatment. Generally speaking, the higher the brightness of the display device, the less likely the display screen will have the problem of uneven brightness distribution. Vanishing grayscale refers to the brightness of the display device when it just does not produce uneven brightness distribution. The lower the vanishing grayscale, the less obvious the problem of uneven brightness distribution in the display device. Table 4 shows the vanishing grayscale value of the display device after high temperature treatment, where the vanishing grayscale is preferably less than 180.

From Tables 1 to 3, it can be seen that when the ratio of C _MIS to C _total is 6.1%, a lower thermal discrimination difference can be obtained. In addition, from Table 4, it can be seen that when the ratio of C _MIS to C _total is 6.1%, even if the display device is subjected to high temperature treatment for 169 hours, the vanishing gray level is still less than 180. However, if the ratio of C _MIS to C _total is too high (for example, 14.3% or 20.4%), the vanishing gray level will increase.

In summary, the present invention can improve the problem of uneven brightness of the display device after long-term use by adjusting the ratio R of C _MIS to C _total to 0%~10%, and can reduce the recognition error of the display device.

10: Pixel structure

110: The first metal pattern

112: Scan line

114: Gate

116: Shared electrode

116a: Electrode part

116b Main Branch

116c: First branch

116d: Second branch

130: Semiconductor pattern

132: Data line carrier

133: First connection line

134: Semiconductor channel

135: Second connection line

136: Capacitor electrode

140: Second metal pattern

142: Data line

144: Source

146: Drainage

146a: Extension

146b: Connection part

151:Through hole

160: Pixel electrode

D1: First direction

D2: Second direction

Claims (10)

A pixel structure includes: a substrate; a first metal pattern located on the substrate and including: a scan line; a gate connected to the scan line; and a common electrode; a gate insulating layer covering the first metal pattern; a semiconductor pattern located on the gate insulating layer and including: a semiconductor channel, a data line carrying portion, and a capacitor electrode, wherein the semiconductor channel overlaps the gate; a first connecting line connecting the data line carrying portion and the semiconductor channel ; and a second connection line connecting the semiconductor channel and the capacitor electrode; and a second metal pattern directly located on the semiconductor pattern and including: a data line directly located on the data line carrying portion; a source connected to the data line and directly located on the semiconductor channel; and a drain directly located on the semiconductor channel, the first connection line and the capacitor electrode; and a pixel electrode electrically connected to the drain, wherein the total capacitance of the pixel structure is C _total , and the capacitance value of the metal-insulator-semiconductor capacitance generated by the stacking of the common electrode, the gate insulating layer, the semiconductor pattern and the drain is C _MIS , and the ratio of C _MIS to C _total is R, 10%>R>0%. The pixel structure as described in claim 1 further comprises: a dielectric layer located on the second metal pattern, and the pixel electrode is located on the dielectric layer, wherein the total capacitance generated by the first metal pattern, the gate insulation layer, the semiconductor pattern, the second metal pattern, the dielectric layer and the pixel electrode is C _total . A pixel structure as described in claim 1, wherein the width of the data line is less than or equal to the width of the data line carrier. The pixel structure as described in claim 1, wherein 10%>R>5%. The pixel structure as described in claim 1, wherein the _CMIS includes a capacitor in a region where the common electrode, the gate insulating layer, the capacitor electrode and the drain overlap each other. A pixel structure as described in claim 1, wherein the drain includes an extension portion directly located on the second connection line and a connection portion directly located on the capacitor electrode, the width of the connection portion is greater than the width of the extension portion, and wherein the connection portion and the capacitor electrode completely overlap or partially overlap on the common electrode. A pixel structure as described in claim 6, wherein the connecting portion and the capacitor electrode partially overlap the common electrode, and the common electrode has an opening that overlaps the connecting portion and the capacitor electrode. A pixel structure as described in claim 1, wherein the source is directly located on the first connection line. The pixel structure as described in claim 1, wherein the common electrode comprises: an electrode portion, which completely overlaps or partially overlaps the capacitor electrode; a main trunk, wherein one end of the main trunk is connected to the electrode portion; two first branches, the two first branches respectively extend outward from both sides of the main trunk, wherein the two first branches are parallel to a first direction; and two second branches, wherein the two first branches are respectively connected to the two second branches to the main trunk, and the main trunk and the two second branches are parallel to a second direction. A pixel structure as described in claim 9, wherein the drain includes a connecting portion directly located on the capacitor electrode, wherein the electrode portion has an opening overlapping the connecting portion and the capacitor electrode.

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