TWI839031B - Inspection method and inspection system - Google Patents

Abstract

The present disclosure provides an inspection method for inspecting a semiconductor structure. The semiconductor structure includes a first conductive line, a second conductive line, first transistors connected to the first conductive line, second transistors connected to the second conductive line, and a first conductive line contact connected to the first conductive line. Each of the first transistors includes a first contact. Each of the second transistors includes a second contact. The inspection method includes a pre-charge operation, irradiating the first conductive line contact with an electron beam; an imaging operation, obtaining an image of the semiconductor structure; and a determining operation, determining whether the second contact of the second transistors becomes bright in the image, and in response to the second contact of the second transistors becomes bright, determing that there is a defect between the first conductive line and the second conductive line.

Description

Detection method and detection system

The present disclosure relates to a detection method, and in particular to a detection method for determining defects between conductive lines by using the light and dark states of source/drain contacts in a scanning electron microscope (SEM) image.

Electron beam inspection (EBI) is often used to inspect semiconductor device defects in-line. It uses scanning electron microscope (SEM) images to find defects on semiconductor devices through image processing.

However, as semiconductor devices and components are miniaturized, the size of defects is reduced, and it is becoming increasingly difficult to find defects from SEM images. For example, when the size of the defect only occupies a few pixels in the SEM image, it is very difficult to find the defect from the SEM image due to the limitation of resolution.

The disclosed embodiment provides a detection method for detecting a semiconductor structure. The semiconductor structure includes a first wire and a second wire extending along a first direction and spaced apart from each other along a second direction; a plurality of first transistors connected to the first wire, each of the plurality of first transistors including a first contact; a plurality of second transistors connected to the second wire, each of the plurality of second transistors including a second contact; and a first wire contact connected to the first wire. The detection method includes a pre-charging operation to irradiate the first wire contact with an electron beam; an imaging operation to obtain an image of the semiconductor structure; and a judgment operation to judge whether the second contact of any one of the plurality of second transistors becomes brighter in the image, and as a response to the second contact of any one of the plurality of second transistors becoming brighter in the image, it is judged that there is a defect between the first wire and the second wire.

The disclosed embodiment provides a semiconductor structure, including a first wire and a second wire, extending along a first direction and spaced apart from each other along a second direction; a plurality of first transistors connected to the first wire, each of the first transistors including a first contact; a plurality of second transistors connected to the second wire, each of the second transistors including a second contact; and a first wire contact connected to the first wire.

The disclosed embodiment provides a detection system for detecting the semiconductor structure. The detection system includes an electron beam emitting system having an electron source and a detector; a carrier configured to carry the semiconductor structure; and a processing device. The processing device performs a pre-charging operation, emitting an electron beam to a first wire contact of the semiconductor structure through the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons from the semiconductor structure through the detector to generate an image of the semiconductor structure; and a judgment operation, judging the light and dark state of the image to judge whether there is a defect between the first wire and the second wire of the semiconductor structure.

As the size of semiconductor devices shrinks, defects become smaller and smaller, and it becomes more difficult to directly find defects from SEM images using the EBI method. In view of this, the present disclosure provides an indirect detection method using voltage contrast (VC) to more easily and clearly find defects from SEM images using the EBI method.

The method provided by the present disclosure includes setting a plurality of wires (e.g., word lines) in parallel with each other. Each wire is respectively connected to (or serves as) the gate of a corresponding plurality of transistors. Then, the non-adjacent wires in the plurality of wires are pre-charged to turn on the transistors connected by the pre-charged wires. In this way, in the SEM image, the contacts of these transistors set on the source/drain region will produce a bright voltage contrast because they have more electrons, that is, they become "brighter" in the SEM image. On the other hand, because the transistors connected to the wires that are not pre-charged are still in the turn-off state, theoretically the contacts of these transistors should remain in the "dark" state in the SEM image.

However, if there are defects between these wires (e.g., cracks in the isolation structure), and conductive materials fill these defects to connect these wires together (e.g., short circuit), the wires that are not pre-charged will receive voltage because they are connected to the pre-charged wires. In this way, the transistors connected to the wires that are not pre-charged will be turned on, and the contacts of these transistors will also become brighter in the SEM image. Therefore, by observing whether these contacts that should remain in a "dark" state become "bright", it can be determined whether there are defects (e.g., short circuits) between the wires. In addition, because the size of the source/drain contact is much larger than the size of the defect, the presence of the defect can be more easily and clearly found from the SEM image.

1A , the semiconductor structure 100 includes a first conductive line 110, a second conductive line 112, and a third conductive line 114 extending along a first direction X and spaced apart from each other along a second direction Y. The semiconductor structure 100 further includes a plurality of first transistors 130, a plurality of second transistors 132, and a plurality of third transistors 134, each having a plurality of first contacts 140, a plurality of second contacts 142, and a plurality of third contacts 144 disposed on a source/drain region 120. The plurality of first transistors 130 are disposed along the first conductive line 110 (i.e., along the first direction X), and the two first contacts 140 of each first transistor 130 are disposed on both sides of the first conductive line 110 along the second direction Y. The plurality of second transistors 132 are disposed along the second wire 112, and the two second contacts 142 of each second transistor 132 are disposed on both sides of the second wire 112 along the second direction Y. The plurality of third transistors 134 are disposed along the third wire 114, and the two third contacts 144 of each third transistor 134 are disposed on both sides of the third wire 114 along the second direction Y.

In some embodiments, the first wire 110, the second wire 112, and the third wire 114 are word lines and respectively serve as gates of the first transistor 130, the second transistor 132, and the third transistor 134. In other embodiments, the first wire 110, the second wire 112, and the third wire 114 are respectively connected to the gates of the first transistor 130, the second transistor 132, and the third transistor 134. In the illustrated embodiment, the first transistor 130/the third transistor 134 and the second transistor 132 are arranged alternately along the first direction X. As shown in FIG. 1A , the first of the second transistors 132 is disposed in the first row, the first of the first transistors 130 / the third transistors 134 is disposed in the second row, the second of the second transistors 132 is disposed in the third row, and the second of the first transistors 130 / the third transistors 134 is disposed in the fourth row, and so on.

The semiconductor structure 100 also includes a first wire contact 150, a second wire contact 152, and a third wire contact 154, which are respectively disposed on the first wire 110, the second wire 112, and the third wire 114, and can be respectively connected to the first wire 110, the second wire 112, and the third wire 114, and are respectively used to precharge the first wire 110, the second wire 112, and the third wire 114. In some embodiments, the first wire contact 150, the second wire contact 152, and the third wire contact 154 are alternately disposed on both sides of the semiconductor structure 100 along the first direction X. For example, the first wire contact 150 and the third wire contact 154 are disposed on one side of the semiconductor structure 100, and the second wire contact 152 is disposed on the other side of the semiconductor structure 100. In an alternative embodiment, the semiconductor structure 100 may include only wire contacts disposed on one side. For example, the semiconductor structure 100 may include only the first wire contact 150 and the third wire contact 154, and does not include the second wire contact 152.

To simplify the description, FIG. 1A only shows three wires and corresponding wire contacts, transistors, and contacts disposed on the source/drain regions, but in practice the semiconductor structure 100 may have any number of wires, and each wire may be connected to any number of corresponding transistors and contacts.

1B , the semiconductor structure 100 includes a substrate 105 and an interlayer dielectric (ILD) layer 190 above the substrate 105. A first wire 110, a second wire 112, and a third wire 114 are disposed in the substrate 105. A first isolation structure 180, a second isolation structure 182, and a third isolation structure 184 are disposed in the substrate 105 and are disposed above the first wire 110, the second wire 112, and the third wire 114, respectively.

The first contact 140 (only one is shown in FIG. 1B ) is disposed above the source/drain region 120 of the substrate 105, in the ILD layer 190, and on both sides of the first conductive line 110. The third contact 144 (only one is shown in FIG. 1B ) is disposed above the source/drain region 120 of the substrate 105, in the ILD layer 190, and on both sides of the third conductive line 114. In the cross-sectional view shown in FIG. 1B , the line segment A-A crosses the first transistor 130 and the third transistor 134, so the second contact 142 is not shown. However, in the region of the second transistor 132, the second contact 142 is also disposed above the source/drain region 120 of the substrate 105, in the ILD layer 190, and on both sides of the second conductive line 112.

Because the line segment A-A crosses the first transistor 130 and the third transistor 134, in FIG. 1B , the semiconductor structure 100 includes the gate dielectric layer 160 disposed around the first wire 110, the first isolation structure 180, the third wire 114, and the third isolation structure 184, and includes the isolation structure 170 disposed around the second wire 112 and the second isolation structure 182. In the region of the second transistor 132, the semiconductor structure 100 includes the gate dielectric layer 160 disposed around the second wire 112 and the second isolation structure 182, and includes the isolation structure 170 disposed around the first wire 110, the first isolation structure 180, the third wire 114, and the third isolation structure 184. In an embodiment where the first wire 110, the second wire 112, and the third wire 114 do not serve as gates of the transistors, the first transistor 130, the second transistor 132, and the third transistor have additional gate structures, wherein gate dielectric layers are disposed around these gate structures, and the first wire 110, the second wire 112, and the third wire 114 are connected to these gate structures via additional components (e.g., gate contacts and/or gate through holes).

In some embodiments, the materials of the first wire 110, the second wire 112, and the third wire 114 may include polysilicon, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, and/or combinations thereof. In some embodiments, the materials of the first contact 140, the second contact 142, and the third contact 144 may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof.

According to some embodiments of the present disclosure, FIG. 2A and FIG. 2B respectively show the bright (eg, bright voltage contrast) and dark states of the contacts of the semiconductor structure 100 in a normal state and an abnormal state in a SEM image.

According to the detection method provided by the present disclosure, the wire contact is first irradiated with a first electron beam to perform pre-charging. The detection method is performed by a detection system 500 as shown in FIG. 5. In some embodiments, the first electron beam irradiates the first wire contact 150 and the third wire contact 154 to pre-charge the first wire 110 and the third wire 114, thereby turning on the first transistor 130 and the third transistor 134 connected to the first wire 110 and the third wire 114.

Next, the semiconductor structure 100 is scanned with a second electron beam, and a detector is used to receive secondary electrons from the semiconductor structure 100 to generate a SEM image of the semiconductor structure 100. Then, a processing device is used to process the SEM image to determine whether there is a defect (e.g., a short circuit) between the first wire 110, the second wire 112, and the third wire 114 of the semiconductor structure 100.

As shown in FIG. 2A , because the first transistor 130 and the third transistor 134 are turned on, the first contact 140 and the third contact 144 of the first transistor 130 and the third transistor 134 have more electrons, and thus a bright voltage contrast is generated. Therefore, in the SEM image, the first contact 140 and the third contact 144 appear in a "bright" state. On the other hand, in a normal state, because the second wire contact 152 is not irradiated by the first electron beam and the second transistor 132 is not turned on, the second contact 142 does not obtain additional electrons and thus remains in a "dark" state.

However, in an abnormal state, for example, when a short circuit occurs between the first wire 110, the second wire 112, and the third wire 114, the light and dark states of the contacts of the semiconductor structure 100 in the SEM image will be different from the schematic diagram shown in FIG2A. Referring to FIG2B, because the first transistor 130 and the third transistor 134 are turned on, the first contact 140 and the third contact 144 also present a "light" state, which is the same as FIG2A.

On the other hand, although the second wire contact 152 is not irradiated by the first electron beam and thus the second wire 112 is not pre-charged, the second wire 112 obtains a voltage through the first wire 110 and/or the third wire 114 because a short circuit occurs between the second wire 112 and the first wire 110 and/or the third wire 114. As a result, the second transistor 132 connected to the second wire 112 is turned on. Therefore, in the SEM image, the second contact 142 of the second transistor 132 no longer remains in a "dark" state, but appears in a "bright" state due to having more electrons. Since the second contact 142 becomes brighter due to a defect (e.g., a short circuit) between the second wire 112 and other wires, it can be judged that there is a defect between the second wire 112 and other wires based on the brightened second contact 142 in the SEM image.

As described above, in the SEM image, a defect between the wires (e.g., a short circuit) will cause the contact that should be in a "dark" state to change to a "light" state. Therefore, by processing the SEM image, it is possible to determine whether there is a defect between the wires based on the "light" and "dark" states of the contact. In this way, it is possible to use the contact that is much larger than the defect and therefore easier to observe to determine whether there is a defect in the semiconductor structure. Furthermore, because the wire is indirectly judged through the contact, the wire may be covered by other components when the detection method provided by the present disclosure is performed. For example, as shown in FIG. 1B , during testing, the first wire 110, the second wire 112, and the third wire 114 are covered by the first isolation structure 180, the second isolation structure 182, and the third isolation structure 184. This means that the testing method does not need to be performed immediately after the wires are completed and exposed to the surface of the semiconductor structure, but can be performed after a relatively complete process sequence is completed. In this way, the time and cost of redesigning the process, interrupting the process midway, and/or frequently entering and exiting the process chamber can be avoided. In addition, since the testing method utilizes components of actual semiconductor devices, there is no need to specially design a test structure for testing. In this way, the semiconductor structure used as a test key will have a structure that is extremely similar to the effective chip used as a product. This will make the test result of the test key highly consistent with the effective chip, thereby improving the accuracy of the test.

In an alternative embodiment, the first electron beam irradiates the second wire contact 152 instead of the first wire contact 150 and the third wire contact 154, and thus the second transistor 132 connected to the second wire 112 is turned on, while the first transistor 130 and the third transistor 134 are not turned on. Therefore, in a normal state, in the SEM image, the second contact 142 appears "bright", while the first contact 140 and the third contact 144 remain "dark". On the other hand, in an abnormal state, in the SEM image, the first contact 140 and the third contact 144 become bright due to defects (e.g., short circuit) between the first wire 110, the second wire 112, and the third wire 114. In this way, it is also possible to determine whether there is a defect between the wires by the change of the “brightness” and “darkness” of the contacts (eg, the first contact 140 and/or the third contact 144).

In some embodiments, the wire that is not pre-charged (eg, the second wire 112) may be further divided into a plurality of sub-wires to further determine the defective area.

Referring to FIG. 3A , the second conductor 112 is divided into a plurality of sub-conductors 112-1, 112-2, 112-3, ..., 112-N, where N is any positive integer. In some embodiments, the second conductor is cut off at a transistor that is in a "bright" state in both normal and abnormal states, such as the first transistor 130 and the third transistor 134 when the first conductor 110 and the third conductor 114 are pre-charged, and both ends of each sub-conductor are transistors that are in a "dark" state in a normal state, such as the second transistor 132. In other words, each sub-conductor crosses M groups of transistors that are in a "dark" state in a normal state (e.g., the second transistor 132) and M-1 groups of transistors that are in a "bright" state in both normal and abnormal states (e.g., the first transistor 130 and the third transistor 134, which form a group), where M is any positive integer and depends on design requirements. In FIG. 3A, M is shown as 2 to simplify the description. However, the present disclosure is not limited thereto.

The semiconductor structure 200 shown in FIG. 3B is a cross-sectional view taken along the line segment B-B of FIG. 3A. The cross-sectional view taken along the line segment A-A of FIG. 3A is the same as FIG. 1B, so it is not repeated. In FIG. 3B, the semiconductor structure 200 has a structure similar to the semiconductor structure 100 of FIG. 1B, except that the second conductive line 112 is cut off, so only the isolation structure 170 remains.

FIG. 4A and FIG. 4B respectively show the bright (eg, bright voltage contrast) and dark states of the contacts of the semiconductor structure 200 in the SEM images in the normal state and abnormal state. In order to simplify the description and make it clear and understandable, some features in FIG. 3A are omitted in FIG. 4A and FIG. 4B.

According to the detection method provided by the present disclosure, the wire contacts are first irradiated with a first electron beam for pre-charging. In some embodiments, the detection method is performed by a detection system 500 as shown in FIG. 5 . In some embodiments, the first electron beam irradiates the first wire contact 150 and the third wire contact 154 to pre-charge the first wire 110 and the third wire 114, thereby turning on the first transistor 130 and the third transistor 134 connected to the first wire 110 and the third wire 114. Then, the semiconductor structure 200 is scanned with a second electron beam, and a detector is used to receive secondary electrons from the semiconductor structure 200 to generate a SEM image of the semiconductor structure 200. Then, a processing device is used to process the SEM image to determine whether there is a defect (eg, a short circuit) between the first conductive line 110 , the second conductive line 112 , and the third conductive line 114 of the semiconductor structure 200 .

As described above with reference to FIG. 2A, because the first transistor 130 and the third transistor 134 are turned on, the first contact 140 and the third contact 144 of the first transistor 130 and the third transistor 134 appear in a "bright" state in the SEM image, as shown in FIG. 4A. On the other hand, in a normal state, because the second wire contact 152 is not irradiated by the first electron beam and the second transistor 132 is not turned on, the second contact 142 remains in a "dark" state.

Referring to FIG. 4B , in an abnormal state, for example, when a short circuit occurs between the first wire 110, the sub-wire of the second wire 112 and the third wire 114, because the first transistor 130 and the third transistor 134 are turned on, the first contact 140 and the third contact 144 also appear to be “lit”, which is the same as FIG. 4A .

On the other hand, although the second wire contact 152 is not irradiated by the first electron beam and/or the second wire 112 is divided into a plurality of sub-wires and thus cannot obtain a voltage from the wire contact, because one or more of the sub-wires 112-1 to 112-N of the second wire 112 are short-circuited with the first wire 110 and/or the third wire 114, the one or more of the short-circuited sub-wires 112-1 to 112-N obtain a voltage via the first wire 110 and/or the third wire 114. In this way, the second transistor 132 connected to the one or more of the short-circuited wires 112-1 to 112-N is turned on. Therefore, in the SEM image, the second contact 142 of the turned-on second transistor 132 no longer remains in a "dark" state, but appears in a "bright" state due to having more electrons. For example, assuming that a short circuit occurs between the sub-conductor 112-2 and the first conductor 110 and/or the third conductor 114, the second transistors 132-3 and 132-4 connected to the sub-conductor 112-2 are turned on, so the second contacts 142 of the second transistors 132-3 and 132-4 appear in a "bright" state, thereby judging that there is a defect between the sub-conductor 112-2 of the second conductor 112 and other conductors.

By dividing the second conductor 112 into a plurality of sub-conductors 112-1 to 112-N, the region where the defect is located can be determined more accurately. When the second contact 142 of the second transistor 132 connected to a sub-conductor becomes bright, it means that there is a defect (e.g., a short circuit) between the sub-conductor and other conductors, that is, the defect occurs in the region where the sub-conductor is located. This can help with subsequent defect analysis.

In an alternative embodiment, the first wire 110 and the third wire 114 may be divided into a plurality of sub-wires while the second wire 112 is kept intact, and the second wire contact 152 is irradiated with a first electron beam, so that the second transistor 132 is turned on, while the first transistor 130 and the third transistor 134 are not turned on. Therefore, in a normal state, in the SEM image, the second contact 142 appears "bright", while the first contact 140 and the third contact 144 remain "dark". On the other hand, in an abnormal state, in the SEM image, the first contact 140 associated with the sub-wire of the first wire 110 that is short-circuited and/or the third contact 144 associated with the sub-wire of the third wire 114 that is short-circuited will appear "bright". In this way, it is also possible to determine whether there is a defect (e.g., a short circuit) between the wires by the changes in the "light" and "dark" of the contacts (e.g., the first contact 140 and/or the third contact 144), and further determine the area where the defect exists by the multiple sub-conductors of the first wire 110 and the third wire 114.

To simplify the description and make it clear and understandable, only necessary features are shown in FIGS. 1A to 4B . However, a person skilled in the art should understand that they can easily add other features to improve the semiconductor device, and can also add other elements to the semiconductor structures 100 and 200 to form other semiconductor applications.

Referring to FIG. 5 , the detection system 500 may include the function of a scanning electron microscope. The detection system 500 includes an electron beam emission system, which includes an electron source 510, a first aperture diaphragm 520, a condenser lens 530, a second aperture diaphragm 525, a deflector 540, and a detector 570. The detection system 500 further includes a carrier 550 and a processing device 580. The carrier 550 may be used to carry a sample 560. The sample 560 is, for example, a semiconductor structure 100 or 200.

The electron source 510 can be used to emit electron beams toward the specimen 560, such as a first electron beam for precharging the wire contacts and a second electron beam for scanning the specimen to generate a SEM image. The first aperture light bar 520 and the second aperture light bar 525 can be used to control the convergence angle of the electron beam. The focusing lens 530 and the objective lens (not shown) closer to the specimen 560 can be used to focus the electron beam. The deflector 540, such as a coil, can be used to control the path of the electron beam.

The detector 570 can receive secondary electrons generated by the second electron beam of the electron source 510 and generate a SEM image of the specimen 560, for example, by generating the SEM image through the processing device 580. The processing device 580 can be used to execute the detection method provided by the present disclosure, such as the method 600 described below with reference to FIG. 6. For example, the method 600 can be implemented as a computer program product and stored in a storage device (not shown) of the detection system 500. The above-mentioned computer program product stored in the storage device can be loaded and executed by the processing device 580 to execute the method 600 in the detection system 500.

FIG. 6 is a flow chart of a method 600 for testing a semiconductor structure (e.g., semiconductor structure 100, 200) according to an embodiment of the present disclosure. It should be noted that additional operations may be provided before, during, or after method 600, and for additional embodiments of method 600, some of the operations described may be moved, replaced, or eliminated. FIG. 6 will be described below with reference to FIGS. 1A to 5.

In operation 610, a semiconductor structure is first received. The semiconductor structure includes at least a first wire, a second wire, a first transistor connected to the first wire and having a first contact, a second transistor connected to the second wire and having a second contact, and a first wire contact connected to the first wire.

In operation 620, at least one wire contact of the semiconductor structure is irradiated with an electron beam to precharge the wire connected to the at least one wire contact and turn on the transistor connected to the wire. For example, the electron source 510 can precharge at least one wire of the semiconductor structure 100 and/or the semiconductor structure 200 with a first electron beam and turn on the transistor connected to the at least one wire.

In operation 630, the semiconductor structure is scanned with an electron beam to obtain an image of the semiconductor structure, such as a SEM image. For example, the semiconductor structure 100 and/or the semiconductor structure 200 can be scanned with a second electron beam by the electron source 510, and the secondary electrons from the semiconductor structure 100 and/or the semiconductor structure 200 can be received by the detector 570 to generate the SEM image of the semiconductor structure 100 and/or the semiconductor structure 200.

In operation 640, it is determined whether the target joint is brightened based on the image obtained in operation 630. In response to the target joint being brightened, operation 650 is entered, and in response to the target joint not being brightened, operation 660 is entered. For example, the image can be processed by the processing device 580 to determine whether the target joint is brightened.

As mentioned above, the "bright" and "dark" state of the contacts in the SEM image can be used to determine whether the transistor is turned on. The transistor connected to the wire that is not pre-charged can be set as the target transistor so that the target transistor will not be turned on due to pre-charging. At the same time, the contact of the target transistor can be set as the target contact, and the wire connected to the target transistor that is not pre-charged can be set as the target wire. In this way, under normal conditions, the target contact of the target transistor should appear "dark" in the SEM image. If the target contact becomes brighter in the SEM image, that is, it appears "bright" indicating conduction, it means that the target wire of the target transistor has obtained voltage from other places due to defects and turned on the target transistor. Thereby, it can be determined that the target wire of the target transistor has a defect (for example, a short circuit with other pre-charged wires).

After determining that the target contact becomes bright, the method proceeds to operation 650. In operation 650, it is determined that a short circuit occurs in the wire connected to the target contact. As described above, the target contact appears "bright" in the SEM image, indicating that the target wire has a defect. Therefore, in response to the target contact becoming bright, the method 600 determines in operation 650 that a defect (e.g., a short circuit) occurs in the wire in the semiconductor structure.

After determining that the target contact has not become bright, the method proceeds to operation 660. In operation 660, it is determined that the wires of the semiconductor structure are not short-circuited. As described above, in a normal state, the contact of the target transistor should appear "dark" in the SEM image. Therefore, in response to the target contact not becoming bright, the method 600 determines in operation 660 that the semiconductor structure is in a normal state, that is, there is no short circuit between the wires of the semiconductor structure.

In a further embodiment, the method 600 may further divide the target wire connected to the target transistor into a plurality of sub-wires. As described above, the area where the defect is located may be determined more accurately.

After operation 650, further operations may be performed, such as performing defect analysis (e.g., physical failure analysis (PFA)) on the semiconductor structure to facilitate subsequent process improvement. As described above, by dividing the target wire of the target transistor into a plurality of sub-wires, the region where the defect is located can be more accurately determined, thereby being more conducive to defect analysis. For example, after determining the region where the defect is located based on the sub-wires, defect analysis can be performed on the region.

The present disclosure provides a detection method and a detection system using the detection method. The detection method uses the change of "bright" and "dark" of the contact of the transistor in the SEM image to determine whether there is a defect that will cause a short circuit between the wire connected to the gate of the transistor or serving as the gate of the transistor and other wires. As mentioned above, in the SEM image, a defect between the wires (e.g., a short circuit) will cause the contact that should be in a "dark" state to change to a "bright" state. Therefore, it is possible to determine whether there is a defect between the wires based on the "bright" and "dark" states of the contact. The detection method provided by the present disclosure can provide many benefits as described above, such as being able to more easily discover the existence of defects, being able to perform detection when other components are covering the wires, avoiding the time and cost of redesigning the process, interrupting the process midway, and frequently entering and exiting the process chamber, the detection results of the test key are highly consistent with the effective chip, thereby improving the accuracy of the detection, and more accurately determining the area where the defect is located.

The above text summarizes the features of various embodiments or examples, so that those with ordinary knowledge in the art can better understand the present disclosure. Those with ordinary knowledge in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and/or achieve the same advantages as the embodiments or examples introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

100: semiconductor structure 105: substrate 110: first conductor 112: second conductor 112-1~112-N: sub-conductor 114: third conductor 120: source/drain region 130: first transistor 132: second transistor 134: third transistor 140: first contact 142: second contact 144: third contact 150: first conductor contact 152: second conductor contact 154: third conductor contact 160: gate dielectric layer 170: isolation structure 180: first isolation structure 182: second isolation structure 184: third isolation structure 190: ILD layer A-A: line segment B-B: line segment X: first direction Y: second direction 200: semiconductor structure 500: detection system 510: electron source 520: first aperture light bar 525: second aperture light bar 530: focusing lens 540: deflector 550: stage 560: specimen 570: detector 580: processing device 600: method 610~660: operation

FIG. 1A is a top view of a semiconductor structure according to some embodiments of the present disclosure. FIG. 1B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure taken along line segment A-A of FIG. 1A. FIG. 2A is a schematic diagram showing the bright and dark states of a contact of a semiconductor structure in a SEM image in a normal state according to some embodiments of the present disclosure. FIG. 2B is a schematic diagram showing the bright and dark states of a contact of a semiconductor structure in a SEM image in an abnormal state according to some embodiments of the present disclosure. FIG. 3A is a top view of a semiconductor structure according to some embodiments of the present disclosure. FIG. 3B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure taken along line segment B-B of FIG. 3A. FIG. 4A is a schematic diagram showing the bright and dark states of the contacts of a semiconductor structure in a SEM image in a normal state according to some embodiments of the present disclosure. FIG. 4B is a schematic diagram showing the bright and dark states of the contacts of a semiconductor structure in a SEM image in an abnormal state according to some embodiments of the present disclosure. FIG. 5 is a block diagram of a detection system according to some embodiments of the present disclosure. FIG. 6 is a flow chart of a method for detecting a semiconductor structure according to some embodiments of the present disclosure.

600:Methods

610~660: Operation

Claims (10)

A detection method is used to detect a semiconductor structure, the semiconductor structure comprising: a first wire and a second wire extending along a first direction and spaced apart from each other along a second direction; a plurality of first transistors connected to the first wire, each of the first transistors comprising a first contact; a plurality of second transistors connected to the second wire, each of the second transistors comprising a second contact; and a first wire contact connected to the first wire; the detection method comprises: a pre-charging operation, irradiating the first wire contact with an electron beam; an imaging operation, obtaining an image of the semiconductor structure; and a judging operation, judging whether the second contact of any one of the second transistors becomes bright in the image, and judging that there is a defect between the first wire and the second wire in response to the second contact of any one of the second transistors becoming bright in the image. The detection method of claim 1, wherein the second conductor includes a plurality of sub-conductors, wherein the sub-conductors include at least a first sub-conductor and a second sub-conductor, and the judgment operation further includes: judging that there is a defect between the first sub-conductor and the first conductor in response to the second contacts of the second transistors connected to the first sub-conductor becoming brighter in the image. The detection method of claim 2 further includes performing a physical property failure analysis on the area where the first sub-conductor is located in the semiconductor structure. As in the detection method of claim 1, the first transistors and the second transistors are arranged alternately along the first direction. As in the detection method of claim 1, the semiconductor structure further includes a second wire contact connected to the second wire, wherein the first wire contact is disposed on one side of the semiconductor structure, and the second wire contact is disposed on an opposite side of the semiconductor structure along the first direction. A detection method as claimed in claim 1, wherein the first conductor serves as a gate of the first transistors, and the second conductor serves as a gate of the second transistors. As in the detection method of claim 6, wherein: each of the first transistors further includes a first isolation structure, the first isolation structure is disposed above the first conductive line; and each of the second transistors further includes a second isolation structure, the second isolation structure is disposed above the second conductive line. As in the detection method of claim 7, the semiconductor structure further comprises a substrate, wherein the first isolation structure, the first conductive line, the second isolation structure and the second conductive line are disposed in the substrate, and the first contact and the second contact are disposed in an inter-dielectric layer above the substrate. As in the detection method of claim 1, wherein: each of the first transistors further comprises a third contact, wherein the first contact and the third contact are arranged on both sides of the first conductor along the second direction; and each of the second transistors further comprises a fourth contact, wherein the second contact and the fourth contact are arranged on both sides of the second conductor along the second direction. A detection system is used to detect a semiconductor structure, the semiconductor structure comprising: a first wire and a second wire extending along a first direction and spaced apart from each other along a second direction; a plurality of first transistors connected to the first wire, each of the first transistors comprising a first contact; a plurality of second transistors connected to the second wire, each of the second transistors comprising a second contact; and a first wire contact connected to the first wire; the detection system comprising: an electron beam emitting system having an electron source and a detector; a carrier configured to carry the semiconductor structure; and a processing device that performs the following operations: a pre-charging operation, emitting an electron beam to the first wire contact of the semiconductor structure by the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons from the semiconductor structure by the detector to generate an image of the semiconductor structure; and a judging operation, judging the light and dark state of the image to judge whether there is a defect between the first wire and the second wire of the semiconductor structure.

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