TWI838751B - Electronic device - Google Patents

Abstract

The present disclosure provide a circuit structure in an electronic device, the circuit structure includes a substrate and a blocking wall. A plurality of wires are disposed on the substrate. The blocking wall is disposed on the substrate and includes a plurality of partitions. In a top view, at least a portion of one of the wires is located between two adjacent ones of the partitions.

Description

Electronic devices

The present disclosure relates to an electronic device, and in particular to a circuit structure in the electronic device.

In the process of bonding the circuit board to the substrate, the anisotropic conductive film coated on the contact surface of the substrate and the circuit board is easily pressed by the bonding blade and overflows, which may cause a short circuit between the wires. Therefore, a circuit structure is needed to improve the shortcomings of the existing technology.

Some embodiments of the present disclosure provide a circuit structure in an electronic device, including a substrate and a baffle. A plurality of wires are disposed on the substrate. The baffle is disposed on the substrate and includes a plurality of spacers. In a top view, at least a portion of one of the wires is located between two adjacent ones of the spacers.

10: Substrate

11: Wire

20: Circuit board

21: Circuit board pad

30:Block

30a: Insulating layer

30a’: Insulating layer

30b: Organic layer

30c: Metal layer

30d: Metal layer

30e: Insulating layer

31: Partition

32: Connection part

40:Joint element

40A: Conductive particles

50: Driving element

60: Stacked structure

100: Circuit structure

111: Substrate pad

311: Accommodation space

CP: contact surface

D: Drain

D1: Extension direction of substrate edge

D2: Normal direction, substrate normal direction

D3: Extension direction

E1: Electrode

E2: Electrode

G: Gate

GD: Spacing distance

GI: Gate insulation layer

h: retaining wall thickness

INS1: First insulation layer

INS2: Second insulation layer

INS3: Insulation layer

INS4: Insulation layer

INS5: Insulation layer

INS6: Insulation layer

INS7: Insulation layer

OG: Organic layer

S: Source

SM1: semiconductor layer

SM2: protrusion

The various aspects of the present disclosure can be fully understood from the following detailed description in conjunction with the attached drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

Figure 1 is a schematic diagram of the circuit structure of an electronic device according to some embodiments of the present disclosure.

Figure 2 is a schematic diagram showing the circuit structure of an electronic device according to some embodiments of the present disclosure.

Figure 3A shows a schematic diagram of the cross-sectional structure of the internal stacking structure of the electronic device disclosed herein.

FIG. 3B shows a cross-sectional view of the circuit structure along the A-A’ line in FIG. 1 according to some embodiments of the present disclosure.

FIG. 4 shows a cross-sectional view of the circuit structure along the A-A’ line in FIG. 1 according to other embodiments of the present disclosure.

FIG. 5 shows a cross-sectional view of the circuit structure along the A-A’ line in FIG. 1 according to other embodiments of the present disclosure.

FIG. 6 shows a cross-sectional view of the circuit structure along the A-A’ line in FIG. 1 according to other embodiments of the present disclosure.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that in order to make it easier for readers to understand and the drawings are concise, the multiple drawings in the present disclosure only depict a portion of the display device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure. In addition, similar and/or corresponding reference numerals may be used in different embodiments, which is only for the purpose of simply and clearly describing some embodiments, and does not represent any relationship between the different embodiments and/or structures discussed.

Certain terms are used throughout this disclosure and in the claims that follow to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "include", "contain", "have" and the like are open-ended terms and should therefore be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "below" side will become the element on the "above" side.

When a corresponding component (such as an element or a film layer or a region) is referred to as being "on another component" or "connected to another component", it may be directly on another component or directly connected to another component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component" or "directly connected to another component", there is no component between the two. In addition, when a component is referred to as being "on another component", the two have a vertical relationship in the top view direction, and this component may be above or below the other component, and this vertical relationship depends on the orientation of the device.

The terms "approximately", "equal to", "equal" or "same", "substantially" or "substantially" are generally interpreted as within 20% of a given value, or within a range of 10%, 5%, 3%, 2%, 1% or 0.5% of a given value.

It is understood that although the terms "first", "second", etc. may be used herein to describe various elements, layers and/or parts, these elements, layers and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, layers and/or parts. Therefore, a first element, layer and/or part discussed below may be referred to as a second element, layer and/or part without departing from the teachings of some embodiments disclosed herein. In addition, for the sake of brevity, the terms "first", "second", etc. may not be used in the specification to distinguish different elements. Without violating the scope defined by the attached patent scope, the first element and/or second element recorded in the patent scope may be interpreted as any element that meets the description in the specification.

In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto.

It should be noted that the technical solutions provided in the following different embodiments can be replaced, combined or mixed with each other to form another embodiment without violating the spirit of this disclosure.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

The electronic device disclosed herein may include a display device, an antenna device, and a sensing device, but is not limited thereto. The display device may be, for example, a touch display device, a curved display device, a free shape display, or a flexible display device, but is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The aforementioned devices may be formed by splicing, for example, including a spliced display device or a spliced antenna device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support the electronic device. The following will use a display device to illustrate the contents of this disclosure, but the types of electronic devices disclosed in this disclosure are not limited to this.

FIG. 1 is a schematic diagram of a circuit structure 100 of an electronic device according to some embodiments of the present disclosure. The circuit structure 100 may include a substrate 10, a circuit board 20, a baffle 30, a bonding element 40, and a driving element 50. The substrate 10 and the circuit board 20 may be electrically connected to each other via the bonding element 40. The baffle 30 may be disposed on the substrate 10 and adjacent to the bonding element 40.

A plurality of wires 11 may be disposed on the substrate 10. The wires 11 may extend from, for example, the location of the driving element 50 toward the circuit board 20, and each wire 11 may include a substrate pad 111.

The circuit board 20 may include a plurality of circuit board pads 21. In some embodiments, at least one substrate pad 111 overlaps with a corresponding circuit board pad 21 along the normal direction D2 of the substrate 10.

A bonding element 40 may be disposed between the substrate pad 111 and the corresponding circuit board pad 21, so that the substrate pad 111 and the corresponding circuit board pad 21 may be electrically connected to each other through the bonding element 40. In some embodiments, the bonding element 40 may have a conductive property to electrically connect the substrate pad 111 and the corresponding circuit board pad 21. For example, the bonding element 40 may be an anisotropic conductive film (ACF) having conductive particles 40A, but the present disclosure is not limited thereto.

In some embodiments, the baffle 30 may be disposed near the wire 11, but the baffle 30 may not directly contact the wire 11. In some embodiments, the coating range of the bonding element 40 may be larger than a contact surface CP between the substrate pad 111 and the circuit board pad 21, that is, the bonding element 40 may overflow outside the substrate pad 111 or outside the circuit board pad 21, so that the bonding element 40 contacts the baffle 30.

In some embodiments, the retaining wall 30 has an insulating material, and the retaining wall 30 may include a plurality of spacers 31. As shown in FIG. 1, in some embodiments, from a top view, at least a portion of a conductor 11 is located between two adjacent spacers 31. Two adjacent spacers 31 may form a receiving space 311. When observed along the substrate normal direction D2, a receiving space 311 may correspond to a conductor 11 and at least one conductive particle 40A. More specifically, the two sides of the conductor 11 may correspond to the spacers 31 respectively, separating the conductive particles 40A adjacent to different conductors 11 from each other, thereby reducing the short circuit (short) of different conductors 11 due to contact between the conductive particles 40A.

Please continue to refer to FIG. 1. When observed along the extension direction D1 of the substrate edge, the baffle 30 and the circuit board pad 21 do not overlap each other. In some embodiments, in the extension direction D3 of the circuit board pad 21, the spacer 31 and the circuit board pad 21 may be separated by a spacing distance GD. More specifically, one end of the circuit board pad 21 is close to one end of the adjacent spacer 31, and the spacing distance GD is the minimum distance between the two ends measured in the extension direction D3 of the circuit board pad 21. In some embodiments, the spacing distance GD is between 0.05 mm and 1 mm (0.05 mm≦ spacing distance≦1 mm). In this way, the risk of subsequent processes damaging the barrier 30 can be reduced.

In summary, by providing the spacer 31 between the wires 11, the short circuit between the wires 11 caused by the conductive particles 40A overflowing the contact surface CP can be reduced, thereby making the circuit structure 100 more stable or improving the reliability of the circuit structure 100.

FIG. 2 is a schematic diagram of a circuit structure 100 of an electronic device according to some embodiments of the present disclosure. In the embodiment shown in FIG. 2, the retaining wall 30 may further include a connecting portion 32, and the connecting portion 32 may extend along the substrate edge extension direction D1.

As shown in FIG. 2, the connecting portion 32 connects at least two spacers 31, so that when viewed from the substrate normal direction D2, the connecting portion 32 and its corresponding two spacers 31 can present an inverted U shape. In this embodiment, the accommodating space 311 can be composed of the connecting portion 32 and its corresponding two adjacent spacers 31, that is, the accommodating space 311 can be a semi-enclosed space and present an inverted U shape.

The connecting portion 32 can block the conductive particles 40A to reduce the conductive particles 40A from overflowing the retaining wall 30 and contacting each other, thereby reducing the possibility of short circuits between wires. In addition, the connecting portion 32 can also protect the wire 11 and reduce the probability of the wire 11 being damaged.

The inside of the electronic device may include a stacked structure 60 composed of electronic elements such as wires, transistors, and film layers. FIG. 3A is a schematic diagram of the cross-sectional structure of the stacked structure 60 inside the electronic device disclosed herein. As shown in FIG. 3A, the stacked structure 60 may include a transistor disposed on a substrate 10, and the transistor may at least include a gate G, a drain D, a source S, a semiconductor layer SM1, and a gate insulating layer GI. The gate insulating layer GI may be between the gate G and the semiconductor layer SM1, and the drain D and the source S are respectively located on both sides of the semiconductor layer SM1 and electrically connected to the semiconductor layer SM1, and there is a gap between the drain D and the source S. In addition, the electronic device may also include a first insulating layer INS1 covering the source S and the drain D, the organic layer OG is located above the first insulating layer INS1, and because of its thickness, the surface that is undulating due to the setting of the transistor can be flattened, the second insulating layer INS2 can be set above the organic layer OG, and an electrode E1 is electrically connected to the drain D through a through hole located in the second insulating layer INS2, the organic layer OG, and the first insulating layer INS1. It should be noted that the above structure is only an example, and the structure and layers of the transistor in the present disclosure are not limited to the above content. For example, as shown in FIG. 3A, the drain D and the source S may each include a protrusion SM2 between the semiconductor layer SM1, and the protrusion SM2 may be formed by etching the semiconductor layer SM1 or depositing on the semiconductor layer SM1. The electronic device may also include another electrode E2, and the electrode E1 and the electrode E2 may be separated by a second insulating layer INS2, for example.

FIG. 3B is a cross-sectional view of the circuit structure 100 along the line A-A' in FIG. 1 according to some embodiments of the present disclosure. In the present disclosure, the stacking structure 60 may be located in the working area of the electronic device, and the circuit structure 100 may be located in the peripheral area of the electronic device. In the present disclosure, the circuit structure 100 may be at least partially formed by the same process as the stacking structure 60 shown in FIG. 3A, that is, in the circuit structure 100, at least a portion of the layers are the same as a portion of the layers in the stacking structure 60 shown in FIG. 3A. For example, in the circuit structure 100 shown in FIG. 3B , the wire 11 above the substrate 10 may be on the same layer as the gate G in FIG. 3A , and then an insulating layer INS3 on the same layer as the gate insulating layer GI in FIG. 3A , an insulating layer INS4 on the same layer as the first insulating layer INS1 in FIG. 3A , a first portion 30b of the barrier on the same layer as the organic layer OG in FIG. 3A , and an insulating layer 30a on the same layer as the second insulating layer INS2 in FIG. 3A are formed above the wire 11 . The first part 30b of the baffle can be patterned and then the insulating layer 30a can be formed on the first part 30b to form the baffle 30 and the accommodating space 311. It should be noted that after the insulating layer 30a is formed, it can be selectively patterned again to increase the thickness of the baffle 30. As shown in Figure 3B, a part of the insulating layer 30a is patterned, and the other part of the insulating layer 30a is not patterned and is located between the two first parts 30b of the baffle.

In some embodiments, the barrier thickness h of the barrier 30 may be between 1 μm and 5 μm (1 μm ≦ barrier thickness ≦ 5 μm). It should be noted that the barrier thickness h may be the maximum distance measured from the top surface of the insulating layer INS4 to the top surface of the barrier 30 in the substrate normal direction D2.

FIG. 4 shows a cross-sectional view of the circuit structure 100 along the line A-A' in FIG. 1 according to some other embodiments of the present disclosure. Similar to FIG. 3B, as shown in FIG. 4, the circuit structure 100 may include a conductive line 11 disposed on the substrate 10 and on the same layer as the gate G in FIG. 3A, an insulating layer INS5 on the same layer as the gate insulating layer GI in FIG. 3A, and an insulating layer INS6 on the same layer as the first insulating layer INS1 in FIG. 3A. Different from FIG. 3B, a metal layer 30c may be formed on the insulating layer INS6, and then an insulating layer 30a is formed to cover the metal layer 30c. It should be noted that in this embodiment, after the metal layer 30c is patterned, the insulating layer 30a is formed on the metal layer 30c to form the baffle 30 and the accommodating space 311. The insulating layer 30a and the second insulating layer INS2 in FIG. 3A can be formed simultaneously or in different processes to reduce the possibility of electrical connection between the metal layer 30c and the conductive particles 40A in FIG. 1. In addition, after the insulating layer 30a is formed, it can be selectively patterned again to increase the thickness of the baffle 30, as shown in FIG. 4. In this embodiment, the barrier thickness h of the barrier 30 may be in the range of 0.2 microns to 3 microns (0.2 microns ≦ barrier thickness ≦ 3 microns), but is not limited thereto. The measurement method of the barrier thickness h is the same as that of the aforementioned embodiment, so it will not be repeated.

FIG. 5 shows a cross-sectional view of the circuit structure 100 along the line A-A' in FIG. 1 according to other embodiments of the present disclosure. Compared with FIG. 4, FIG. 5 is different in that a metal layer 30d is added to the circuit structure 100 shown in FIG. 4, and an insulating layer 30a' is formed to cover the metal layer 30d. It should be noted that in this embodiment, the metal layer 30d can be patterned and then an insulating layer 30a' can be formed to cover the metal layer 30d, so as to form the baffle 30 and the accommodating space 311. In this embodiment, the baffle thickness h of the baffle 30 can be between 0.1 micrometers and 2 micrometers (0.1 micrometers ≦ baffle thickness ≦ 2 micrometers), but is not limited thereto. For example, if the continuously laid insulating layer 30a' in this embodiment is patterned, a portion of the insulating layer 30a' between two adjacent metal layers 30d can be removed to increase the thickness of the retaining wall 30.

In addition, the circuit structure 100 may be provided with another metal layer at a position corresponding to the baffle 30 for the purpose of further increasing the height of the baffle 30. The metal layer may be provided at the same layer as the wire 11, but the present disclosure is not limited thereto.

FIG6 is a cross-sectional view of the circuit structure 100 along the line A-A' in FIG1 according to some embodiments of the present disclosure. As shown in FIG6, the circuit structure 100 may include a conductive line 11 on the same layer as the gate G in FIG3A, an insulating layer INS7 on the same layer as the gate insulating layer GI in FIG3A, an insulating layer 30e on the same layer as the first insulating layer INS1 in FIG3A, and an insulating layer 30a on the same layer as the second insulating layer INS2 in FIG3A above the substrate 10. It should be noted that in this embodiment, the insulating layer 30a and the insulating layer 30e can be patterned to form the baffle 30 and the accommodating space 311. As shown in FIG. 6, the insulating layer 30a can overlap with the insulating layer 30e but does not cover the side surface of the insulating layer 30e, but in some embodiments, the insulating layer 30a can also cover the side surface of the insulating layer 30e. In this embodiment, the baffle thickness h of the baffle 30 can be between 0.5 microns and 2 microns (0.5 microns ≦ baffle thickness ≦ 2 microns), but is not limited thereto.

It should be noted that the circuit structure 100 shown in FIG. 3B to FIG. 6 may be based on different embodiments, and the circuit structure 100 disclosed herein is not limited to FIG. 3B to FIG. 6. Moreover, the user may decide which circuit structure 100 to use according to the process used. In this way, the process of the retaining wall 30 may be combined with the process of the stacking structure 60, which may reduce the manufacturing process and time cost.

In summary, the disclosed embodiment can reduce the situation of internal short circuit of the circuit structure 100, and the structure of the retaining wall 30 can be arranged according to the selected process, so that the circuit structure 100 of the disclosed embodiment has the advantages of convenient manufacturing or cost reduction.

Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that any person with ordinary knowledge in the relevant technical field can make combinations, changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to the present disclosure. Therefore, the protection scope of this disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps, and the features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other. In addition, each patent application constitutes a separate embodiment, and the protection scope of this disclosure also includes the combination of each patent application and embodiment.

10: Substrate

11: Wire

20: Circuit board

21: Circuit board pad

30:Block

31: Partition

40:Joint element

40A: Conductive particles

50: Driving element

100: Circuit structure

111: Substrate pad

311: Accommodation space

CP: contact surface

D1: Extension direction of substrate edge

D2: Normal direction, substrate normal direction

D3: Extension direction

GD: Spacing distance

Claims (11)

An electronic device includes: a circuit structure including: a substrate; a plurality of wires disposed on the substrate; a baffle disposed on the substrate and including a plurality of spacers; a bonding element; and a circuit board including a plurality of circuit board pads, wherein, in a top view, at least a portion of the wires is located between two adjacent ones of the spacers, wherein one of the wires includes a substrate pad, and the bonding element electrically connects the substrate pad and one of the circuit board pads. As in claim 1, the electronic device, wherein in an extension direction of the circuit board pad, there is a spacing distance between the spacing portions and the circuit board pads. As in claim 2, the electronic device, wherein the spacing distance is between 0.05 mm and 1 mm. An electronic device as claimed in claim 1, wherein the bonding element comprises conductive particles. As in claim 1, the electronic device, wherein the baffle further includes a connecting portion, and the connecting portion connects the partitions. As in claim 1, the electronic device, wherein the barrier comprises an organic layer and an insulating layer, and the insulating layer is disposed on the organic layer. An electronic device as claimed in claim 6, wherein a thickness of one of the baffles is between 1 micron and 5 microns. As in claim 1, the electronic device, wherein the barrier comprises an insulating layer and a metal layer, and the insulating layer is disposed on the metal layer. The electronic device of claim 8 is characterized in that a thickness of one of the baffles is between 0.1 micrometers and 2 micrometers. An electronic device includes: a circuit structure including: a substrate; a plurality of wires disposed on the substrate; and a baffle disposed on the substrate and including a plurality of spacers; wherein, in a top view, at least a portion of the wires is located between two adjacent ones of the spacers, wherein the baffle includes an organic layer and an insulating layer, and the insulating layer is disposed on the organic layer. An electronic device includes: a circuit structure including: a substrate; a plurality of wires disposed on the substrate; and a baffle disposed on the substrate and including a plurality of spacers; wherein, in a top view, at least a portion of the wires is located between two adjacent ones of the spacers, wherein the baffle includes an insulating layer and a metal layer, and the insulating layer is disposed on the metal layer.

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