TWI838228B - Control circuit for controlling pixels of a display panel - Google Patents

Abstract

A control circuit, for controlling pixels of a display panel, includes an amplitude modulation control circuit, a with modulation control circuit, a first width control transistor, a second width control transistor and the following elements. A third width control transistor, coupled between the first width control transistor and the second width control transistor. A first capacitor, coupled to a gate of the third width control transistor, the gate of the third width control transistor receives a sweep signal through the first capacitor. A second capacitor, coupled to the gate of the third width control transistor, the gate of the third width control transistor receives a first voltage through the second capacitor. A regulating transistor, with a source coupled to the first capacitor and a drain coupled to the second capacitor, the first voltage is provided to the sweep signal through the regulating transistor.

Description

Control circuit used to control the pixels of a display panel

This disclosure relates to an electronic circuit, and in particular to a control circuit for use in a display panel.

With the development of semiconductor technology, the size of display panels is increasing, and the resolution of pixels of display panels is also greatly improved. When the pixels of the display panel display grayscale brightness, in order to achieve a good viewing experience for users, the brightness of pixels in different areas of the display panel must be uniform. In addition, cross-talk interference between pixels in adjacent areas must also be avoided.

However, when the pixels of the display panel have high resolution, the distance between pixels is reduced, and pixels in adjacent areas share signal lines. Due to the parasitic capacitance effect of the transistors in the pixel control circuit, the control signal transmitted on the signal line is disturbed, resulting in inconsistent duration of the luminescence period of pixels in adjacent areas, causing crosstalk interference and destroying the uniformity of pixel brightness.

In response to the above technical problems, technicians in the relevant industries in this field are committed to improving the pixel control circuit, hoping to overcome the disturbance of the control signal, thereby suppressing crosstalk interference and improving the uniformity of pixel brightness.

According to one aspect of the present disclosure, a control circuit is provided for controlling pixels of a display panel, the control circuit including an amplitude modulation control circuit and a width modulation control circuit and the following elements. A first width control transistor receives a width modulation supply voltage. A second width control transistor is coupled to the amplitude modulation control circuit. A third width control transistor is coupled between the first width control transistor and the second width control transistor. A first capacitor is coupled to a gate of the third width control transistor, and the gate of the third width control transistor receives a sweep signal via the first capacitor. A second capacitor is coupled to a gate of the third width control transistor, and the gate of the third width control transistor receives a first voltage via the second capacitor. A voltage regulator transistor, the source of the voltage regulator transistor is coupled to the first capacitor, the drain of the voltage regulator transistor is coupled to the second capacitor, and the first voltage is provided to the sweep signal via the voltage regulator transistor.

Other aspects and advantages of the present disclosure may be seen by reading the following drawings, detailed descriptions and claims.

1000,2000:Control circuit

3000: Display panel

100,100a: Width modulation control circuit

200: Amplitude modulation control circuit

300: Light-emitting unit

I1: driving current

310: LED

311: Yang pole

312: cathode

T01~T06: Transistor

T1~T3: Width control transistor

T5: voltage regulator transistor

T4, T6: Amplitude control transistor

g1~g6,g01~g06: gate

d1~d6,d01~d06: drain

s1~s6,s01~s06: source

C1: Capacitor

C2: Capacitor

C3: Capacitor

Cgd: parasitic capacitance

SWEEP, SWEEP_A: sweep signal

SWEEP_B, SWEEP_C: sweep signal

V_GH: first voltage

V_GL: Second voltage

VSS: ground voltage

V1: voltage

V0: Lower limit voltage

Vd3, Vg3, Vg4: voltage

VDD_PWM: Width modulation supply voltage

VDD_PAM: Amplitude modulation supply voltage

EPWM: width modulation control signal

V_PAM: amplitude modulation control signal

S_1: Compensation control signal

V_sig: control signal

VSET: Setting signal

ESET: Setting signal

S_0: control signal

t1,t2,t3,t3_A,t3_B,t4: time points

ET,ET_A,ET_B: Luminescence period

A,B,C: Area

Figure 1 is a block diagram of a control circuit of an embodiment of the present disclosure.

Figure 2 is the circuit diagram of the width modulation control circuit in Figure 1.

Figure 3 is the circuit diagram of the amplitude modulation control circuit in Figure 1.

Figure 4 is a circuit diagram of a portion of the control circuit in Figure 1.

Figure 5 is a waveform diagram showing the timing changes of some signals in the control circuit of Figure 4.

Figure 6 is a circuit diagram of a portion of a control circuit of a comparative example.

Figure 7 is a waveform diagram showing the timing changes of some signals in the control circuit of Figure 6.

Figure 8 is a schematic diagram of the control circuit of the comparative example of Figure 6 applied to pixels in adjacent areas.

Figures 9A to 9C are waveform diagrams of the timing changes of the scanning signals of the control circuits of the pixels in the three regions of Figure 8.

Figures 10A to 10D are comparison diagrams of the waveforms of the sweep signal of the control circuit, the gate voltage of the transistor, and the drive current of the pixels in the three regions of Figure 8.

Figures 11A to 11C are waveform diagrams of the timing changes of the sweep signal when the control circuit disclosed in this disclosure is applied to three regions.

Figures 12A to 12D are comparison diagrams of the waveforms of the sweep signal, the gate voltage of the transistor, and the drive current when the control circuit disclosed in this disclosure is applied to three regions.

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 is a block diagram of a control circuit 1000 of an embodiment of the present disclosure. The control circuit 1000 is used to control the grayscale brightness of a pixel of a display panel. As shown in FIG. 1, the control circuit 1000 includes a width modulation control circuit 100 and an amplitude modulation control circuit 200, and the control circuit 1000 is used to control the brightness of a light-emitting unit 300. The light-emitting unit 300 is a pixel of the display panel. More specifically, the width modulation control circuit 100 is used to perform pulse width modulation (PWM), and the amplitude modulation control circuit 200 is used to perform pulse amplitude modulation (PAM). The control circuit 1000 adjusts the brightness of the light-emitting unit 300 according to the pulse width modulation and the pulse amplitude modulation.

The width modulation control circuit 100 receives a sweep signal SWEEP, a first voltage V_GH, a width modulation supply voltage VDD_PWM, a width modulation control signal EPWM, a compensation control signal S_1, a control signal V_sig, a setting signal VSET, a setting signal ESET and a control signal S_0. The first voltage V_GH represents a logic high potential or a gate high potential, and the first voltage V_GH is, for example, 10V. The width modulation supply voltage VDD_PWM is, for example, 10V.

The amplitude modulation control circuit 200 receives the amplitude modulation supply voltage VDD_PAM and the amplitude modulation control signal V_PAM. The amplitude modulation supply voltage VDD_PAM is, for example, 10V. In addition, the amplitude modulation control circuit 200 generates a driving current I1, which is provided to the light-emitting unit 300.

The light-emitting unit 300 is a pixel of the display panel, and the light-emitting unit 300 is, for example, a light-emitting diode 310. The anode 311 of the light-emitting diode 310 is coupled to the amplitude modulation control circuit 200 to receive the driving current I1, and the cathode 312 of the light-emitting diode 310 is coupled to the ground voltage VSS. The ground voltage VSS is, for example, 0V. The light-emitting diode 310 is, for example, a micro-light-emitting diode (Micro-LED).

The width modulation control circuit 100 performs pulse width modulation to control the duration of the driving current I1, and the amplitude modulation control circuit 200 performs pulse amplitude modulation to control the current amount of the driving current I1. By adjusting the duration and current amount of the driving current I1, the control circuit 1000 can adjust the brightness of the light-emitting unit 300. For example, the brightness of the light-emitting unit 300 is directly related to the duration and current amount of the driving current I1. When the duration of the driving current I1 is longer or the current amount is larger, the light-emitting unit 300 has a higher brightness.

FIG. 2 is a circuit diagram of the width modulation control circuit 100 of FIG. 1. As shown in FIG. 2, the width modulation control circuit 100 includes a width control transistor T1, a width control transistor T2, a width control transistor T3, a voltage regulator transistor T5, transistors T01 to T04, a capacitor C1, a capacitor C2, and a capacitor C3. In this embodiment, the width control transistor T1, the width control transistor T2, the width control transistor T3, the voltage regulator transistor T5, and the transistors T01 to T04 are all P-type metal oxide semiconductor transistors, referred to as PMOS transistors.

The source s1 of the width control transistor T1 is coupled to the supply voltage source (the supply voltage source is not shown in Figure 2), and the source s1 of the width control transistor T1 receives the width modulation supply voltage VDD_PWM from the supply voltage source. The gate g1 of the width control transistor T1 receives the width modulation control signal EPWM. The drain d1 of the width control transistor T1 is coupled to the source s01 of the transistor T01, and the drain d1 of the width control transistor T1 receives the control signal V_sig through the transistor T01.

The width control transistor T3 is disposed between the width control transistor T1 and the width control transistor T2. The source s3 of the width control transistor T3 is coupled to the drain d1 of the width control transistor T1, the drain d3 of the width control transistor T3 is coupled to the source s2 of the width control transistor T2, and the gate g3 of the width control transistor T3 is coupled to the capacitor C1. The gate g3 of the width control transistor T3 receives the sweep signal SWEEP through the capacitor C1.

The source s2 of the width control transistor T2 is coupled to the drain d3 of the width control transistor T3 and the source s02 of the transistor T02. The gate g2 of the width control transistor T2 receives the width modulation control signal EPWM. The drain d2 of the width control transistor T2 is coupled to the source s04 of the transistor T04, and the drain d2 of the width control transistor T2 is coupled to the amplitude modulation control circuit 200 (the amplitude modulation control circuit 200 is not shown in FIG. 2).

The source s5 of the voltage regulator transistor T5 is coupled to the capacitor C1. The gate g5 of the voltage regulator transistor T5 is coupled to the gate g01 of the transistor T01 and the gate g02 of the transistor T02. The gate g5 of the voltage regulator transistor T5, the gate g01 of the transistor T01 and the gate g02 of the transistor T02 all receive the compensation control signal S_1. The drain d5 of the voltage regulator transistor T5 receives the first voltage V_GH. In one example, the drain d5 of the voltage regulator transistor T5 is coupled to a node or a voltage source of an internal circuit to receive a fixed voltage provided by the internal circuit. For example, the drain d5 of the voltage regulator transistor T5 is coupled to the internal gate driver array (Gate Driver on Array, GOA) to receive the first voltage V_GH provided by the gate driver array.

The gate g02 of transistor T02 is coupled to the gate g01 of transistor T01 and receives the compensation control signal S_1. The drain d02 of transistor T02 is coupled to the source s03 of transistor T03, capacitor C1 and capacitor C2. The source s02 of transistor T02 is coupled to the source s2 of the width control transistor T2.

The gate g03 of transistor T03 is coupled to the drain d03 of transistor T03 and receives the control signal S_0. The source s04 of transistor T04 is coupled to the drain d2 of the width control transistor T2, the gate g04 of transistor T04 receives the setting signal ESET, and the drain d04 of transistor T04 receives the setting signal VSET.

One end of capacitor C1 is coupled to the source s5 of voltage regulator transistor T5 and receives the sweep signal SWEEP, and the other end of capacitor C1 is coupled to the gate g3 of width control transistor T3 and capacitor C2. One end of capacitor C2 is coupled to the drain d5 of voltage regulator transistor T5 and receives the first voltage V_GH, and the other end of capacitor C2 is coupled to the gate g3 of width control transistor T3 and capacitor C1. One end of capacitor C3 is coupled to the source s04 of transistor T04, and the other end of capacitor C3 is coupled to the drain d04 of transistor T04.

FIG. 3 is a circuit diagram of the amplitude modulation control circuit 200 of FIG. 1. As shown in FIG. 3, the amplitude modulation control circuit 200 includes an amplitude control transistor T4, an amplitude control transistor T6, a transistor T05, and a transistor T06. In this embodiment, the amplitude control transistor T4, the amplitude control transistor T6, the transistor T05, and the transistor T06 are all PMOS transistors.

The gate g4 of the amplitude control transistor T4 is coupled to the width modulation control circuit 100 (the width modulation control circuit 100 is not shown in FIG. 3). The source s4 of the amplitude control transistor T4 is coupled to the drain d6 of the amplitude control transistor T6.

The gate g6 of the amplitude control transistor T6 receives the amplitude modulation control signal V_PAM, and the source s6 of the amplitude control transistor T6 is coupled to the drain d06 of the transistor T06.

The drain d05 of the transistor T05 is coupled to the light-emitting unit 300. In this embodiment, the drain d05 of the transistor T05 is coupled to the anode 311 of the diode 310 of the light-emitting unit 300. The source s05 of the transistor T05 is coupled to the drain d4 of the amplitude control transistor T4. The drain d4 of the amplitude control transistor T4 provides a driving current I1, and the driving current I1 is transmitted to the diode 310 through the transistor T05.

The source s06 of transistor T06 is coupled to another supply voltage source (this supply voltage source is not shown in FIG. 3 ), and the source s06 of transistor T06 receives the amplitude modulated supply voltage VDD_PAM from this supply voltage source.

FIG. 4 is a circuit diagram of a portion of the control circuit 1000 of FIG. 1. FIG. 4 shows a portion of the width modulation control circuit 100 of FIG. 2 and a portion of the amplitude modulation control circuit 200 of FIG. 3. FIG. 5 is a waveform diagram of the timing change of a portion of the signal of the control circuit 1000 of FIG. 4. The control circuit 1000 can be operated in different working stages to control the light emission of the light-emitting unit 300. The working stages of the control circuit 1000 include, for example, a compensation stage and an emission stage.

Please refer to Figures 4 and 5 at the same time. From time point t1 to time point t2, the control circuit 1000 operates in the compensation stage. From time point t2 to time point t4, the control circuit 1000 operates in the light-emitting stage.

First, when the control circuit 1000 operates in the compensation stage, the voltage of the compensation control signal S_1 is reduced from the first voltage V_GH to the second voltage V_GL. The first voltage V_GH is a higher voltage, the second voltage V_GL is a lower voltage, and the first voltage V_GH is higher than the second voltage V_GL. The first voltage V_GH is, for example, 10V, and the second voltage V_GL is, for example, 0V. In addition, the voltage of the control signal V_sig gradually increases from the second voltage V_GL to the first voltage V_GH. The voltage of the sweep signal SWEEP is maintained at the first voltage V_GH.

The gate g01 of transistor T01 receives the compensation control signal S_1. Transistor T01 is turned on (i.e., turned ON) or turned off (i.e., turned OFF) in response to the compensation control signal S_1. In the compensation stage, the voltage of the compensation control signal S_1 is reduced to the second voltage V_GL. Transistor T01 is a PMOS transistor, so transistor T01 is turned on. The control signal V_sig is transmitted to the source s3 of the width control transistor T3 through the turned-on transistor T01.

The gate g3 of the width control transistor T3 receives the sweep signal SWEEP through the capacitor C1, and the source s3 of the width control transistor T3 receives the control signal V_sig through the turned-on transistor T01. The width control transistor T3 is turned on or off in response to the voltage changes of the sweep signal SWEEP and the control signal V_sig. When the voltage difference Vsg3 between the source s3 and the gate g3 of the width control transistor T3 is greater than the critical voltage Vth3 of the width control transistor T3, the width control transistor T3 is turned on.

On the other hand, when the voltage of the width modulation control signal EPWM is the second voltage V_GL, the width control transistor T1 and the width control transistor T2 are turned on. When the width control transistors T1, T2 and T3 are all turned on, the gate g4 of the amplitude control transistor T4 can be charged, so that the voltage Vg4 of the gate g4 of the amplitude control transistor T4 gradually increases. For example, at time point t2, the voltage Vg4 of the gate g4 increases to the width modulation supply voltage VDD_PWM.

Furthermore, the voltage Vg4 of the gate g4 is transmitted to the drain d3 of the width control transistor T3 through the turned-on width control transistor T2, so the voltage Vd3 of the drain d3 of the width control transistor T3 also increases accordingly. For example, at time point t2, the voltage Vd3 of the drain d3 increases to the width modulation supply voltage VDD_PWM.

There is a parasitic capacitor Cgd between the gate g3 and the drain d3 of the width control transistor T3, so the change of the voltage Vd3 may be reflected in the voltage Vg3 of the gate g3 through the parasitic capacitor Cgd, causing the voltage Vg3 to fluctuate during the period from time point t1 to time point t2. In addition, the change of the voltage Vg3 may be reflected in the voltage of the sweep signal SWEEP through the capacitor C1, causing the sweep signal SWEEP to fluctuate.

The control circuit 1000 of the present embodiment is provided with a voltage regulator transistor T5. The gate g5 of the voltage regulator transistor T5 receives the compensation control signal S_1, and the voltage regulator transistor T5 is turned on or off in response to the compensation control signal S_1. In the compensation stage, the voltage of the compensation control signal S_1 is the second voltage V_GL, and the voltage regulator transistor T5 is a PMOS transistor, so the voltage regulator transistor T5 is turned on. The source s5 of the voltage regulator transistor T5 is coupled to the sweep signal SWEEP, and the drain d5 of the voltage regulator transistor T5 is coupled to the first voltage V_GH. The first voltage V_GH is transmitted to the sweep signal SWEEP through the turned-on voltage regulator transistor T5 to stably maintain the voltage of the sweep signal SWEEP at the first voltage V_GH. The above mechanism is called "sweep holding", which stably maintains the voltage of the sweep signal SWEEP at the first voltage V_GH provided by the internal gate driver array.

Then, from time point t2 to time point t4, the control circuit 1000 operates in the light-emitting stage, and the voltage of the sweep signal SWEEP gradually decreases. The sweep signal SWEEP is transmitted to the gate g3 of the width control transistor T3 via the capacitor C1, and the width control transistor T3 is turned on or off in response to the voltage change of the sweep signal SWEEP. When the width control transistor T3 is turned on, the gate g4 of the amplitude control transistor T4 can be charged to increase the voltage Vg4 of the gate g4. From time point t2 to time point t3, the amplitude control transistor T4 is turned on, and the drain d4 of the amplitude control transistor T4 provides a driving current I1, which is transmitted to the light-emitting unit 300 via the transistor T05. The light-emitting unit 300 emits light in response to the driving current I1.

At time point t3, the voltage of the sweep signal SWEEP drops to the lower limit voltage V0, the voltage Vg4 of the gate g4 of the amplitude control transistor T4 increases to a higher voltage, and the amplitude control transistor T4 is cut off. At time point t3, the amplitude modulation control circuit 200 stops providing the driving current I1 to the light-emitting unit 300, and the light-emitting unit 300 stops emitting light. In the light-emitting stage, the light-emitting period ET during which the light-emitting unit 300 actually emits light is between time point t2 and time point t3.

The control circuit 1000 of this embodiment is provided with a capacitor C2. When the control circuit 1000 operates in the light-emitting stage, the coupling amount of the parasitic capacitance Cgd of the width control transistor T3 can be reduced by the capacitor C2, thereby reducing the influence of the change of the voltage Vd3 of the drain d3 of the width control transistor T3 on the voltage Vg3 of the gate g3, thereby reducing the disturbance of the sweep signal SWEEP.

。寬度控制電晶體T3的閘極g3的電壓Vg3的變化量△V是 正相關於分壓比例

，如式(1)所示：

More specifically, capacitor C2 and capacitor C1 provide voltage division for parasitic capacitance Cgd of width control transistor T3. Capacitor C2 reduces the coupling of parasitic capacitance Cgd of width control transistor T3 to voltage Vg3 of gate g3 by voltage division. When capacitor C2 is not set, only capacitor C1 performs voltage division, and the voltage division ratio is

The change △V of the gate voltage Vg3 of the width control transistor T3 is positively correlated with the voltage division ratio

, as shown in formula (1):

。寬度控制電晶體T3的閘極g3的電壓Vg3的變化量△V如式(2)所示：

In the embodiment of FIG. 4, a capacitor C2 is added between the gate g3 of the width control transistor T3 and the drain d5 of the voltage regulator transistor T5. The voltage is divided by the capacitors C1 and C2, and the voltage division ratio is

The change △V of the voltage Vg3 of the gate g3 of the width control transistor T3 is shown in formula (2):

小於未設置電容 C2時的分壓比例

。據此，可減少寄生電容Cgd對於閘極g3的電壓Vg3的耦合量，進而減少掃掠訊號SWEEP的擾動。 After adding capacitor C2, the voltage division ratio

Less than the voltage division ratio when capacitor C2 is not set

Accordingly, the coupling amount of the parasitic capacitance Cgd to the voltage Vg3 of the gate g3 can be reduced, thereby reducing the disturbance of the sweep signal SWEEP.

FIG. 6 is a circuit diagram of a portion of a control circuit 2000 of a comparative example. FIG. 6 shows a portion of a width modulation control circuit 100a and a portion of an amplitude modulation control circuit 200 of the control circuit 2000. FIG. 7 is a waveform diagram of the timing changes of a portion of the signal of the control circuit 2000 of FIG. 6.

Please refer to Figures 6 and 7 at the same time. Compared with the control circuit 1000 of the present disclosure in Figure 4, the width modulation control circuit 100a of the comparative example in Figure 6 does not have the voltage regulator transistor T5 and the capacitor C2. During the period from time point t1 to time point t2, the gate g4 of the amplitude control transistor T4 is charged, so that the voltage Vg4 of the gate g4 gradually increases, so the voltage Vd3 of the drain d3 of the width control transistor T3 also increases accordingly. The change of the voltage Vd3 of the drain d3 is reflected in the voltage Vg3 of the gate g3 through the parasitic capacitor Cgd, and the change of the voltage Vg3 is reflected in the voltage of the sweep signal SWEEP through the capacitor C1, causing the sweep signal SWEEP to be disturbed.

Since the width modulation control circuit 100a of the comparative example of FIG. 6 does not have a voltage-stabilizing transistor T5, and does not provide a fixed voltage of the internal circuit to the sweep signal SWEEP, the sweep signal SWEEP cannot be stably maintained at the first voltage V_GH. As shown in FIG. 7, the sweep signal SWEEP increases to a voltage V1 at time t2. The increase in the voltage of the sweep signal SWEEP causes the conduction period of the width control transistor T3 and the amplitude control transistor T4 to change, thereby causing the light-emitting period ET of the light-emitting unit 300 to change. The duration of the luminescence period ET is related to the voltage of the sweep signal SWEEP. When the sweep signal SWEEP increases to the voltage V1 at time point t2, the luminescence period ET increases accordingly.

FIG. 8 is a schematic diagram of the control circuit 2000 of the comparative example of FIG. 6 being applied to pixels in adjacent regions. The display panel 3000 includes regions A, B, and C that are adjacent to each other. Regions B and C are arranged in the same horizontal row in the display panel 3000, and region A is arranged in another horizontal row. The horizontal row in which regions B and C are arranged is adjacent to the horizontal row in which region A is arranged. The control circuit 2000 is used to control the pixels in region A, the pixels in region B, and the pixels in region C.

Figures 9A to 9C are waveform diagrams of the timing changes of the sweep signal of the control circuit 2000 for the pixels in regions A, B, and C of Figure 8. When the control circuit 2000 operates in the compensation stage, the change of the voltage Vd3 of the drain d3 is reflected in the voltage Vg3 of the gate g3 via the parasitic capacitor Cgd, and the change of the voltage Vg3 is reflected in the voltage of the sweep signal via the capacitor C1, causing disturbance of the sweep signal. As shown in Figure 9A, the sweep signal SWEEP_A of the pixel in region A is less affected by the voltage Vd3 of the drain d3 and the voltage Vg3 of the gate g3, so the disturbance of the sweep signal SWEEP_A is smaller. For example, the voltage of the sweep signal SWEEP_A increases to the voltage V1_A at time point t2. The duration of the luminous period ET_A of the pixel in region A is related to the voltage of the sweep signal SWEEP_A. When the sweep signal SWEEP_A increases to the voltage V1_A at time point t2, the duration of the luminous period ET_A increases accordingly.

Moreover, as shown in FIG. 9B , the sweep signal SWEEP_B of the pixel in region B is more affected by the voltage Vd3 of the drain d3 and the voltage Vg3 of the gate g3, so the disturbance of the sweep signal SWEEP_B is greater. For example, the voltage of the sweep signal SWEEP_B increases to the voltage V1_B at the time point t2, and the voltage V1_B is greater than the voltage V1_A after the sweep signal SWEEP_A changes. When the sweep signal SWEEP_B increases to the voltage V1_B at the time point t2, the duration of the luminous period ET_B of the pixel in region B increases accordingly.

Since the voltage V1_B is greater than the voltage V1_A, the duration of the luminescence period ET_B of the pixels in area B is greater than the luminescence period ET_A of the pixels in area A. The brightness of the pixels in area B is greater than the brightness of the pixels in area A. Therefore, the pixels in areas A and B have crosstalk and poor uniformity.

On the other hand, in FIG. 9C, for the control circuit 2000 of the pixel in region C, the sweep signal SWEEP_C gradually decreases from the lower limit voltage V0 at time point t1. The pixel in region C does not emit light during the period from time point t1 to time point t4.

Figures 10A to 10D are comparison diagrams of the waveforms of the sweep signal of the control circuit 2000, the gate voltage of the transistor, and the driving current of the pixels in regions A, B, and C of Figure 8. As shown in Figure 10A, the perturbation of the sweep signal SWEEP_A of the pixel in region A is smaller, and the perturbation of the sweep signal SWEEP_B of the pixel in region B is larger. Similarly, as shown in FIG. 10B, the voltage Vg3(A) of the gate g3 of the width control transistor T3 of the control circuit 2000 applied to region A has a smaller disturbance, and the voltage Vg3(B) of the gate g3 of the width control transistor T3 of region B has a larger disturbance.

As shown in Figure 10C, the rising slope of the voltage Vg4(A) of the gate g4 of the amplitude control transistor T4 in region A is inconsistent with the rising slope of the voltage Vg4(B) of the gate g4 of the amplitude control transistor T4 in region B. Therefore, the charging speed of the gate g4 of the amplitude control transistor T4 in region A and region B is inconsistent, resulting in inconsistent turn-on or turn-off time of the amplitude control transistor T4.

As shown in Figure 10D, since the amplitude control transistor T4 of region A and region B is turned on or off at different times, the driving current I1(A) and driving current I1(B) of the pixels of region A and region B are inconsistent.

In contrast, when the control circuit 1000 disclosed in the present invention is used to control the pixels of regions A, B, and C, since the sweep signal SWEEP is stably maintained at a fixed first voltage V_GH through the voltage regulator transistor T5, and the coupling amount of the parasitic capacitance Cgd of the width control transistor T3 is reduced by the capacitor C2, the sweep signal SWEEP is almost not disturbed in the compensation phase and the light-emitting phase. Figures 11A to 11C are waveform diagrams of the timing changes of the sweep signal of the control circuit 1000 disclosed in the present invention applied to regions A, B, and C, respectively. As shown in FIG. 11A, during the period from time point t1 to time point t2, the sweep signal SWEEP_A of the pixel in region A is stably maintained at the first voltage V_GH. Similarly, as shown in FIG. 11B, during the period from time point t1 to time point t2, the sweep signal SWEEP_B of the pixel in region B is also stably maintained at the first voltage V_GH. Therefore, the duration of the luminescence period ET_A of the pixel in region A is roughly equal to the duration of the luminescence period ET_B of the pixel in region B.

Figures 12A to 12D are comparison diagrams of the waveforms of the sweep signal, the gate voltage of the transistor, and the driving current when the control circuit 1000 disclosed in the present invention is applied to regions A, B, and C. As shown in Figure 12A, the disturbances of the sweep signal SWEEP_A and the sweep signal SWEEP_B in regions A and B are very small, and the voltage changes of the sweep signal SWEEP_A and the sweep signal SWEEP_B are roughly the same.

Similarly, as shown in FIG. 12B, the disturbances of the voltage Vg3(A) and the voltage Vg3(B) of the gate g3 of the width control transistor T3 in regions A and B are very small, and the changes of the voltage Vg3(A) and the voltage Vg3(B) are roughly the same.

As shown in Figure 12C, the rising slopes of the voltage Vg4(A) and the voltage Vg4(B) of the gate g4 of the amplitude control transistor T4 in region A and region B are roughly the same, so the charging speeds of the gate g4 of the amplitude control transistor T4 in region A and region B are roughly the same.

As shown in Figure 12D, the currents of the driving currents I1(A) and I1(B) of the pixels in area A and area B are roughly the same. Therefore, the brightness of the pixels in area A and area B is roughly the same, effectively overcoming the problems of crosstalk and poor uniformity.

Although the present disclosure has been disclosed in detail with preferred embodiments and examples, it is understood that these examples are intended to be illustrative rather than restrictive. It is expected that a person with ordinary knowledge in the relevant technical field can think of various modifications and combinations, and the various modifications and combinations fall within the spirit of the present disclosure and the scope of the attached patent application.

1000: Control circuit

100: Width modulation control circuit

200: Amplitude modulation control circuit

300: Light-emitting unit

I1: driving current

T01, T02, T05: Transistor

T1~T3: Width control transistor

T5: voltage regulator transistor

T4: Amplitude control transistor

g01,g3,g4,g5: gate

d01,d3,d5: drain

s01,s3,s5: source

C1: Capacitor

C2: Capacitor

Cgd: parasitic capacitance

SWEEP: sweep signal

V_GH: first voltage

VSS: ground voltage

VDD_PWM: Width modulation supply voltage

EPWM: width modulation control signal

S_1: Compensation control signal

V_sig: control signal

Claims (10)

A control circuit for controlling pixels of a display panel, the control circuit comprising: an amplitude modulation control circuit; and a width modulation control circuit, comprising: a first width control transistor, receiving a width modulation supply voltage; a second width control transistor, coupled to the amplitude modulation control circuit; a third width control transistor, coupled between the first width control transistor and the second width control transistor; a first capacitor, coupled to the third width control transistor A gate of the third width control transistor, the gate of the third width control transistor receives a sweep signal via the first capacitor; a second capacitor, coupled to the gate of the third width control transistor, the gate of the third width control transistor receives a first voltage via the second capacitor; and a voltage regulating transistor, a source of the voltage regulating transistor is coupled to the first capacitor, a drain of the voltage regulating transistor is coupled to the second capacitor, and the first voltage is provided to the sweep signal via the voltage regulating transistor. A control circuit as described in claim 1, wherein when the control circuit operates in a compensation stage, the voltage-stabilizing transistor is turned on in response to a compensation control signal, and the sweep signal is stably maintained at the first voltage through the turned-on voltage-stabilizing transistor. A control circuit as described in claim 2, wherein the source of the voltage-stabilizing transistor is coupled to the sweep signal, the drain of the voltage-stabilizing transistor receives the first voltage, and a gate of the voltage-stabilizing transistor receives the compensation control signal. A control circuit as described in claim 3, wherein the first voltage represents a logic high potential or a gate high potential. A control circuit as described in claim 1, wherein the amplitude modulation control circuit comprises: an amplitude control transistor, a gate of the amplitude control transistor is coupled to the second width control transistor, and a drain of the amplitude control transistor is indirectly coupled to a light-emitting unit; wherein when the control circuit operates in a light-emitting phase, the amplitude control transistor provides a driving current to the light-emitting unit. The control circuit as described in claim 5, wherein when the control circuit operates in a compensation phase, the first width control transistor, the second width control transistor and the third width control transistor are all turned on, the gate of the amplitude control transistor is charged, and the voltage of the gate of the amplitude control transistor increases. A control circuit as described in claim 6, wherein when the control circuit operates in the compensation stage, the voltage of a drain of the third width control transistor increases, and the voltage of the gate of the third width control transistor increases. A control circuit as described in claim 7, wherein the first capacitor, the second capacitor and a parasitic capacitor of the third width control transistor have a voltage division ratio, and the change in the voltage of the gate of the third width control transistor is positively correlated to the voltage division ratio. A control circuit as described in claim 5, wherein when the control circuit operates in the light-emitting phase, the light-emitting unit has a light-emitting period, and the duration of the light-emitting period is related to the voltage of the sweeping signal. A control circuit as described in claim 9, wherein the display panel includes a first area and a second area, the first area is adjacent to the second area, and the control circuit is used to control a first pixel in the first area and a second pixel in the second area, wherein when the control circuit operates in the light-emitting phase, the first pixel in the first area has a first light-emitting period, and the second pixel in the second area has a second light-emitting period, and the duration of the first light-emitting period is substantially equal to the duration of the second light-emitting period.

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