TWI836306B - A new type of transistor device - Google Patents

Abstract

A new type of transistor device has a bipolar transistor with a semiconductor structure, which structure includes a channel of the same semiconductor type as the collector region and the emitter region. This channel is significantly shallower than the base region it borders. The novel structure provides improved current gain. It also enables the device, when turned on, to selectively operate in predominantly unipolar conduction or predominantly bipolar conduction by controlling the voltage across the emitter and collector terminals.

Description

A new type of transistor device

The present invention relates to a novel transistor which, among other advantages, has better current gain characteristics than conventional lateral bipolar junction transistor (BJT) transistors.

The semiconductor structure and doping configuration of BJT make the current (controlled current) between the emitter and collector become the result of the movement of two charge carriers, electrons and holes, which is called bipolar conduction.

In contrast, in a field effect transistor (FET) or junction field effect transistor (JFET), the current (controlled current) between the source and drain terminals is primarily (if not exclusively) attributable to the movement of electrons or holes, but not both. This is called unipolar conduction or single-carrier operation.

US patents US6251716B1, US200316704A1 and US2009206375 are examples of conventional JFET configurations, so the current between their source and drain is mainly due to unipolar conduction. Therefore, ordinary users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the above-mentioned problems encountered in the conventional art and provide a device that can operate as a normally-on device or a normally-off device due to the existence of channels, which is different from the basically traditional BJT semiconductor structure. Depends on the voltage applied across the emitter and collector terminals.

In a first aspect, the present invention provides a transistor device having: a collector region provided by a semiconductor first region of a first type; a collector terminal associated with the collector region; an emitter region provided by a semiconductor second region of the first type; an emitter terminal associated with the emitter region; a base region provided by a semiconductor third region located between and bordering the collector region and the emitter region; a base terminal associated with the base region; wherein the base region includes: a semiconductor base sub-region of a second type, and A semiconductor channel of the first type, wherein the base terminal contacts the semiconductor base subdivision; the semiconductor base subdivision intersects the semiconductor channel to provide a first diode junction, and intersects both the emitter region and the collector region to further form a plurality of second diode junctions, and the semiconductor channel intersects and interconnects the collector region and the emitter region, so that when the transistor device is implemented in a circuit under a first condition, a voltage higher than a first threshold voltage is configured to pass through the emitter terminals and the collector terminals, and the When the base terminal is floating or short-circuited with the emitter terminal, a current between the collector terminals and the emitter terminals is at least mainly due to unipolar conduction; the net doping concentration of the semiconductor channel is less than the net doping concentration of the emitter regions and the collector regions; and the semiconductor channel has a sufficiently small depth extending from the first diode junction so that when the transistor device is implemented in a circuit under a second condition, that is, the voltage disposed through the emitter terminals and the collector terminals is lower than the first threshold voltage, and the base terminal is floating or when a short circuit is formed with the emitter terminal, a depletion region is formed near the first diode junction sufficient to clamp the semiconductor channel so that there is substantially no current between the collector terminals and the emitter terminals of the transistor device; and, when the transistor device is implemented in a circuit under a third condition, i.e., a voltage is configured to pass through the emitter terminals and the collector terminals, and a voltage is configured to pass through the emitter terminals and the base terminal to generate a current through the base terminal, the current between the collector terminals and the emitter terminals is at least primarily due to bipolar conduction.

Due to the presence of the semiconductor channel, unlike essentially conventional BJT semiconductor structures, the transistor device can operate as a normally-on device or a normally-off device, depending on the voltage applied across the emitter and collector terminals. .

The value of the threshold voltage is related to the length of the semiconductor channel extending between the emitter and collector regions, and therefore usually also to the separation distance between the emitter and collector regions. Thus, for a desired range of emitter-collector voltages, the transistor device can be made to operate in either a normally-on or normally-off state by selecting the length of the semiconductor channel.

The same masking process can be used to define the spacing of all transistor devices in a circuit. This advantage makes it possible to manufacture integrated circuits containing normally-on and normally-off transistors without additional processing steps. Such circuits can be used to perform functions that normally require the use of complementary transistors, such as NMOS and PMOS, which require more semiconductor layers and/or production steps to implement. Applications that can benefit from this advancement include logic gate circuits, analog comparators, and operational amplifier circuits.

When operating under the first condition, the applied voltage (Vce) across the emitter terminals and collector terminals is greater than the first threshold, and the transistor device acts as a normally-on device; the semiconductor channel allows the Unipolar conduction between the collector and emitter terminals, although no current flows through the base terminal.

When operating under the second condition, the voltage across the emitter and collector terminals is below the first threshold, and the very small depth of the semiconductor channel (a function of the small depth of the semiconductor layer provided for the semiconductor channel) means that a depletion region present near the first diode junction is sufficient to make the semiconductor channel have a sufficiently high resistance to prevent current from flowing through the semiconductor channel.

This can be seen as when Vce is greater than the threshold, it is sufficient to overcome the depletion region, allowing current to flow between the emitter and collector. As the length of the semiconductor channel increases, the Vce value required to overcome the depletion region also increases.

The very small absolute depth of the semiconductor channel and its relatively small depth compared to the depth of the semiconductor base subdivision means that when operating under the third condition, i.e. when the voltage across the emitter and base terminals (Vbe) is greater than the forward bias voltage (bias voltage) of the base-emitter diode junction (Vft), a large part of the current through the base terminal will be due to the bipolar conduction of the emitter region and the semiconductor base subdivision rather than the bipolar conduction of the semiconductor channel.

Nonetheless, the presence of the semiconductor channel provides the transistor with improved gain characteristics compared to BJT transistors with conventional structures when operating under the third condition. This is thought to be because the semiconductor channel provides a conductive path between the emitter and collector regions without passing through a diode junction, and it therefore provides relatively low resistance.

A consequence of the operation of the transistor device is that when the value of Vbe changes above Vft, the proportion of Ice that can be attributed to bipolar conduction and unipolar conduction changes, and thus the current gain of the transistor changes; as the proportion of bipolar conduction increases, the current gain also decreases.

Another unexpected but advantageous feature of the novel transistor design is that by selecting the length of the semiconductor channel for a known Vce operating range, a normally-off transistor can be switched on when the Vbe value is lower than the forward bias voltage of the base-emitter diode junction.

In other words, when operating under a fourth condition, i.e., where the voltage across the emitter terminals and the collector terminals is between the first threshold (Vt) and the second threshold (Vt') (where |Vt'| < |Vt|), the transistor device operating as a normally-off transistor is switched on when Vbe is less than the forward bias voltage (Vft) of the base-emitter diode junction.

When operating under a fourth condition, the current between the emitter and the collector is the result of unipolar conduction through the semiconductor channel, so the transistor device has a higher gain than when operating under the fourth condition, although the maximum current between the emitter and the collector is smaller.

The transistor device is used to switch between turning off and the fourth condition, with a semiconductor channel that is too long (when Vbe=0) for a Vce value less than Vt to overcome the depletion region near the first diode junction. However, the semiconductor channel is short enough to apply a small forward voltage through the base and emitter terminals (Vbe greater than 0), but not enough to overcome a depletion region near the base-emitter diode junction (Vbe<Vft), thus making Ibe=0, which is enough to weaken the intrinsic depletion region near the first diode junction to the extent that current is allowed to flow between the emitter and the collector through the semiconductor channel. The minimum Vbe required to operate the transistor device under the fourth condition will depend on the Vce and Vt values of the transistor device.

A useful application includes a driver circuit that helps several first-stage transistors reduce bipolar conduction (i.e. more unipolar conduction - where there may be only unipolar conduction) to provide higher gain, while several first-stage transistors The second stage transistor increases bipolar conduction to allow higher current ratings while minimizing The surface area (planar area) of the transistor device.

On the benefit, the presence of the semiconductor channel allows the transistor device to switch between on (operating under the first or fourth conditions) and off in response to Vbe changes that are less than the absolute value of the base-emitter diode forward voltage (Vft), which allows, for example, two transistor devices of the same configuration, such as both NPN or both PNP, to be used to switch the two sides (high and low) of a driver circuit, rather than in accordance with the traditional requirements for a complementary circuit.

The appropriate depth of the semiconductor channel will depend on the Vce value that the transistor is designed to operate at and/or the doping concentration of the semiconductor channel.

For example, for a transistor designed to operate at voltages between 0V and |5V|, a channel depth of less than 0.25μm (0.1μm or less is better) may be appropriate.

However, at a given operating voltage, the maximum depth allowed by the semiconductor channel will be significantly less than the depth that would exist in a JFET designed to operate at a comparable operating voltage.

On the contrary, the depth of the semiconductor base sub-region extending in the opposite direction to the first diode junction may be equal to or greater than five times the depth of the semiconductor channel; in some embodiments, the depth of the semiconductor base sub-region may be at least twenty times the depth of the semiconductor channel.

The semiconductor base subdivision may include a first portion and a second portion, and wherein: the first portion has a higher net doping concentration than the second portion; the base terminal is electrically connected to the second portion through the first portion; and wherein the second portion interfaces with the semiconductor channel to provide the first diode junction, and interfaces with the emitter region and the collector region to form the second diode junction. This ensures that a relatively highly doped region is used at the base contact to provide an ohmic contact, while a less doped region interfaces with the semiconductor channels, emitter region and collector region.

To ensure that bipolar conduction is dominant when operating under the third condition, the net doping concentrations of the emitter, collector and base subdivisions, as well as the spacing between the emitter and collector regions (also called the base width) need to be carefully selected; the exact values will depend on variables such as the expected operating voltage range of Vce and Vbe and the size of the semiconductor manufacturing process and the materials used; the methods used to select the values of these variables are the same and common methods for designing a traditional BJT structure, so those familiar with the art will easily understand.

The net doping concentration of the semiconductor channel may be equal to or less than (e.g., between 0.1 and 1 times) the net doping concentration of the semiconductor base subregion; this ensures that the depletion region at the first diode junction is present in the semiconductor channel in preference to the semiconductor base subregion. For example, when the semiconductor channel is formed of a P-type semiconductor material and the semiconductor base subregion is formed of an N-type semiconductor material, the net doping concentration of the P-type dopant in the semiconductor channel may be 0.1 to 1 times the net doping concentration of the N-type dopant in the semiconductor channel.

To provide good conductive properties within the first portion of the semiconductor base sub-region, the first portion of the semiconductor base sub-region may have a net doping concentration of 1e16 to 5e17 per square centimeter, inclusive.

Good bipolar conduction characteristics also depend on the relatively small side spacing between the collector regions and the emitter regions. Therefore, the side spacing between the collector regions and the emitter regions can be less than or equal to 1.5 microns.

The emitter regions and/or collector regions may be at least partially located within the semiconductor base subregion.

In another aspect, the invention provides a transistor device having: a collector region provided by a first region of a semiconductor of a first type; a collector terminal associated with the collector region; an emitter region provided by a second region of a type of semiconductor; an emitter terminal associated with the emitter region; a third semiconductor region located between the collector region and the emitter region and at the interface between the two a base region provided by the region; a base terminal associated with the base region, wherein the base region includes: a second type semiconductor base subdivision, and a first type semiconductor channel, wherein the semiconductor base sub-region interfaces with the semiconductor channel to provide a first diode junction, and the semiconductor channel interfaces with and interconnects the collector region and the emitter region; the semiconductor channel The net doping concentration is less than the emitter region and collector the net doping concentration of the pole region; and the semiconductor channel has a depth extending far from the first diode junction that is small enough compared to the semiconductor base sub-region, when the semiconductor channel is implemented in a circuit In a transistor device, when a voltage passes through several emitter terminals and collector terminals and the base terminal is floating or short-circuited with the emitter terminal, it is sufficient to form a depletion region near the first diode junction. The semiconductor channel is clamped so that there is substantially no current between the collector terminals and the emitter terminals of the transistor device.

The semiconductor base subdivision system may be formed in a semiconductor substrate of the first type, which may thereby provide the functionality of isolating individual semiconductor integrated devices.

In order to minimize the influence of a parasitic transistor formed by the semiconductor substrate, the semiconductor base sub-region and the collector region and/or the emitter region, the transistor device may further include a high-voltage semiconductor device of the second type. A doped region is disposed so as to be separated between the semiconductor base subregion and the semiconductor substrate, and the highly doped region has a higher net doping concentration than the semiconductor base subregion.

The emitter region and the collector region may be provided, at least in part, by a polysilicon layer; the pattern of the doped polysilicon may be located on the surface of a silicon wafer forming the base region.

The emitter region may have a higher net doping concentration than the collector region; or, the net doping concentrations of the emitter region and the collector region may be substantially the same.

1: Transistor device

2:Collection area

3: Emitter area

4: Base region

4A: N-type base sub-division

4B:Channel

5: PN interface

100:P type substrate

101: N-type area

101A: N+ type area

102: N+ type area

103: P-Zone

104, 105: P-type area

104A, 105A: Part 1

104B, 105B: Part 2

5A, 5B: Diode junction

6: Arrow

7A, 7B: Arrows

8:Depleted area

C: Collector terminal

E: Emitter terminal

B: Base terminal

K, M, L, N, J: Area

O: Transition area

200:P type substrate

210: N-type well

211: Upper N-type area

212: Lower N-type area

213:N+ type area

214:N+ type area

220:P-channel layer

221: Oxide layer

222, 223: P-type area

222A, 223A: Part I

222B, 223B: Part 2

222C, 223C: Part 3

224:Metal layer

224A:Part 1

224B:Part 2

300: Photoresist

400:Polycrystalline silicon layer

401:P-type injection procedure

500:Oxide layer

Figure 1 is a schematic cross-sectional view of a semiconductor structure implementing a transistor.

Figure 2 is a schematic diagram showing how the operating characteristics of the transistor device in Figure 1 change with changes in Vbe and Vce.

Figure 3A is a schematic cross-sectional view of the transistor in Figure 1 configured in the on condition and with conduction between the emitter and collector mainly due to bipolar conduction.

Figure 3B is a schematic cross-sectional view of the transistor configured in the off condition in Figure 1.

Figure 3C is a schematic cross-sectional view of the transistor in Figure 1 configured in the on condition and the conduction between the emitter and the collector is mainly due to unipolar conduction.

Figure 4A is a schematic diagram of a transistor cross section similar to Figure 1 but with a shorter spacing X and configured in an on condition where the current between the emitter and the collector is mainly due to unipolar conduction.

Figure 4B is a schematic cross-sectional view of the transistor configured in a closed condition in Figure 4A.

Figure 5A is a cross-sectional schematic diagram of another semiconductor structure implementing a transistor device.

Figure 5B is a schematic diagram of a transistor plane implemented by the semiconductor structure in Figure 5A.

Figures 6A to 6I are schematic diagrams of the manufacturing process of the transistor device in Figures 5A and 5B.

The invention will now be described by way of example with reference to the following figures.

Please refer to "Figure 1", which is a schematic cross-sectional view of a semiconductor structure implementing a transistor. As shown in the figure: The present invention is a novel transistor device 1, which is considered to be an improvement on a bipolar junction transistor (BJT) device and operates in a similar manner in some aspects; for this purpose, the terminals of the device are labeled with BJT.

The device 1, which is of a PNP type in this example and is not shown to scale, is made of a doped semiconductor material to provide a collector region 2, an emitter region 3 and a base region 4. The base region 4 is located between the collector region 2 and the emitter region 3.

The collector region 2 and the emitter region 3 are both P-type semiconductors. According to convention, the emitter region 3 can be more doped than the collector region 2 . For example, the net doping concentration of the collector region 2 can be greater than or equal to 1×10 ¹⁸ cm ^-3 , and the net doping concentration of the emitter region 3 can be greater than or equal to 2×10 ¹⁸ cm ^-3 ; or, for convenience Fabricated, can be changed to have substantially the same net doping concentration. The collector terminal C is connected to the collector region 2 , the emitter terminal E is connected to the emitter region 3 , and the base terminal B is connected to the base region 4 .

Compared to conventional BJTs, the base region 4 of the transistor device 1 is composed of two different types of semiconductor regions: a first region of N-type material, hereinafter referred to as the N-type base subregion 4A, and a second region of P-type material, hereinafter referred to as the channel 4B.

The base terminal B is connected to the base region 4 through the N-type base sub-region 4A. The N-type base sub-region 4A directly borders the channel 4B to form a PN junction 5. The N-type base sub-region 4A directly borders the collector region 2 and the emitter region 3.

The channel 4B extends between the collector region 2 and the emitter region 3 and directly borders them. Compared with the collector region 2 and the emitter region 3, the net doping concentration of the channel 4B is very small; for example, the net doping concentration of the channel may be less than or equal to 5x10 ¹⁶ cm ^-3 .

In addition, the channel 4B is formed to have a depth, that is, a dimension extending orthogonally to the PN junction 5, which is much shallower than that of a conventional junction field effect transistor (JFET).

The N-type base sub-region 4A is composed of a first part and a second part. The net N dopant concentration of the first portion may be about 1e17/cm ³ ; the net doping concentration of the second portion may be, for example, about 1e18/cm ³ or 1e19/cm ³ .

A semiconductor structure implementing the above features is described below.

The structure has a P-type substrate 100, which may be, for example, a silicon wafer or a silicon layer deposited by epitaxial deposition on top of the wafer. An N-type region 101 is provided in the P-type substrate 100; the N-type region 101 and the P-type substrate 100 are separated by an N+-type region 102; an additional N+-type region 101A is provided in the N-type region 101 and extends to a surface of the substrate material; the N-type region 101 and the additional N+-type region 101A constitute an N-type base subregion 4A of the transistor device 1, and the base terminal B is connected through the additional N+-type region 101A; the net concentration of the N dopant in the N-type region 101 may be approximately 1e17/cm ³ ; the net doping concentration of the N+-type region 102 and the additional N+-type region 101A may be, for example, approximately 1e18/cm ³ or 1e19/cm ³ .

The top of the N-type region 101 is extended through a lightly doped P-region 103 to have a channel 4B and intersect with the N-type region 101 to provide the PN junction 5; the structure also includes two separated P-type regions 104 and 105. The first portion 104A and 105A of each P-type region 104 and 105 is provided by a respective independent portion of a P-type doped polysilicon layer; the second portion 104B and 105B of each P-type region 104 and 105 is formed in the silicon wafer and intersects with the N-type region 101 to provide corresponding diode junctions 5A and 5B.

An example manufacturing process of the semiconductor structure is described as follows. A first implantation and diffusion process uses a first mask to form the N+ type region 102 in the P type substrate 100; a second mask is used to form the N type region 101, and the N+ type region 102 is counter-doped by a P dopant to extend the N type region 101 to the wafer surface.

Without using a mask, the wafer surface is further doped with a P dopant to form the P-region 103 through the wafer surface; the net doping concentration of the P-region 103 can be, for example, 5e16/ ^cm3 or less; by ensuring that little or no diffusion occurs, the depth of the P-region 103 is kept very small. For ease of understanding, the relative thickness of the P-region 103 is exaggerated in Figure 1 compared to other layers.

Using a third mask, N dopant is implanted through the wafer surface to counter-dope a portion of the P- region 103 to form the additional N+ region 101A, which continues the N-type region 101.

Using the fourth mask, a polysilicon material layer is deposited and etched to provide several first portions 104A, 105A of the collector and emitter regions 2, 3. Using the fifth mask, the polysilicon material is doped with a P dopant and diffused downward to form several second portions 104B, 105B that intersect with the N-type region 101.

The P dopant implantation is followed by a short annealing, for example 10 seconds, to repair the crystal structure of the polysilicon and silicon wafer.

operating mode

Please refer to "Figure 2", which shows how the operating characteristics or modes of the transistor device of Figure 1 are based on the voltage (Vce) across the collector terminal and emitter terminal and across the base terminal and A schematic diagram showing changes in voltage (Vbe) at the emitter terminal. As shown in the picture:

With a PNP device, such as the one shown in Figure 1, regardless of the operating mode, it is usually operated with a negative Vce, i.e. the voltage applied to the collector is more negative than the voltage applied to the emitter, and Vbe can be positive or negative with a negative base-emitter junction in a positive relationship with the threshold voltage Vft. Any current through the base terminal will be negative (i.e., current is drawn out through the base terminal). In contrast, an NPN device is usually operated with a positive Vce and has a positive Vft, and any current through the base will be positive (i.e., current is pushed into the device through the base).

The five operating modes are indicated by zones K, J, L, M and N. When the device is off and no current flows through any of the terminals, the device is operating in zone K; when the device is on, it can operate in one of the zones J, L, M and N.

When the device is turned on (i.e., there is current between the collector and the emitter) and there is no or almost no (deminimus) current through the base terminal (i.e., Ib=0A), excluding any temporary switching current caused by the capacitive effect, the device is operated in region L or M; when the device is turned on (i.e., there is a non-zero current between the collector and the emitter) and there is current in the base terminal (i.e., Ib<0A), the device is operated in region J or N.

Operation under |Vce|<|Vt|

When the transistor device 1 is operated when |Vce| is less than |Vt|, the transistor device 1 acts as a normally-off device. That is, when Vbe is zero, there is no current between the emitter region 3 and the collector region 2 (the device is off (operating in region K)).

If |Vbe| increases causing the base-emitter diode junction 5B to become forward biased (that is, for a PNP transistor, Vbe becomes more negative than -Vft; for an NPN transistor , Vbe becomes more positive than Vft), the device switches to on, operating in the on-Majority bipolar (Majority Bipolar) region J, the current is drawn through the base terminal, and the current between the collector and the emitter is mainly due to bipolar conduction; or, if |Vbe| increases in the opposite direction, so that the base - The reverse bias of emitter diode junction 5B is stronger (i.e., for a PNP transistor, Vbe becomes more positive; for an NPN transistor, Vbe becomes more negative), and then the The device remains closed (operating in area K).

Where |Vce| is greater than |Vt'| and less than |Vt|, the operation of the device is similar to where |Vce| is less than |Vt'|, except that when |Vbe| is close to but less than |Vft|, the device enters Operating in the on-prime bipolar region L, where the device is on and the current through the base terminal is zero, the current between the collector and emitter is primarily due to unipolar conduction.

When |Vbe| becomes larger than |Vft|, it enters a region N, in which the unipolar conduction current is a maximum, and the bipolar conduction current increases until the bipolar conduction current is greater than the unipolar conduction current, so that the The device operates in the open main bipolar conducting region J.

Advantageously, a normally-off device can be switched on and operated in region L at a lower Vbe than existing BJTs, and advantageously lower than the base-emitter diode junction forward voltage (Vft). When operated in region L, the device has a significantly higher current gain for the same Vce than when operated in region J, but with a smaller value of maximum collector current. Due to the significantly lower Vbe, the device has a significantly higher current gain than existing BJTs when operated in region L - approaching infinite gain, since the current through the base terminal is essentially zero.

Operations under |Vce|>|Vt|

When the transistor device 1 operates when |Vce| is greater than the threshold voltage |Vt|, the transistor device 1 acts as a normally-on device. That is, when Vbe is zero, for example because the base is floating or connected to the emitter, the current between the emitter and collector exceeds a de minimis current.

When |Vce| is greater than |Vt| and Vbe is zero or close to zero, the transistor operates in the on-state, predominantly unipolar operating region M, where the current through the base terminal is zero and the current between the collector and emitter is primarily due to unipolar conduction.

When |Vbe| increases above Vft, causing the base-emitter diode junction 5B to become forward biased (i.e., for a PNP transistor, Vbe becomes more negative than -Vft; For an NPN transistor, Vbe becomes more positive than Vft), the device operates in the region N where the unipolar conduction reaches a maximum and the bipolar conduction increases. As |Vbe| increases further, the proportion of Ice attributable to bipolar conduction becomes greater than the proportion attributable to unipolar conduction current, over which operation is on and predominantly bipolar (region J).

The Vbe amplitude required to operate in this region J increases with the increase in Vce.

Alternatively, if |Vbe| increases in the opposite direction, causing the base-emitter diode junction 5B to be more reverse biased (i.e., Vbe becomes more positive for a PNP transistor and more negative for an NPN transistor), the device will turn off (operating region K).

Between the closed region K and the open main unipolar regions L and M is a transition region O where the operation of the device is unpredictable or difficult to control. For example, if the collector current in the closed region K is less than 1nA, and the collector current in the open regions L and M is on the order of 1uA or greater, then the collector current in the transition region O will be on the order of 10nA to 100nA.

The device 1 has a lateral spacing of distance X between the collector region 2 and the emitter region 3 to control the length of the channel 4B. The values of Vt and Vt' are related to the distance X between the emitter region and the collector interval. As the value of X increases, the amplitudes of |Vt| and |Vt'| also increase. In order for the device to have good bipolar conduction characteristics when operating in this region J, the maximum value of X is usually 1.5 microns.

The rated operating voltage range of a circuit determines the range of Vce values that will be applied to the transistors therein. When Vce is known, the spacing X of each transistor device 1 in the circuit can be selected when designing the circuit to determine whether it is operated as a normally open device or a normally closed device.

Please refer to "FIG. 3A to FIG. 3C", which respectively show the cross-sectional schematic diagram of the transistor in FIG. 1 configured under the on condition and the conduction between the emitter and the collector is mainly attributed to bipolar conduction, the cross-sectional schematic diagram of the transistor in FIG. 1 configured under the off condition, and the cross-sectional schematic diagram of the transistor in FIG. 1 configured under the on condition and the conduction between the emitter and the collector is mainly attributed to unipolar conduction. As shown in the figure: FIG. 3A to FIG. 3C show the device in FIG. 1, and the lateral spacing X between the emitter region and the collector region is relatively large, so that |Vce| is less than |Vt|, and therefore the device is operated as a normally-off transistor. In the present example, the spacing X is such that Vce is between Vt and Vt', thereby allowing the device to operate with characteristics of either region J, K or L, depending on Vbe.

Figure 3A is a schematic cross-section of the transistor in Figure 1 configured in an on condition and with conduction between its emitter and collector primarily due to bipolar conduction.

Figure 3A shows a normally closed device operating under a predominantly ON bipolar condition (area J in Figure 2). Since the emitter terminal E has a relatively positive voltage compared to the base terminal B, Vbe is more negative than Vft and is provided by the N-type region 101 between the emitter region 3 and the N-type base subregion 4A. The diode junction 5B is forward biased, allowing current to flow through the diode junction 5B between the emitter terminal E and the base terminal B (indicated by arrow 6). Therefore, there is a corresponding but much larger current between the emitter region 3 and the collector region 2, which is due to the two unipolar currents (indicated by arrow 7A) flowing together through the channel 4B, and due to A larger current flows through the N-type base sub-region 4A bipolar conduction (indicated by arrow 7B). The presence of unipolar conduction through channel 4B provides the transistor with gain characteristics superior to those of transistors with conventional BJT structures.

At locations with large collector-emitter currents, the bipolar current 7B can be significantly larger than the unipolar current 7A (eg, on the order of 10 times larger). In contrast, all (or nearly all) the current in a JFET can be attributed to unipolar conduction through the channel.

Figure 3B shows the device shown in area K in Figure 2 in a closed state. The VCE is the same as shown in Figure 3A, except that the base terminal B is floating or connected to the emitter terminal E, so no current flows through the base terminal B.

Under this condition, a depletion region 8 is generated, as shown by the dotted line near the PN junction 5. Since the channel 4B is very thin and weakly doped compared to the N-type base sub-region, the channel 4B is clamped to increase the resistance of the channel 4B so that there is basically no current between the emitter region 3 and the collector region 2.

FIG. 3C shows the device operating in a predominantly on unipolar condition (region L of FIG. 2 ) by applying a non-zero voltage Vbe that is less than Vft and across the emitter and base. Since Vbe is less than Vft, the diode junction 5B between the emitter region 3 and the N-type base subdivision region 4A is not sufficiently forward biased to allow current to flow, and thus no current flows through the base terminal B or the N-type base subdivision region 4A; however, since the net doping level of the channel 4B is very low, Vbe is sufficient to reduce the depletion region 8 around the PN junction 5 to a level that allows current to flow through the channel 4B via unipolar conduction between the emitter region 3 and the collector region 2 (indicated by arrow 7A). When operating in region L, the transistor has a high gain characteristic with Ib=0A. However, due to the shallowness of the channel, the maximum current that can be obtained before the channel is saturated is relatively low compared to operating in region J.

Please refer to "Figure 4A and Figure 4B", which respectively show a schematic diagram of a transistor cross section similar to Figure 1 but with a shorter spacing X and configured under the on condition and the current between the emitter and the collector is mainly attributed to unipolar conduction, and a schematic diagram of a transistor cross section configured under the off condition in Figure 4A. As shown in the figure: Figure 4A and Figure 4B show a different device with the same semiconductor structure as Figure 1, which differs in that the spacing X between the collector region 2 and the emitter region 3 is smaller and therefore has a shorter channel 4B. The selected spacing allows Vce to be greater than Vt and the device to operate as a normally-on transistor when operating in a circuit providing the same Vce range as the device in Figures 3A to 3C.

It should be noted that while choosing the lateral spacing between the collector and emitter regions is the most convenient way to control the channel length, a longer channel length can be provided for a given lateral emitter-collector spacing by forming the channel with a circuitous path between the emitter and collector regions.

FIG. 4A shows the device in a mainly open unipolar condition. VCE is the same as described in FIG. 3A to FIG. 3C, but is closer to the distance X between the collector 2 and the emitter 3, and therefore the channel 4B is shorter, so even when the base terminal B is suspended or connected to the emitter terminal E, it is sufficient to overcome the intrinsic depletion region 8 around the PN junction 5. Therefore, although there is no current flowing through the base terminal B, there is still current flowing through the channel 4B between the emitter and the collector.

Figure 4B shows the device in an off state, which is achieved by making the base terminal B significantly more positive than the emitter terminal E.

Please note that the surface area of the transistor (i.e., the dimensions shown in Figures 1, 3A~3C, and 4A, 4B) can be selected according to the maximum rated current that the transistor device 1 needs to meet to increase the The width of the base region including the channel 4B.

The P-type substrate 100 can be connected to a low voltage to ensure that the PN junction between the substrate and the N+ region 102 is reverse biased, which can suppress the adverse effects of parasitic lateral NPN BJT transistors between adjacent transistor base regions.

Part of the reason why the lateral N+ type region 102 is needed is to prevent the P- region 103 from causing a short circuit between the emitter and the substrate and to ensure that the parasitic vertical PNP BJT formed between the emitter and the substrate has poor performance. The current conduction characteristics are conducive to reducing the parasitic current by more than 100 times greater than the collector current of the device.

Alternative embodiments with different semiconductor structures and manufacturing methods

Please refer to "Figure 5A and Figure 5B", which are respectively a cross-sectional schematic diagram of another semiconductor structure for implementing a transistor device, and a schematic plan view of a transistor implemented by the semiconductor structure in Figure 5A. As shown in the figure: Figure 5A is another semiconductor structure for implementing the transistor device. Compared with the structure in Figure 1, this structure is more conducive to manufacturing. The dotted line QR represents the tangential axis of Figure 5A.

For example, a P-type substrate 200 is provided, which may be a silicon wafer or silicon crystal layer deposited on the top of the wafer by epitaxy. An N-type well 210 consisting of an upper N-type region 211, a lower N-type region 212 and an N+ type region 213 therebetween is provided in the P-type substrate 200.

Another N+ type region 214 surrounds the upper N type region 211 and the N+ type region 213. The N+ type region 214 overlaps with the N type well 210 and extends outward therefrom to provide the N type base sub-region 4A of the transistor.

A P-channel layer 220 providing channel 4B of the transistor is located above and in direct contact with the upper N-type region 211. The P-channel layer is in direct contact with the upper N-type region 211 below it to provide a PN junction 5 .

It is worth noting that the N+ type region 214 extends upward and surrounds the P- channel layer 220 to isolate the channel 4B from the substrate.

The doping concentration of the upper N-type region 211 is in the range of 1e17/cm ³ to 5e17/cm ^3. This is in contrast to the high doping levels (>1e19/cm ³ ) often found in JFET gates.

The P-channel layer 220 has a net doping concentration on the order of 1e16/cm ³ to 1e17/cm ³ .

An oxide layer 221 is located above the P-channel layer 220 . The structure also includes two separate P-type regions 222, 223, each P-type region extending through the oxide layer 221 and the P-channel layer 220 to provide corresponding collector and emitter regions 2, 223. 3.

The first portion 222A, 223A of each P-type region 222, 223 is provided by portions of a P-doped polysilicon layer located on the oxide layer 221 to connect the emitter and collector terminals to the circuit. middle. The second portion 222B, 223B of each P-type region 222, 223 is provided by portions of the polysilicon layer extending through the oxide layer 221 to contact the wafer surface. The third portion 222C, 223C of each P-type region 222, 223 is formed in the silicon wafer and interfaces with the upper N-type region 211 to provide corresponding diode junctions 5A, 5B.

A patterned oxide layer 500 and a metal layer 224 are located on the oxide layer 221 and the P-type regions 222 and 223 of the polysilicon layer. The first portion 224A of the metal layer 224 is patterned to provide conductive areas. A second portion 224B of the metal layer 224 extends through a hole in the oxide layer 500, 221 to contact the N+ region. 214 provides the base terminal.

Please refer to "Figure 6A ~ Figure 6I", which is a schematic diagram showing the manufacturing process of the transistor device in Figure 5A and Figure 5B. As shown in the figure: Figure 6A ~ Figure 6I is an example process, showing the manufacturing of a partial area of an integrated circuit, which is two transistors with the structure of Figure 5A and Figure 5B.

The first of the transistors is formed with a relatively small distance X between the collector and emitter regions, while the other has a relatively large distance, the distance being chosen such that during operation, the third One operates as a normally-on transistor and the other operates as a normally-off transistor. The channel length of the second transistor can be selected so that when turned on it operates with characteristics associated with regions L, N or J of Figure 2.

Please refer to Figure 6A, which provides a P-type substrate 200. Referring to Figure 6B, a mask, implantation and diffusion process is used to form a plurality of separate annular (circular or other similar shapes) N+ type regions 214 in a P-type substrate 200, one for each transistor.

Referring to FIG. 6C, a masking and injection process is used to form a plurality of N-type wells 210 in the corresponding annular N+-type regions 214. The diffusion process is omitted to leave the more highly doped N+-type region 213 below the surface (between the upper and lower N-type regions 211, 212).

Referring to FIG. 6D , an unmasked P-type implantation process is used to form the P-channel layer 220. This can be performed without diffusion or annealing. Because the doping required to form the P-channel layer 220 is very weak, the implantation will not have a decisive effect on the N+ region.

Referring to Figure 6E, an oxide layer 221 is added to the wafer through a deposition process. A deposition process is used to ensure that the P-channel layer 220 is not damaged.

A photoresist 300 is applied to the oxide layer. The photoresist 300 is patterned to define the spacing X between the collector and emitter regions and thereby define the length of the channel 4B. In this example, the spacing X of the left transistor is selected to be relatively small to provide a normally-on transistor, while the spacing X of the right transistor is selected to be relatively large to provide a normally-off transistor.

Taking a 1um manufacturing process as an example, the right transistor can have a channel length between 1.2 microns and 1.5 microns; while the left transistor can have a channel length equal to or less than 0.8 microns.

Please refer to Figure 6F, which shows etching the oxide layer and removing the mask.

Please refer to Figure 6G, where a polysilicon layer 400 is deposited on the wafer (the entire wafer can be selected). The P-type region 223 of the polysilicon layer directly contacts the exposed surface of the P-channel layer 220, and the oxide layer 221 thereon has been removed to form the second parts 222B and 223B of the collector and emitter contacts.

A P-type implantation process 401 (indicated by arrows) is performed to convert the polysilicon to P-type, which also increases the net doping concentration of the P-layer regions in direct contact with the polysilicon to form the third portions 222C, 223C of the collector and emitter regions 2, 3. A short annealing step activates the implantation without inducing diffusion of the P-channel layer 220. Alternatively, to reduce processing time, a P-type polysilicon may be deposited.

Referring to Figure 6H, the polysilicon layer 400 is masked and etched to pattern the collector and emitter regions 2, 3 with the first portions 222A, 223A.

Referring to Figure 6I, a mask and etching process is further used to subsequently expose a region of the N+ type region 214 and a metal layer 224 is deposited to provide the second portion 224B as a base contact, and a pattern is etched to This first portion 224A is provided as a winding layer.

Each of the devices described above can be replaced by an NPN device with an N-type channel, several emitter and collector regions, and a P-type base sub-section; in this way, the device can be used with Operate with the opposite polarity above.

The emitter region and/or the collector region can be formed entirely within the wafer, rather than using a crystalline silicon layer.

The above structure can be modified in conjunction with a zener diode by providing an additional P-type region to electrically connect between the base and collector terminals, as described in WO2019/229432;

The metal base contact can be replaced with a polysilicon doped contact; this will introduce a Zener diode into the base terminal, with the benefit of not requiring any metal layers to be routed adjacent to the device.

In summary, the present invention is a transistor device that can effectively improve various shortcomings of conventional devices. Among other advantages, it has better current gain characteristics than traditional lateral bipolar junction transistor (BJT). The existence of a channel is utilized to allow the transistor device to switch between on (operating under the first or fourth condition) and off in response to changes in Vbe that are less than the absolute value of the base-emitter diode forward voltage (Vft), such that This allows two transistor devices with the same configuration, e.g. both NPN or both PNP, to be used to switch both sides (high and low) of a driver circuit, rather than following the traditional requirements for a complementary circuit. The creation of an invention that can be more advanced, more practical, and better meet the needs of users has indeed met the requirements for an invention patent application, and a patent application must be filed in accordance with the law.

However, the above are only preferred embodiments of the present invention, and should not be used to limit the scope of the present invention; therefore, any simple equivalent changes and modifications made based on the patent scope of the present invention and the content of the invention description , should still fall within the scope covered by the patent of this invention.

1: Transistor device

2: Collector region

3: Emitter area

4A: N-type base sub-division

4B:Channel

5:PN junction

100:P type substrate

101:N type area

101A: N+ type area

102: N+ type area

103:P-Zone

104A, 105A: Part 1

104B, 105B: Part 2

5A, 5B: Diode junction

C: collector terminal

E: Emitter terminal

B: Base terminal

Claims (22)

A transistor device having: a collector region provided by a first region of a semiconductor of a first type; a collector terminal associated with the collector region; and a second region of a semiconductor of the first type. An emitter region is provided; an emitter terminal associated with the emitter region; a base region provided by a semiconductor third region located between the collector region and the emitter region and at the interface between the two. ; a base terminal associated with the base region; wherein the base region includes: a second type semiconductor base subregion, and a first type semiconductor channel, wherein the base terminal is in contact with the semiconductor base sub-region; the semiconductor base sub-region interfaces with the semiconductor channel to provide a first diode junction, and interfaces with both the emitter region and the collector region to further form a digital a second diode junction, and the semiconductor channel interfaces with and interconnects the collector region and the emitter region, so that when the device is implemented in a circuit under a first condition, the configuration is higher than When a voltage of a first threshold voltage penetrates the emitter terminals and the collector terminals, and the base terminal is floating or forms a short circuit with the emitter terminal, a current between the collector terminals and the emitter terminals is At least mainly due to unipolar conduction; the net doping concentration of the semiconductor channel is less than the net doping concentration of the emitter regions and the collector regions; and the semiconductor channel has a distance from the first diode junction to extends to a depth sufficiently small that when the device is implemented in a circuit under a second condition, the voltage configured across the emitter terminals and collector terminals is lower than the first threshold voltage, and When the base terminal is floating or short-circuited with the emitter terminal, a depletion region is formed near the first diode junction, which is sufficient to clamp the semiconductor channel so that the current There is substantially no current between the collector terminals and the emitter terminals of the crystal device; and wherein, when the transistor device is implemented in a circuit under a third condition, a voltage is configured to pass through the emitter terminals and the collector terminal, and there is a voltage across the emitter terminal and the base terminal to generate a current through the base terminal, the current between the collector terminal and the emitter terminal is at least mainly due to bipolar conduction . A transistor device according to item 1 of the patent application, wherein the distance between the collector regions and the emitter regions is less than or equal to 1.5 microns. A transistor device according to item 1 of the patent application, wherein the semiconductor channel extends from the first diode junction and has a depth less than or equal to 0.25 microns, preferably less than or equal to 0.1 microns. . A transistor device according to item 1 of the patent application, wherein the semiconductor base subdivision includes a first portion and a second portion, and wherein: the first portion has a higher net doping concentration than the second portion; the base terminal is electrically connected to the second portion through the first portion; and wherein the second portion is bounded by the semiconductor channel to provide the first diode junction, and is bounded by the emitter region and the collector region to further form the plurality of second diode junctions. A transistor device according to item 4 of the patent application, wherein the net doping concentration of the semiconductor channel is less than or equal to one time of the net doping concentration of the second part of the semiconductor base sub-region. A transistor device according to item 5 of the patent application, wherein the net doping concentration of the semiconductor channel is less than or equal to 0.1 times the net doping concentration of the second part of the semiconductor base sub-region. A transistor device according to claim 6 of the patent application, wherein the second part of the semiconductor base sub-region has a net doping concentration between 5e16/cm ³ and 5e17/cm ³ . A transistor device according to item 4 of the patent application, wherein the first part of the semiconductor base sub-region has a net doping concentration greater than or equal to 1e18/cm ³ . According to the transistor device described in item 1 of the patent application, the semiconductor base sub-region is located in a semiconductor substrate of the first type, and the transistor device further includes a highly doped semiconductor of the second type. A region is located between and separates the second portion of the semiconductor base sub-region from the semiconductor substrate; the highly doped region has a high net doping concentration compared to the semiconductor base sub-region. A transistor device according to item 1 of the patent application, wherein the emitter region and/or the collector region are provided by a doped polycrystalline silicon layer, and the doped polycrystalline silicon layer is located to define the base region on one of the silicon wafers. An integrated circuit includes two transistor devices as described in item 1 of the patent application, wherein a semiconductor channel of a first transistor device among the transistor devices is relatively long, and a relatively large lateral distance exists between the collector region and the emitter region of the first transistor device; and a semiconductor channel of a second transistor device among the transistor devices is relatively short, and a relatively small lateral distance exists between the collector region and the emitter region of the second transistor device. The integrated circuit according to claim 11, wherein the first transistor device and the second transistor device operate with the same collector-emitter voltage range, and the voltage range is selected to The first transistor device and the second transistor device both operate as normally-off transistors, such that the current in the emitter region and collector region of the first transistor device has a bipolar conduction component greater than that of the second transistor device. A transistor device, wherein the first transistor device operates as a normally-on transistor and the second transistor device operates as a normally-off transistor. A method for manufacturing an integrated circuit. The integrated circuit includes the transistor device described in item 1 of the two patent applications. The method includes manufacturing a first transistor device among the transistor devices. A transistor device having a first lateral spacing between the emitter regions and the collector regions; and fabricating a second transistor device of the transistor devices having a first lateral spacing between the emitter regions and the collector regions. The intervals have a second lateral spacing; and the first lateral spacing and the second lateral spacing are different. The manufacturing method of the integrated circuit described in Item 13 of the patent application scope includes: using the same mask to define the distance between the emitter regions and the collector regions of the first transistor device and the second transistor device. The method for manufacturing an integrated circuit according to claim 14 includes using the mask in a material removal process to define the emitter regions and collector regions of the first transistor device and the second transistor device. The manufacturing method of the integrated circuit described in Item 15 of the patent application scope includes depositing an oxide layer between the emitter region and the collector region and on a base region at the junction of the two; using the mask to remove part of the oxide layer; and depositing polysilicon in the region where the oxide layer has been removed to provide the collector region and the emitter region. A transistor device having: a collector region provided by a first region of a semiconductor of a first type; a collector terminal associated with the collector region; a second region of a semiconductor of the first type An emitter region is provided; an emitter terminal associated with the emitter region; a base region provided by a semiconductor third region located between the collector region and the emitter region and at the interface between the two. ; a base terminal associated with the base region; wherein the base region includes: a second type semiconductor base subregion, and a first type semiconductor channel, wherein the base terminal is in contact with the semiconductor base sub-region; The semiconductor base sub-region system interfaces with the semiconductor channel to provide a first diode junction, and the semiconductor channel interfaces with and interconnects the collector region and the emitter region; the net doping concentration of the semiconductor channel is less than the net doping concentration of the emitter regions and collector regions; and the semiconductor channel has a depth extending far from the first diode junction that is small enough. When the circuit is implemented in a circuit In a crystal device, when a voltage passes through several emitter terminals and collector terminals and the base terminal is floating or short-circuited with the emitter terminal, a depletion region is formed near the first diode junction that is sufficient to clamp The semiconductor channel is bundled so that there is substantially no current between the collector terminals and the emitter terminals of the transistor device. A transistor device according to item 25 of the patent application, wherein the semiconductor channel provides a unique interface with one or both of the collector regions and the emitter regions. A transistor device according to item 25 of the patent application, wherein the semiconductor base sub-region is respectively connected with the emitter region and the collector region to further form a plurality of second diode junctions . A transistor device according to item 25 or 27 of the patent application, wherein the semiconductor base sub-region surrounds the emitter region and the collector region. A transistor device according to claim 25, wherein the semiconductor base sub-region is formed in a semiconductor substrate of the first type, and the transistor device further includes a semiconductor substrate of the second type. A doped region is located between the semiconductor base sub-region and the semiconductor substrate and separates the two; the highly doped region has a high net doping concentration compared with the semiconductor base sub-region. A transistor device according to claim 25, wherein the emitter region and the collector region are provided by a doped polysilicon layer, and the doped polysilicon layer is deposited on a silicon grain defining the base region.