TW202404028A - A novel transistor device - Google Patents

A novel transistor device Download PDF

Info

Publication number
TW202404028A
TW202404028A TW112138744A TW112138744A TW202404028A TW 202404028 A TW202404028 A TW 202404028A TW 112138744 A TW112138744 A TW 112138744A TW 112138744 A TW112138744 A TW 112138744A TW 202404028 A TW202404028 A TW 202404028A
Authority
TW
Taiwan
Prior art keywords
region
emitter
collector
semiconductor
base
Prior art date
Application number
TW112138744A
Other languages
Chinese (zh)
Other versions
TWI855892B (en
Inventor
薩默蘭 大衛
萊特 羅傑
奈特 盧克
Original Assignee
英商尋找未來有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英商尋找未來有限公司 filed Critical 英商尋找未來有限公司
Publication of TW202404028A publication Critical patent/TW202404028A/en
Application granted granted Critical
Publication of TWI855892B publication Critical patent/TWI855892B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H01L29/1008—Base region of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A bipolar transistor having a semiconductor structure that includes a channel of semiconductor type that is the same as the collector and emitter regions. The channel is significantly shallower than the base region with which it interfaces. The novel structure provides improved current gain. It also enables the device to operate, when on, selectively either with primarily unipolar conduction or primarily bipolar conduction by control of the voltage across the emitter and collector terminals.

Description

一種新型電晶體裝置A new type of transistor device

本發明係有關於一種新穎的電晶體，除其他優點外，具有優於傳 統橫向雙極性接面型電晶體（bipolar junction transistor, BJT）之電流增益特性。 The present invention relates to a novel transistor which, among other advantages, has advantages over conventional Current gain characteristics of traditional lateral bipolar junction transistor (BJT).

BJT之半導體結構與摻雜配置使其射極與集極間之電流（受控電 流）成為電子與電洞二電荷載子之運動的結果，稱為雙極傳導。 The semiconductor structure and doping configuration of BJT make the current between emitter and collector (controlled current The flow) becomes the result of the movement of two charge carriers, electrons and holes, which is called bipolar conduction.

相比之下，在場效電晶體（field effect transistor, FET）或接面場效 電晶體（junction field effect transistor, JFET）中，該些源極與汲極端子間之電流（受控電流）主要（即使並非唯獨）可歸因於電子或電洞的移動，而無法同時歸因於兩者，此稱為單極傳導或單載子型操作。 In contrast, field effect transistors (FETs) or junction field effect In a junction field effect transistor (JFET), the current (controlled current) between the source and drain terminals can be attributed mainly, if not exclusively, to the movement of electrons or holes, but not both. Because of both, this is called unipolar conduction or monocarrier type operation.

美國專利US6251716B1、US200316704A1與US2009206375係習知 JFET配置之範例，因此其源極與汲極間之電流主要歸因於單極傳導。故，一般習用者係無法符合使用者於實際使用時之所需。 U.S. patents US6251716B1, US200316704A1 and US2009206375 are common knowledge Example of a JFET configuration such that the current between its source and drain is primarily due to unipolar conduction. Therefore, ordinary users cannot meet the needs of users in actual use.

本發明之主要目的係在於，克服習知技藝所遭遇之上述問題並提 供一種由於通道的存在，與基本上傳統BJT半導體結構不同，本裝置可作為一常開裝置或一常關裝置來操作，取決於所施加貫穿該些射極端子與集極端子之電壓。 The main purpose of the present invention is to overcome the above-mentioned problems encountered in the conventional art and to provide Due to the presence of channels, unlike essentially conventional BJT semiconductor structures, the device can operate as a normally-on device or a normally-off device, depending on the voltage applied across the emitter and collector terminals.

在第一方面，本發明係提供一電晶體裝置，具有：由一第一類型 之一半導體第一區所提供之一集極區；與該集極區關聯之一集極端子；一由第一類型之半導體第二區所提供之射極區；與該射極區關聯之一射極端子；由位於該集極區與該射極區之間且與該二者交界之一半導體第三區所提供之一基極區；與該基極區關聯之一基極端子；其中，該基極區係包括：一第二類型之一半導體基極次分區，及該第一類型之一半導體通道，其中，該基極端子係接觸該半導體基極次分區；該半導體基極次分區係與該半導體通道交界以提供一第一二極體接面，並且與該射極區及集極區二者交界以進一步形成數個第二二極體接面，而該半導體通道係與該集極區及該射極區交界並互連，使該電晶體裝置在一第一條件下之一電路中實作時，即配置高於一第一閾值電壓之一電壓貫穿該些射極端子與集極端子，且該基極端子係浮動或與該射極端子形成短路時，該些集極端子與射極端子間之一電流係至少主要歸因於單極傳導；該半導體通道之淨摻雜濃度係小於該些射極區與集極區之淨摻雜濃度；並且該半導體通道具有自遠離該第一二極體接面所延伸而來足夠小之一深度，使該電晶體裝置在一第二條件下之一電路中實作時，即所配置穿該些射極端子與集極端子之電壓低於該第一閾值電壓，且該基極端子係浮動或與該射極端子形成短路時，在該第一二極體接面附近係形成一空乏區足以夾束該半導體通道，使該電晶體裝置之該些集極端子與射極端子間基本上沒有電流；以及，當該電晶體裝置在一第三條件下之一電路中實作時，即配置電壓貫穿該些射極端子與集極端子，且具一電壓貫穿該些射極端子與基極端子以透過該基極端子產生電流時，該些集極端子與射極端子間之電流係至少主要歸因於雙極傳導。 In a first aspect, the present invention provides a transistor device having: a first type a collector region provided by a first region of a semiconductor; a collector terminal associated with the collector region; an emitter region provided by a second region of a semiconductor of the first type; associated with the emitter region an emitter terminal; a base region provided by a semiconductor third region located between the collector region and the emitter region and at the interface between the two; a base terminal associated with the base region; Wherein, the base region includes: a second type semiconductor base sub-region, and a first type semiconductor channel, wherein the base terminal is in contact with the semiconductor base sub-region; the semiconductor base The sub-regions interface with the semiconductor channel to provide a first diode junction, and interface with the emitter region and the collector region to further form a plurality of second diode junctions, and the semiconductor channel is Interconnected and interconnected with the collector region and the emitter region, the transistor device, when implemented in a circuit under a first condition, disposes a voltage higher than a first threshold voltage across the emitters. terminal and the collector terminal, and when the base terminal is floating or forms a short circuit with the emitter terminal, one of the currents between the collector terminal and the emitter terminal is at least mainly due to unipolar conduction; the semiconductor channel The net doping concentration is less than the net doping concentration of the emitter regions and the collector regions; and the semiconductor channel has a depth that is small enough from extending away from the first diode junction so that the electrical When the crystal device is implemented in a circuit under a second condition, that is, the voltage across the emitter terminals and collector terminals is lower than the first threshold voltage, and the base terminal is floating or connected to the emitter terminal. When the terminals are short-circuited, a depletion region is formed near the first diode junction, which is sufficient to clamp the semiconductor channel, so that there is basically no current between the collector terminals and the emitter terminals of the transistor device; and , when the transistor device is implemented in a circuit under a third condition, a voltage is configured to pass through the emitter terminals and the collector terminals, and a voltage passes through the emitter terminals and the base terminal to pass through When the base terminal generates current, the current between the collector terminals and the emitter terminals is at least mainly due to bipolar conduction.

由於該半導體通道的存在，與基本上傳統BJT半導體結構不同， 該電晶體裝置可作為一常開裝置或一常關裝置來操作，取決於所施加貫穿該些射極端子與集極端子之電壓。 Due to the existence of this semiconductor channel, it is different from basically the traditional BJT semiconductor structure. The transistor device may operate as a normally-on device or a normally-off device, depending on the voltage applied across the emitter and collector terminals.

該閾值電壓之值與在射極區與集極區間延伸之該半導體通道的 長度相關，因此通常也與該射極區與集極區間之間隔距離相關。因此，對於預期之射極—集極電壓範圍而言，可以通過選擇該半導體通道的長度來製作該電 晶體裝置以在常開或常關下操作。 The value of the threshold voltage is related to the value of the semiconductor channel extending between the emitter region and the collector region. It is related to the length and therefore usually to the distance between the emitter region and the collector region. Therefore, the circuit can be made by selecting the length of the semiconductor channel for the expected emitter-collector voltage range. The crystal device can operate in either a normally open or normally closed state.

相同的遮罩程序可以用來定義電路中所有電晶體裝置之間距。此 一優勢，使得製造包含常開與常關電晶體之積體電路成為可能，而無需額外的處理步驟。此類電路可用來執行通常需要使用互補電晶體的功能，例如NMOS與PMOS，其需要更多的半導體層及／或生產步驟來實現。可受益於此一進步之應用包含邏輯門電路、模擬比較器與運算放大器電路。 The same masking procedure can be used to define the spacing between all transistor devices in the circuit. this An advantage makes it possible to fabricate integrated circuits containing normally-on and normally-off transistors without the need for additional processing steps. Such circuits can be used to perform functions that normally require the use of complementary transistors, such as NMOS and PMOS, which require more semiconductor layers and/or production steps to implement. Applications that can benefit from this advancement include logic gate circuits, analog comparators, and operational amplifier circuits.

在該第一條件下操作時，所施加貫穿該些射極端子與集極端子之 電壓（Vce）係大於該第一閾值，且本電晶體裝置係作為常開裝置；該半導體通道允許該些集極端子與射極端子間之單極傳導，儘管沒有電流通過該基極端子。 When operating under the first condition, the applied voltage across the emitter terminals and collector terminals The voltage (Vce) is greater than the first threshold and the transistor device acts as a normally-on device; the semiconductor channel allows unipolar conduction between the collector and emitter terminals, although no current flows through the base terminal.

在該第二條件下操作時，貫穿該些射極端子與集極端子之電壓係 低於第一閾值，該半導體通道之非常小的深度（一提供給該半導體通道之半導體層的小深度功能）意味著一存在於該第一二極體接面附近之空乏區足以使該半導體通道具有足夠高的電阻防止電流通過該半導體通道。 When operating under the second condition, the voltage system across the emitter terminals and collector terminals Below the first threshold, the very small depth of the semiconductor channel (a function of the small depth of the semiconductor layer provided to the semiconductor channel) means that a depletion region present near the first diode junction is sufficient for the semiconductor The channel has a resistance high enough to prevent current flow through the semiconductor channel.

此可視為，當Vce大於閾值時，足可克服空乏區，允許該射極與 集極間存在電流。隨著該半導體通道長度增加，克服空乏區所需之Vce值也增加。 This can be regarded as, when Vce is greater than the threshold, it is enough to overcome the depletion region, allowing the emitter to There is current between the collectors. As the length of the semiconductor channel increases, the Vce value required to overcome the depletion region also increases.

該半導體通道之非常小的絕對深度，以及其與半導體基極次分區 之深度相比相對較小的深度，意味著在第三條件下操作時，即貫穿該些射極端子與基極端子之電壓（Vbe）大於該基極—射極二極體接面之正向偏電壓（bias voltage）（Vft）時，通過該基極端子之電流的一大部分將歸因於該射極區及該半導體基極次分區之雙極傳導而非該半導體通道之雙極傳導。 The very small absolute depth of the semiconductor channel and its subdivision with respect to the semiconductor base The relatively small depth compared to the depth means that when operating under the third condition, that is, the voltage (Vbe) across the emitter terminals and the base terminal is greater than the positive voltage of the base-emitter diode junction. At a bias voltage (Vft), a large portion of the current through the base terminal will be due to the ambipolar conduction of the emitter region and the semiconductor base subregion rather than the ambipolar conduction of the semiconductor channel. conduction.

儘管如此，在第三條件下操作時，與具傳統結構之BJT電晶體相 比，該半導體通道之存在係給該電晶體提供改進的增益特性。此被視為係因該半導體通道提供該些射極區與集極區間之一傳導路徑，而無需穿過一二極體接面，且其因此提供相對較低電阻。 Nevertheless, when operating under the third condition, it is comparable to the BJT transistor with a conventional structure. The presence of the semiconductor channel provides improved gain characteristics to the transistor. This is thought to be because the semiconductor channel provides a conductive path between the emitter and collector regions without passing through a diode junction, and it therefore provides relatively low resistance.

本電晶體裝置之運作方式的一個結果為，當Vbe之值變化至高於 Vft時，Ice的比例可歸因於雙極傳導與單極傳導之變化，從而該電晶體之電流增 益發生變化；隨著雙極傳導之比例的增加，該電流增益亦下降。 One consequence of the way this transistor device operates is that when the value of Vbe changes above At Vft, the ratio of Ice can be attributed to the change in bipolar conduction and unipolar conduction, thereby increasing the current of the transistor. The gain changes; as the proportion of bipolar conduction increases, the current gain also decreases.

本新型電晶體設計之另一意外但有利的特徵為，通過為一已知之 Vce的操作範圍選擇該半導體通道之長度，可讓一常關電晶體在Vbe值低於該基極—射極二極體接面之正向偏電壓時切換為開啟。 Another unexpected but advantageous feature of the new transistor design is that by using a known The operating range of Vce selects the length of the semiconductor channel to allow a normally-off transistor to switch on when the Vbe value is lower than the forward bias voltage of the base-emitter diode junction.

換句話說，當操作在一第四條件下，即其中貫穿該些射極端子與 集極端子之該電壓係介於該第一閾值（Vt）與第二閾值（Vt'）之間（其中|Vt'|＜|Vt|）時，操作為一常關電晶體之該電晶體裝置，當Vbe小於該基極—射極二極體接面之正向偏電壓（Vft）時，係切換為開啟。 In other words, when operating under a fourth condition in which the emitter terminals and When the voltage at the collector terminal is between the first threshold (Vt) and the second threshold (Vt') (where |Vt'|<|Vt|), the transistor operates as a normally-off transistor. The device switches on when Vbe is less than the forward bias voltage (Vft) of the base-emitter diode junction.

在一第四條件下操作時，該射極與集極間之電流係通過該半導體 通道之單極傳導的結果，因此與在該第四條件下操作時相比，該電晶體裝置具有更高的增益，儘管該射極與集極間之最大電流較小。 When operating under a fourth condition, the current between the emitter and the collector passes through the semiconductor As a result of the unipolar conduction of the channel, the transistor device has a higher gain than when operating under the fourth condition, although the maximum current between the emitter and collector is smaller.

本電晶體裝置用於在轉為關閉及該第四條件間作切換時，係具一 半導體通道，因其太長（當Vbe=0時），對一個小於Vt值的Vce來說，得以克服該第一二極體接面附近之空乏區。然而，該半導體通道足夠短，以施加小的正向電壓貫穿該些基極端子與射極端子（Vbe大於0），又不足以克服該基極—射極二極體接面附近之一空乏區（Vbe＜Vft），因此使Ibe=0，足以削弱該第一二極體接面附近之本質空乏區至容許該射極與集極間藉該半導體通道流通電流的程度。在該第四條件下操作本電晶體裝置所需之Vbe最小值將取決於該電晶體裝置之Vce與Vt值。 The transistor device is used to switch between turning off and the fourth condition. The semiconductor channel, because it is too long (when Vbe=0), can overcome the depletion region near the first diode junction for a Vce value smaller than Vt. However, the semiconductor channel is short enough to apply a small forward voltage across the base terminals and emitter terminals (Vbe greater than 0), but is not short enough to overcome a depletion near the base-emitter diode junction. region (Vbe<Vft), so setting Ibe=0 is enough to weaken the intrinsic depletion region near the first diode junction to an extent that allows current to flow between the emitter and the collector through the semiconductor channel. The minimum value of Vbe required to operate the transistor device under the fourth condition will depend on the Vce and Vt values of the transistor device.

一個有用的應用包括一個驅動器電路，其有助於數個第一級電晶 體減少雙極傳導（即較多的單極傳導—其中可能只有單極傳導）以提供更高的 增益，而數個第二級電晶體則增加雙極傳導以允許更高的額定電流，同時最小 化該電晶體裝置之表面積（平面面積）。 A useful application involves a driver circuit that helps several first-stage transistors The body reduces bipolar conduction (i.e. more unipolar conduction - where there may only be unipolar conduction) to provide higher gain, while several second-stage transistors increase bipolar conduction to allow higher current ratings while minimizing The surface area (planar area) of the transistor device.

究其益處，該半導體通道之存在允許本電晶體裝置在開啟（在第 一或第四條件下操作）與關閉間切換以回應小於該基極—射極二極體正向電壓絕對值（Vft）之Vbe變化，如此可允許例如二個具有相同配置之電晶體裝置，例如皆為NPN或皆為PNP，用於切換一驅動電路之兩側（高與低），而非依照對一互補電路之傳統要求。 As a benefit, the presence of the semiconductor channel allows the transistor device to be switched on (in Section 1. operating under conditions 1 or 4) and switching off in response to changes in Vbe that are less than the absolute value of the base-emitter diode forward voltage (Vft), thus allowing, for example, two transistor devices with the same configuration, For example, both NPN or both PNP are used to switch both sides (high and low) of a driver circuit, rather than following the traditional requirements for a complementary circuit.

該半導體通道之合適深度將取決於該電晶體所設計以操作之Vce 值及／或該半導體通道之摻雜濃度。 The appropriate depth of the semiconductor channel will depend on the Vce the transistor is designed to operate value and/or the doping concentration of the semiconductor channel.

例如，對於一用來在0V與│5V│間電壓下操作之電晶體而言， 一小於0.25μm（0.1μm或更小更好）之通道深度可能是合適的。 For example, for a transistor designed to operate at a voltage between 0V and │5V│, A channel depth of less than 0.25 μm (0.1 μm or less is better) may be suitable.

然而，在一給定之操作電壓下，該半導體通道所允許之最大深度 將明顯小於一設計來操作在可比對之操作電壓下之JFET所會存在的深度。 However, at a given operating voltage, the maximum depth allowed by the semiconductor channel will be significantly less than the depth that a JFET designed to operate at comparable operating voltages would exist.

相反地，與該第一二極體接面相反方向所延伸之該半導體基極次 分區的深度可以等於或大於該半導體通道之深度的五倍；在一些實施例中，該半導體基極次分區之深度可以是該半導體通道之深度的至少二十倍。 On the contrary, the semiconductor base sub-section extending in the opposite direction to the first diode junction The depth of the sub-region may be equal to or greater than five times the depth of the semiconductor channel; in some embodiments, the depth of the semiconductor base sub-region may be at least twenty times the depth of the semiconductor channel.

該半導體基極次分區可包含一第一部分與一第二部分，且其中： 該第一部分具比該第二部分更高之淨摻雜濃度；該基極端子係透過該第一部分電性連接該第二部分；以及，其中該第二部分係與該半導體通道交界以提供該第一二極體接面，且與該射極區與集極區交界以形成該第二二極體接面。如此可確保在該基極接點使用一相對高摻雜之區域以提供一歐姆接點，而一較低摻雜之區域則與該些半導體通道、射極區與集極區交界。 The semiconductor base sub-region may include a first part and a second part, and wherein: The first portion has a higher net doping concentration than the second portion; the base terminal is electrically connected to the second portion through the first portion; and wherein the second portion interfaces with the semiconductor channel to provide the The first diode junction interfaces with the emitter region and the collector region to form the second diode junction. This ensures that a relatively highly doped region is used at the base contact to provide an ohmic contact, while a less doped region borders the semiconductor channels, emitter and collector regions.

為確保在第三條件下操作時以雙極傳導為主，需要仔細選擇該些 射極區、集極區與基極區之次分區的淨摻雜濃度，以及該些射極區與集極區間之間距（亦稱為基極寬度）；其確切數值將取決於各變量，例如Vce與Vbe之預期操作電壓範圍以及其半導體製造程序之大小與所使用之材料；用於選擇該些變量之值的方法與設計一傳統BJT結構的方法係相同且常見，因此熟知本領域技術之人員將很容易理解。 To ensure that bipolar conduction dominates when operating in the third condition, these need to be carefully selected. The net doping concentration of the sub-regions of the emitter, collector and base regions, and the distance between these emitter and collector regions (also known as the base width); the exact value will depend on various variables, For example, the expected operating voltage range of Vce and Vbe as well as the size of the semiconductor fabrication process and the materials used; the methods used to select the values of these variables are the same and common in designing a traditional BJT structure, and therefore are well known in the art. It will be easy for people to understand.

該半導體通道之淨摻雜濃度可以等於或小於（例如0.1到1倍間） 該半導體基極次分區淨摻雜濃度；如此可確保該第一二極體接面處之空乏區與該半導體基極次分區相比係優先存在於該半導體通道內。例如，在該半導體通道由P型半導體材料所構成而該半導體基極次分區由N型半導體材料所構成之情況下，該半導體通道中P型摻雜劑之淨摻雜濃度可為該半導體通道中N型摻雜劑之淨摻雜濃度的0.1到1倍。 The net doping concentration of the semiconductor channel can be equal to or less than (for example, between 0.1 and 1 times) The net doping concentration of the semiconductor base sub-region; this ensures that the depletion region at the first diode junction preferentially exists in the semiconductor channel compared with the semiconductor base sub-region. For example, in the case where the semiconductor channel is composed of P-type semiconductor material and the semiconductor base sub-region is composed of N-type semiconductor material, the net doping concentration of the P-type dopant in the semiconductor channel can be 0.1 to 1 times the net doping concentration of the medium N-type dopant.

為在該半導體基極次分區之第一部分內提供良好導電特性，該半 導體基極次分區之第一部分可每平方公分具有1e16至5e17之淨摻雜濃度，包括端值。 To provide good conductive properties within the first portion of the semiconductor base sub-region, the half The first portion of the conductor base sub-region may have a net doping concentration of 1e16 to 5e17 per square centimeter, inclusive.

良好的雙極傳導特性還取決於該些集極區與射極區間相對小之 側面間距，因此該些集極區與射極區間之側面間距可小於或等於1.5微米。 Good bipolar conduction characteristics also depend on the relatively small collector and emitter regions. The side spacing, therefore, the side spacing between the collector regions and the emitter regions may be less than or equal to 1.5 microns.

該些射極區及／或集極區可至少部分位於該半導體基極次分區 內。 The emitter regions and/or collector regions may be at least partially located in the semiconductor base sub-region within.

另一方面，本發明提供一電晶體裝置，係具有：由一第一類型之 一半導體第一區所提供之一集極區；與該集極區關聯之一集極端子；由該第一類型之一半導體第二區所提供之一射極區；與該射極區關聯之一射極端子；由位於該集極區與該射極區之間且與二者交界之一半導體第三區所提供之一基極區；與該基極區關聯之一基極端子，其中，該基極區係包括：一第二類型之一半導體基極次分區，及該第一類型之一半導體通道，其中，該半導體基極次分區係與該半導體通道交界以提供一第一二極體接面，且該半導體通道與該集極區及該射極區交界並互連；該半導體通道之淨摻雜濃度係小於該些射極區與集極區之淨摻雜濃度；且該半導體通道具有遠自該第一二極體接面延伸而來之與該半導體基極次分區相比足夠小的一深度，當在一電路中實作該電晶體裝置，而其中一電壓貫穿數個射極端子與集極端子且該基極端子係浮動或與該射極端子短路時，在該第一二極體接面附近係形成一空乏區足以夾束該半導體通道，使該電晶體裝置之該些集極端子與射極端子間基本上沒有電流。 In another aspect, the present invention provides a transistor device having: a first type a collector region provided by a first region of a semiconductor; a collector terminal associated with the collector region; an emitter region provided by a second region of a semiconductor of the first type; associated with the emitter region an emitter terminal; a base region provided by a semiconductor third region located between the collector region and the emitter region and at the interface between the two; a base terminal associated with the base region, Wherein, the base region includes: a second type semiconductor base sub-region, and a first type semiconductor channel, wherein the semiconductor base sub-region interfaces with the semiconductor channel to provide a first A diode junction, and the semiconductor channel borders and interconnects the collector region and the emitter region; the net doping concentration of the semiconductor channel is less than the net doping concentration of the emitter region and the collector region; and the semiconductor channel has a depth extending far from the first diode junction that is sufficiently small compared to the semiconductor base subregion that when the transistor device is implemented in a circuit in which a voltage When several emitter terminals and collector terminals are penetrated and the base terminal is floating or short-circuited with the emitter terminal, a depletion region is formed near the first diode junction, which is enough to clamp the semiconductor channel so that the There is essentially no current flowing between the collector terminals and the emitter terminals of the transistor device.

該半導體基極次分區係可形成於一該第一類型之半導體基板中， 半導體基板因此可提供隔離多個個別半導體積體元件之功能。 The semiconductor base sub-region system may be formed in a semiconductor substrate of the first type, The semiconductor substrate thus provides the function of isolating multiple individual semiconductor integrated devices.

為最小化由該半導體基板、半導體基極次分區及集極區及／或射 極區所組合而成之一寄生電晶體的影響，該電晶體裝置可進一步包含一該半導體第二類型之高摻雜區，使其安插，以便分隔，於該半導體基極次分區與該半導體基板之間，而該高摻雜區係具有比該半導體基極次分區高之淨摻雜濃度。 In order to minimize the interference caused by the semiconductor substrate, semiconductor base sub-region and collector region and/or emitter The transistor device may further include a highly doped region of the second type of the semiconductor disposed to separate the base sub-region of the semiconductor from the semiconductor between the substrates, and the highly doped region has a higher net doping concentration than the semiconductor base sub-region.

該射極區與該集極區可，至少一部分，由一多晶矽層提供；所摻 雜之多晶矽的圖樣可位於形成該基極區之一矽晶片的表面上。 The emitter region and the collector region may be, at least partially, provided by a polycrystalline silicon layer; doped A pattern of hybrid polysilicon may be located on the surface of a silicon wafer forming the base region.

該射極區可具一比該集極區更高之淨摻雜濃度；或，該射極區與 集極區之淨摻雜濃度可基本相同。 The emitter region can have a higher net doping concentration than the collector region; or, the emitter region and The net doping concentration of the collector region can be substantially the same.

本發明現在將參考以下圖示藉由範例加以描述。 請參閱『第１圖』所示，係實作一電晶體之半導體結構的截面示意圖。如圖所示：本發明係一新穎電晶體裝置１，該電晶體裝置１被視為對雙極性接面電晶體（bipolar junction transistor, BJT）裝置之改進並且在某些方面以類似方式操作；為此，係使用BJT標示該裝置之各端子。 The invention will now be described by way of example with reference to the following figures. Please refer to "Figure 1", which is a cross-sectional schematic diagram of a semiconductor structure for implementing a transistor. As shown in the figure: the present invention is a novel transistor device 1. The transistor device 1 is regarded as an improvement on the bipolar junction transistor (BJT) device and operates in a similar manner in some aspects; For this reason, BJT is used to mark each terminal of the device.

該裝置１在本範例中為一PNP型且未按比例顯示，係由摻雜之半 導體材料所構成，以提供一集極區２、一射極區３與一基極區４。該基極區４係位於該集極區２與射極區３之間。 Device 1, in this example a PNP type and not shown to scale, is composed of half doped Made of conductive material to provide a collector region 2, an emitter region 3 and a base region 4. The base region 4 is located between the collector region 2 and the emitter region 3 .

該集極區２與射極區３皆為P型半導體，按照慣例，該射極區３ 可有比該集極區２更多的摻雜。例如，該集極區２之淨摻雜濃度可大於或等於1×10 18cm -3，該射極區３之淨摻雜濃度可大於或等於2×10 18cm -3；或，為便於製造，可改為具有基本相同之淨摻雜濃度。該集極端子Ｃ係連接至該集極區２，該射極端子Ｅ連接至該射極區３，該基極端子Ｂ連接至該基極區４。 The collector region 2 and the emitter region 3 are both P-type semiconductors. According to convention, the emitter region 3 can be more doped than the collector region 2 . For example, the net doping concentration of the collector region 2 can be greater than or equal to 1×10 18 cm -3 , and the net doping concentration of the emitter region 3 can be greater than or equal to 2×10 18 cm -3 ; or, for convenience Fabricated, can be changed to have substantially the same net doping concentration. The collector terminal C is connected to the collector region 2 , the emitter terminal E is connected to the emitter region 3 , and the base terminal B is connected to the base region 4 .

與傳統BJT相比，該電晶體裝置１之基極區４係由二個不同類型 之半導體區域組成：一N型材料之第一區，下文中稱為N型基極次分區４Ａ，以及P型材料之第二區，下文中係指該通道４Ｂ。 Compared with the traditional BJT, the base region 4 of the transistor device 1 is composed of two different types The semiconductor region consists of: a first region of N-type material, hereinafter referred to as N-type base sub-region 4A, and a second region of P-type material, hereinafter referred to as the channel 4B.

該基極端子Ｂ係通過該N型基極次分區４Ａ連接至該基極區４。 該N型基極次分區４Ａ係與該通道４Ｂ直接交界以形成一PN接面５。該N型基極次分區４Ａ係與該集極區２與射極區３直接交界。 The base terminal B is connected to the base region 4 through the N-type base sub-region 4A. The N-type base sub-region 4A is directly connected to the channel 4B to form a PN junction 5 . The N-type base sub-region 4A is directly connected to the collector region 2 and the emitter region 3.

該通道４Ｂ係在該集極區２與射極區３間延伸並與其直接交界。 與該集極區２及射極區３相比，該通道４Ｂ之淨摻雜濃度非常小；例如，該通道之淨摻雜濃度可小於或等於5x10 16cm -3。 The channel 4B extends between the collector region 2 and the emitter region 3 and directly interfaces with them. Compared with the collector region 2 and the emitter region 3, the net doping concentration of the channel 4B is very small; for example, the net doping concentration of the channel can be less than or equal to 5x10 16 cm -3 .

此外，該通道４Ｂ係形成具有一深度，即與PN接面５正交所延 伸之尺寸，比傳統接面場效電晶體（junction field effect transistor, JFET）淺得多。 In addition, the channel 4B is formed to have a depth extending orthogonally to the PN junction 5 The extended size is much shallower than traditional junction field effect transistor (JFET).

該N型基極次分區４Ａ係由一第一部分與一第二部分所構成。該 第一部分之N摻雜劑的淨濃度可在1e17/cm 3左右；該第二部分之淨摻雜濃度可為例如約1e18/cm 3或1e19/cm 3。 The N-type base sub-region 4A is composed of a first part and a second part. The net N dopant concentration of the first portion may be about 1e17/cm 3 ; the net doping concentration of the second portion may be, for example, about 1e18/cm 3 or 1e19/cm 3 .

下面描述實作上述特徵之半導體結構。 該結構具一P型基板１００，可為例如一矽晶圓或藉在該晶圓頂部磊晶所沉積之矽層。在該P型基板１００內係具一N型區１０１；該N型區１０１與該P型基板１００係以一N+型區１０２加以區隔；在該N型區１０１內係具延伸至該基板材料一表面之額外的N+型區１０１Ａ；該N型區１０１與額外的N+型區１０１Ａ係構成該電晶體裝置１之N型基極次分區４Ａ，伴隨基極端子Ｂ透過額外的N+型區１０１Ａ加以連接；該N型區１０１中N摻雜劑之淨濃度可約為1e17/cm 3；該N+型區１０２與額外的N+型區１０１Ａ之淨摻雜濃度可為例如大約1e18/cm 3或 1e19/cm 3。 A semiconductor structure implementing the above features is described below. The structure has a P-type substrate 100, which may be, for example, a silicon wafer or a silicon layer epitaxially deposited on top of the wafer. There is an N-type region 101 in the P-type substrate 100; the N-type region 101 and the P-type substrate 100 are separated by an N+-type region 102; there is an N-type region 101 extending to the substrate An additional N+ type region 101A on a surface of the material; the N-type region 101 and the additional N+ type region 101A constitute the N-type base subregion 4A of the transistor device 1, with the base terminal B passing through the additional N+ type region 101A is connected; the net concentration of N dopant in the N-type region 101 can be about 1e17/cm 3 ; the net doping concentration of the N+-type region 102 and the additional N+-type region 101A can be, for example, about 1e18/cm 3 Or 1e19/cm 3 .

該N型區１０１頂部係貫穿延伸一輕摻雜的P-區１０３，以具備 通道４Ｂ且與該N型區１０１交界以提供該PN接面５；該結構亦包含二個分離之P型區１０４、１０５。每一P型區１０４、１０５之第一部分１０４Ａ、 １０５Ａ係由一P型摻雜多晶矽層之各自獨立部分所提供；每一P型區１０４、１０５之第二部分１０４Ｂ、１０５Ｂ係形成於該矽晶圓中且與該N型區１０１交界以提供相應之二極體接面５Ａ、５Ｂ。 A lightly doped P-region 103 extends through the top of the N-type region 101 to have Channel 4B interfaces with the N-type region 101 to provide the PN junction 5; the structure also includes two separate P-type regions 104 and 105. The first portion 104A of each P-type region 104, 105 105A is provided by separate portions of a P-type doped polysilicon layer; second portions 104B, 105B of each P-type region 104, 105 are formed in the silicon wafer and interface with the N-type region 101 to provide Corresponding diode junctions 5A and 5B.

該半導體結構之一範例製造程序係描述如下。一第一注入與擴散 程序係使用一第一遮罩以在該P型基板１００中形成該N+型區１０２；使用一第 二遮罩形成該N型區１０１，藉由P摻雜劑來反摻雜該N+型區１０２以將該N型 區１０１延伸至該晶圓表面。 An example fabrication process for the semiconductor structure is described below. - First injection and diffusion The process uses a first mask to form the N+ type region 102 in the P-type substrate 100; Two masks form the N-type region 101, and the N+-type region 102 is counter-doped with P dopant to convert the N-type Region 101 extends to the wafer surface.

更可以不使用遮罩，該晶圓表面係進一步摻雜P摻雜劑以形成該 P-區１０３貫穿該晶圓表面；該P-區１０３之淨摻雜濃度可為例如5e16/cm 3或更小；藉由確保很少或沒有擴散發生，該P-區１０３之深度被保持得非常小。為便於理解，該P-區１０３之相對厚度與其他層相比在第１圖中被誇大了。 It is also possible not to use a mask, and the wafer surface is further doped with P dopant to form the P-region 103 penetrating the wafer surface; the net doping concentration of the P-region 103 can be, for example, 5e16/cm 3 or Smaller; by ensuring that little or no diffusion occurs, the depth of the P-region 103 is kept very small. For ease of understanding, the relative thickness of the P-region 103 compared to the other layers is exaggerated in Figure 1.

使用一第三遮罩，N摻雜劑透過該晶圓表面被注入以反摻雜該P- 區１０３之一部分來形成該額外之N+型區１０１Ａ，使之延續該N型區１０１。 Using a third mask, N dopants are implanted through the wafer surface to counter-dope the P- A part of the region 103 is used to form the additional N+ type region 101A to continue the N type region 101.

使用第四遮罩，沉積並蝕刻一多晶矽材料層以提供該些集極與射 極區２、３之數個第一部分１０４Ａ、１０５Ａ。使用第五遮罩，該多晶矽材料係以P摻雜劑加以摻雜並向下擴散以形成與該N型區１０１交界之數個第二部 分１０４Ｂ、１０５Ｂ。 Using a fourth mask, a layer of polysilicon material is deposited and etched to provide the collector and emitter The first parts of polar regions 2 and 3 are 104A and 105A. Using a fifth mask, the polysilicon material is doped with a P dopant and diffused downward to form a plurality of second portions at the interface with the N-type region 101 Divided into 104B and 105B.

P摻雜劑注入後接著有一短暫退火，例如10秒，以修復該多晶矽 與矽（polysilicon and silicon）之晶圓的晶體結構。 P dopant implantation is followed by a short anneal, such as 10 seconds, to repair the polycrystalline silicon The crystal structure of polysilicon and silicon wafers.

操作模式請參閱『第２圖』所示，係顯示該第１圖之該電晶體裝置之操作特性或模式係如何根據貫穿該集極端子與射極端子之電壓（Vce）以及貫穿該基極端子與射極端子之電壓（Vbe）之變化而改變的示意圖。如圖所示： The operating mode is shown in "Figure 2", which shows how the operating characteristics or mode of the transistor device in Figure 1 is based on the voltage across the collector terminal and emitter terminal (Vce) and across the base terminal. A schematic diagram showing changes in the voltage (Vbe) of the sub- and emitter terminals. As shown in the picture:

藉由一PNP裝置，例如第１圖所示之裝置，無論操作模式如何， 通常都以一負極Vce操作，即施加至該集極之電壓比施加至該射極之電壓為更強負極，而Vbe藉與閾值電壓Vft為正向關係之一負極之基極—射極接面則可為正極或負極。任何通過該基極端子之電流皆為負極的（亦即，電流係經由該基極端子引出）。相比之下，一NPN裝置係通常以一正極Vce操作且具有一正極Vft，而任何通過該基極之電流將為正極（亦即，電流係經由該基極推送入該裝置）。 With a PNP device, such as the one shown in Figure 1, regardless of the operating mode, Usually it operates with a negative Vce, that is, the voltage applied to the collector is stronger than the voltage applied to the emitter, and Vbe is in a positive relationship with the threshold voltage Vft. The negative base-emitter connection The surface can be positive or negative. Any current flowing through the base terminal is negative (that is, current is drawn through the base terminal). In contrast, an NPN device typically operates with a positive Vce and has a positive Vft, and any current through the base will be positive (ie, current is pushed into the device through the base).

五種操作模式係標示為區域Ｋ、Ｊ、Ｌ、Ｍ與Ｎ來加以顯示。當 該裝置關閉且沒有電流通過任何端子時，該裝置係操作於區域Ｋ；當該裝置開啟時，則可在區域Ｊ、Ｌ、Ｍ與Ｎ中之一種模式下操作。 The five operating modes are shown as areas K, J, L, M and N. when When the device is turned off and no current flows through any terminal, the device operates in zone K; when the device is turned on, it can operate in one of the modes of zones J, L, M and N.

當該裝置開啟（即該集極與射極間有電流）且沒有或幾乎沒有 （deminimus）電流通過該基極端子（即Ib=0A）時，排除任何由電容效應所引起之臨時開關電流，該裝置係操作在區域Ｌ或Ｍ；當該裝置開啟（即該集極與射極間存在非零電流）且該基極端子有電流（即Ib＜0A）時，該裝置係操作在區域Ｊ或Ｎ。 When the device is turned on (i.e. there is current between the collector and emitter) and there is no or little (deminimus) When current passes through the base terminal (i.e. Ib = 0A), excluding any temporary switching current caused by capacitive effects, the device operates in region L or M; when the device is turned on (i.e. the collector and emitter When there is a non-zero current between the poles) and there is current at the base terminal (i.e. Ib < 0A), the device operates in region J or N.

|Vce|＜|Vt|下之操作 當本電晶體裝置１在|Vce|小於|Vt|時操作，本電晶體裝置１係作為一常關裝置。亦即，當Vbe為零時，該射極區３與集極區２間沒有電流（該裝置關閉（在區域Ｋ操作））。 Operations under |Vce|＜|Vt| When the transistor device 1 operates when |Vce| is less than |Vt|, the transistor device 1 acts as a normally-off device. That is, when Vbe is zero, there is no current between the emitter region 3 and the collector region 2 (the device is turned off (operating in region K)).

若|Vbe|增加致使該基極—射極二極體接面５Ｂ變為正向偏壓時 （即對一PNP電晶體而言，Vbe變得比–Vft更為負極；對一NPN電晶體而言，Vbe變得比Vft更為正極），則該裝置切換為開啟，操作於開啟之主要雙極（Majority Bipolar）區域Ｊ中，其電流係通過該基極端子汲取，且該集極與射極間之電流主要歸因於雙極傳導； If |Vbe| increases causing the base-emitter diode junction 5B to become forward biased (That is, for a PNP transistor, Vbe becomes more negative than –Vft; for an NPN transistor, Vbe becomes more positive than Vft), then the device is switched on and operates in the main state of turning on. In the Majority Bipolar region J, the current is drawn through the base terminal, and the current between the collector and the emitter is mainly due to bipolar conduction;

或者，若|Vbe|以相反方向增加，使該基極—射極二極體接面５Ｂ 之反向偏壓更強（即對一PNP電晶體而言，Vbe變得更為正極；對一NPN電晶體而言，Vbe變得更為負極），之後該裝置維持關閉（操作於區域Ｋ）。 Alternatively, if |Vbe| increases in the opposite direction, making the base-emitter diode junction 5B The reverse bias voltage is stronger (i.e., for a PNP transistor, Vbe becomes more positive; for an NPN transistor, Vbe becomes more negative), after which the device remains off (operating in region K ).

在|Vce|大於|Vt'|且小於|Vt|處，該裝置之操作係與|Vce|小於|Vt'|處類 似，惟當|Vbe|接近但小於|Vft|時例外，該裝置進入開啟之主要雙極區域Ｌ中操作， 在其中該裝置為開啟狀態且通過該基極端子之電流為零，而該集極與射極間之電流主要歸因於單極傳導。 Where |Vce| is greater than |Vt'| and less than |Vt|, the device operates similarly to where |Vce| is less than |Vt'| Similar, except when |Vbe| is close to but less than |Vft|, the device enters the open main bipolar region L and operates, In which the device is on and the current through the base terminal is zero, the current between the collector and emitter is primarily due to unipolar conduction.

而當|Vbe|變得大於|Vft|，就進入一區域Ｎ，其中該單極傳導電流 為一最大宜，且雙極傳導電流增加直到雙極傳導電流大於單極傳導電流，以此使該裝置操作在開啟之主要雙極傳導區域Ｊ。 And when |Vbe| becomes larger than |Vft|, it enters a region N, in which the single pole conducts current is a maximum and the bipolar conduction current is increased until the bipolar conduction current is greater than the unipolar conduction current, thereby allowing the device to operate in the open primary bipolar conduction region J.

有利的是，一常關裝置可以在低於現有BJT之Vbe下切換為開啟 並在區域Ｌ中操作，且是具有優勢地低於該基極—射極二極體接面正向電壓（Vft）。當在區域Ｌ內操作時，與在區域Ｊ內操作相比，對於相同之Vce而言，該裝置具有明顯更高之電流增益，但最大集極電流之數值較小。由於Vbe顯著較低，當該裝置在該區域Ｌ操作時，具有一比現有BJT顯然更高之電流增益—接近無限增益，因其通過該基極端子之電流基本為零。 Advantageously, a normally-off device can be switched on at a lower Vbe than existing BJTs and operates in region L, advantageously below the base-emitter diode junction forward voltage (Vft). When operating in region L, the device has a significantly higher current gain for the same Vce but a smaller maximum collector current compared to operating in region J. Because Vbe is significantly lower, the device has a significantly higher current gain than existing BJTs when operating in this region L—nearly infinite gain since the current through the base terminal is essentially zero.

|Vce|＞|Vt|下之操作 當本電晶體裝置１在|Vce|大於閾值電壓|Vt|下運作時，本電晶體裝置１係作為一常開裝置。亦即，當Vbe為零，例如因為該基極係浮動或連接至該射極時，該射極與集極間之電流係超過一極小（de minimis）電流。 Operations under |Vce|＞|Vt| When the transistor device 1 operates with |Vce| greater than the threshold voltage |Vt|, the transistor device 1 acts as a normally-on device. That is, when Vbe is zero, for example because the base is floating or connected to the emitter, the current between the emitter and collector exceeds a de minimis current.

當|Vce|大於|Vt|且Vbe為零或接近零時，該電晶體係操作在開啟之 主要單極操作區域Ｍ中，其中，通過該基極端子之電流為零，且該集極與射極 間之電流主要歸因於單極傳導。 When |Vce| is greater than |Vt| and Vbe is zero or close to zero, the transistor operates before turning on In the main unipolar operating region M, the current through the base terminal is zero and the collector and emitter The current between them is mainly due to unipolar conduction.

當|Vbe|增加至Vft以上，致使該基極—射極二極體接面５Ｂ變為 正向偏壓時（即，對一PNP電晶體而言，Vbe變得比-Vft更為負極；對一NPN電晶體而言，Vbe變得比Vft更為正極），則該裝置係操作在該區域Ｎ，其中，該單極傳導達至一最大值，且該雙極傳導增加。當|Vbe|進一步增加，可歸因於雙極傳導之Ice比例變得大於歸因於單極傳導電流之比例，其上之操作係為開啟且主要為雙極（區域Ｊ）。 When |Vbe| increases above Vft, the base-emitter diode junction 5B becomes When forward biased (i.e., for a PNP transistor, Vbe becomes more negative than -Vft; for an NPN transistor, Vbe becomes more positive than Vft), the device is operated at The region N in which the unipolar conduction reaches a maximum value and the bipolar conduction increases. As |Vbe| increases further, the proportion of Ice attributable to bipolar conduction becomes greater than the proportion of current attributable to unipolar conduction, above which the operation is on and mainly bipolar (region J).

在該區域Ｊ中運行所需之Vbe幅度隨著Vce之增幅而增加。The Vbe amplitude required to operate in this area J increases with the increase in Vce.

或者，若|Vbe|以反方向增加，致使該基極—射極二極體接面５Ｂ 之反向偏壓更強時（即對一PNP電晶體而言，Vbe變得更為正極；對一NPN電晶體而言，Vbe變得更為負極），則該裝置將關閉（操作區域Ｋ）。 Alternatively, if |Vbe| increases in the opposite direction, causing the base-emitter diode junction 5B When the reverse bias voltage is stronger (that is, for a PNP transistor, Vbe becomes more positive; for an NPN transistor, Vbe becomes more negative), the device will turn off (operating region K ).

在該關閉之區域Ｋ與該開啟之主要單極區域Ｌ與Ｍ之間係一過 渡區Ｏ，其中，該裝置之操作係不可預測或難以控制。例如，若該關閉之區域Ｋ中該集極電流小於1 nA，且該開啟之區域Ｌ與Ｍ中該集極電流為1 uA或更大之數量級，則該過渡區Ｏ內該集極電流將為10 nA至100 nA之數量級。 There is a pass between the closed area K and the open main unipolar areas L and M. Transition area O, where the operation of the device is unpredictable or difficult to control. For example, if the collector current in the closed region K is less than 1 nA, and the collector current in the open regions L and M is 1 uA or greater, then the collector current in the transition region O will On the order of 10 nA to 100 nA.

該裝置１在該集極區２與射極區３間係具有距離X之橫向間距， 控制該通道４Ｂ之長度。Vt及Vt'之值與該射極區及集極區間之間距X係為相關。隨X值之增加，|Vt|與|Vt'|之幅度亦增加。為使裝置在該區域Ｊ操作時具良好之雙極傳導特性，X之最大值通常為1.5微米。 The device 1 has a lateral spacing of distance X between the collector region 2 and the emitter region 3, Control the length of the channel 4B. The values of Vt and Vt' are related to the distance X between the emitter region and the collector interval. As the value of X increases, the amplitudes of |Vt| and |Vt'| also increase. In order for the device to have good bipolar conduction characteristics when operating in this region J, the maximum value of X is usually 1.5 microns.

一電路之額定操作電壓範圍決定了將應用於其中電晶體之Vce值 的範圍。在已知Vce之情況下，可在設計該電路時選擇電路內每個電晶體裝置１之間距X以決定其為一常開裝置或常關裝置來操作。 The rated operating voltage range of a circuit determines the Vce value that will be used for the transistors in it range. When Vce is known, the distance X between each transistor device 1 in the circuit can be selected to determine whether it operates as a normally open device or a normally closed device when designing the circuit.

請參閱『第３Ａ圖～第３Ｃ圖』所示，係分別顯示該第１圖中配 置在開啟條件下且其射極與集極間之傳導主要歸因於雙極傳導之電晶體截面示 意圖、該第１圖中配置在關閉條件下之電晶體截面示意圖、及該第１圖中配置在開啟條件下且其射極與集極間之傳導主要歸因於單極傳導之電晶體截面示意圖。如圖所示：第３Ａ圖～第３Ｃ圖係顯示第１圖之裝置，其射極區與集極區間之橫向間距X被相對選擇為較大，致使|Vce|小於|Vt|，且因此該裝置係操作為一常關電晶體。在當前示例中，該間距X係使Vce位於Vt與Vt'之間，從而允許該裝置根據Vbe以區域Ｊ、Ｋ或Ｌ中任一個之特性操作。 Please refer to "Figure 3A ~ Figure 3C", which show the configurations in Figure 1 respectively. Cross-section of a transistor placed in the on condition with conduction between emitter and collector due primarily to bipolar conduction. Intention, the schematic cross-section of the transistor configured in the off condition in Figure 1, and the cross-section of the transistor configured in the on condition in Figure 1 with the conduction between the emitter and the collector mainly due to unipolar conduction Schematic diagram. As shown in the figure: Figures 3A to 3C show the device in Figure 1. The lateral distance X between the emitter region and the collector interval is relatively selected to be large, resulting in |Vce| being smaller than |Vt|, and therefore The device operates as a normally-off transistor. In the present example, the spacing

第３Ａ圖係第１圖中配置在開啟條件下且其射極與集極間之傳 導主要歸因於雙極傳導之電晶體截面示意性。 Figure 3A shows the conduction between the emitter and collector configured in Figure 1 under the on condition. The conduction is mainly due to the schematic cross-section of a transistor with bipolar conduction.

第３Ａ圖係顯示在一主要為開啟之雙極條件下（第２圖之區域 Ｊ）操作之常關裝置。由於該射極端子Ｅ與基極端子Ｂ相比處具相對正極之電壓，致使Vbe比Vft更為負極，由N型區１０１所提供居於該射極區３與N型基極次分區４Ａ間之二極體接面５Ｂ係具正向偏壓，允許電流通過該射極端子Ｅ與基極端子Ｂ間之二極體接面５Ｂ流動（以箭頭６表示）。因此，在該射極區３與集極區２間係存在相應但大得多之電流，其歸因於共同流過該通道４Ｂ之兩種單極電流（以箭頭７Ａ表示），及歸因於流過該N型基極次分區４Ａ雙極傳導之一更大電流（以箭頭７Ｂ表示）。通過該通道４Ｂ之單極傳導的出現為該電晶體提供優於具有傳統BJT結構電晶體之增益特性。 Figure 3A shows a predominantly ON bipolar condition (the area of Figure 2 J) Normally closed device for operation. Since the emitter terminal E has a relatively positive voltage compared to the base terminal B, Vbe is more negative than Vft and is provided by the N-type region 101 between the emitter region 3 and the N-type base sub-region 4A. The diode junction 5B is forward biased, allowing current to flow through the diode junction 5B between the emitter terminal E and the base terminal B (indicated by arrow 6). Therefore, there is a corresponding but much larger current between the emitter region 3 and the collector region 2, which is due to the two unipolar currents (indicated by arrow 7A) flowing together through the channel 4B, and due to A larger current flows through the N-type base sub-partition 4A bipolar conduction (indicated by arrow 7B). The presence of unipolar conduction through channel 4B provides the transistor with gain characteristics superior to those of transistors with conventional BJT structures.

在具有大幅集極—射極電流處，該雙極電流７Ｂ可明顯大於該單 極電流７Ａ（例如大10倍之數量級）。相比之下，一JFET之所有（或幾乎所有）電流皆可歸因於通過該通道之單極傳導。 At locations with large collector-emitter currents, the bipolar current 7B can be significantly larger than the single Extreme current 7A (for example, on the order of 10 times greater). In contrast, all (or nearly all) the current in a JFET can be attributed to unipolar conduction through the channel.

第３Ｂ圖係顯示第２圖中區域Ｋ所展示之處於一關閉狀態之該 裝置。VCE與第３Ａ圖中之所示相同，惟該基極端子Ｂ係浮動或連結至該射極端子Ｅ，因此沒有電流通過該基極端子Ｂ。 Figure 3B shows the area K shown in Figure 2 in a closed state. device. The VCE is the same as shown in Figure 3A, except that the base terminal B is floating or connected to the emitter terminal E, so no current flows through the base terminal B.

此條件下係生出一空乏區８，其概念如該PN接面５附近之虛線 所示，由於該通道４Ｂ與該N型基極次分區相比非常淺薄且摻雜較弱，因此夾束該通道４Ｂ以增加該通道４Ｂ之電阻使該射極區３與集極區２間達到基本上沒有電流之程度。 Under this condition, a depletion region 8 is generated, and its concept is as the dotted line near the PN junction 5 As shown, since the channel 4B is very shallow and weakly doped compared with the N-type base sub-region, the channel 4B is clamped to increase the resistance of the channel 4B to make the gap between the emitter region 3 and the collector region 2 To the point where there is basically no current.

第３Ｃ圖係顯示該裝置操作於一主要為開啟之單極條件下（第２ 圖之區域Ｌ），通過施加一小於Vft且貫穿該射極與基極之非零電壓Vbe。由於Vbe小於Vft，該射極區３與N型基極次分區４Ａ間之二極體接面５Ｂ沒有足夠之正向偏壓以允許電流通過，因此沒有電流通過該基極端子Ｂ或N型基極次分區４Ａ；然而，由於該通道４Ｂ之淨摻雜級數非常低，Vbe足以將PN接面５周圍之該空乏區８減小至允許電流透過該射極區３與集極區２間之單極傳導流過該通道４Ｂ的程度（以箭頭７Ａ表示）。在區域Ｌ內操作時，該電晶體藉由Ib=0A而具高增益特性。然而，由於該通道淺薄，在該通道飽合之前可獲得之最大電流與在區域Ｊ操作相比係相對較低。 Figure 3C shows the device operating in a predominantly ON unipolar condition (Figure 2 Region L of the figure), by applying a non-zero voltage Vbe less than Vft across the emitter and base. Since Vbe is less than Vft, the diode junction 5B between the emitter region 3 and the N-type base subregion 4A does not have enough forward bias to allow current to pass, so no current passes through the base terminal B or the N-type Base subregion 4A; however, since the net doping level of channel 4B is very low, Vbe is enough to reduce the depletion region 8 around PN junction 5 to allow current to pass through the emitter region 3 and collector region 2 The degree of unipolar conduction flowing through channel 4B (indicated by arrow 7A). When operating in region L, the transistor has high gain characteristics with Ib=0A. However, due to the shallowness of the channel, the maximum current that can be obtained before the channel is saturated is relatively low compared to operating in region J.

請參閱『第４Ａ圖與第４Ｂ圖』所示，係分別顯示類似於該第１ 圖但具更短間距X且其配置在開啟條件下而射極與集極間之電流主要歸因於單極傳導之電晶體截面示意圖、及該第４Ａ圖中配置在關閉條件下之電晶體截面示意圖。如圖所示：第４Ａ圖與第４Ｂ圖係顯示具有與第１圖半導體結構相同之一不同裝置，其不同在於該集極區２與射極區３間之間距X更小而因此具一更短通道４Ｂ。所選擇之間距使得在為第３Ａ圖～第３Ｃ圖之裝置提供相同Vce範圍之電路中操作時，Vce係大於Vt且使該裝置作為一常開電晶體操作。 Please refer to "Figure 4A and Figure 4B", which respectively show similar to the first Figure 4A shows a cross-sectional view of a transistor with a shorter pitch Schematic cross-section. As shown in the figure: Figures 4A and 4B show a different device with the same semiconductor structure as Figure 1. The difference is that the distance X between the collector region 2 and the emitter region 3 is smaller and therefore has a Shorter channel 4B. The spacing is chosen such that when operating in a circuit that provides the same Vce range for the devices of Figures 3A-3C, Vce is greater than Vt and causes the device to operate as a normally-on transistor.

應該注意的是，雖然選擇該些集極與射極區之間的橫向間距是控 制該通道長度最方便的方法，但是藉由在該些射極與集極區間形成具一迂迴路徑之該通道，係可對一給定之橫向射極—集極間距提供一更長之通道長度。 It should be noted that although the choice of the lateral spacing between the collector and emitter regions is a control is the most convenient method of controlling the channel length, but by forming the channel with a circuitous path between the emitter and collector regions, a longer channel length can be provided for a given lateral emitter-collector spacing. .

第４Ａ圖係顯示處在一主要為開啟之單極條件下之該裝置。VCE 係與第３Ａ圖～第３Ｃ圖中相關描述相同，惟與該集極２與射極３間之間距X更 近，且因此該通道４Ｂ更短，所以即便在該基極端子Ｂ懸空或連接至該射極端子Ｅ之條件下，也足以克服PN接面５周圍之本質空乏區８。因此，雖然沒有電流通過該基極端子Ｂ，該射極與集極間仍有電流通過該通道４Ｂ。 Figure 4A shows the device in a predominantly ON unipolar condition. VCE The system is the same as the relevant descriptions in Figures 3A to 3C, except that the distance X between the collector 2 and the emitter 3 is changed. Close, and therefore the channel 4B is shorter, so even under the condition that the base terminal B is suspended or connected to the emitter terminal E, it is enough to overcome the intrinsic depletion region 8 around the PN junction 5. Therefore, although there is no current flowing through the base terminal B, there is still current flowing through the channel 4B between the emitter and collector.

第４Ｂ圖係顯示處於一關閉狀態之該裝置，其係通過使該基極端 子Ｂ比該射極端子Ｅ更大幅地為正極而達成。 Figure 4B shows the device in a closed state by turning the base terminal Sub-B is achieved by being more positive than the emitter terminal E.

請注意，該電晶體之表面積（即第１圖、第３Ａ～３Ｃ圖及第 ４Ａ、４Ｂ圖頁面所示之尺寸）可根據該電晶體裝置１所需要滿足之最大額定 電流加以選擇，以增加包括該通道４Ｂ在內之該基極區域的寬度。 Please note that the surface area of the transistor (i.e. Figure 1, Figures 3A-3C and Figures 4A and 4B) can be determined according to the maximum rating required by the transistor device 1 The current is selected to increase the width of the base region including channel 4B.

該P型基板１００係可連接至一低電壓以確保該基板與該N+型 區１０２間之該PN接面係具反向偏壓，其可抑制來自相鄰電晶體基極區之間的寄生橫向NPN BJT電晶體之不良影響。 The P-type substrate 100 can be connected to a low voltage to ensure that the substrate is connected to the N+-type The PN junction between regions 102 is reverse biased, which suppresses the adverse effects of parasitic lateral NPN BJT transistors between adjacent transistor base regions.

需要該橫向N+型區１０２之部分原因係為防止該P-區１０３ 在該射極與基板間造成一短路，並保證在該射極與該基板間所形成之該寄生垂直PNP BJT具很差之電流傳導特性，有利於以比該裝置集極電流大100多倍之幅度降低該寄生電流。 The lateral N+ region 102 is needed in part to prevent the P- region 103 Create a short circuit between the emitter and the substrate, and ensure that the parasitic vertical PNP BJT formed between the emitter and the substrate has poor current conduction characteristics, which is beneficial to more than 100 times greater than the collector current of the device. The amplitude reduces the parasitic current.

具不同半導體結構與製造方法之替代實施例 請參閱『第５Ａ圖與第５Ｂ圖』所示，係分別顯示實作電晶體裝置之另一半導體結構的截面示意圖、及該第５Ａ圖中半導體結構所實作之電晶體平面示意圖。如圖所示：第５Ａ圖係一實作該電晶體裝置之另一半導體結構。與第１圖之結構相比，該結構更有利於製造生產。該虛線QR係代表第５Ａ圖之切面軸線。 Alternative embodiments with different semiconductor structures and fabrication methods Please refer to "Figure 5A and Figure 5B", which are respectively a cross-sectional schematic diagram of another semiconductor structure for implementing a transistor device, and a schematic plan view of a transistor implemented by the semiconductor structure in Figure 5A. As shown in the figure: Figure 5A is another semiconductor structure for implementing the transistor device. Compared with the structure in Figure 1, this structure is more conducive to manufacturing and production. The dotted line QR represents the tangential axis of Figure 5A.

例如，提供一P型基板２００，其可以是一通過磊晶而沉積在晶 圓頂部之矽晶圓或矽晶層。在該P型基板２００內提供由一上層N型區２１１、一下層N型區２１２及一位於其間之N+型區２１３所組成之一N型井２１０。 For example, a P-type substrate 200 is provided, which may be a substrate deposited on a crystal by epitaxial crystallization. The silicon wafer or silicon layer on the top of the dome. An N-type well 210 is provided in the P-type substrate 200 and is composed of an upper N-type region 211, a lower N-type region 212 and an N+-type region 213 therebetween.

另一N+型區２１４之環係圍繞該上層N型區２１１與該N+型區 ２１３。該N+型區２１４係與該N型井２１０重疊並據以向外延伸以提供該電晶體之該N型基極次分區４Ａ。 Another ring of N+ type regions 214 surrounds the upper N type region 211 and the N+ type region. 213. The N+ type region 214 overlaps and extends outwardly from the N-type well 210 to provide the N-type base sub-region 4A of the transistor.

一提供該電晶體之通道４Ｂ的P-通道層２２０係位於該上層N型 區２１１上方並與之直接接觸。該P-通道層與其下方之該上層N型區２１１直接接觸以提供PN接面５。 A P-channel layer 220 providing channel 4B of the transistor is located in the upper N-type Above and in direct contact with area 211. The P-channel layer is in direct contact with the upper N-type region 211 below it to provide a PN junction 5 .

值得注意的是，該N+型區２１４係向上延伸，圍繞該P-通道層 ２２０以使該通道４Ｂ與該基板隔離。 It is worth noting that the N+ type region 214 extends upward and surrounds the P- channel layer 220 to isolate channel 4B from the substrate.

該上層N型區２１１之摻雜濃度係在1e17/cm 3至5e17/cm 3之範圍 內。此與經常在JFET柵極中發現之高摻雜級數（＞1e19/cm 3）形成對比。 The doping concentration of the upper N-type region 211 is in the range of 1e17/cm 3 to 5e17/cm 3 . This is in contrast to the high doping levels (>1e19/cm 3 ) often found in JFET gates.

該P-通道層２２０具一1e16/cm 3至1e17/cm 3數量級之淨摻雜濃度。 The P-channel layer 220 has a net doping concentration of the order of 1e16/cm 3 to 1e17/cm 3 .

一氧化層２２１係位於該P-通道層２２０上方。該結構亦包含二 個分離之P型區２２２、２２３，每個P型區皆延伸穿過該氧化層２２１及該P-通道層２２０，以提供相應之該些集極與射極區２、３。 An oxide layer 221 is located above the P-channel layer 220. This structure also contains two There are separate P-type regions 222, 223, each extending through the oxide layer 221 and the P-channel layer 220 to provide corresponding collector and emitter regions 2, 3.

每個P型區２２２、２２３之第一部分２２２Ａ、２２３Ａ係由 一位於該氧化層２２１上之P摻雜多晶矽層之數個部分所提供，以將該些射極與集極端子連接至該電路中。每個P型區２２２、２２３之第二部分２２２Ｂ、 ２２３Ｂ係由該延伸穿過該氧化層２２１之多晶矽層之數個部分所提供，以接觸該晶圓表面。每個P型區２２２、２２３之第三部分２２２Ｃ、２２３Ｃ係形成在該矽晶圓中且與該上層N型區２１１交界，以提供相應之二極體接面５Ａ、５Ｂ。 The first portion 222A, 223A of each P-type region 222, 223 is composed of Portions of a P-doped polysilicon layer on the oxide layer 221 are provided to connect the emitter and collector terminals to the circuit. The second portion 222B of each P-type region 222, 223 223B is provided by portions of the polysilicon layer extending through the oxide layer 221 to contact the wafer surface. The third portion 222C, 223C of each P-type region 222, 223 is formed in the silicon wafer and interfaces with the upper N-type region 211 to provide corresponding diode junctions 5A, 5B.

一圖形化之氧化層５００及一金屬層２２４係位於該氧化層 ２２１與多晶矽層的P型區２２２、２２３之上。該金屬層２２４之第一部分 ２２４Ａ係被圖形化，以提供數個導電區域。該金屬層２２４之一第二部分 ２２４Ｂ係延伸穿過氧化層５００、２２１內之一孔洞，以接觸該N+型區 ２１４提供該基極端子。 A patterned oxide layer 500 and a metal layer 224 are located on the oxide layer 221 and the P-type regions 222 and 223 of the polycrystalline silicon layer. The first portion of the metal layer 224 The 224A system is patterned to provide several conductive areas. The second part of the metal layer 224 224B extends through a hole in the oxide layer 500, 221 to contact the N+ type region 214 provides the base terminal.

請參閱『第６Ａ圖～第６Ｉ圖』所示，係顯示該第５Ａ圖與第 ５Ｂ圖中電晶體裝置其製造程序之示意圖。如圖所示：該第６Ａ圖～第６Ｉ圖係一範例程序，顯示製造一積體電路之部分區域，為二個具有第５Ａ圖與第 ５Ｂ圖結構之電晶體。 Please refer to "Figure 6A ~ Figure 6I", which shows the difference between Figure 5A and Figure 6I. Figure 5B is a schematic diagram of the manufacturing process of the transistor device. As shown in the figure: Figures 6A to 6I are a sample program showing a partial area for manufacturing an integrated circuit. They are two diagrams with Figures 5A and 6I. Figure 5B shows the structure of a transistor.

該電晶體中之第一個係在該些集極與射極區之間形成有相對小 之間距X，而另一個則具有相對大之間距，選擇該間距係為使在操作時，該第一個作為一常開電晶體操作，而另一個則作為一常關電晶體操作。可選擇該第二 電晶體之通道長度，使其在開啟時以與第２圖之區域Ｌ、Ｎ或Ｊ所述相關之特 性進行操作。 The first of the transistors has a relatively small gap formed between the collector and emitter regions. are separated by a distance You can choose the second The channel length of the transistor is such that when turned on it behaves with the characteristics associated with areas L, N or J in Figure 2. Sexually operated.

請參考第６Ａ圖，係提供一P型基板２００。再參考第６Ｂ圖， 係使用一遮罩、注入再擴散之程序以在一P型基板２００中形成數個單獨之環形（圓形或其他相似形狀）N+型區２１４，每個電晶體一個。 Please refer to Figure 6A, a P-type substrate 200 is provided. Refer to Figure 6B again, A process of masking, implantation and then diffusion is used to form several individual annular (circular or other similar shapes) N+ type regions 214 in a P-type substrate 200, one for each transistor.

請參考第６Ｃ圖，係使用一遮罩及注入之程序以在該些相應之環 形N+型區２１４內形成數個N型井２１０。該擴散程序係被省略以在表面下方（在該些上層與下層N型區２１１、２１２間）留下更高摻雜之該N+型區２１３。 Please refer to Figure 6C, which uses a masking and injection process to create the corresponding Several N-type wells 210 are formed in the N+-shaped region 214. The diffusion process is omitted to leave a more highly doped N+-type region 213 below the surface (between the upper and lower N-type regions 211, 212).

請參考第６Ｄ圖，係使用一未被遮罩之P型注入程序以形成該P- 通道層２２０。此可以一無擴散或退火之程序加以實施。因為形成該P-通道層２２０所需之摻雜非常弱，所以該注入對該N+型區不會有決定性影響。 Please refer to Figure 6D, an unmasked P-type injection process is used to form the P- Channel layer 220. This can be carried out in a diffusion-free or annealing process. Since the doping required to form the P-channel layer 220 is very weak, the implant will not have a decisive impact on the N+ type region.

請參考第６Ｅ圖，係將一氧化層２２１通過一沉積程序添加至該 晶圓。一沉積程序係被使用以確保該P-通道層２２０不受損。 Referring to Figure 6E, an oxide layer 221 is added to the oxide layer through a deposition process. wafer. A deposition process is used to ensure that the P-channel layer 220 is not damaged.

一光刻膠３００係被施加於該氧化層上。該光刻膠３００係被圖 形化以限定該些集極與射極區間之間距X，並從而限定該通道４Ｂ之長度。在本範例中，該左側電晶體之間距X係被選擇為相對較小以提供一常開電晶體，而該 右側電晶體之間距X則被選擇為相對較大以提供一常關電晶體。 A photoresist 300 is applied to the oxide layer. The photoresist 300 series is patterned Shaped to define the distance X between the collector and emitter intervals, and thereby define the length of the channel 4B. In this example, the distance X between the left transistors is chosen to be relatively small to provide a normally-on transistor, and the The distance X between the right transistors is chosen to be relatively large to provide a normally-off transistor.

僅以一1 um製造程序之尺寸為例，該右側電晶體可具一介於1.2 微米與1.5微米間之通道長度；而該左側電晶體則可具一等於或小於0.8微米之通道長度。 Just taking the size of a 1 um manufacturing process as an example, the right transistor can have a size between 1.2 The channel length is between 1.5 microns and 1.5 microns; and the left transistor can have a channel length equal to or less than 0.8 microns.

請參考第６Ｆ圖，係蝕刻該氧化層並移除該遮罩。Please refer to Figure 6F to etch the oxide layer and remove the mask.

請參考第６Ｇ圖，係沉積一多晶矽層４００在該晶圓上（可選擇 整片晶圓）。該多晶矽層的P型區２２３直接接觸該P-通道層２２０被暴露之表面，其上之該氧化層２２１已被去除以形成該些集極與射極接點之第二部分 ２２２Ｂ、２２３Ｂ。 Please refer to Figure 6G, a polysilicon layer 400 is deposited on the wafer (optional entire wafer). The P-type region 223 of the polycrystalline silicon layer directly contacts the exposed surface of the P-channel layer 220, and the oxide layer 221 thereon has been removed to form the second portion of the collector and emitter contacts. 222B, 223B.

一P型注入程序４０１（以箭頭表示）係實施以將該多晶矽轉化 為P型，該程序亦增加與該多晶矽直接接觸之該些P-層區域的淨摻雜濃度，以形成該些集極與射極區２、３之第三部分２２２Ｃ、２２３Ｃ。一短退火步驟係激活注入而不引發該P-通道層２２０之擴散。亦或，為減少處理時間，可沉積一P型多晶矽。 A P-type implant process 401 (indicated by the arrow) is performed to convert the polysilicon For P-type, this process also increases the net doping concentration of the P-layer regions in direct contact with the polysilicon to form the third portions 222C, 223C of the collector and emitter regions 2, 3. A short anneal step activates the implant without causing diffusion of the P-channel layer 220. Alternatively, to reduce processing time, a P-type polysilicon can be deposited.

請參考第６Ｈ圖，係遮罩並蝕刻該多晶矽層４００，以圖形化具 第一部分２２２Ａ、２２３Ａ之該集極與射極區２、３。 Referring to Figure 6H, the polysilicon layer 400 is masked and etched to pattern the The first part 222A, 223A is the collector and emitter regions 2 and 3.

請參考第６Ｉ圖，係進一步使用一遮罩與蝕刻程序以隨之暴露該 N+型區２１４之一區域及沉積金屬層２２４以提供該第二部分２２４Ｂ作為基極接點，並蝕刻一圖樣以提供該第一部分２２４Ａ作為繞線層。 Referring to Figure 6I, a masking and etching process is further used to subsequently expose the A metal layer 224 is deposited on an area of the N+ type region 214 to provide the second portion 224B as a base contact, and a pattern is etched to provide the first portion 224A as a winding layer.

如以上各式所述之裝置皆可被替代為一NPN裝置，使其具一N型 通道、數個射極及集極區，並一P型基極次分區；如此，該裝置將可以與上述相反之極性加以操作。 Each of the devices described above can be replaced with an NPN device to have an N-type channel, several emitter and collector regions, and a P-type base sub-section; thus, the device will be able to operate with the opposite polarity as described above.

該射極區及／或該集極區可完全形成在該晶圓內，而非使用一晶 矽層。 The emitter region and/or the collector region can be formed entirely within the wafer, rather than using a single wafer. Silicon layer.

上述結構係可結合一齊納二極管（zener diode）加以改變，通過 提供一附加P型區以在該些基極與集極端子間電性連接，如WO2019/229432所述參考引用； The above structure can be modified by combining a zener diode. Providing an additional P-type region to electrically connect the base and collector terminals, as described in WO2019/229432;

該金屬基極接點係可以一多晶矽摻雜接點代替；如此將在該基極 端子中引入一齊納二極管，好處為不需要任何金屬層在鄰近該裝置處佈線。 The metal base contact can be replaced by a polycrystalline silicon doped contact; this will The benefit of introducing a Zener diode into the terminal is that no metal layer is required to be routed adjacent to the device.

綜上所述，本發明係一種電晶體裝置，可有效改善習用之種種缺 點，除其他優點外，具有優於傳統橫向雙極性接面型電晶體（bipolar junction transistor, BJT）之電流增益特性，係利用通道之存在允許本電晶體裝置在開啟（在第一或第四條件下操作）與關閉間切換以回應小於該基極—射極二極管正向電 壓絕對值（Vft）之Vbe變化，如此可允許二個具有相同配置之電晶體裝置，例如 皆為NPN或皆為PNP，用於切換一驅動電路之兩側（高與低），而非依照對一互 補電路之傳統要求，進而使本發明之產生能更進步、更實用、更符合使用者之 所須，確已符合發明專利申請之要件，爰依法提出專利申請。 In summary, the present invention is a transistor device that can effectively improve various shortcomings of conventional devices. Among other advantages, it has better current gain characteristics than conventional lateral bipolar junction transistors (BJTs) by exploiting the presence of channels that allow the present transistor device to be turned on (either in the first or fourth operating conditions) and switches off in response to a base-emitter diode forward current less than Vbe changes in absolute value (Vft), thus allowing two transistor devices with the same configuration, e.g. Both are NPN or both are PNP, used to switch both sides (high and low) of a driving circuit, rather than according to the mutual Compensating the traditional requirements of circuits, thereby making the invention more advanced, more practical, and more in line with the needs of users Required, the requirements for invention patent application have indeed been met, and the patent application must be filed in accordance with the law.

惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定 本發明實施之範圍；故，凡依本發明申請專利範圍及發明說明書內容所作之簡 單的等效變化與修飾，皆應仍屬本發明專利涵蓋之範圍內。 However, the above are only preferred embodiments of the present invention and should not be limited thereto. scope of implementation of the present invention; therefore, any summary made based on the scope of the patent application for the present invention and the contents of the description of the invention Simple equivalent changes and modifications should still fall within the scope of the patent of the present invention.

１:電晶體裝置 ２:集極區 ３:射極區 ４:基極區 ４Ａ:N型基極次分區 ４Ｂ:通道 ５:PN接面 １００:P型基板 １０１:N型區 １０１Ａ:N+型區 １０２:N+型區 １０３:P-區 １０４、１０５:P型區 １０４Ａ、１０５Ａ:第一部分 １０４Ｂ、１０５Ｂ:第二部分 ５Ａ、５Ｂ:二極體接面 ６:箭頭 ７Ａ、７Ｂ:箭頭 ８:空乏區 Ｃ:集極端子 Ｅ:射極端子 Ｂ:基極端子 Ｋ、Ｍ、Ｌ、Ｎ、Ｊ:區域 Ｏ:過渡區 ２００:P型基板 ２１０:N型井 ２１１:上層N型區 ２１２:下層N型區 ２１３:N+型區 ２１４:N+型區 ２２０:P-通道層 ２２１:氧化層 ２２２、２２３:P型區 ２２２Ａ、２２３Ａ:第一部分 ２２２Ｂ、２２３Ｂ:第二部分 ２２２Ｃ、２２３Ｃ:第三部分 ２２４:金屬層 ２２４Ａ:第一部分 ２２４Ｂ:第二部分 ３００:光刻膠 ４００:多晶矽層 ４０１:P型注入程序 ５００:氧化層 1: Transistor device 2:Collection area 3: Emitter region 4: Base region 4A: N-type base sub-division 4B: Channel 5:PN junction 100:P type substrate 101:N type area 101A:N+ type area 102:N+ type area 103:P-area 104, 105: P-type area 104A, 105A: Part 1 104B, 105B: Part 2 5A, 5B: Diode junction 6:Arrow 7A, 7B: Arrow 8:Depleted area C: collector terminal E: Emitter terminal B: Base terminal K, M, L, N, J: Area O: Transition area 200:P type substrate 210:N-type well 211: Upper N-type area 212: Lower N-type area 213:N+ type area 214:N+ type area 220:P-channel layer 221:Oxide layer 222, 223: P-type area 222A, 223A: Part 1 222B, 223B: Part 2 222C, 223C: Part 3 224:Metal layer 224A:Part 1 224B:Part 2 300: Photoresist 400:Polycrystalline silicon layer 401:P type injection procedure 500:Oxide layer

第１圖，係實作一電晶體之半導體結構的截面示意圖。 第２圖，係顯示第１圖該電晶體裝置之操作特性如何隨Vbe與Vce之變化而變化 的示意圖。 第３Ａ圖，係第１圖中配置在開啟條件下且其射極與集極間之傳導主要歸因於 雙極傳導之電晶體截面示意圖。 第３Ｂ圖，係第１圖中配置在關閉條件下之電晶體截面示意圖。 第３Ｃ圖，係第１圖中配置在開啟條件下且其射極與集極間之傳導主要歸因於 單極傳導之電晶體截面示意圖。 第４Ａ圖，係類似於第１圖但具更短間距X且其配置在開啟條件下而射極與集極 間之電流主要歸因於單極傳導之電晶體截面示意圖。 第４Ｂ圖，係第４Ａ圖中配置在關閉條件下之電晶體截面示意圖。 第５Ａ圖，係實作電晶體裝置之另一半導體結構的截面示意圖。 第５Ｂ圖，係第５Ａ圖中半導體結構所實作之電晶體平面示意圖。 第６Ａ圖～第６Ｉ圖，係第５Ａ圖與第５Ｂ圖中電晶體裝置其製造程序之示 意圖。 Figure 1 is a schematic cross-sectional view of a semiconductor structure for implementing a transistor. Figure 2 shows how the operating characteristics of the transistor device in Figure 1 change as Vbe and Vce change. schematic diagram. Figure 3A is the configuration in Figure 1 under the on condition and the conduction between the emitter and collector is mainly due to Schematic cross-section of a bipolar conduction transistor. Figure 3B is a schematic cross-sectional view of the transistor configured in the off condition in Figure 1. Figure 3C is the configuration in Figure 1 under the on condition and the conduction between the emitter and collector is mainly due to Schematic cross-section of a transistor with unipolar conduction. Figure 4A is similar to Figure 1 but has a shorter spacing X and is configured in the on condition with the emitter and collector Schematic cross-section of a transistor where the current flow is mainly due to unipolar conduction. Figure 4B is a schematic cross-sectional view of the transistor configured in the off condition in Figure 4A. Figure 5A is a schematic cross-sectional view of another semiconductor structure for implementing a transistor device. Figure 5B is a schematic plan view of a transistor implemented by the semiconductor structure in Figure 5A. Figures 6A to 6I show the manufacturing process of the transistor device in Figures 5A and 5B. intention.

1:電晶體裝置 1: Transistor device

2:集極區 2:Collection area

3:射極區 3: Emitter area

4A:N型基極次分區 4A: N-type base sub-division

4B:通道 4B:Channel

5:PN接面 5:PN junction

100:P型基板 100:P type substrate

101:N型區 101:N type area

101A:N+型區 101A:N+ type area

102:N+型區 102:N+ type area

103:P-區 103:P-Zone

104A、105A:第一部分 104A, 105A: Part 1

104B、105B:第二部分 104B, 105B: Part 2

5A、5B:二極體接面 5A, 5B: Diode junction

C:集極端子 C: collector terminal

E:射極端子 E: Emitter terminal

B:基極端子 B: Base terminal

Claims (8)

一種電晶體裝置，係具有： 由一第一類型之一半導體第一區所提供之一集極區；與該集極區關聯之一集極端子； 由該第一類型之一半導體第二區所提供之一射極區；與該射極區關聯之一射極端子； 由位於該集極區與射極區之間且與二者交界之一半導體第三區所提供之一基極區；與該基極區關聯之一基極端子； 其中，該基極區係包括： 一第二類型之一半導體基極次分區，及 該第一類型之一半導體通道， 其中，該基極端子係接觸該半導體基極次分區， 其中，該半導體基極次分區包含一第一部分與一第二部分， 該第一部分具比該第二部分更高之一淨摻雜濃度； 該基極端子通過該第一部分電性連接該第二部分；並且， 該第二部分係與該半導體通道交界以提供一第一二極體接面，並且與該射極區及該集極區二者交界以進一步形成數個第二二極體接面， 而該半導體通道係與該集極區及該射極區交界並互連。 A transistor device having: a collector region provided by a first region of a semiconductor of the first type; a collector terminal associated with the collector region; an emitter region provided by a second region of a semiconductor of the first type; an emitter terminal associated with the emitter region; a base region provided by a semiconductor third region located between and at the interface between the collector region and the emitter region; a base terminal associated with the base region; Among them, the base zone includes: a second type semiconductor base sub-division, and One of the first types of semiconductor channels, wherein the base terminal is in contact with the semiconductor base sub-region, Wherein, the semiconductor base sub-division includes a first part and a second part, the first part has a higher net doping concentration than the second part; The base terminal is electrically connected to the second part through the first part; and, The second portion interfaces with the semiconductor channel to provide a first diode junction, and interfaces with both the emitter region and the collector region to further form a plurality of second diode junctions, The semiconductor channel interfaces with and interconnects the collector region and the emitter region. 依申請專利範圍第１７項所述之一種電晶體裝置，其中，該些集極區與射極區之橫向間距係小於或等於1.5微米。A transistor device according to claim 17, wherein the lateral spacing between the collector regions and the emitter regions is less than or equal to 1.5 microns. 依申請專利範圍第１７項所述之一種電晶體裝置，其中，該半導體通道之淨摻雜濃度係小於該些射極區與集極區之淨摻雜濃度。A transistor device according to claim 17, wherein the net doping concentration of the semiconductor channel is smaller than the net doping concentration of the emitter regions and collector regions. 依申請專利範圍第１７項所述之一種電晶體裝置，其中，該 半導體通道具遠自該第一二極體接面延伸而來且小於或等於0.25微米之一深度，且最好小於或等於0.1微米。 A transistor device according to item 17 of the patent application, wherein the The semiconductor channel extends away from the first diode junction and has a depth less than or equal to 0.25 microns, and preferably less than or equal to 0.1 microns. 依申請專利範圍第１７項所述之一種電晶體裝置，其中，該半導體基極次分區之第二部分具有在1e16/cm 3至5e17/cm 3間之一淨摻雜濃度。 A transistor device according to claim 17 of the patent application, wherein the second part of the semiconductor base sub-region has a net doping concentration between 1e16/cm 3 and 5e17/cm 3 . 依申請專利範圍第１７項所述之一種電晶體裝置： 其中，當該電晶體裝置開啟時，|Vce|＜|Vft|，且|Vbe|＜=|Vce|； 其中，該Vce係貫穿該些集極端子與射極端子之電壓，該Vft係基極—射極二極體接面之正向偏電壓；以及該Vbe係貫穿該些集極端子與射極端子之電壓。 A transistor device according to item 17 of the patent application scope: Wherein, when the transistor device is turned on, |Vce|<|Vft|, and |Vbe|<=|Vce|; Wherein, the Vce is the voltage across the collector terminals and the emitter terminals, the Vft is the forward bias voltage of the base-emitter diode junction; and the Vbe is the voltage across the collector terminals and the emitter terminals. The voltage of the son. 依申請專利範圍第２２項所述之一種電晶體裝置，其中，|Vce|≤½|Vft|。A transistor device according to item 22 of the patent application, wherein |Vce|≤½|Vft|. 依申請專利範圍第２２項或第２３項所述之一種電晶體裝置，其中，當該電晶體裝置處於關閉狀態時：|Vbe|＜|Vft|。A transistor device according to item 22 or 23 of the patent application, wherein when the transistor device is in a closed state: |Vbe|<|Vft|.
TW112138744A 2021-11-08 2021-12-10 A new transistor device TWI855892B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2116047.8A GB2612643A (en) 2021-11-08 2021-11-08 A novel transistor device
GBGB2116047.8 2021-11-08

Publications (2)

Publication Number Publication Date
TW202404028A true TW202404028A (en) 2024-01-16
TWI855892B TWI855892B (en) 2024-09-11

Family

ID=

Also Published As

Publication number Publication date
GB2612643A (en) 2023-05-10
TW202320293A (en) 2023-05-16
TWI836306B (en) 2024-03-21

Similar Documents

Publication Publication Date Title
US7605412B2 (en) Distributed high voltage JFET
JP3469967B2 (en) Power device integrated structure
KR20120091231A (en) Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices
JPH05259443A (en) Insulation gate type semiconductor device
JPH0347593B2 (en)
EP4070384B1 (en) A transistor device
KR0158608B1 (en) A three terminal power insulated gate transistor and method for fabricating thereof
WO2014079381A1 (en) Junction field-effect transistor and preparation method therefor
JPH10504940A (en) Semiconductor element
WO2023079316A1 (en) A transistor device and a method of operating thereof
TWI836306B (en) A novel transistor device
TWI855892B (en) A new transistor device
US8878238B2 (en) MCT device with base-width-determined latching and non-latching states
JPH11266014A (en) Silicon carbide semiconductor device and its manufacture
US20240021712A1 (en) A novel transistor device
CN116686094A (en) Transistor device
TW202412260A (en) A novel transistor device
KR100480674B1 (en) Bipolar transistor with a diode embedded between the collector and the emitter and its manufacturing method
CN118382934A (en) Transistor device and method of operating the same
JP2957795B2 (en) Semiconductor device and manufacturing method thereof
CN212161820U (en) Electronic device product
JP2501236B2 (en) Thyristor with turn-off gate
GB2615153A (en) A novel transistor device and circuits comprising said transistor device
JPS6241427B2 (en)
JPS6380571A (en) Conductivity modulation vertical mos-fet