TWI835158B - Image sensor and method for forming the same - Google Patents

Abstract

The present disclosure provides an image sensor and a method for forming the same. The image sensor includes a substrate including a first and a second surfaces opposite to each other, a first isolation structure disposed in the substrate and extending into the substrate from the first surface to define a pixel region, an image sensing element disposed in the pixel region of the substrate, and a first and a second gate structures respectively disposed on the first surface of the substrate in the pixel region. The image sensing element includes a first and a fourth doped regions having first conductive types and a second and a third doped regions having second conductive types. The first doped region extends into the substrate from the second surface. The fourth doped region extends into the substrate from the first surface. The second doped region surrounds the first doped region and includes a portion between the first doped region and the fourth doped region. The third doped region is disposed between the second doped region and the fourth doped region.

Description

Image sensor and method of forming same

The present invention relates to a semiconductor structure and a method of forming the same, and in particular, to an image sensor and a method of forming the same.

Image sensor integrated circuits (ICs) are widely used in devices such as cameras, mobile phones, and automotive lenses. In recent years, compared with charge-coupled devices (CCD), image sensors complementary metal-oxide semiconductor (CMOS) image sensors have low power consumption, small size, Fast data processing, direct data output, and low manufacturing costs are becoming more and more advantageous. Therefore, CMOS image sensors have largely replaced CCD image sensors. Generally speaking, CMOS image sensors can include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors.

However, as device sizes continue to shrink, the full well capacity (FWC) of CMOS image sensors also shrinks. Therefore, how to make small-sized CMOS image sensors have sufficient full well capacity to have good sensitivity The degree and image lag are one of the goals that those skilled in the art are eager to strive for.

The present invention provides an image sensor and a method for forming the same, by designing the second doping region with the second conductivity type in the image sensing element to surround the first doping region with the first conductivity type. The image sensing element includes additional lateral depletion capacitance. In this way, the image sensor can still have sufficient full well capacity despite its small size design, so that the image sensor has good sensitivity and image delay.

An embodiment of the present invention provides an image sensor, which includes a substrate, a first isolation structure, an image sensing element, a first gate structure and a second gate structure. The base includes a first surface and a second surface opposite to each other. The first isolation structure is disposed in the substrate and extends from the first surface into the substrate to define the pixel area. The image sensing element is disposed in the pixel region of the substrate and includes a first doping region with a first conductivity type, a second doping region with a second conductivity type different from the first conductivity type, and a second doping region with a second conductivity type. a third doped region and a fourth doped region having a first conductivity type. The first doped region extends from the second surface of the substrate into the substrate. The fourth doped region extends from the first surface of the substrate into the substrate. The second doped region surrounds the first doped region and includes a portion disposed between the first doped region and the fourth doped region. The third doped region is disposed between the second doped region and the fourth doped region. The first gate structure and the second gate structure are respectively disposed on the first surface in the pixel area of the substrate.

In some embodiments, the interface where the first doped region and the second doped region contact each other has a cup-shaped profile, and the opening portion of the cup-shaped profile faces the second surface of the substrate.

In some embodiments, the first gate structure is closer to the image sensing element than the second gate structure, and the third doped region and the fourth doped region each include a portion in contact with the first gate structure.

In some embodiments, the image sensor further includes color filters and microlenses. The color filter is disposed on the second surface of the substrate. Microlenses are provided on the color filter.

In some embodiments, the image sensor further includes a second isolation structure disposed in the substrate and extending from the second surface of the substrate into the substrate.

An embodiment of the present invention provides a method of forming an image sensor, which includes the following steps. A doped region having a first conductivity type is formed in the base layer. An epitaxial growth process is performed on the base layer to form an epitaxial layer on the base layer, and the doped region is diffused into the epitaxial layer to form a first doped region extending from the base layer to the epitaxial layer, wherein The first doped region has a first conductivity type. A first isolation structure extending from a first surface of the epitaxial layer to the epitaxial layer is formed in the epitaxial layer to define a pixel region. A second doped region surrounding the first doped region is formed in the pixel region of the epitaxial layer, wherein the second doped region has a second conductivity type different from the first conductivity type. A third doping region having a second conductivity type and a fourth doping region having a first conductivity type are respectively formed in the pixel region of the epitaxial layer. The fourth doped region extends from the first surface of the epitaxial layer into the epitaxial layer. The third doped region is disposed between the fourth doped region and the third doped region. The second doped region includes a portion disposed between the first doped region and the third doped region. The first doped region, the second The doped region, the third doped region and the fourth doped region form an image sensing element of the image sensor.

In some embodiments, the interface where the first doped region and the second doped region contact each other has a cup-shaped profile, and the opening portion of the cup-shaped profile faces the second surface of the epitaxial layer opposite to the first surface.

In some embodiments, the method of forming the image sensor further includes forming a first gate structure and a second gate structure on the first surface of the epitaxial layer before forming the third doped region and the fourth doped region. Extreme structure. The first gate structure is closer to the image sensing element than the second gate structure. Each of the third doped region and the fourth doped region includes a portion in contact with the first gate structure.

In some embodiments, the method of forming the image sensor further includes forming an interconnect structure on the first surface of the epitaxial layer; after forming the interconnect structure, removing the base layer to expose the epitaxial layer and the a second surface opposite the first surface; and a second isolation structure formed in the epitaxial layer extending from the second surface of the epitaxial layer to the epitaxial layer.

In some embodiments, the method of forming an image sensor further includes forming a color filter on the second surface of the epitaxial layer; and forming microlenses on the color filter.

Based on the above, in the above image sensor and its forming method, since the second doping region with the second conductivity type in the image sensing element is designed to surround the first doping region with the first conductivity type, so that The image sensing element includes additional lateral depletion capacitance. In this way, the image sensor can still have sufficient full well capacity despite its small size design, making the image sensor have good Good sensitivity and image delay.

1:Image sensor

10: Support base

100: Basal layer

102, 116, 118: Doped area

110: Epitaxial layer, substrate

111, 111a: first doped region

113: Second doping region

114:Well area

115: The third doping region

117: The fourth doped region

120:Dielectric layer

122:Internal connection

124. C1, C2, C3, C4, GC1, GC2, GC3, GC4: conductive contacts

130: Color filter

140: Microlens

GS1: first gate structure

GS2: Second gate structure

STI1: first isolation structure

STI2: Second isolation structure

TX: transfer transistor

SF: source follower transistor

Sel: column select transistor

RST: reset transistor

PR: Pixel area

PD: image sensing element

S1: first surface

S2: Second surface

1 to 7 are schematic diagrams of a method of forming an image sensor according to an embodiment of the present invention.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to a physical and/or electrical connection, and "electrical connection" or "coupling" may refer to the presence of other components between two components. "Electrical connection" as used herein may include physical connections (such as wired connections) and physical disconnections (such as wireless connections).

As used herein, "about," "approximately" or "substantially" includes the recited value and the average within an acceptable range of deviations from the specific value that a person with ordinary skill in the art can determine, taking into account the Discussion of measurement and measurement related A specific amount of error (i.e., the limits of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and one standard deviation does not apply to all properties. .

The terminology used herein is used only to describe illustrative embodiments and does not limit the disclosure. In such cases, the singular form includes the plural form unless the context dictates otherwise.

1 to 7 are schematic diagrams of a method of forming an image sensor according to an embodiment of the present invention. (a) and (b) in Figures 1 to 7 are respectively schematic cross-sectional views taken along different sections. For example, (a) of Figure 5 is a schematic cross-sectional view taken along the cross-section line AA' shown in (c) of Figure 5 , and (b) of Figure 5 is a schematic cross-sectional view taken along the line AA' shown in (c) of Figure 5 A schematic cross-section taken along the section line BB' is shown.

First, referring to FIG. 1 , a doped region 102 having a first conductivity type (eg, P type) is formed in the base layer 100 . Base layer 100 may be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.). In some embodiments, the base layer 100 may be a bulk semiconductor substrate having a first conductivity type. In some embodiments, the doped region 102 may be formed at a certain depth from the surface of the base layer 100 through an ion implantation process. In some embodiments, the doped region 102 may be formed as a lightly doped region, that is, the doped region 102 may be adjacent to the above-mentioned surface of the base layer 100 .

Next, referring to FIG. 2 , an epitaxial growth process is performed on the base layer 100 to form an epitaxial layer 110 on the base layer 100 and to diffuse the doped region 102 into the epitaxial layer. 110 to form a first doped region 111 extending from the base layer 100 to the epitaxial layer 110 . The first doped region 111 has a first conductivity type (for example, P type). In some embodiments, the epitaxial layer 110 may include first and second surfaces S1 and S2 opposite each other. The first surface S1 of the epitaxial layer 110 may be a surface away from the base layer 100 . The second surface S2 of the epitaxial layer 110 may be an interface between the base layer 100 and the epitaxial layer 110 .

Then, referring to FIG. 3 , a first isolation structure STI1 extending from the first surface S1 of the epitaxial layer 110 to the epitaxial layer 110 is formed in the epitaxial layer 110 to define the pixel area (for example, (c) of FIG. 5 The pixel area PR shown). In some embodiments, in a direction perpendicular to the first surface S1, the first doping region 111 is located in the pixel region defined by the first isolation structure STI1. The first isolation structure STI1 may include one or more dielectric materials. The dielectric material may include oxides (such as silicon oxide), tetraethyl orthosilicate (TEOS), nitrides (such as silicon nitride, silicon oxynitride, etc.), carbides (such as silicon carbide, carbon silicon oxide, etc.) or similar. The first isolation structure STI1 may be, for example, a shallow trench isolation structure, but is not limited thereto.

Then, a second doped region 113 surrounding the first doped region 111 is formed in the pixel region of the epitaxial layer 110, wherein the second doped region 113 has a second conductivity type (for example, N) that is different from the first conductivity type. type). As a result, the image sensing element PD to be described later includes an additional lateral depletion capacitance formed by the interface of the second doping region 113 surrounding the first doping region 111, so that the image sensor (for example, as shown in FIG. 7 The resulting image sensor 1) can still have sufficient full well capacity (FWC) in a small size design to have good sensitivity and image delay. In some embodiments, the interface where the first doped region 111 and the second doped region 113 contact each other may have a cup-shaped profile, where the cup-shaped profile The opening portion faces the second surface S2 of the epitaxial layer 110 .

In some embodiments, the second doped region 113 may be formed at a certain depth from the first surface S1 of the epitaxial layer 110 through an ion implantation process. In some embodiments, the second doped region 113 is further away from the first surface S1 of the epitaxial layer 110 than the second surface S2 of the epitaxial layer 110 . That is to say, a deep doping method can be used for the epitaxial layer 110 . A second doped region 113 is formed in the crystal layer 110 .

Afterwards, a well region 114 having a first conductivity type (for example, P type) is formed in the pixel region of the epitaxial layer 110 . In some embodiments, the well region 114 extends from the first surface S1 of the epitaxial layer 110 into the epitaxial layer 110 . In some embodiments, well region 114 may be spaced apart from second doped region 113 . In some embodiments, well region 114 may include a portion beneath first isolation structure STI1.

Next, referring to FIG. 4 , a first gate structure GS1 and a second gate structure GS2 are respectively formed on the first surface S1 of the epitaxial layer 110 . The first gate structure GS1 and the second gate structure GS2 may each correspond to a gate structure of a transfer transistor, a source follower transistor, a column select transistor or a reset transistor. In this embodiment, the first gate structure GS1 may be the gate structure of the transfer transistor, and the second gate structure GS2 may be the gate structure of the reset transistor. In some embodiments, the first gate structure GS1 and the second gate structure GS2 may each include a gate (not shown) formed on the first surface S1 of the epitaxial layer 110, a gate formed between the gate and the epitaxial layer 110. A gate dielectric layer (not shown) between layers 110 and a gate spacer (not shown) formed on the gate sidewalls. The gate may include any material that can be used as a gate, such as polysilicon. The gate dielectric layer may include any material that may function as a gate dielectric layer, such as silicon oxide. Gate spacers may include Any material that can be used as a gate spacer, such as silicon nitride.

Then, a third doping region 115 having a second conductivity type (eg, N-type) and a fourth doping region 117 having a first conductivity type (eg, P-type) are respectively formed in the pixel region of the epitaxial layer 110 . The fourth doped region 117 is formed extending from the first surface S1 of the epitaxial layer 110 into the epitaxial layer 110 , and the third doped region 115 is formed between the fourth doped region 117 and the third doped region 115 , and the second doped region 113 includes a portion disposed between the first doped region 111 and the third doped region 115 . The first doped region 111, the second doped region 113, the third doped region 115 and the fourth doped region 117 form the image sensing element PD of the image sensor.

In some embodiments, the third doped region 115 and the fourth doped region 117 may be formed through the following steps. First, the third doped region 115 in contact with the second doped region 113 can be formed at a certain depth from the first surface S1 of the epitaxial layer 110 through an ion implantation process. In some embodiments, the third doped region 115 may extend from the first surface S1 of the epitaxial layer 110 into the epitaxial layer 110 . In some embodiments, the first gate structure GS1 is closer to the image sensing element PD than the second gate structure GS2, and the third doped region 115 may include a portion in contact with the first gate structure GS1. Next, an ion implantation process may be used to form a fourth doped region 117 at a certain depth from the first surface S1 of the epitaxial layer 110 . In some embodiments, the fourth doped region 117 may include a portion formed in the third doped region 115 and in contact with the first gate structure GS1 and a portion formed in the epitaxial layer 110 and in contact with the first isolation structure STI1 part. In some embodiments, the fourth doped region 117 may extend from the first surface S1 of the epitaxial layer 110 into the epitaxial layer 110 .

After that, please continue to refer to FIG. 4 to form the doping region 116 and the doping region 118 respectively in the epitaxial layer 110 between the first gate structure GS1 and the second gate structure GS2 and the second gate structure GS2 and GS2 respectively. in the epitaxial layer 110 between the first isolation structures STI1. Doped region 116 and doped region 118 may each have a second conductivity type (eg, N-type). In some embodiments, when the first gate structure GS1 and the second gate structure GS2 are respectively the gate structure of the transfer transistor and the gate structure of the reset transistor, the first gate structure GS1 may be configured To selectively control the movement of charge carriers between the image sensing element PD and the doped region 116 . The doped region 116 may be a floating node and may be electrically connected to the source follower transistor SF shown in FIG. 5 via interconnects 122 and conductive contacts 124 that will be formed later. The doped region 118 may be a drain connected to the operating voltage (VDD).

Then, referring to FIG. 5 , an interconnect structure is formed on the first surface S1 of the epitaxial layer 110 . In some embodiments, the interconnect structure may include a dielectric layer 120 formed on the first surface S1 of the epitaxial layer 110 and a conductive contact formed in the dielectric layer 120 (as shown in (b) of FIG. 5 The conductive contacts 124 shown and the conductive contacts C1, C2, C3, C4, GC1, GC2, GC3, GC4) shown in FIG. 5(c) and the interconnects 122 formed in the dielectric layer 120 .

Dielectric layer 120 may include one or more dielectric layers. In some embodiments, dielectric layer 120 may include an insulating material such as one or more of silicon dioxide, SiCOH, fluorosilicate glass, phosphate glass (eg, borophosphate silicate glass), or the like. By. In some embodiments, conductive contacts 124, C1, C2, C3, C4, GC1, GC2, GC3, GC4 may include conductive materials such as copper, tungsten, ruthenium, Aluminum and/or similar.

Referring to (c) of FIG. 5 , in some embodiments, the image sensor may include a transfer transistor TX, a source follower transistor SF, a column selection transistor Sel, and a reset transistor RST. The conductive contacts GC1, GC2, GC3 and GC4 can be respectively connected to the gate structures of the transfer transistor TX, the reset transistor RST, the pole follower transistor SF and the column selection transistor Sel. The transfer transistor TX can be connected to the source follower transistor SF via the conductive contact C1 and the interconnect structure. The conductive contact C2 can be connected to the operating voltage via an interconnection structure. The conductive contact C3 can be connected to the pixel power supply voltage through an interconnect structure. Conductive contact C4 may be connected to the output line through an interconnection structure. In some embodiments, (a) of FIG. 5 is a cross-sectional view taken along line AA' shown in (c) of FIG. 5 , and (b) of FIG. 5 is a cross-sectional view taken along line AA' shown in FIG. 5(c) . (c) is a cross-sectional view taken along the section line BB', so the conductive contact C1 and the conductive contact C2 shown in (c) of Figure 5 can correspond to (b) of Figure 5 The conductive contact 124 is shown, and the first gate structure GS1 and the second gate structure GS2 shown in FIG. 5(b) can respectively correspond to the transfer transistor shown in FIG. 5(c) The gate structure of TX and the gate structure of reset transistor RST.

Next, please refer to FIGS. 5 and 6 , after forming the interconnect structure, the dielectric layer 120 of the interconnect structure is bonded to the supporting substrate 10 . For example, in some embodiments, support substrate 10 may include a semiconductor material, such as silicon. Then, after the dielectric layer 120 is bonded to the supporting substrate 10, the base layer 100 can be removed through a thinning process to expose the second surface S2 of the epitaxial layer 110, which allows radiation (eg, light) to be more easily to the image sensing element PD. In some embodiments, after thinning After the process, the portion of the first doped region 111 in the base layer 100 is also removed, and a first doped region 111a extending from the second surface S2 of the epitaxial layer 110 to the epitaxial layer 110 is formed. In some embodiments, the thinning process can be performed by etching and/or mechanical grinding.

Afterwards, referring to FIG. 6 , a second isolation structure STI2 extending from the second surface S2 of the epitaxial layer 110 to the epitaxial layer 110 is formed in the epitaxial layer 110 . In some embodiments, the second isolation structure STI2 overlaps the first isolation structure STI1 in a direction perpendicular to the second surface S2 of the epitaxial layer 110 . In some embodiments, the second isolation structure STI2 may be spaced apart from the first isolation structure STI1 in a direction perpendicular to the epitaxial layer 110 . In other embodiments, the second isolation structure STI2 may be in contact with the first isolation structure STI1. In some alternative embodiments, the second isolation structure STI2 may penetrate a portion of the first isolation structure STI1. The second isolation structure STI2 may include one or more dielectric materials. The dielectric material may include oxides (such as silicon oxide), tetraethyl orthosilicate (TEOS), nitrides (such as silicon nitride, silicon oxynitride, etc.), carbides (such as silicon carbide, carbon silicon oxide, etc.) or similar. The second isolation structure STI2 may be, for example, a deep trench isolation structure, but is not limited thereto. In some embodiments, the second isolation structure STI2 can substantially limit the incident radiation in the pixel area to avoid crosstalk problems between two adjacent pixel areas.

Then, referring to FIG. 7 , a color filter 130 is formed on the second surface S2 of the epitaxial layer 110 . The color filter 130 may be formed over the pixel area. The interface where the color filters 130 contact each other may be located on the second isolation structure STI2. Color filter 130 allows transmission of radiation (eg, light) having a specific range of wavelengths while blocking waves A material formed from light that grows outside the specified range. In some embodiments, color filter 130 may be formed from a monomer, a polymer, or the like.

Then, microlenses 140 are formed on the color filter 130 to form the image sensor 1 . In some embodiments, the microlens 140 may be formed by depositing microlens material on the color filter 130 (eg, by a spin coating method or a deposition process). A microlens template with a curved upper surface is patterned over the microlens material (not shown). The microlens template may include photoresist material that is exposed using a distributed exposure dose (eg, for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a rounded shape. Microlenses 140 are then formed by selectively etching the microlens material according to the microlens template.

Based on the above, in the above method of forming an image sensor, since the second doped region 113 in the image sensing element PD is formed to surround both sides and the bottom of the first doped region 111a, the image sensing element In addition to the depletion capacitance in the vertical direction, PD also includes lateral depletion capacitance in the lateral direction. In this way, the image sensor 1 can still have sufficient full well capacity despite its small size design, so that the image sensor 1 has good sensitivity and image delay. On the other hand, since the first doped region 111 is formed by an epitaxial growth process on the back side (such as the second surface S2 shown in FIG. 7 ), it can avoid the front side (such as the second surface S2 shown in FIG. 7 ). A surface S1) is damaged during high-energy doping to avoid dark current caused by lattice defects.

Hereinafter, the image sensor 1 will be explained using (b) of FIG. 7 . It should be noted that the image sensor 1 shown in FIG. 7(b) can be formed by the above method, but Not limited to this method.

Referring to (b) of FIG. 7 , the image sensor 1 includes a substrate 110, a first isolation structure STI1, an image sensing element PD, and a first gate structure GS1 and a second gate structure GS2.

The substrate 110 may include a first surface S1 and a second surface S2 opposite to each other. In this embodiment, the substrate 110 may be an epitaxial layer formed on a bulk silicon substrate having a first conductivity type that is the same as the first conductivity type of the epitaxial layer (eg, P type), or an epitaxial layer formed on an image sensor. In the manufacturing of 1, the P-type epitaxial layer of the bulk silicon substrate is removed from it, so the substrate 110 is also called the epitaxial layer 110 in the above manufacturing process. In this embodiment, the image sensor 1 is a backside illumination (BSI) image sensor, and the image sensing element PD can transmit radiation incident from the second surface S2 of the substrate 110 toward the first surface S1 of the substrate 110 (such as light) into electrical signals.

The first isolation structure STI1 may be disposed in the substrate 110 and extend from the first surface S1 into the substrate 110 to define a pixel region (the pixel region PR shown in (c) of FIG. 5 ). In some embodiments, the image sensor 1 may further include a second isolation structure STI2 disposed in the substrate 110 and extending from the second surface S2 of the substrate 110 into the substrate 110 .

The image sensing device PD may be disposed in a pixel region of the substrate 110 and include a first doped region 111a having a first conductivity type (e.g., P type), a second doped region 113 having a second conductivity type (e.g., N type) different from the first conductivity type, a third doped region 115 having the second conductivity type (e.g., N type), and a fourth doped region 117 having the first conductivity type (e.g., P type). The first doped region 111a may extend from the second surface S2 of the substrate 110 into the substrate 110. The fourth doped region 117 may extend from the first surface S1 of the substrate 110 into the substrate 110. The second doped region 113 may surround the first doped region 111a and may include a portion disposed between the first doped region 111a and the fourth doped region 117. The third doped region 115 may be disposed between the second doped region 113 and the fourth doped region 117. In some embodiments, the interface where the first doped region 111a and the second doped region 113 contact each other is a cup-shaped profile, and the opening portion of the cup-shaped profile faces the second surface S2 of the substrate 110. In some embodiments, the cup-shaped profile is U-shaped or U-shaped in a certain cross section, but is not limited thereto.

The first gate structure GS1 and the second gate structure GS2 may be respectively disposed on the first surface S1 in the pixel area of the substrate 110 . In some embodiments, the first gate structure GS1 is closer to the image sensing element PD than the second gate structure GS2. In some embodiments, the third doped region 115 and the fourth doped region 117 may each include a portion in contact with the first gate structure GS1.

In some embodiments, the image sensor 1 may further include a color filter 130 disposed on the second surface S2 of the substrate 110 and a microlens 140 disposed on the color filter 130 .

To sum up, in the image sensor and its forming method in the above embodiments, since the second doping region with the second conductivity type in the image sensing element is designed to surround the first doping region with the first conductivity type, Doping the region so that the image sensing element includes additional lateral depletion capacitance. In this way, the image sensor can still have sufficient full well capacity despite its small size design, so that the image sensor has good sensitivity and image delay. On the other hand, since the first doping region is formed on the back side of the image sensor by It is formed by an epitaxial growth process, so it can avoid damage to the front side of the image sensor caused by high-energy doping and avoid dark current caused by lattice defects.

1:Image sensor 10: Support base 116, 118: Doped area 110: Epitaxial layer 111a: first doped region 113: Second doping region 114:Well area 115: The third doping region 117: The fourth doped region 120:Dielectric layer 122:Internal connection 124: Conductive contacts 130: Color filter 140: Microlens GS1: first gate structure GS2: Second gate structure STI1: First isolation structure STI2: Second isolation structure PD: image sensing element S1: first surface S2: Second surface

Claims (10)

An image sensor includes: a substrate including a first surface and a second surface opposite each other; a first isolation structure disposed in the substrate and extending from the first surface to the substrate to define pixels Region; an image sensing element, which is disposed in the pixel region of the substrate and includes a first doping region with a first conductivity type, a second doping region with a second conductivity type different from the first conductivity type. a doping region, a third doping region having the second conductivity type and a fourth doping region having the first conductivity type, wherein the first doping region is formed from the second surface of the substrate Extending into the substrate, the fourth doped region extends from the first surface of the substrate into the substrate, the second doped region surrounds the first doped region and includes a a portion between the first doped region and the fourth doped region, and the third doped region is disposed between the second doped region and the fourth doped region; and A gate structure and a second gate structure are respectively disposed on the first surface in the pixel area of the substrate. The image sensor of claim 1, wherein the interface where the first doped region and the second doped region contact each other has a cup-shaped profile, and the opening portion of the cup-shaped profile faces the substrate of the second surface. The image sensor of claim 1, wherein the first gate structure is closer to the image sensing element than the second gate structure, and the third doped region and the fourth doped region Each of the hybrid regions includes a portion in contact with the first gate structure. The image sensor of claim 1, further comprising: a color filter disposed on the second surface of the substrate; and a microlens disposed on the color filter. The image sensor of claim 1, further comprising: a second isolation structure disposed in the substrate and extending from the second surface of the substrate into the substrate. A method of forming an image sensor, including: forming a doped region with a first conductivity type in a base layer; performing an epitaxial growth process on the base layer to form an epitaxial layer on the base layer, and The doped region is diffused into the epitaxial layer to form a first doped region extending from the base layer into the epitaxial layer, wherein the first doped region has the first Conductive type; forming a first isolation structure in the epitaxial layer extending from the first surface of the epitaxial layer to the epitaxial layer to define a pixel area; in the picture of the epitaxial layer A second doped region surrounding the first doped region is formed in the element region, wherein the second doped region has a second conductivity type different from the first conductivity type; and in the epitaxial layer A third doping region having the second conductivity type and a fourth doping region having the first conductivity type are respectively formed in the pixel region, wherein the fourth doping region is formed from the epitaxial layer. The first surface extends into the epitaxial layer, the third doped region is disposed between the fourth doped region and the third doped region, and the second doped region including being disposed in the first doped region and the The portion between the third doped regions, and the first doped region, the second doped region, the third doped region and the fourth doped region form the image sensor image sensing element. The method of forming an image sensor according to claim 6, wherein the interface where the first doped region and the second doped region contact each other has a cup-shaped profile, and the opening portion of the cup-shaped profile faces A second surface of the epitaxial layer opposite to the first surface. The method of forming an image sensor as claimed in claim 6, further comprising: before forming the third doped region and the fourth doped region, forming on the first surface of the epitaxial layer A first gate structure and a second gate structure are respectively formed, wherein the first gate structure is closer to the image sensing element than the second gate structure, and the third doped region and the third gate structure are Each of the four doped regions includes a portion in contact with the first gate structure. The method of forming an image sensor as claimed in claim 6, further comprising: forming an interconnect structure on the first surface of the epitaxial layer; and after forming the interconnect structure, removing the interconnect structure. The base layer is configured to expose a second surface of the epitaxial layer opposite to the first surface; and the epitaxial layer is formed in the epitaxial layer extending from the second surface of the epitaxial layer to the epitaxial layer. Second isolation structure in the crystal layer. The method of forming an image sensor according to claim 9, further comprising: forming a color filter on the second surface of the epitaxial layer; and Microlenses are formed on the color filter.

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