TWI834917B - Phase-locked loop, method and multi-modulus divider for fractional-n frequency synthesis - Google Patents

Abstract

Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.

Description

Phase locked loop, method and multi-mode frequency divider for fractional N-type frequency synthesis Priority

This application is based on and claims priority to U.S. Provisional Patent Application No. 62/984,427 filed in the U.S. Patent and Trademark Office on March 3, 2020, the contents of which are incorporated by reference. in this article.

The present disclosure relates generally to phase-locked loops (PLLs), and more specifically, to a method and system for quantization error (QE) reduction for fractional-N PLLs.

A sigma-delta modulator (SDM or ΣΔM) is commonly used to control a multi-modulus divider (MMDIV) in a PLL used for fractional N-type frequency synthesis. Referring first to Figure 1, a diagram shows a fractional N-type PLL. MMDIV 102 driven by SDM 104 is used in the feedback path of fractional N-mode frequency synthesis. The SDM 104 receives a frequency control word (FCW) and outputs a division ratio sequence (NDIV) to the driver MMDIV 102 . The output clock of MMDIV 102 (which is also called feedback clock (CLKFB)) is fed to a phase detector (PD), which is implemented as a phase frequency detector ( phase frequency detector; PFD) 106 and charge pump 108. PFD 106 receives CLKFB along with a reference clock (CLKREF). PFD 106 provides a signal proportional to the phase difference between the received clock signals, and charge pump 108 is used to sink and provide current to low pass loop filter 110 based on the output from PFD 106 current. The low-pass loop filter 110 filters the received signal and outputs a control voltage V _ctrl that controls the frequency of a voltage-controlled oscillator (VCO) 112 that outputs a periodic signal CLKVCO to MMDIV102.

SDM 104 introduces QE in CLKFB of MMDIV 102. In some aspects, this QE reduces PLL performance. First, QE causes in-band phase noise (PN) in the PLL. Second, QE increases the required linear operating range of the PD after lock-in, making PD design difficult.

Various techniques have been proposed to reduce QE. One such technology uses high-efficiency PDs capable of handling larger QE. The PD may be implemented as a PFD 106 and charge pump 108 in an analog PLL, or as a time-to-digital converter (TDC) in a digital PLL. Charge pump and TDC are challenging sub-blocks in fractional-N-type PLL.

Another technique for reducing QE is to add a digital-to-time converter (DTC) in the CLKREF path to eliminate QE in CLKFB. Figure 2 is a diagram illustrating a fractional N-type PLL using DTC to compensate for QE. The PLL of Figure 2 includes MMDIV 202, SDM 204, PD 206, low pass loop filter 210, and VCO 212 operating in a manner similar to that described with respect to Figure 1 . SDM 204 provides QE (or Φ _e (n)) to multiplier 214 for combination with the DTC gain. The DTC control word is output from multiplier 214 and provided to DTC 216, which uses the DTC control word to adjust CLKREF to CLKDTC. CLKDTC is fed to PD 206 with CLKFB from MMDIV 202 so that QE can be canceled from CLKFB.

This technique attempts to prevent PD from discovering QE. The DTC range needs to be sufficient to cover the entire range of QE. For a given order of SDM, QE in CLKFB is proportional to the MMDIV input clock period, which is the VCO period (T _VCO ) in a given PLL. QE also increases rapidly with the order of SDM. For 1st order SDM, QE is within 1 T _VCO . For 2nd order SDM, QE doubles to 2*T _VCO , and for 3rd order SDM, QE becomes 4*T _VCO . Generally speaking, 2nd or 3rd order SDM is required in fractional N-type PLL to randomize the sequence, which produces lower fractional spurs to meet the requirements of communication systems.

Therefore, a QE canceller circuit such as, for example, DTC 216 needs to cover a delay range greater than 4*Tvco for 3rd order SDM. For example, if the VCO frequency is 4 GHz, the required DTC range is 1 nanosecond (ns). It is challenging to design DTCs with a large delay range (DR) while achieving low integral nonlinearity (INL), which is critical for low fractional spurious levels. Additionally, DTC thermal noise increases proportionally to the square of the delay, which causes additional in-band PN in the PLL.

According to one embodiment, a method for fractional N-type frequency synthesis is provided PLL. The PLL consists of a PD configured to receive the clock and CLKFB and to generate and output the resulting phase difference between the clock and CLKFB. The PLL also contains: a low-pass loop filter configured to receive the resulting phase difference and generate and output a control voltage. The PLL additionally includes: a VCO configured to receive a control voltage and generate and output a periodic signal based on the voltage; and an SDM configured to receive a frequency command word and generate and output a division sequence ratio and select control signal. The PLL further includes: MMDIV, configured to receive differential inputs of periodic signals from the VCO and to receive frequency division sequence ratio and selection control signals from the SDM. The MMDIV is configured to generate first and second CLKFB based on the differential input and the frequency division sequence ratio and to output one of the first and second CLKFB as CLKFB to the PD based on the select control signal.

According to one embodiment, a method for fractional N-type frequency synthesis using a PLL is provided. The PD of the PLL determines the phase difference between the clock and CLKFB. The PLL's low-pass loop filter detects the control voltage based on the phase difference. The VCO of the PLL generates periodic signals based on the control voltage. The PLL's SDM generates frequency division sequence ratio and selection control signals based on frequency command words. MMDIV generates the first CLKFB and the second CLKFB based on the frequency division sequence ratio and the differential input of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as CLKFB to the PD based on the selection control signal.

According to one embodiment, a MMDIV for fractional N-type frequency synthesized PLL is provided. The MMDIV consists of a frequency divider configured to receive the differential input of the periodic signal from the PLL's VCO, receive the frequency division sequence ratio from the PLL's ΣΔ modulator (SDM), and generate and output a clock signal. The MMDIV also includes: a first flip-flop configured to receive a first differential input of a clock signal and a period signal and generate and output First CLKFB. The MMDIV further includes: a second flip-flop configured to receive a second differential input of the clock signal and the period signal and to generate and output a second CLKFB. The MMDIV further includes: a multiplexer configured to receive the first CLKFB, the second CLKFB and the selection control signal from the SDM and to output one of the first CLKFB and the second CLKFB as the CLKFB to the PLL based on the selection control signal. PD.

102, 202, 302-1, 302-2, 402, 702: multi-mode frequency divider

104, 204, 304-1, 304-2, 504, 704: Σ△ modulator

106: Phase frequency detector

108:Charge pump

110, 210, 710: low-pass loop filter

112, 212, 712: Voltage controlled oscillator

206, 706: Phase detector

214, 502: Multiplier

216, 716: Digital time converter

404: First delay flip-flop

406: Second delay flip-flop

408:Multiplexer

506: First frequency divider

508: Second frequency divider

510: Modulo 2 adder

512, 718: Adder

514: Delay block Z ^-2

516: Delay block Z ^-1

602: First adder

604: First delayed block Z ^-1

606:Quantizer

608: Second adder

610: Third adder

612: Second delay block Z ^-1

614: Fourth adder

714: First multiplier

720:Duty cycle correction block

722: Gain calibration block

724: Second multiplier

726: Accumulator

728: Third multiplier

730:Digital to Analog Converter

732: Voltage comparator

802, 804, 806, 808, 810, 812, 814, 816, 902, 904, 906, 908, 910, 912, 914, 916, 918: Steps

1000: Network environment

1001, 1002, 1004: Electronic devices

1008:Server

1020: Processor

1021: Main processor

1023: Auxiliary processor

1030:Memory

1032: Volatile memory

1034:Non-volatile memory

1036: Internal memory

1038:External memory

1040:Program

1042:Operating system

1044: Intermediate software

1046:Application

1050:Input device

1055: Sound output device

1060:Display device

1070: Audio module

1076: Sensor module

1077:Interface

1078:Connection terminal

1079: Tactile module

1080:Camera module

1088:Power management module

1089:Battery

1090: Communication module

1092:Wireless communication module

1094: Wired communication module

1096:User identification module

1097:Antenna module

1098:First Network

1099:Second Network

co: carry output bit

CLKDTC:DTC clock

CLKFB: feedback clock

CLKFB1: first feedback clock

CLKFB2: Second feedback clock

CLKREF: reference clock

CLKVCO: periodic signal

e1, e2: output

f _VCO , F _VCO : frequency

K _DTC : DTC gain

NDIV: frequency division ratio sequence

NDIV_int, QE_int(n), Φ _e , _int (n): integer part

PHE_Sign:Sign information

QE, Φ _e (n): quantization error

s: sum

Tvco: given PLL

_Vctrl : control voltage

VCO_dcc_cmp: convergence value

VCO_N, VCO_P: Differential input clock

Vref_adj: reference voltage

The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent from the following detailed description when taken in conjunction with the accompanying drawings:

Figure 1 is a diagram showing a fractional N-type PLL.

Figure 2 is a diagram illustrating a fractional N-type PLL using DTC to compensate for QE.

FIG. 3A is a diagram illustrating conventional MMDIV and SDM of fractional N-type PLL.

3B is a diagram illustrating MMDIV and SDM of a fractional-N-type PLL according to an embodiment of the present disclosure.

4A and 4B are diagrams illustrating a retimed MMDIV output clock of a fractional-N-type PLL according to embodiments of the present disclosure.

FIG. 5 is a diagram illustrating an SDM of a fractional N-type PLL according to an embodiment of the present disclosure.

6 is a diagram illustrating an SDM of a fractional N-type PLL according to an embodiment of the present disclosure.

7 is a diagram illustrating a fractional N-type PLL using DTC and VCO duty cycle correction according to an embodiment of the present disclosure.

8 is a diagram illustrating a method for performing fractional N using a PLL in accordance with an embodiment of the present disclosure. Flowchart of the frequency synthesis method.

9 is a flowchart illustrating a method for fractional N-type frequency synthesis using a DTC PLL according to an embodiment of the present disclosure.

FIG. 10 is a block diagram of an electronic device in a network environment according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that although elements are illustrated in different figures, identical elements will be designated by the same reference numerals. In the following description, specific details such as detailed configurations and components are only provided to assist in an overall understanding of embodiments of the present disclosure. Accordingly, it should be apparent to those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions are omitted for the sake of clarity and conciseness. The terms described below are terms defined taking into account the functions in the present disclosure, and may differ according to the user, the user's intention, or habits. Therefore, the definition of terms should be determined based on the content throughout this specification.

The present disclosure may have various modifications and various embodiments, some of which are described in detail below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

Although terms including ordinal numbers such as first, second, etc. may be used to describe various elements, the structural elements are not limited by the terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this disclosure, In this case, the first structural element may be called a second structural element. Similarly, the second structural element may also be called a first structural element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated items.

The terminology used herein is used only to describe various embodiments of the disclosure and is not intended to limit the disclosure. The singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. In this disclosure, it should be understood that the terms "comprising" or "having" indicate the presence of features, numbers, steps, operations, structural elements, portions, or combinations thereof, and do not exclude the presence or addition of one or more other features, numbers, Possibility of steps, operations, structural elements, parts or combinations thereof.

Unless defined differently, all terms used herein have the same meanings as understood by a person of ordinary skill in the technical field to which this disclosure belongs. Unless expressly defined in this disclosure, terms (such as those defined in commonly used dictionaries) should be interpreted to have the same meaning as the contextual meaning in the relevant technical field and should not be interpreted as having an ideal or excessive form meaning.

The electronic device according to one embodiment may be one of various types of electronic devices. Electronic devices may include, for example, portable communication devices (such as smartphones), computers, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. According to one embodiment of the present disclosure, the electronic device is not limited to those described above.

The terms used in the present disclosure are not intended to limit the present disclosure, but are intended to include various changes, equivalents, or substitutions of the corresponding embodiments. With regard to the description of the accompanying drawings, similar reference numbers may be used to refer to similar or related elements. Unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an item may include one or more of things. As used herein, "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "A, B and C" Each of such phrases "at least one of" and "at least one of A, B, or C" may include all possible combinations of the items listed together in the corresponding one of the phrase. As used herein, terms such as “first,” “second,” “first,” and “second” may be used to distinguish a corresponding component from another component but are not intended to limit other aspects (e.g., importance or order). It is intended that if an element (e.g. a first element) is referred to as being "coupled" to another element (e.g. a second element), with or without the term "in operation" or "in communication", "Coupled to", "connected to" or "connected to" another element indicates that the element may be coupled to another element directly (such as wired), wirelessly, or via a third element. catch.

As used herein, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as, for example, "logic," "logic." "Block", "Part" and "Circuit System". A module may be a single integrated component, or the smallest unit or portion thereof, adapted to perform one or more functions. For example, according to one embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

The present systems and methods provide a technique for reducing QE in half for any given order of SDM. Therefore, the required linear operating range of the PD (ie, TDC or PFD and charge pump) can be halved. This results in lower noise, less power consumption, and low fractional spurs.

In DTC based PLL where DTC is used to eliminate QE before PD, The systems and methods described may also help reduce the required DTC range by half. This results in DTC designs with less DTC thermal noise, better linearity, and lower power consumption.

Digital logic is added before and after the SDM to generate a new NDIV for MMDIV, a clock select control signal for MMDIV, and a halved QE for QE cancellation used in a DTC or other canceller circuit.

Changes in the digital domain of the PLL can be synthesized, placed, and routed via the digital stream with negligible effects on area and power. The analog domain requires the addition of two digital flip-flops to retime the MMDIV output clock via CLKVCO (VCO_P) and an inverted version of CLKVCO (VCO_N), and therefore, a multiplexer is used to Choose between flip-flops and flip-flops. The selection control signal is generated by the modified SDM.

Since QE is reduced by half, the required DTC range is halved. The simulated DTC PN is reduced by 4 decibels (dB) and the INL is reduced to half the original INL. The system and method can also be applied to other fractional N-type PLL topologies to improve PD performance and reduce the impact of QE on PLL PN.

Referring to Figure 3A, a diagram shows conventional MMDIV and SDM of a fractional N-type PLL. SDM 304-1 receives FCW and outputs QE and NDIV. NDIV along with CKVCO (with frequency of f _VCO ) is provided from the VCO to MMDIV 302-1 and outputs CLKFB(F _VCO /FCW).

3B is a diagram illustrating MMDIV and SDM of a fractional-N-type PLL according to an embodiment of the present disclosure. SDM 304-2 receives FCW and outputs QE/2. In addition, SDM 304-2 provides NDIV and SEL_CLKFB to MMDIV 302-2. SEL_CLKFB is used to select between CLKFBs generated in MMDIV 302-2, as described in greater detail below with respect to Figure 4A.

With the changes described in Figure 3B, MMDIV can support an NDIV of (N+0.5). Therefore, compared to the conventional embodiment of FIG. 3A , the QE introduced due to fractional N-type frequency division in CLKFB is reduced by half.

Referring now to FIGS. 4A and 4B , diagrams illustrate retimed MMDIV output clocks of a Fractional-N PLL in accordance with embodiments of the present disclosure. MMDIV 402 receives differential input clock VCO_P and differential input clock VCO_N from the VCO and NDIV from the SDM. MMDIV 402 outputs CLKFB_int to a first delay flip-flop (DFF) 404 and a second DFF 406 . Conventionally, CLKFB_int is the CLKFB provided to PD and contains QE.

The first DFF 404 also receives VCO_P, and then outputs the first feedback clock CLKFB1. The second DFF 406 also receives VCO_N, and then outputs the second feedback clock CLKFB2. Multiplexer (MUX) 408 receives CLKFB1 from the first DFF 404, CLKFB2 from the second DFF 406, and SEL_CLKFB from the SDM. Based on SEL_CLKFB, MUX 408 selects one of CLKFB1 and CLKFB2 as the output CLKFB. If QE in CLKFB_int is greater than T _VCO /2, CLKFB2 is selected because CLKFB2 is delayed by T _VCO /2 compared to CLKFB1. Therefore, QE in CLKFB is reduced to T _VCO /2, which is equivalent to dividing by (N+0.5).

FIG. 4B shows that due to the differential input clock VCO_P and the differential input clock VCO_N, the rising edge of CLKFB2 is delayed by T _VCO /2 compared to the rising edge of CLKFB1 .

FIG. 5 is a diagram illustrating an SDM of a fractional N-type PLL according to an embodiment of the present disclosure. The FCW is received and multiplied by 2 at multiplier 502 (left shift). The output from multiplier 502 is divided into an integer part of FCW and a fractional part of FCW and provided to a conventional SDM 504 which outputs the integer part of QE (QE_int(n) or _Φe,int (n)) And the integer part of NDIV (NDIV_int). To achieve the correct division ratio, both QE_int(n) and NDIV_int must be divided by 2 (right-shifted). QE_int(n) is divided by 2 at first divider 506, resulting in QE(n) (or Φ _e (n)). NDIV_int is divided by 2 (right shifted) at the second divider 508. Dividing NDIV_int produces a fractional bit (0 or 0.5), which is sent to modulo 2 adder (mod2 adder) 510. mod2 adder 510 outputs a carry-out bit co, which is added to the integer portion of NDIV_int/2 at adder 512 to produce NDIV. This resulting NDIV is provided to MMDIV. Therefore, the average NDIV is equal to the NDIV achieved by conventional methods.

mod2 adder 510 also outputs the sum s to delay block Z ^-2 514 which implements a delay with two clock cycles and provides ^the resulting SEL_CLKFB to MMDIV. Delay block Z ⁻¹ 516 also receives the sum s , implements a delay of one clock cycle, and provides the resulting output back to the mod2 adder 510 .

Referring now to FIG. 6, a diagram illustrates an SDM of a fractional-N PLL according to an embodiment. Specifically, the SDM of FIG. 6 corresponds to SDM 504 of FIG. 5 . The fractional portion of the FCW is provided to the first summer 602, and the output from the first summer 602 is provided to the first delay block Z ^-1 604 that implements a delay of one clock cycle. The delayed output from the first delay block Z ^-1 604 is provided to a quantizer 606, and the quantized output, along with the integer portion of the FCW, is provided to a second adder 608. The output of the second adder 608 is the integer portion of NDIV (or NDIV_int).

The quantized output from quantizer 606 is also provided to the third adder 610 along with the delayed output from the first delay block Z ⁻¹ 604 . The output e2 from the third adder 610 is provided to the first adder 602 along with the fractional portion of the FCW.

The fractional portion of the FCW is also provided to a second delay block Z ^-1 612 that implements a delay of one clock cycle. The delayed output from the second delay block Z ⁻¹ 612 is provided to the fourth adder 614 along with the quantized output from the quantizer 606 . The output e1 from the fourth adder 614 is the integer part of QE(n) (QE_int(n) or Φ _e,int (n)).

When the VCO clock is not an ideal 50% duty cycle (for example, it has an analog circuit defect), in order to robustly implement the system and method, an LMS-based background calibration loop can be added to correct the duty cycle of the VCO clock.

Specifically, if VCO_P and VCO_N have duty cycle errors (that is, they are not fully differential), then the CLKFB1 and CLKFB2 timings will not exactly differ by T _VCO /2, which introduces errors. These errors slow down the DTC gain calibration, causing convergence at incorrect values. Therefore, a VCO duty cycle calibration (DCC) least-mean square (LMS) loop can be added by correlating the phase error polarity with SEL_CLKFB. Specifically, the DTC gain converges quickly without error, and the calibration results are applied to the DTC to compensate for the error. Since the VCO duty cycle error is small, a simple and small extension can be added to the desired DTC range.

Referring now to Figure 7, a diagram illustrates a fractional N-type PLL using DTC and VCO duty cycle correction, according to an embodiment. Specifically, FIG. 7 provides a more detailed illustration of the PLL of FIG. 2 and incorporates the MMDIV of FIG. 4A and the SDM of FIG. 5 . Additionally, Figure 7 provides VCO duty cycle correction.

The PLL of Figure 7 includes MMDIV 702, SDM 704, PD 706, low pass loop filter 710, and VCO 712. MMDIV 702 operates generally as described above with respect to FIG. 4A, and SDM 704 operates generally as described above with respect to FIGS. 5 and 6. SDM 704 provides QE(n) (or Φ _e (n)) to adder 718 , which also receives the convergence value VCO_dcc_cmp from VCO duty cycle correction block 720 . The result from adder 718 is provided to first multiplier 714 for combination with the DTC gain (K _DTC ) from DTC gain calibration block 722 . The DTC control word is output from first multiplier 714 and provided to DTC 716, which uses the DTC control word to adjust CLKREF to CLKDTC. CLKDTC is fed to PD 706 with CLKFB from MMDIV 702 so that QE can be canceled from CLKFB.

PHE_Sign is the sign information of the phase error between CLKDTC and CLKFB. If CLKDTC leads CLKFB, PHE_Sign is +1. If CLKDTC does not lead CLKFB, PHE_Sign is -1.

The VCO duty cycle error creates a phase shift in the CLKFB edge and eventually becomes apparent in PHE_Sign. Therefore, since SEL_CLKFB is used to select CLKFB1 or CLKFB2 as CLKFB, PHE_Sign has a strong correlation with SEL_CLKFB. Therefore, a least mean square (LMS) adaptation loop based on sign-sign regression is added to extract the VCO duty cycle error.

VCO duty cycle correction block 720 receives SEL_CLKFB from SDM 704 and PHE_Sign at second multiplier 724 . The output from the second multiplier 724 is provided to an accumulator 726 with a gain factor. The accumulated output from accumulator 726, along with SEL_CLKFB from SDM 704, is provided to third multiplier 728 to apply the correction. The output from the third multiplier 728 is the convergence value VCO_dcc_cmp, which is provided to the adder 718 along with QE(n) (or _Φe (n)) to control the DTC delay.

The same phase shift on CLKFB due to the VCO duty cycle error is applied to CLKDTC via the DTC delay code, and therefore the phase detector will no longer detect this phase error. The proposed VCO duty cycle correction does not require additional analog circuitry and instead uses the pre-existing PHE_Sign signal for DTC gain calibration.

DTC gain calibration block 722 receives the result of adder 718 as input and provides the output to a digital to analog converter (DAC) 730 . The reference voltage Vref_adj output from DAC 730 is provided to voltage comparator 732 along with the output from PD 706 . Voltage comparator 732 provides PHE_Sign to VCO duty cycle correction block 720. The DTC gain calibration block includes components and functions as generally known in the art, such as, for example, SDM, multipliers, delay blocks, and accumulators. Similarly, PD 706 includes components such as, for example, a ramp generator, and also includes functionality generally known in the art.

Referring to Figure 8, a flowchart illustrates a method for fractional N-type frequency synthesis using a PLL, in accordance with an embodiment of the present disclosure. At step 802, the PLL's PFD generates a signal proportional to the phase difference between the clock and CLKFB. At step 804, the charge pump of the PLL provides sink and source current based on the signal. At step 806, the PLL's low-pass loop filter generates a control voltage based on the sink and source currents. At step 808, the VCO of the PLL generates a periodic signal based on the control voltage. At step 810, the PLL's SDM generates NDIV and SEL_CLKFB based on the frequency command words.

By doubling the frequency command characters, execute on the doubled frequency command characters ΣΔ modulation to generate the first NDIV, and the first NDIV is halved to output the final NDIV to generate the NDIV.

At step 812, the MMDIV of the PLL generates the first CLKFB based on the first differential input (VCO_P) of the periodic signal and the clock signal using the first and second differential inputs (VCO_P and VCO_N) and the NDIV. produce. At step 814, MMDIV generates a second CLKFB based on the second differential input (VCO_N) of the periodic signal and the clock signal. At step 816, MMDIV selects one of the first CLKFB and the second CLKFB as the CLKFB output of the PFD based on SEL_CLKFB.

Referring to Figure 9, a flowchart illustrates a method for fractional N-type frequency synthesis using a DTC PLL in accordance with an embodiment of the present disclosure. At step 902, the PD receives the clock and CLKFB and outputs the resulting phase difference between the clock and CLKFB. At step 904, the PLL's low-pass loop filter generates a control voltage based on the phase difference. At step 906, the VCO of the PLL generates a periodic signal based on the control voltage. At step 908, the PLL's SDM generates NDIV, SEL_CLKFB, and QE based on the frequency command words.

By doubling the frequency command words, performing ΣΔ modulation on the doubled frequency command words to generate the first NDIV and the first QE, halving the first NDIV to output the final NDIV, and halving the first QE to output the final NDIV. Output the final QE to generate NDIV and QE.

At step 910, the QE and DTC gains are combined to generate a DTC control word. At step 912, the DTC generates CLKDTC as the clock input of the PD based on CLKREF and the DTC control word.

At step 914, the MMDIV of the PLL generates the first CLKFB based on the first differential input (VCO_P) of the periodic signal and the clock signal. Generated using the first and second differential inputs (VCO_P and VCO_N) and NDIV. At step 916, MMDIV generates a second CLKFB based on the second differential input (VCO_N) of the periodic signal and the clock signal. At step 918, MMDIV selects one of the first CLKFB and the second CLKFB as the CLKFB output of the PD based on SEL_CLKFB.

The disclosed systems and methods can support high-level SDM operations, support lower VCO oscillation frequencies for a given DTC range, provide minimal analog circuit changes or overhead, and digital background calibration ensures that the proposed systems and methods operate in the presence of VCO duty cycle errors. robustness under the circumstances.

The systems and methods described may also be used in instances where a quadrature VCO (QVCO) or ring oscillator is used to handle a ¼ T _VCO delay.

Figure 10 is a block diagram of an electronic device in a network environment according to one embodiment. Referring to FIG. 10 , the electronic device 1001 in the network environment 1000 can communicate with the electronic device 1002 via the first network 1098 (such as a short-range wireless communication network), or with the electronic device via the second network 1099 (such as a long-range wireless communication network). 1004 or server 1008 communication. Electronic device 1001 can communicate with electronic device 1004 via server 1008 . The electronic device 1001 may include a processor 1020, a memory 1030, an input device 1050, a sound output device 1055, a display device 1060, an audio module 1070, a sensor module 1076, an interface 1077, a haptic module 1079, and a camera module 1080. , power management module 1088, battery 1089, communication module 1090, subscriber identification module (subscriber identification module; SIM) 1096 or antenna module 1097. In one embodiment, at least one of the components (eg, display device 1060 or camera module 1080 ) may be omitted from electronic device 1001 , or one or more other components may be added to electronic device 1001 . Some of the components may be implemented as a single integrated circuit (integrated circuit; IC). For example, the sensor module 1076 (eg, a fingerprint sensor, an iris sensor, or an illumination sensor) may be embedded in the display device 1060 (eg, a display).

The processor 1020 may execute, for example, software (eg, the program 1040) to control at least one other component (eg, a hardware component or a software component) of the electronic device 1001 coupled to the processor 1020, and may perform various data processing or calculations. As at least part of the data processing or calculation, the processor 1020 may load commands or data received from another component (such as the sensor module 1076 or the communication module 1090) in the volatile memory 1032, and process the data stored in the volatile memory 1032. command or data in the volatile memory 1032, and store the obtained data in the non-volatile memory 1034. The processor 1020 may include a main processor 1021 (such as a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 1023 (such as a graphics processing unit (GPU)). , image signal processor (ISP), sensor hub processor or communication processor (CP)), the auxiliary processor 1023 can operate independently of the main processor 1021 or with the main processor 1021 1021 combined operation. Additionally or alternatively, secondary processor 1023 may be adapted to consume less power or perform specific functions than primary processor 1021 . The secondary processor 1023 may be implemented separately from the main processor 1021 or implemented as part of the main processor 1021 .

The auxiliary processor 1023 may replace the main processor 1021 when the main processor 1021 is in an inactive state (eg, sleeping) or may control the main processor 1021 together with the main processor 1021 when the main processor 1021 is in an active state (eg, executing an application program). At least one of functions or states related to at least one of the components of the electronic device 1001 (such as the display device 1060, the sensor module 1076, or the communication module 1090) some. The auxiliary processor 1023 (eg, an image signal processor or a communications processor) may be implemented as part of another component (eg, the camera module 1080 or the communications module 1090) that is functionally related to the auxiliary processor 1023.

The memory 1030 may store various data used by at least one component of the electronic device 1001 (eg, the processor 1020 or the sensor module 1076). Various data may include, for example, software (eg, program 1040) and input data or output data for commands associated therewith. Memory 1030 may include volatile memory 1032 or non-volatile memory 1034.

Program 1040 may be stored as software in memory 1030 and may include, for example, an operating system (OS) 1042, middleware 1044, or an application 1046.

The input device 1050 can receive commands or data from outside the electronic device 1001 (eg, a user) to be used by other components of the electronic device 1001 (eg, the processor 1020). Input device 1050 may include, for example, a microphone, a mouse, or a keyboard.

The sound output device 1055 can output sound signals to the outside of the electronic device 1001 . Sound output device 1055 may include, for example, a speaker or receiver. The speaker can be used for general purposes such as playing multimedia or recording, and the receiver can be used to receive incoming phone calls. The receiver may be implemented separate from the speaker, or as part of the speaker.

The display device 1060 can visually provide information to the outside of the electronic device 1001 (eg, a user). Display device 1060 may include, for example, a display, a hologram device, or a projector, and control circuitry to control a corresponding one of the display, hologram device, and projector. Display device 1060 may include touch circuitry adapted to detect a touch or adapted to measure the intensity of a force induced by a touch. Sensor circuitry (e.g. pressure sensor).

The audio module 1070 can convert sounds into electrical signals and vice versa. The audio module 1070 may obtain sound via the input device 1050 , or output the sound via the sound output device 1055 or a headset of an external electronic device 1002 that is directly (eg, wired) or wirelessly coupled to the electronic device 1001 .

The sensor module 1076 can detect the operating status (such as power or temperature) of the electronic device 1001 or the environmental status (such as the user's status) external to the electronic device 1001, and then generate an electrical signal corresponding to the detected status or data value. The sensor module 1076 may include, for example, a posture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, and a color sensor. , infrared (infrared; IR) sensor, biometric sensor, temperature sensor, humidity sensor or illumination sensor.

Interface 1077 may support one or more specified protocols to be used for electronic device 1001 to be directly (eg, wired) or wirelessly coupled to external electronic device 1002 . The interface 1077 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

The connection terminal 1078 may include a connector through which the electronic device 1001 may be physically connected to the external electronic device 1002 . The connection terminal 1078 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 1079 can convert electrical signals into mechanical stimulation (such as vibration or movement) or electrical stimulation that can be recognized by the user through touch or kinesthetic sense. Haptic module 1079 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

The camera module 1080 can capture still images or moving images. The camera module 1080 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 1088 can manage the power supplied to the electronic device 1001 . The power management module 1088 may be implemented as, for example, at least part of a power management integrated circuit (PMIC).

Battery 1089 may supply power to at least one component of electronic device 1001 . Battery 1089 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

The communication module 1090 can support establishing a direct (such as wired) communication channel or wireless communication channel between the electronic device 1001 and an external electronic device (such as the electronic device 1002, the electronic device 1004 or the server 1008) and executing through the established communication channel. Communication. Communication module 1090 may include one or more communication processors that may operate independently of processor 1020 (eg, AP) and support direct (eg, wired) communication or wireless communication. The communication module 1090 may include a wireless communication module 1092 (such as a cellular communication module, a short-range wireless communication module or a global navigation satellite system (GNSS) communication module) or a wired communication module 1094 (such as a regional Network (local area network; LAN) communication module or wire communication (power line communication; PLC) module). A corresponding one of these communication modules may communicate via the first network 1098 ( ^for example, a short-range communication network such as Bluetooth ^™ , Wireless Fidelity (Wi-Fi), or Infrared Data Association (IrDA) ) standard) or a second network 1099 (such as a long-range communication network such as a cellular network, the Internet, or a computer network (such as a LAN or wide area network (WAN))) to communicate with external electronic devices. These various types of communication modules may be implemented as a single component (eg, a single IC), or may be implemented as multiple components that are separate from each other (eg, multiple ICs). The wireless communication module 1092 can use the user information (such as international mobile subscriber identity; IMSI) stored in the subscriber identification module 1096 to communicate over a communication network (such as the first network 1098 or the second network 1099 ) to identify and verify the electronic device 1001.

The antenna module 1097 can transmit/receive signals or power to/from the outside of the electronic device 1001 (eg, an external electronic device). The antenna module 1097 may include one or more antennas, and may be selected from the one or more antennas by the communication module 1090 (such as the wireless communication module 1092) to be suitable for use in a communication network (such as the first network). 1098 or at least one antenna for the communication scheme used in the second network 1099). Signals or power can then be transmitted or received between the communication module 1090 and the external electronic device via the selected at least one antenna.

At least some of the above components may be coupled to each other via inter-peripheral communication schemes such as bus, general purpose input and output (GPIO), serial peripheral interface (SPI) or mobile Mobile industry processor interface (MIPI) transmits signals (such as commands or data).

Commands or data may be transmitted or received between the electronic device 1001 and the external electronic device 1004 via the server 1008 coupled to the second network 1099. Each of electronic device 1002 and electronic device 1004 may be the same type of device as electronic device 1001 or a different type of device. All or some of the operations to be performed at electronic device 1001 may be performed at one or more of external electronic device 1002, external electronic device 1004, or external electronic device 1008. For example, if the electronic device 1001 should automatically To perform a function or service, or in response to a request from a user or another device, instead of or in addition to performing a function or service, the electronic device 1001 may also request one or more external electronic devices to perform a function or service. At least part of the service. One or more external electronic devices receiving the request may perform at least part of the requested function or service or additional functions or additional services related to the request, and transmit the results of the execution to the electronic device 1001 . The electronic device 1001 may provide the result to the request as at least part of a reply, with or without further processing the result. For this purpose, cloud computing, distributed computing or master-slave computing technologies can be used, for example.

One embodiment may be implemented as software (e.g., program 1040) that includes one or more instructions stored on a storage medium (e.g., internal memory 1036 or external memory 1038). For example, the processor of the electronic device 1001 may invoke at least one of one or more instructions stored in the storage medium, and under the control of the processor with or without the use of one or more other components. Execute at least one of the one or more instructions. Accordingly, the machine is operable to perform at least one function according to the at least one instruction invoked. One or more instructions may include code generated by a compiler or code executable by an interpreter. Machine-readable storage media may be provided in the form of non-transitory storage media. The term "non-transitory" indicates that the storage medium is a tangible device and does not contain signals (such as electromagnetic waves), but the term does not distinguish between situations where data is stored semi-permanently in the storage medium and situations where data is temporarily stored in the storage medium. Distinguish.

According to one embodiment, the method of the present disclosure may be included in and provided in a computer program product. Computer program products may be traded as products between sellers and buyers. A computer program product may be distributed in the form of a machine-readable storage medium (such as a compact disc read only memory (CD-ROM)) or online through an application store (such as the Play Store ^TM ) (such as a download or upload), or spread directly between two user devices (such as smartphones). If distributed online, at least part of the computer program product may be temporarily generated or at least temporarily stored on a machine-readable storage medium such as the memory of the manufacturer's server, an application store's server, or a relay server )middle.

According to one embodiment, each of the above-mentioned components (eg, a module or a program) may include a single entity or multiple entities. One or more of the above components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (eg, modules or programs) may be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as before integration by a corresponding one of the plurality of components. one or more functions of each. Operations performed by a module, program, or another component may be performed sequentially, simultaneously, repeatedly, or exploratoryly, or one or more of the operations may be performed in a different order or be omitted, or one or more other operations may be added. operate.

Although certain embodiments of the disclosure have been described in the detailed description of the disclosure, the disclosure may be modified in various forms without departing from the scope of the disclosure. Therefore, the scope of the present disclosure should be determined not based solely on the described embodiments, but rather on the scope of the appended claims and their equivalents.

102:Multi-mode frequency divider

104: Σ △ modulator

106: Phase frequency detector

108:Charge pump

110: Low pass loop filter

112:Voltage controlled oscillator

CLKFB: feedback clock

CLKREF: reference clock

_Vctrl : control voltage

Claims (22)

A phase locked loop (PLL) for fractional N-type frequency synthesis, the phase locked loop includes: a phase detector (PD) configured to receive a clock and a feedback clock (CLKFB) and generate and output the a resulting phase difference between the clock and the feedback clock; a low pass loop filter configured to receive the resulting phase difference and generate and output a control voltage; a voltage controlled oscillator (VCO), configured to receive the control voltage and generate and output a periodic signal based on the control voltage; a ΣΔ modulator (SDM) configured to receive a frequency command word and generate and output a division sequence ratio sequence ratio) and a selection control signal; and a multi-mode frequency divider (MMDIV) configured to receive a differential input of the periodic signal from the voltage controlled oscillator and receive the sigma delta modulator. a divider sequence ratio and the selection control signal, wherein the multi-mode divider is configured to generate a first feedback clock and a second feedback clock based on the differential input and the divider sequence ratio, and One of the first feedback clock and the second feedback clock is output to the phase detector as the feedback clock based on the selection control signal. The phase locked loop of claim 1, wherein the clock is a reference clock (CLKREF). The phase locked loop of claim 1, wherein the rising edge of the second feedback clock is delayed from the rising edge of the first feedback clock by half of the period of the voltage controlled oscillator. The phase locked loop of claim 1, wherein the phase detector includes: a phase frequency detector (PFD) configured to receive the clock and a feedback clock and generate and output a signal proportional to the phase difference between the clock and the feedback clock; and A charge pump configured to receive the signal from the phase frequency detector and to generate sink and source currents based on the received signal and to generate the sink and source currents. output to the low pass loop filter. The phase locked loop of claim 1, wherein the multi-mode frequency divider includes: a first flip-flop configured to receive a first differential input of the periodic signal and use the differential input and the a clock signal generated by dividing the frequency sequence ratio and configured to generate and output the first feedback clock; a second flip-flop configured to receive a second differential input of the periodic signal and the clock signal pulse signal and configured to generate and output the second feedback clock; and a multiplexer configured to receive the first feedback clock, the second feedback clock and the selection control signal, And based on the selection control signal, the one of the first feedback clock and the second feedback clock is output as the feedback clock. The phase locked loop of claim 1, wherein the ΣΔ modulator is configured to double the frequency command word, and perform ΣΔ modulation on the doubled frequency command word to generate the first a frequency dividing sequence ratio, and the first frequency dividing sequence ratio is halved to output the frequency dividing sequence ratio to the multi-mode frequency divider. The phase locked loop of claim 6, wherein a carry-out bit is added to the halved first divisor sequence ratio to produce the divisor sequence ratio. The phase locked loop of claim 1, wherein the ΣΔ modulator is further configured to generate a quantization error, and the phase locked loop further includes: a multiplier configured to receive the quantization error and a digital time converter (DTC) gain and generate and output a digital time converter control word; and a digital time converter configured to receive a reference clock and the digital time converter control word and generate and output a digital time converter The clock (CLKDTC) is used as the clock input of the phase detector. The phase locked loop of claim 8, wherein the ΣΔ modulator is configured to double the frequency command word, and perform ΣΔ modulation on the doubled frequency command word to generate the first a quantization error, and the first quantization error is halved to output the quantization error to the multiplier. The phase locked loop of claim 9, wherein voltage controlled oscillator clock duty cycle error correction is performed on the quantization error before the multiplier. A method for fractional N-type frequency synthesis using a phase locked loop (PLL), the method comprising: detecting a clock and a feedback clock (CLKFB) through a phase detector (PD) of the phase locked loop The phase difference between them; the low-pass loop filter of the phase-locked loop determines the control voltage based on the phase difference; the voltage-controlled oscillator (VCO) of the phase-locked loop determines the control voltage based on the control voltage. Generate a periodic signal; generate a frequency division sequence ratio and a selection control signal based on the frequency command word through the ΣΔ modulator (SDM) of the phase locked loop; and use the multi-mode frequency divider (MMDIV) based on the The frequency dividing sequence is compared to the period differential input of signals to generate a first feedback clock and a second feedback clock; and based on the selection control signal, one of the first feedback clock and the second feedback clock is used as the feedback clock Pulses are output from the multi-mode frequency divider to the phase detector. The method of claim 11, wherein the clock is a reference clock (CLKREF). The method of claim 11, wherein the rising edge of the second feedback clock is delayed from the rising edge of the first feedback clock by half of the period of the voltage controlled oscillator. The method of claim 11, wherein detecting the phase difference includes generating, by a phase frequency detector (PFD), a signal proportional to the phase difference between the clock and the feedback clock. a signal; and providing a sink current and a source current to the low-pass loop filter based on the signal by a charge pump. The method of claim 11, wherein generating the first feedback clock and the second feedback clock includes: using a first flip-flop of the multi-mode frequency divider based on a third of the periodic signal. A differential input and clock signal are used to generate the first feedback clock, the clock signal is generated using the differential input and the frequency division sequence ratio; and by the second positive frequency of the multi-mode frequency divider The inverter generates the second feedback clock based on the second differential input of the periodic signal and the clock signal. The method of claim 11, wherein outputting one of the first feedback clock and the second feedback clock as the feedback clock includes: multiplexing by the multi-mode frequency divider The device selects based on the selection control signal The one of the first feedback clock and the second feedback clock serves as the feedback clock. The method of claim 11, wherein generating the frequency division sequence ratio includes: doubling the frequency command characters; performing ΣΔ modulation on the doubled frequency command characters to generate a first frequency division sequence ratio; and halving the first frequency dividing sequence ratio to output the frequency dividing sequence ratio to the multi-mode frequency divider. The method of claim 17, further comprising adding a carry-out bit to the halved first divisor sequence ratio to generate the divisor sequence ratio. The method of claim 11, further comprising: generating a quantization error by the ΣΔ modulator, and combining the quantization error with a digital time converter (DTC) gain to generate a DTC control word; and A digital time converter clock (CLKDTC) is generated by a digital time converter based on a reference clock and the digital time converter control word as a clock input of the phase detector. The method of claim 19, wherein generating the quantization error includes: doubling the frequency command word; performing ΣΔ modulation on the doubled frequency command word to generate a first quantization error; and The first quantization error is halved to output the quantization error. The method of claim 20, further comprising performing voltage controlled oscillator clock duty cycle error correction on the quantization error before combining with the digital time converter gain. A multi-mode frequency divider (MMDIV) for a phase-locked loop (PLL) with fractional N-type frequency synthesis, the multi-mode frequency divider comprising: a frequency divider configured to The controlled oscillator (VCO) receives the differential input of the periodic signal, receives the frequency division sequence ratio from the ΣΔ modulator (SDM) of the phase-locked loop, and generates and outputs the clock signal; the first flip-flop is assembled A first differential input configured to receive the clock signal and the periodic signal and generate and output a first feedback clock (CLKFB); a second flip-flop configured to receive the clock signal and the periodic signal a second differential input of a periodic signal and generating and outputting a second feedback clock; and a multiplexer configured to receive the first feedback clock, the second feedback clock and the modulation from the ΣΔ modulation and based on the selection control signal, one of the first feedback clock and the second feedback clock is output as a feedback clock to the phase detector of the phase locked loop ( PD).