TWI833156B - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor memory device with simplified manufacturing steps and a manufacturing method thereof. The semiconductor memory device of the embodiment includes a first chip 40. The first chip 40 includes: a plurality of first conductive layers arranged at intervals in a first direction; and a first semiconductor layer on the plurality of first conductive layers. The inner layer extends along the first direction; a first insulating film between the first semiconductor layer and the plurality of first conductive layers; a second semiconductor layer 41 disposed on the plurality of first conductive layers The upper part is in contact with the first semiconductor layer; and the first electrode PD3a is arranged in contact with the upper part of the second semiconductor layer and includes a second wafer 50. The second wafer 50 includes: a second electrode PD4 , connected to the first electrode; and the second conductive layer 51 , connected to the second electrode.

Description

Semiconductor memory device and manufacturing method thereof

The embodiment relates to a semiconductor memory device and a manufacturing method thereof.

[Related applications]

This application enjoys the priority of the application based on Japanese Patent Application No. 2021-152185 (filing date: September 17, 2021). This application incorporates the entire content of the basic application by reference to the basic application.

There is known a Not-And (NAND) type flash memory in which memory cells are arranged in a three-dimensional shape.

Embodiments provide a semiconductor memory device with simplified manufacturing steps and a manufacturing method thereof.

The semiconductor memory device of the embodiment includes a first wafer. The first wafer includes: a plurality of first conductive layers arranged at intervals in a first direction; and a first semiconductor layer within the plurality of first conductive layers. extending along the first direction; a first insulating film between the first semiconductor layer and the plurality of first conductive layers; a second semiconductor layer disposed above the plurality of first conductive layers, and The first semiconductor layer is in contact with each other; and a first electrode is provided in contact with the top of the second semiconductor layer and includes a second wafer, the second wafer includes: a second electrode and the first electrode The electrodes are in contact with each other; and a second conductive layer is in contact with the second electrode.

The semiconductor memory device of the embodiment includes a plurality of cell wafers arranged in a first direction. The lowermost cell wafer among the plurality of cell wafers includes: a plurality of first conductive layers arranged at intervals. in the first direction; the first semiconductor layer extends along the first direction in the plurality of first conductive layers; the first semiconductor layer between the first semiconductor layer and the plurality of first conductive layers an insulating film; a second semiconductor layer connected to the first semiconductor layer above the plurality of first conductive layers; and a first electrode connected to the second semiconductor layer and connected to The cell wafer adjacent to the lowermost cell wafer among the plurality of cell wafers, and the uppermost cell wafer among the plurality of cell wafers includes: a second electrode connected to the A cell chip adjacent to the uppermost cell chip among the plurality of cell chips; a second conductive layer connected to the second electrode; a plurality of third conductive layers located on the second conductive layer The upper layers are arranged in the first direction with intervals; a third semiconductor layer extends along the first direction in the plurality of third conductive layers; the third semiconductor layer and the plurality of third conductive layers are a second insulating film between three conductive layers; a fourth semiconductor layer connected to the third semiconductor layer above the plurality of third conductive layers; and a fourth conductive layer connected to the fourth semiconductor layer layer.

The manufacturing method of the semiconductor memory device of the embodiment includes forming a laminate including a plurality of first conductive layers arranged at intervals in a first direction, The first semiconductor layer extending in the first direction, the first insulating film between the first semiconductor layer and the plurality of first conductive layers, and the second semiconductor layer connected to the first semiconductor layer; Formed with the stated A first electrode connected to two semiconductor layers to produce a first wafer including the laminate and the first electrode; forming a second conductive layer; forming a second electrode connected to the second conductive layer to A second wafer including the second conductive layer and the second electrode is manufactured; and the first wafer and the second wafer are connected in such a way that the first electrode and the second electrode are connected.

1: Semiconductor memory device

11: Memory cell array

12: Column decoder

13: Sense amplifier

14: Sequencer

2:Memory controller

3: Memory system

30: Peripheral circuit chip

31, 42, 42a, 42b, 43, 46, 54, 54a, 54b, 55, 58: Insulator

40: Cell chip/first chip

40x, 50x, 60: Cell chip

41: Conductor/second semiconductor layer

41a, 44, 51a, 51x, 52, 52a, 53, 53a, 56, 61, 62: conductor

451, 571: Core

452, 456, 572, 576: Semiconductors

453, 573: Tunneling oxide film

454, 574: Insulating film

455, 575: Block insulation film

50: Cell chip/second chip

51: Conductor/second conductive layer

ADD:Address information

ALE: address latch enable signal

BL, BL0, BL1, BL(m-1): bit lines

BLK, BLK0, BLK1…BLK(n-1): block

C0, C1, CX, C2, C3, CH, CC, VIa, VIb: contact plug

CLE: command latch enable signal

CMD: command

CU: Cell unit

D0, D1, DX, D2, D3: metal wiring layer

DAT: write data/read data/data/symbol

IC1, IC2, IC3, L0: Wiring

ILG1, ILG2, ILG3: metal wiring layer group

I/O: input/output signals, signals

MP1, MP2: memory column

MS1, MS2, MS3: laminated body

MT, MT0~MT7: memory cell transistor

NS:NAND string

PD1, PD2, PD3, PD3a, PD3b, PD3x, PD4, PD4x, PD5, PD6: conductor

PRC: peripheral circuit

RBn: ready busy signal

REn: Read enablement signal

SB1, SB2, SB3: Semiconductor substrate

SGD, SGS: select gate line

SL: source line

ST, ST1, ST2: select transistor

SU, SU0~SU3: string unit

Tr:MOS transistor/transistor

WEn: Write empowerment signal

WL: word line

FIG. 1 is a block diagram showing an example of the structure of the semiconductor memory device according to the first embodiment.

FIG. 2 is a diagram showing an example of the circuit structure of the memory cell array of the semiconductor memory device according to the first embodiment.

3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the first embodiment.

4 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor memory device according to the first embodiment.

5 is a cross-sectional view illustrating the structural details of two laminated bodies of the semiconductor memory device according to the first embodiment.

6 to 22 are cross-sectional views showing an example of a certain step of manufacturing the semiconductor memory device according to the first embodiment.

23 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the comparative example of the first embodiment.

FIG. 24 shows a semiconductor memory device according to a first modification of the first embodiment. A cross-sectional view of an example of a cross-sectional structure.

25 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the second modification of the first embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, common reference numerals are assigned to components having the same function and structure. When distinguishing a plurality of constituent elements having a common reference symbol, the common reference symbol is distinguished by adding a subscript. When there is no need to particularly distinguish a plurality of constituent elements, only a common reference symbol is attached to the plurality of constituent elements without adding a subscript.

Each functional block can be implemented by either hardware and software or a combination of both. In addition, each functional block does not necessarily need to be distinguished as explained below. For example, some functions may also be performed by functional blocks different from the illustrated functional blocks. Furthermore, the illustrated functional blocks can also be divided into more detailed functional sub-blocks. In addition, the names of each functional block and each component in the following description are for convenience only and do not limit the structure and operation of each functional block and each component.

<First Embodiment>

Hereinafter, the semiconductor memory device 1 according to the first embodiment will be described.

[Structure example]

(1) Semiconductor memory device

FIG. 1 is a block diagram showing an example of the structure of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner, and is controlled by an external memory controller 2 . The combination of the semiconductor memory device 1 and the memory controller 2 can constitute a memory system 3 as a semiconductor memory device. The memory system 3 is, for example, a memory card like a Secure Digital (SD) ^TM card or a solid state drive (SSD).

The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. In the communication between the semiconductor memory device 1 and the memory controller 2, for example, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the ready busy signal are used. Line signal RBn and input/output signal I/O.

The input/output signal I/O is, for example, an 8-bit signal, which may include command CMD, address information ADD, data DAT, etc. In the following description, both writing data and reading data will be described with the reference symbol DAT. The semiconductor memory device 1 receives the command CMD, the address information ADD and the write data DAT from the memory controller 2 via the input/output signal I/O.

The command latch enable signal CLE is used to notify the semiconductor memory device 1 of the period of time when the command CMD is sent via the signal I/O. The address latch enable signal ALE is used to notify the semiconductor memory device 1 of the period of sending the address information ADD via the signal I/O. The write enable signal WEn is used to enable input of signal I/O by the semiconductor memory device 1 . The read enable signal REn is used to enable the output of signal I/O by the semiconductor memory device 1 . The ready busy signal RBn is used to notify the memory controller 2 which of the ready state and the busy state the semiconductor memory device 1 is in. One. In the ready state, the semiconductor memory device 1 accepts instructions from the memory controller 2 . In the busy state, the semiconductor memory device 1 does not accept instructions from the memory controller 2 except for exceptions.

The semiconductor memory device 1 includes a memory cell array 11 and a peripheral circuit PRC. The peripheral circuit PRC includes a column decoder 12 , a sense amplifier 13 and a sequencer 14 .

The memory cell array 11 includes blocks BLK0 ~ BLK(n-1) (n is an integer greater than 1). The block BLK includes a plurality of non-volatile memory cells associated with bit lines and word lines, such as data erasure units.

The sequencer 14 controls the overall operation of the semiconductor memory device 1 based on the received command CMD. For example, the sequencer 14 controls the column decoder 12 and the sense amplifier 13 to perform various operations such as a write operation and a read operation. During the writing operation, the received writing data DAT is stored in the memory cell array 11 . In the read operation, the read data DAT is read from the memory cell array 11 .

Based on the received address information ADD, the column decoder 12 selects a certain block BLK as a target to perform various operations such as reading operations and writing operations. The column decoder 12 transmits voltages to the word lines of the selected block BLK.

The sense amplifier 13 performs the data DAT transmission operation between the memory controller 2 and the memory cell array 11 based on the received address information ADD. That is, the sense amplifier 13 holds the received write data DAT during the write operation, and applies a voltage to the bit line based on the write data DAT. In the readout operation, the sense amplifier 13 applies a voltage to the bit line to read out the data stored in the memory cell array 11. As the read data DAT, the read data DAT is output to the memory controller 2 .

(2) Memory cell array

FIG. 2 shows an example of the circuit structure of the memory cell array 11 of the semiconductor memory device 1 according to the first embodiment. As an example of the circuit structure of the memory cell array 11, an example of the circuit structure of a certain block BLK of the memory cell array 11 is shown. The other blocks BLK of the memory cell array 11 have, for example, the same circuit structure as that shown in FIG. 2 .

The block BLK includes, for example, four string units SU0~SU3. Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are corresponding to m bit lines BL0~BL(m-1) (m is an integer greater than 1) one by one. Each NAND string NS is connected to a corresponding bit line BL, including, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate (hereinafter also referred to as a gate) and a charge accumulation layer, and stores data in a non-volatile manner. The selection transistor ST1 and the selection transistor ST2 are respectively used for selecting the NAND string NS including the selection transistor ST1 and the selection transistor ST2 during various operations.

The drain of the selection transistor ST1 of each NAND string NS is connected to the bit line BL corresponding to the NAND string NS. The memory cell transistors MT0 to MT7 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The source of selection transistor ST2 is connected to source line SL.

Use integer j and integer k pairs to connect to each of the selection transistor ST1 and the selection transistor ST2, and the memory cell transistor MT0~memory cell transistor MT7. Gate wiring is explained. The following description is applicable to the case where j is an integer from 0 to 3, and when k is an integer from 0 to 7 in the example of FIG. 2 .

The gates of the select transistors ST1 of the NAND strings NS included in the string unit SUj are commonly connected to the select gate line SGDj. The gates of the selection transistors ST2 of the NAND strings NS included in the block BLK are commonly connected to the selection gate line SGS. The gates of the memory cell transistors MTk of the NAND strings NS included in the block BLK are commonly connected to the word line WLk.

Each bit line BL is connected to the drain electrode of the selection transistor ST1 of the corresponding NAND string NS included in each string unit SU of the block BLK. The source line SL is shared between the string units SU of the block BLK by being commonly connected to the sources of the selection transistors ST2 of the NAND strings NS included in the block BLK. The source line SL is shared among the blocks BLK by being connected similarly in different blocks BLK, for example.

A set of memory cell transistors MT in a string unit SU that are commonly connected to a word line WL is, for example, called a cell unit CU. For example, a set of co-located 1-bit data held by each of the memory cell transistors MT in the cell unit CU is called "1 page data." For example, when multi-bit data is held in each memory cell using a multi-level cell (MLC) method, multiple such "1-page data" can be held in one cell unit CU. .

The circuit structure of the memory cell array 11 has been described above, but the circuit structure of the memory cell array 11 is not limited to the structure described above. For example, The number of string units SU included in each block BLK can be designed to be any number. Furthermore, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The numbers of word lines WL, selection gate lines SGD and selection gate lines SGS are respectively changed based on the numbers of memory cell transistors MT, selection transistors ST1 and selection transistors ST2 in the NAND string NS.

(3) Structure of semiconductor memory device

The structure of the semiconductor memory device 1 of the first embodiment will be described with reference to the drawings. The structure shown in the drawings referred to below is only an example, and the structure of the semiconductor memory device 1 is not limited to the structure shown in the drawings. Referring to the diagram showing that object A and object B are connected, in the case where object B is disposed on the upper surface of object A, object A and object B are, for example, connected. However, unless it is explicitly mentioned that object A and object B are connected, There are no other objects between B, otherwise it does not rule out that there are other objects between object A and object B. Furthermore, when it is stated that the object C contains a certain element or compound, for example, the object C is substantially intended to contain the element or compound. The use of this expression is intended to allow for errors within the design limits.

FIG. 3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 1 according to the first embodiment.

The semiconductor memory device 1 has a structure in which the peripheral circuit wafer 30 , the cell wafer 40 and the cell wafer 50 are bonded together. The peripheral circuit chip 30 is provided with a peripheral circuit PRC. A part of the memory cell array 11 is provided on the cell chip 40 and the cell chip 50 respectively.

Hereinafter, for the purpose of easy reference, the direction is defined based on the semiconductor substrate SB1 included in the peripheral circuit chip 30 . Two directions parallel to a certain surface of the semiconductor substrate SB1, for example orthogonal to each other, are defined as the X direction and the Y direction. The direction that intersects this surface and forms peripheral circuit elements based on this surface is defined as the Z direction. The Z direction is described as orthogonal to the X direction and the Y direction, but it is not necessarily limited to this. In the following description, the Z direction is referred to as "up" and the direction opposite to the Z direction is referred to as "down". However, these expressions are only for convenience and have nothing to do with the direction of gravity, for example.

The peripheral circuit wafer 30 , the cell wafer 40 and the cell wafer 50 are arranged adjacent to each other in this order along the Z direction.

First, the structure of the peripheral circuit chip 30 will be described.

The semiconductor substrate SB1 included in the peripheral circuit chip 30 contains silicon (Si), for example. On the upper surface of the semiconductor substrate SB1, a plurality of metal oxide semiconductor (MOS) transistors Tr as peripheral circuit elements included in the peripheral circuit PRC are provided. Each transistor Tr includes a gate insulator on the upper surface of the semiconductor substrate SB1, a gate electrode on the upper surface of the gate insulator, and a pair of source/drain electrodes sandwiching a region below the gate insulator in the semiconductor substrate SB1. area.

A metal wiring layer D0, a metal wiring layer D1, a metal wiring layer DX, a metal wiring layer D2 and a metal wiring layer D3 are provided above the transistor Tr. Each metal wiring layer includes a plurality of mutually insulated wirings. Through this kind of wiring, each circuit can be The source, drain and gate of the crystal Tr are electrically connected to other components respectively. In FIG. 3 , the case where five metal wiring layers are provided has been described, but it is not necessarily limited to this.

Specifically, for example, a contact plug C0 is provided on the upper surface of the source/drain region of a certain transistor Tr. The upper surface of the contact plug C0 is in contact with a certain wiring in the metal wiring layer D0. For example, a contact plug C1 is provided on the upper surface of the wiring. The upper surface of the contact plug C1 is in contact with a certain wiring in the metal wiring layer D1. For example, a contact plug CX is provided on the upper surface of the wiring. The upper surface of this contact plug CX is in contact with a certain wiring in the metal wiring layer DX. For example, a contact plug C2 is provided on the upper surface of the wiring. The upper surface of the contact plug C2 is in contact with a certain wiring in the metal wiring layer D2. For example, a contact plug C3 is provided on the upper surface of the wiring. The upper surface of the contact plug C3 is in contact with a certain wiring in the metal wiring layer D3. Conductor PD1 is provided on the upper surface of this wiring. The conductor PD1 contains, for example, a metal material such as copper (Cu). The upper surface of the conductor PD1 constitutes a part of the upper surface of the peripheral circuit chip 30 and is located at substantially the same position in the Z direction as the upper surface of the peripheral circuit chip 30 . The conductor PD1 functions as an electrode pad for electrical connection with another chip. Hereinafter, the conductor provided on the upper surface of the peripheral circuit chip 30 and functioning as an electrode pad will be collectively referred to as conductor PD1. In the following description, the conductor functioning as an electrode pad in this manner is denoted by the symbol PD. In this specification, the contact plug C2 and the wiring in the metal wiring layer D2 are distinguished. However, the contact plug C2 and the wiring in the metal wiring layer D2 are integrated, for example. The same is true for the contact plug C3 and the wiring in the metal wiring layer D3. The combination of contact plugs and wiring in other parts can also be the same. way of integration.

The connection via the wiring in the metal wiring layer D0 , the metal wiring layer D1 , the metal wiring layer DX , the metal wiring layer D2 , and the metal wiring layer D3 described above is only an example. The peripheral circuit chip 30 is also provided with various contact plugs as described above; wiring in the metal wiring layer D0, the metal wiring layer D1, the metal wiring layer DX, the metal wiring layer D2, and the metal wiring layer D3; and Conductor PD1. In FIG. 3 , for ease of reference, such various contact plugs; wiring in metal wiring layers D0 , D1 , DX , D2 , and D3 ; and conductor PD1 are not necessarily shown. of all.

Between the semiconductor substrate SB1 and the upper surface of the peripheral circuit chip 30, there is no transistor Tr; various contact plugs; metal wiring layer D0, metal wiring layer D1, metal wiring layer DX, metal wiring layer D2 and metal wiring layer The wiring in D3 and the conductor PD1 are provided with an insulator 31 . The insulator 31 contains silicon oxide (SiO ₂ ), for example.

Next, the structure of the cell wafer 40 will be described. The cell chip 40 is disposed on the upper surface of the peripheral circuit chip 30 . The cell wafer 40 includes the stacked body MS1 functioning as a part of the memory cell array 11 . More specifically, each memory column included in the multilayer body MS1 functions as one NAND string NS, for example.

A plurality of conductors PD2 are provided on the lower surface of the cell chip 40 . More specifically, it is as follows. For each conductor PD1 of the peripheral circuit chip 30, a conductor PD2 is provided in contact with the upper surface of the conductor PD1. Therefore, the lower surface of the conductor PD2 constitutes a part of the lower surface of the cell wafer 40 and is located substantially the same position in the Z direction as the lower surface of the cell wafer 40 . The conductor PD2 contains, for example, a metal material such as copper (Cu). Hereinafter, the conductor provided on the lower surface of the cell wafer 40 and functioning as an electrode pad will be collectively referred to as conductor PD2.

The upper surface of a certain conductor PD2 is in contact with a certain wiring in the lowermost metal wiring layer of the metal wiring layer group ILG1, for example. This wiring is electrically connected to a certain wiring in the uppermost metal wiring layer of the metal wiring layer group ILG1 via wirings in other metal wiring layers of the metal wiring layer group ILG1. This wiring is, for example, electrically connected to a certain contact plug CH above the metal wiring layer group ILG1. In this way, the conductor PD2 is electrically connected to the contact plug CH. The upper surface of the contact plug CH is in contact with the lower end of one of the memory pillars of the multilayer body MS1. Among the wirings in the metal wiring layer group ILG1, the wirings electrically connected to the contact plugs CH in this way each function as a part of the bit line BL.

The other conductor PD2 is electrically connected to a certain contact plug above the metal wiring layer group ILG1 through the wiring in each wiring layer of the metal wiring layer group ILG1 in the same manner as the conductor PD2 electrically connected to the contact plug CH. Stuff CC. The upper surface of this contact plug CC is in contact with the lower surface of a certain conductive layer in the laminated body MS1. In FIG. 3 , for ease of reference, only two connection relationships from the conductor PD2 to the contact plug CC are shown. Among the wirings in the metal wiring layer group ILG1, the wirings electrically connected to the contact plugs CC function as part of the word line WL and any one of the selection gate line SGD and the selection gate line SGS respectively.

The conductor 41 is provided on the upper surface of the laminated body MS1. The conductor 41 includes a semiconductor, for example, and includes polycrystalline silicon (Si). Conductor 41 serves as source line SL part of the function. In the example of FIG. 3 , two conductors 41 are arranged at intervals. This interval allows, for example, plane division.

Conductor PD3a is provided on the upper surface of conductor 41. The conductor PD3a contains, for example, a metal material such as copper (Cu). The upper surface of the conductor PD3 a forms part of the upper surface of the cell wafer 40 and is located at substantially the same position in the Z direction as the upper surface of the cell wafer 40 . It has been described that the conductor PD3a is provided on the upper surface of the conductor 41, but the present embodiment is not limited to this. For example, other conductors may also be provided between the conductor 41 and the conductor PD3a. In this case, for example, it can be considered that the combination of the conductor PD3a and the other conductor functions as an electrode pad. The same is true for other conductors PD.

Furthermore, the other conductor PD2 is electrically connected to another contact plug CC above the metal wiring layer group ILG1 through the wiring in each wiring layer of the metal wiring layer group ILG1. This contact plug CC is located at a position not overlapping the laminated body MS1 when viewed from above. The upper surface of this contact plug CC is located at substantially the same position in the Z direction as the upper surface of the laminated body MS1. Conductor PD3b is provided on the upper surface of contact plug CC. The conductor PD3b contains, for example, a metal material such as copper (Cu). The upper surface of the conductor PD3 b constitutes a part of the upper surface of the cell wafer 40 and is located at substantially the same position in the Z direction as the upper surface of the cell wafer 40 .

Hereinafter, conductors such as conductor PD3 a and conductor PD3 b that are provided on the upper surface of cell wafer 40 and function as electrode pads are collectively referred to as conductor PD3 . As described above, each of the conductors PD3 includes, for example, a metal material such as copper (Cu).

Between the lower surface and the upper surface of the cell wafer 40, the conductor PD2, the wiring in each wiring layer of the metal wiring layer group ILG1, various contact plugs, the laminated body MS1, the conductor 41, and the conductor are not provided The PD3 part is provided with an insulator 42 . The insulator 42 includes silicon oxide (SiO ₂ ), for example.

Next, the structure of the cell wafer 50 will be described. The cell wafer 50 is disposed on the upper surface of the cell wafer 40 . The cell wafer 50 includes the laminated body MS2 which functions as a part of the memory cell array 11 like the laminated body MS1.

A plurality of conductors PD4 are provided on the lower surface of the cell chip 50 . More specifically, it is as follows. For each conductor PD3 of the cell wafer 40, a conductor PD4 is provided in contact with the upper surface of the conductor PD3. Therefore, the lower surface of the conductor PD4 constitutes a part of the lower surface of the cell wafer 50 and is located at substantially the same position in the Z direction as the lower surface of the cell wafer 50 . The conductor PD4 contains, for example, a metal material such as copper (Cu). Hereinafter, the conductor provided on the lower surface of the cell wafer 50 and functioning as an electrode pad will be collectively referred to as conductor PD4. As described above, each of the conductors PD4 includes, for example, a metal material such as copper (Cu).

Conductors 51 are provided on the upper surfaces of the plurality of conductors PD4. The conductor 51 expands in a planar shape parallel to the X direction and the Y direction, for example. The conductor 51 contains copper (Cu), for example. The conductor 51 functions as a part of the source line SL. In this specification, it is explained that the conductor 51 includes, for example, copper (Cu), but the conductor 51 may also include, for example, aluminum (Al).

A metal wiring layer group ILG2 is provided above the conductor 51 .

For example, a certain wire in the metal wiring layer group ILG2 is electrically connected to a certain contact plug CH above the metal wiring layer group ILG2. The contact plug CH is on The surface is in contact with the lower end of one of the memory columns of the multilayer body MS2. Among the wirings in the metal wiring layer group ILG2, the wirings electrically connected to the contact plugs CH in this way each function as a part of the bit line BL.

For example, a certain wire in the metal wiring layer group ILG2 is electrically connected to a certain contact plug CC above the metal wiring layer group ILG2. The upper surface of this contact plug CC is in contact with the lower surface of a certain conductive layer in the laminated body MS2. In Figure 3, for ease of reference, only two such contact plugs CC are shown. Among the wirings in the metal wiring layer group ILG2, the wirings electrically connected to the contact plugs CC function as part of the word line WL and any one of the selection gate line SGD and the selection gate line SGS.

The conductor 51 passes through a certain contact plug VIb provided on the upper surface of the conductor 51, a certain wiring L0 provided on the upper surface of the contact plug VIb, and a certain wiring L0 provided on the upper surface of the wiring L0. A contact plug VIa is, for example, electrically connected to a certain wiring in the lowermost metal wiring layer of the metal wiring layer group ILG2. This wiring is electrically connected to a certain wiring in the uppermost metal wiring layer of the metal wiring layer group ILG2 via wirings in other metal wiring layers of the metal wiring layer group ILG2. This wiring is, for example, electrically connected to another contact plug CC above the metal wiring layer group ILG2. In this way, the conductor 51 is electrically connected to the contact plug CC. This contact plug CC is located at a position not overlapping the laminated body MS2 when viewed from above. The upper surface of this contact plug CC is located at substantially the same position in the Z direction as the upper surface of the laminated body MS2.

The conductor 52 is provided on the upper surface of the laminated body MS2. Conductor 52 For example, it includes semiconductors and includes polycrystalline silicon (Si). The conductor 52 functions as a part of the source line SL. In the example of FIG. 3 , two conductors 52 are arranged at intervals. This interval allows, for example, plane division.

An electrical conductor 53 is provided on the upper surface of the electrical conductor 52 and on the upper surface of the contact plug CC electrically connected to the electrical conductor 51 . For example, the conductor 53 extends in a planar shape parallel to the X direction and the Y direction in a region overlapping the conductor 52 when viewed from above. The conductor 53 contains aluminum (Al), for example. The conductor 53 functions as a part of the source line SL, for example.

The upper surface of the cell wafer 50 is located above the upper end of the conductor 53 . Between the lower surface and the upper surface of the cell wafer 50, the wiring in each wiring layer in which the conductor PD4, the conductor 51, the wiring L0, the metal wiring layer group ILG2 are not provided, various contact plugs, the multilayer body MS2, An insulator 54 is provided in the conductor 52 and conductor 53 portions. The insulator 54 contains silicon oxide (SiO ₂ ), for example.

In the structure described above, the planar metal wiring that functions as a part of the source line SL does not exist in the cell wafer 40 but exists in the cell wafer 50 . Specifically, the conductor 51 and the conductor 53 are present in the cell wafer 50 .

In the structure described above, the peripheral circuit chip 30, the cell chip 40, and the cell chip 50 are connected through the electrode pads, and each wiring that functions as a part of the source line SL is electrically connected to the peripheral circuit chip. 30 transistor Tr. Furthermore, wirings functioning as part of the bit lines BL, the word lines WL, the select gate lines SGD and the select gate lines SGS are also electrically connected to the peripheral circuit chip 30 The transistor Tr.

FIG. 4 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor memory device 1 according to the first embodiment. In FIG. 4 , for easy reference, a part of the cross-sectional view shown in FIG. 3 is also displayed in an array.

The description will be given focusing on a certain contact plug CC provided on the cell wafer 40 . The upper surface of this contact plug CC is located at substantially the same position in the Z direction as the upper surface of the laminated body MS1. A certain electrical conductor PD3 is provided on the upper surface of the contact plug CC.

Next, the structure provided in the cell chip 50 and electrically connected to the contact plug CC will be described.

A conductor PD4 is provided on the lower surface of the cell wafer 50 so as to be in contact with the upper surface of the conductor PD3. The conductor 51a is provided on the upper surface of the conductor PD4. The conductor 51 a is provided on the same metal wiring layer as the conductor 51 , and includes, for example, copper (Cu) like the conductor 51 . The conductor 51a passes through a certain contact plug VIb provided on the upper surface of the conductor 51a, a certain wiring L0 provided on the upper surface of the contact plug VIb, and a certain wiring L0 provided on the upper surface of the wiring L0. The contact plug VIa and the wiring in each wiring layer of the metal wiring layer group ILG2 are electrically connected to a certain contact plug CC above the metal wiring layer group ILG2. The upper surface of this contact plug CC is located at substantially the same position in the Z direction as the upper surface of the laminated body MS2.

A conductor 53a is provided on the upper surface of the contact plug CC. Like the conductor 53, the conductor 53a contains aluminum (Al), for example.

The upper surface of the cell wafer 50 is located above the upper end of the conductor 53 a, but a part of the conductor 53 a is exposed on the upper surface of the cell wafer 50 . This portion functions, for example, as a pad (IO pad) for transmitting input/output signals of the semiconductor memory device 1 or as a pad (power pad) for supplying power voltage to the semiconductor memory device 1 .

In the structure described above, the peripheral circuit chip 30 , the cell chip 40 and the cell chip 50 are connected through electrode pads, and the IO pad and the power pad are electrically connected to the transistor Tr of the peripheral circuit chip 30 respectively. .

FIG. 5 is a cross-sectional view for explaining the details of the structures of the laminated body MS1 and the laminated body MS2 of the semiconductor memory device 1 according to the first embodiment. FIG. 5 shows a cross-sectional view of a cross section parallel to the cross section shown in FIG. 3 .

First, the structure of the laminated body MS1 is demonstrated.

The laminated body MS1 includes a structure in which insulators 43 and conductors 44 are alternately laminated, and a memory pillar MP1 in the structure. The insulator 43 contains, for example, silicon oxide (SiO ₂ ). The conductor 44 contains, for example, tungsten (W).

In the example of FIG. 5 , the lamination of the insulator 43 and the conductor 44 in this order is repeated eight times from the top. The conductor 41 shown in FIG. 3 is provided on the upper surface of the uppermost insulator 43 . The conductor 44 functions as a part of the word line WL and any one of the select gate line SGD and the select gate line SGS. For each conductor 44, the conductor 44 forms a group with an insulator 43 on the upper surface of the conductor 44. Each group is regarded as one step, and the conductor 44 and the insulator 43 have a stepped shape. In this stepped shape, when viewed from below When viewed, the lower surface of each group of conductors 44 has an area that does not overlap with the group below the group. The contact plug CC described with reference to FIG. 3 is in contact with this area.

The memory pillar MP1 is provided in the laminate of the insulator 43 and the conductor 44 . The memory pillar MP1 extends in the Z direction, for example. The upper end of the memory column MP1 reaches the conductor 41 , and the lower end of the memory column MP1 is located below the lowermost conductor 44 .

The memory pillar MP1 includes, for example, a core 451, a semiconductor 452, a tunnel oxide film 453, an insulating film 454, a block insulating film 455, and a semiconductor 456. Specifically, it is as follows. The upper end of the columnar core 451 is located above the upper surface of the uppermost conductor 44 , and the lower end of the core 451 is located below the lower surface of the lowermost conductor 44 . The side surfaces and upper surface of core 451 are covered with semiconductor 452 . The upper end of the semiconductor 452 is in contact with the conductor 41 . For example, the semiconductor 456 is provided in contact with the core 451 and the lower end of the semiconductor 452 . For example, the tunnel oxide film 453, the insulating film 454, and the block insulating film 455 are sequentially disposed on the side surfaces of the semiconductor 452 and the semiconductor 456 in this order. Semiconductor 452 and semiconductor 456 include silicon (Si), for example. The core portion 451, the tunnel oxide film 453, and the block insulating film 455 each include silicon oxide (SiO ₂ ), for example. The insulating film 454 contains, for example, silicon nitride (SiN), and functions as a charge storage film.

Portions of the memory pillar MP1 that intersect with the conductor 44 function as either the memory cell transistor MT or the selection transistor ST.

The contact plug CH shown in FIG. 3 is in contact with the lower end of the memory pillar MP1.

Next, the structure of the laminated body MS2 is demonstrated.

About the laminated body MS2, the same description as the description about the said laminated body MS1 holds. More specifically, in the description of the laminated body MS1, the conductor 41 is replaced with the conductor 52, the insulator 43 is replaced with the insulator 55, the conductor 44 is replaced with the conductor 56, and the memory pillar MP1 is replaced. The instructions for memory column MP2 hold. In the replacement from the memory pillar MP1 to the memory pillar MP2, the core 451 is replaced by the core 571, the semiconductor 452 is replaced by the semiconductor 572, the tunnel oxide film 453 is replaced by the tunnel oxide film 573, and the insulating film is replaced. 454 is replaced with an insulating film 574 , the block insulating film 455 is replaced with a block insulating film 575 , and the semiconductor 456 is replaced with a semiconductor 576 .

Next, description will be given focusing on a certain contact plug CC in contact with a certain conductor 44 of the laminated body MS1.

This contact plug CC is connected to a certain wiring IC1 in the metal wiring layer group ILG1, for example. Wiring IC1 extends in the X direction, for example. For example, the wiring IC1 is connected to another contact plug CC (indicated by a dotted line in FIG. 5 ) above the metal wiring layer group ILG1 in the direction opposite to the X direction from the cross section shown in FIG. 5 . A certain electrical conductor PD3 is provided on the upper surface of the contact plug CC.

A certain electrical conductor PD4 is provided in contact with the upper surface of the electrical conductor PD3. The upper surface of the conductor PD4 is connected to a certain wiring IC2 in a certain metal wiring layer of the metal wiring layer group ILG2, for example. The wiring IC2 is electrically connected to a certain wiring IC3 extending in the X direction, for example, in another metal wiring layer of the metal wiring layer group ILG2 in the direction opposite to the X direction from the cross section shown in FIG. 5 . The wiring IC3 is connected to a certain contact plug CC above the metal wiring layer group ILG2, for example. As described above, this contact plug CC is in contact with one of the conductors 56 of the multilayer body MS2.

In this way, a certain conductor 44 of the laminated body MS1 is electrically connected to a certain conductor 56 of the laminated body MS2. The conductor 44 and the conductor 56 function as a part of the same word line WL, for example.

The above has been described focusing on the contact plug CC that is in contact with one conductor 44 of the multilayer body MS1. However, the same applies to the contact plugs CC that are in contact with the other conductors 44 respectively.

[Manufacturing method]

6 to 22 are cross-sectional views sequentially showing the steps of manufacturing the semiconductor memory device 1 according to the first embodiment.

First, the peripheral circuit wafer 30 shown in FIG. 6 is manufactured.

Next, the structure shown in Fig. 7 is manufactured. Specifically, it is as follows.

Insulator 46 is formed on the upper surface of semiconductor substrate SB2. The semiconductor substrate SB2 contains silicon (Si), for example. The insulator 46 contains silicon oxide (SiO ₂ ), for example. Conductor 41a is formed on the upper surface of insulator 46. The conductor 41a includes a semiconductor, for example, and includes polycrystalline silicon (Si).

A structure corresponding to the laminated body MS1 shown in FIG. 5 is formed on the upper surface of the conductor 41a. More specifically, it is as follows.

The insulator 43 and the replacement member are alternately stacked on the upper surface of the conductor 41a. The replacement member includes silicon nitride (SiN), for example. Next, for example, through a photolithography step and etching, a stepped shape is formed in a structure in which the insulator 43 and the replacement member are alternately laminated. In this stepped shape, the upper surface of each replacement member has an area that does not overlap with the replacement member and the insulator 43 located above the replacement member. Next, the insulator 42a is formed above the uppermost replacement member. The insulator 42a contains silicon oxide (SiO ₂ ), for example.

Next, the memory pillar MP1 is formed in a structure in which the insulator 43 and the replacement member are alternately laminated. Next, the replacement member is selectively removed by wet etching through the slit, and the conductor 44 is formed in the space in which the replacement member has been removed.

The structure in which the insulator 43 and the conductor 44 are alternately laminated and the memory pillar MP1 thus formed correspond to the laminated body MS1 shown in FIG. 5 .

In the structure manufactured by the above steps, the contact plug CH is formed on the upper surface of each memory pillar MP1, and the contact plug CH on the upper surface of each conductor 44 is not connected to the conductor located above the conductor 44. A contact plug CC is formed in the area where the body 44 and the insulator 43 overlap. Furthermore, the contact plug CC is also formed on the conductor 41a.

Next, a metal wiring layer group ILG1 is formed above the various contact plugs. For example, the insulator 42a is formed above the metal wiring layer group ILG1, and the metal on the top of the metal wiring layer group ILG1 is processed by anisotropic etching and damascene processing such as reactive ion etching (RIE). A plurality of conductors PD2 are formed on the upper surface of the wiring in the wiring layer. The upper surface of the conductor PD2 is planarized, for example, by chemical mechanical polishing (CMP), so as to be located at substantially the same position in the Z direction as the upper surface of the insulator 42a. The conductor PD2 is electrically connected to any one of the various contact plugs formed in the above manner via the wiring in each wiring layer of the metal wiring layer group ILG1.

Then, as shown in Figure 8, the upper surface of the structure thus manufactured is fit to the The upper surface of the peripheral circuit chip 30 shown in 6. During this lamination, any one of the conductors PD2 of each of the conductors PD1 of the peripheral circuit chip 30 comes into contact with the upper surface of the conductor PD1. By this bonding, for example, the structure produced by the steps described with reference to FIG. 7 is turned upside down.

Next, as shown in FIG. 9 , the semiconductor substrate SB2 is removed by, for example, CMP.

Next, as shown in FIG. 10 , for example, an opening is provided in the insulator 46 by a photolithography step, and anisotropic etching such as an RIE method using the insulator 46 with the opening as a mask is used to divide the conductor 41 a into planes. is divided, and further, the portion of the conductor 41a that is in contact with the contact plug CC, for example, is removed. The divided and removed conductor 41a corresponds to the conductor 41 shown in FIG. 3 . The memory pillars MP1 that are in contact with the portions of the conductor 41a that have been removed by plane division respectively correspond to dummy pillars that do not include portions used as memory cell transistors MT. Furthermore, the division of the conductor 41a can be performed immediately following the formation of the conductor 41a described with reference to FIG. 7 .

Next, as shown in FIG. 11 , for example, an insulator is formed on the entire surface of the structure manufactured by the steps up to this point, and the structure after the insulator is formed is planarized by CMP until the upper surface of the conductor 41 is exposed. Then, an insulator is formed above the conductor 41 . In FIG. 11, the insulator thus formed is shown as insulator 42b. The insulator 42b contains silicon oxide (SiO ₂ ), for example.

Next, as shown in FIG. 12 , conductor PD3 a is formed on the upper surface of conductor 41 by anisotropic etching and damascene processing such as RIE method, and conductor PD3 a is formed on the upper surface of contact plug CC in contact with insulator 42 b. body PD3b. Conductor PD3a The upper surface of the conductor PD3b is planarized by, for example, CMP so as to be located at substantially the same position in the Z direction as the upper surface of the insulator 42b. In this way, conductor PD3 shown in FIGS. 3 to 5 is formed. The combination of the insulator 42a and the insulator 42b at this time point corresponds to the insulator 42 shown in FIG. 3 . Furthermore, the structure fabricated on the peripheral circuit wafer 30 in this way corresponds to the cell wafer 40 shown in FIG. 3 .

Next, the structure shown in Fig. 13 is produced.

Regarding the production of this structure, the same explanation as that described with reference to FIG. 7 up to the formation of the metal wiring layer group ILG1 holds. More specifically, in the explanation of FIG. 7 , the semiconductor substrate SB2 is replaced with the semiconductor substrate SB3, the insulator 46 is replaced with the insulator 58, the conductor 41a is replaced with the conductor 52a, and the laminated body MS1 is replaced with the laminated body MS2. , replace the memory pillar MP1 with the memory pillar MP2, replace the insulator 43 with the insulator 55, replace the conductor 44 with the conductor 56, replace the metal wiring layer group ILG1 with the metal wiring layer group ILG2, replace the insulator 42a with The description of the insulator 54a is established. In the structure thus manufactured, for example, the insulator 54 a is formed to substantially the same position as the upper surface of the wiring in the uppermost metal wiring layer of the metal wiring layer group ILG2 .

Next, the structure shown in Fig. 14 is manufactured. Specifically, it is as follows.

A certain contact plug VIa is formed on the upper surface of a certain wiring in the uppermost metal wiring layer of the metal wiring layer group ILG2, a certain wiring L0 is formed on the upper surface of the contact plug VIa, and a certain wiring L0 is formed on the upper surface of the contact plug VIa. A certain contact plug VIb is formed on the upper surface. In this way, various contact plugs and wiring L0 are formed. In the structure thus manufactured, for example, the insulator 54a is formed to be substantially the same as the upper surface of the contact plug VIb. Location. The contact plug VIb, the wiring L0 and the contact plug VIa are electrically connected to the contact plug CC formed on the conductor 52a via the wiring in each wiring layer of the metal wiring layer group ILG2.

Next, as shown in FIG. 15 , an insulator 54b is formed on the upper surface of the structure manufactured by the steps up to this point. The insulator 54b contains silicon oxide (SiO2), for example.

Next, as shown in FIG. 16 , a portion of the insulator 54 b that is in contact with the contact plug VIb is removed by anisotropic etching such as the RIE method.

Next, as shown in FIG. 17 , conductor 51 is formed in the space created by the removal by damascene processing. The upper surface of the conductor 51 is planarized by, for example, CMP so as to be located at substantially the same position in the Z direction as the upper surface of the insulator 54 b. In this damascene process, the conductor 51a shown in FIG. 4 is also formed.

Furthermore, the conductor 51 described using FIGS. 14 to 17 is formed by so-called single damascene processing, but the formation method of the conductor 51 is not limited to this. For example, the conductor 51 and the contact plug VIb can also be formed together by so-called dual damascene processing.

Next, as shown in FIG. 18 , an insulator 54b is formed on the upper surface of the structure manufactured by the steps up to this point.

Next, as shown in FIG. 19 , a plurality of conductors PD4 are formed on the upper surface of the conductor 51 by anisotropic etching and damascene processing such as the RIE method. The upper surface of the conductor PD4 is planarized by, for example, CMP so as to be located at substantially the same position in the Z direction as the upper surface of the insulator 54b. In this way, conductor PD4 shown in FIGS. 3 to 5 is formed.

Then, as shown in FIG. 20 , the upper surface of the structure thus manufactured is bonded to the upper surface of the cell wafer 40 shown in FIG. 12 . During this bonding, any one of the conductors PD4 of each of the conductors PD3 of the cell wafer 40 comes into contact with the upper surface of the conductor PD3. By this bonding, for example, the structure produced by the steps described with reference to FIGS. 13 to 19 is turned upside down.

Next, as shown in FIG. 21 , the semiconductor substrate SB3 is removed by, for example, CMP.

Next, as shown in FIG. 22 , for example, an opening is provided in the insulator 58 by a photolithography step, and anisotropic etching such as an RIE method using the insulator 58 with the opening as a mask is used to divide the conductor 52 a into planes. is divided, and further, a portion of the conductor 52a that is in contact with the contact plug CC is removed. The divided and removed conductor 52a corresponds to the conductor 52 shown in FIG. 3 . The memory pillars MP2 that are in contact with the portions of the conductor 52a that have been removed by plane division respectively correspond to dummy pillars that do not include portions used as memory cell transistors MT. Furthermore, the division of the conductor 52a can be performed immediately following the formation of the conductor 52a described with reference to FIG. 13 .

In the structure manufactured by the above steps, immediately after the removal of the insulator 58, for example, an insulator for electrically insulating the conductors 52 is formed, and then physical vapor deposition (PVD) such as sputtering is performed. method, the conductor 53 and the conductor 53a shown in FIGS. 3 and 4 are formed. Next, an insulator is formed above the upper surface of the conductor 53 . The insulator, the insulator 54a and the insulator 54b formed in this way correspond to the insulator 54 shown in FIGS. 3 and 4 . The structure thus fabricated on the cell wafer 40 is equivalent to the cell wafer 50 shown in FIG. 3 . So one Next, the semiconductor memory device 1 described with reference to FIGS. 3 to 5 is manufactured.

[Comparative example]

23 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the comparative example of the first embodiment.

This semiconductor memory device has a structure in which peripheral circuit wafer 30, cell wafer 40x, and cell wafer 50x are bonded together. The peripheral circuit chip 30 , the cell wafer 40 x , and the cell wafer 50 x are arranged adjacent to each other in this order along the Z direction.

The structure of the peripheral circuit chip 30 is as explained with reference to FIG. 3 .

Next, the structure of the cell wafer 40x will be described. This structure is a structure in which a structure corresponding to the conductor 51 of the cell wafer 50 of the example of FIG. 3 is provided in the structure of the cell wafer 40 of the example of FIG. 3 . More specifically, it is as follows.

Like the conductor 53 in the example of FIG. 3 , the conductor 51x is provided on the upper surface of the conductor 41 and the upper surface of the contact plug CC. The conductor 51x contains aluminum (Al). The conductor 51x functions as a part of the source line SL, for example.

Conductor PD3x is provided on the upper surface of conductor 51x. Conductor PD3x contains copper (Cu). The upper surface of the conductor PD3x constitutes a part of the upper surface of the cell wafer 40x, and is located at substantially the same position in the Z direction as the upper surface of the cell wafer 40x.

Next, the structure of the cell wafer 50x will be described. This structure is equivalent to the structure of the cell wafer 50 in the example of FIG. 3 excluding the conductor 51 .

A plurality of conductors PD4x are provided on the lower surface of the cell chip 50x. Even Specifically, for each of the conductors PD3x, the conductor PD4x is provided in contact with the upper surface of the conductor PD3x. The conductor PD4x contains, for example, a metal material such as copper (Cu).

[Effect]

In the manufacturing of the semiconductor memory device according to the comparative example of the first embodiment, the steps described below are performed immediately following the steps explained with reference to FIG. 10 . That is, for example, immediately after the insulator 46 is removed and the insulator for electrically insulating the conductors 41 is formed, a physical vapor deposition method such as sputtering is used to form an insulator on the upper surface of the conductor 41 and the exposed contact plug. A conductor 51x containing aluminum (Al) is formed on the upper surface of the plug CC. An insulator 42 is formed on the upper surface of the structure thus produced, and the upper surface after the insulator 42 is formed is planarized, for example, by CMP. Next, an insulator 42 is further formed on the planarized upper surface, and conductor PD3x including copper (Cu) is formed on the upper surface of conductor 51x by anisotropic etching and damascene processing such as the RIE method. The upper surface of the conductor PD3x is planarized by, for example, CMP.

Here, there is a large step difference on the upper surface of the conductor 51x formed by a physical vapor deposition method such as sputtering. Therefore, it is difficult to achieve the planarization immediately following the formation of the conductor 51x. If the outer peripheral portion of the planarized upper surface rolls off, the effective area available for the wafer may be reduced. Furthermore, when the conductor PD3x containing copper is formed on the conductor 51x containing aluminum, aluminum and copper may be alloyed.

In contrast, in the manufacturing of the semiconductor memory device 1 of the first embodiment, following the steps described with reference to FIG. 10 , as described with reference to FIGS. 11 and 12 , for example, damascene processing is performed on the conductor 41 Conductor PD3a is formed on the surface, And conductor PD3b is formed on the upper surface of contact plug CC. The upper surfaces of the conductors PD3a and PD3b are planarized by, for example, CMP. The conductor 51 having the same function as the conductor 51x is provided on the cell wafer 50 side as described with reference to FIGS. 15 to 17 . The conductor 51 contains copper (Cu), for example. As explained with reference to FIGS. 18 to 20 , the conductor 51 is electrically connected to the conductor 41 and the contact plug CC via the conductor PD3 and the conductor PD4.

In the manufacturing of the semiconductor memory device 1 of the first embodiment, by arranging the conductor 51 on the side of the cell wafer 50 instead of the conductor 51 change. The conductor 51 on the cell wafer 50 side is formed simply by adding a metal wiring layer to the upper surface of a structure with relatively few steps produced by the steps described with reference to FIG. 14 , which is relatively easy. That is, in the manufacturing of the semiconductor memory device 1 of the first embodiment, compared with the manufacturing of the semiconductor memory device of the comparative example, the number of CMPs is substantially reduced, and the process difficulty is reduced. When the conductor 51 includes copper (Cu), the alloying will not occur between the conductor 51 and the conductor PD4 in contact with the conductor 51 .

[Modification]

The structure of the semiconductor memory device 1 is not limited to the structure described with reference to FIGS. 3 to 5 . Another example will be described below. Hereinafter, differences from those described with reference to FIGS. 3 to 5 will be mainly described. According to the semiconductor memory device 1 of the modified example of the first embodiment described below, the same effects as those described above are also obtained.

FIG. 24 shows a semiconductor memory device according to a first modification of the first embodiment. A cross-sectional view of an example of the cross-sectional structure of Set 1.

This semiconductor memory device 1 has a structure in which peripheral circuit wafer 30 , cell wafer 40 , cell wafer 60 , and cell wafer 50 are bonded together. This structure is equivalent to the structure in which the cell wafer 60 is provided between the cell wafer 40 and the cell wafer 50 in the structure of the example of FIG. 3 . A part of the memory cell array 11 is also provided in the cell chip 60 .

The structures of the peripheral circuit chip 30, the cell chip 40, and the cell chip 50 are the same as those in the example of FIG. 3 .

The structure of the cell wafer 60 will be described. The cell wafer 60 is disposed on the upper surface of the cell wafer 40 . The cell wafer 60 includes the multilayer body MS3 that functions as a part of the memory cell array 11 like the multilayer body MS1 and the multilayer body MS2.

A plurality of conductors PD5 are provided on the lower surface of the cell chip 60 . Conductors 61 are provided on the upper surfaces of the plurality of conductors PD5. The conductor 61 expands in a planar shape parallel to the X direction and the Y direction, for example. The conductor 61 contains copper (Cu), for example. The conductor 61 functions as a part of the source line SL. The conductor PD5 and the conductor 61 have the same structure as the conductor PD4 and the conductor 51 of the cell wafer 50 .

The same structure as that of the cell chip 40 is provided above the conductor 61 . More specifically, metal wiring layer group ILG3, laminated body MS3, contact plugs CH and contact plugs CC, conductor 62 and conductor PD6 are provided. The conductor 62 and the conductor PD6 have the same structure as the conductor 41 and the conductor PD3 of the cell wafer 40 .

The cell wafer 50 is provided on the upper surface of the cell wafer 60 . Regarding each conductor PD6, any one of the conductors PD4 in the cell wafer 50 is in contact with the conductor PD6.

In the structure described above, the planar metal wiring that functions as a part of the source line SL does not exist in the cell wafer 40 but exists in the cell wafer 60 and the cell wafer 50 . Specifically, the conductor 61 is present in the cell wafer 60 , and the conductor 51 and the conductor 53 are present in the cell wafer 50 .

In the manufacturing of the semiconductor memory device 1 according to the first modification of the first embodiment, the conductor 61 and the conductor PD5 are formed in the same manner as described for the conductor 51 and the conductor PD4 of the cell wafer 50 , and the conductor 62 The conductor PD6 and the conductor PD6 are formed in the same manner as described for the conductor 41 and the conductor PD3 of the cell wafer 40 .

FIG. 25 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 1 according to the second modification of the first embodiment.

The semiconductor memory device 1 has a structure in which a peripheral circuit wafer 30 , a cell wafer 40 , a plurality of cell wafers 60 and a cell wafer 50 are bonded together. This structure is equivalent to a structure in which a plurality of cell wafers 60 are provided between the cell wafer 40 and the cell wafer 50 in the example of FIG. 24 .

In this structure, the planar metal wiring that functions as a part of the source line SL does not exist in the cell wafer 40 but exists in each cell wafer 60 and the cell wafer 50 . Specifically, the conductor 61 is present in each cell wafer 60 , and the conductor 51 and the conductor 53 are present in the cell wafer 50 .

<Other embodiments>

In this specification, the so-called "connection" refers to an electrical connection, for example, it does not exclude the passage of other components therebetween.

In this specification, the use of expressions such as the same, consistent, constant, and maintained is intended to include the case where there is an error within the design range when implementing the technology described in the embodiment. If "substantially" is the same, the same applies to the overlapping use of the term "substantially" in these expressions. In addition, the expression "applying or supplying a certain voltage" is intended to include both control to apply or supply the voltage and actual application or supply of the voltage. Furthermore, applying or supplying a certain voltage may also include applying or supplying a voltage of 0V, for example.

Several embodiments have been described above, but these embodiments are presented as examples only and are not intended to limit the scope of the invention. The embodiments of these new regulations can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope or gist of the invention, and are included in the invention described in the patent claims and their equivalent scope.

11: Memory cell array

30: Peripheral circuit chip

31, 42, 54: Insulator

40: Cell chip/first chip

50: Cell chip/second chip

41: Conductor/second semiconductor layer

51: Conductor/second conductive layer

52, 53: Conductor

C0, C1, CX, C2, C3, CH, CC, VIa, VIb: contact plug

D0, D1, DX, D2, D3: metal wiring layer

ILG1, ILG2: metal wiring layer group

L0: Wiring

MS1, MS2: laminated body

PD1, PD2, PD3, PD3b: conductor

PD3a: conductor/first electrode

PD4: conductor/second electrode

PRC: peripheral circuit

SB1: Semiconductor substrate

SL: source line

Tr: transistor

Claims (10)

A semiconductor memory device includes a first wafer and a second wafer, the first wafer includes: A plurality of first conductive layers arranged at intervals in the first direction; A first semiconductor layer extends along the first direction within the plurality of first conductive layers; a first insulating film between the first semiconductor layer and the plurality of first conductive layers; A second semiconductor layer is disposed above the plurality of first conductive layers and is in contact with the first semiconductor layer; and A first electrode is provided in contact with the top of the second semiconductor layer, The second wafer contains: a second electrode connected to the first electrode; and The second conductive layer is connected to the second electrode. The semiconductor memory device of claim 1, wherein the second conductive layer contains copper (Cu). The semiconductor memory device according to claim 1, wherein The second chip further includes: A plurality of third conductive layers arranged at intervals in the first direction; A third semiconductor layer extending along the first direction within the plurality of third conductive layers; a second insulating film between the third semiconductor layer and the plurality of third conductive layers; a fourth semiconductor layer connected to the third semiconductor layer; and A fourth conductive layer is connected to the fourth semiconductor layer. The semiconductor memory device of claim 3, wherein at least one of the second conductive layer and the fourth conductive layer contains aluminum (Al). The semiconductor memory device of claim 1, wherein the second conductive layer is used as a source line. The semiconductor memory device as claimed in claim 1 further includes: The third chip includes a transistor and a third electrode, The first wafer further includes a fourth electrode connected to the third electrode. The semiconductor memory device according to claim 1, wherein The second chip further includes a third electrode, The semiconductor memory device further includes a third chip, the third chip includes a fourth electrode connected to the third electrode, The second chip further includes: A plurality of third conductive layers arranged at intervals in the first direction; A third semiconductor layer extending along the first direction within the plurality of third conductive layers; a second insulating film between the third semiconductor layer and the plurality of third conductive layers; and a fourth semiconductor layer connected to the third semiconductor layer and the third electrode, The third wafer further includes a fourth conductive layer connected to the fourth electrode. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an NAND flash memory. A semiconductor memory device including a plurality of cell chips arranged in a first direction, The lowermost cell chip among the plurality of cell chips includes: A plurality of first conductive layers arranged at intervals in the first direction; A first semiconductor layer extends along the first direction within the plurality of first conductive layers; a first insulating film between the first semiconductor layer and the plurality of first conductive layers; A second semiconductor layer is in contact with the first semiconductor layer above the plurality of first conductive layers; and The first electrode is disposed in contact with the upper part of the second semiconductor layer and connected to the cell wafer adjacent to the lowermost cell wafer among the plurality of cell wafers, The uppermost cell chip among the plurality of cell chips includes: a second electrode connected to the cell chip adjacent to the uppermost cell chip among the plurality of cell chips; a second conductive layer connected to the second electrode; A plurality of third conductive layers are arranged in the first direction with intervals above the second conductive layer; A third semiconductor layer extending along the first direction within the plurality of third conductive layers; a second insulating film between the third semiconductor layer and the plurality of third conductive layers; a fourth semiconductor layer connected to the third semiconductor layer above the plurality of third conductive layers; and A fourth conductive layer is connected to the fourth semiconductor layer. A method of manufacturing a semiconductor memory device, including: Forming a laminate, the laminate including a plurality of first conductive layers spaced apart in a first direction, a first semiconductor layer extending along the first direction in the plurality of first conductive layers, a first insulating film between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer in contact with the first semiconductor layer; Forming a first electrode in contact with the second semiconductor layer to produce a first wafer including the laminate and the first electrode; forming a second conductive layer; Forming a second electrode connected to the second conductive layer to produce a second wafer including the second conductive layer and the second electrode; and The first wafer and the second wafer are connected in such a manner that the first electrode and the second electrode are in contact.