TWI833106B - Apparatus design for photoresist deposition - Google Patents

Abstract

In an embodiment, the a semiconductor processing tool is disclosed. In an embodiment, the semiconductor processing tool comprises a chamber, and a displaceable column that passes through a surface of the chamber. In an embodiment, the column comprises a base plate, an insulator layer over the base plate, a pedestal over the insulator layer, and an edge ring surrounding a perimeter of the ground plate, the insulator and the pedestal. In an embodiment, a fluidic path is provided between the edge ring and the pedestal.

Description

Equipment design for photoresist deposition

This application claims the benefit of U.S. Provisional Application No. 63/065,278, filed on August 13, 2020, the entire contents of which are hereby incorporated by reference.

Embodiments of the present disclosure are in the field of semiconductor processing, and particularly relate to processing tools for depositing photoresist onto a substrate in a vapor phase process.

Lithography has been used in the semiconductor industry for decades to create 2D and 3D patterns in microelectronic components. The lithography process involves the spin-on deposition of a film (photoresist), irradiating the film with a selected pattern by an energy source (exposure), and removing (etching) the exposed (positive tone) or Unexposed (negative toned) areas. Baking will be performed to drive out residual solvents.

The photoresist should be a radiation-sensitive material and, upon irradiation, undergo a chemical transformation in the exposed portion of the film, which achieves a solubility change between exposed and non-exposed areas. Using this change in solubility, exposed or unexposed areas of the photoresist are removed (etched away). The photoresist is now developed and the pattern can be transferred to the underlying film or substrate by etching. After pattern transfer, the remaining photoresist is removed and the process is repeated several times to obtain 2D and 3D structures to be used in microelectronic components.

There are several important characteristics in the lithography process. Such important properties include sensitivity, resolution, low line-edge roughness (LER), etch resistance and the ability to form thinner layers. When the sensitivity is higher, the energy required to change the solubility of the as-deposited film is lower. This enables greater efficiency in the lithography process. Resolution and LER determine how narrow features can be achieved through the lithography process. Pattern transfer requires higher etch-resistant materials to create deep structures. Higher etch-resistant materials also enable thinner films. Thinner films increase the efficiency of the lithography process.

Embodiments of the present disclosure include methods and apparatus for depositing photoresist on a substrate using a vapor phase process.

In one embodiment, a semiconductor processing tool is disclosed. In one embodiment, a semiconductor processing tool includes a chamber and a displaceable post extending through a surface of the chamber. In one embodiment, the post includes a base plate, an insulating layer on the base plate, a pedestal on the insulating layer, and an edge ring surrounding the perimeter of the ground plate, insulator, and pedestal. In one embodiment, a fluid path is provided between the edge ring and the base.

Embodiments may also include components for retaining substrates in semiconductor processing tools. In one embodiment, the assembly includes a base plate, an insulating layer on the base plate, a base on the insulating layer, an edge ring surrounding the perimeter of the base plate, the insulating layer, and the base, and extending from the bottom of the assembly to the top of the assembly. fluid path. In one embodiment, the fluid path passes through a first channel between the base plate and the insulating layer, through a second channel between the edge ring and the insulating layer, and through a third channel between the edge ring and the base .

Embodiments may also include a semiconductor processing tool that includes a chamber and a showerhead assembly that seals the chamber, wherein the showerhead assembly is electrically coupled to an RF source. In one embodiment, the processing tool also includes a displaceable post extending through the chamber opposite the showerhead assembly. In one embodiment, the post includes a base plate, an insulating layer on the base plate, a pedestal on the insulating layer, and an edge ring surrounding the perimeter of the ground plate, insulator, and pedestal. In one embodiment, a fluid path is provided between the edge ring and the base.

Processing tools for depositing photoresist onto substrates in a vapor phase process are described. In the following description, numerous specific details of processing tools for performing vapor deposition are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments illustrated in the drawings are illustrative representations and have not necessarily been drawn to scale.

To give context, photoresist systems used in extreme ultraviolet (EUV) lithography have inefficiencies. That is, existing photoresist material systems for EUV lithography require high dosages in order to provide the required solubility switching that allows development of the photoresist material. Organic-inorganic hybrid materials (eg, metal carbonyl oxygen material systems) have been proposed as material systems for EUV lithography due to increased sensitivity to EUV radiation. Such material systems typically include metals (eg, Sn, Hf, Zr, etc.), oxygen, and carbon. Organic-inorganic hybrid materials based on metal carbonyl oxides have also been shown to provide lower LER and higher resolution, properties necessary for forming narrow features.

Metallic carbonyl oxygen material systems are currently disposed on substrates using wet processes. The metal carbonyl oxygen material system is dissolved in a solvent and distributed on a substrate (eg, a wafer) using a wet chemical deposition process, such as a spin coating process. Wet chemical deposition of photoresists has several disadvantages. One disadvantage of wet chemical deposition is the generation of large amounts of wet by-products. Wet by-products are undesirable, and the semiconductor industry is actively working to reduce them as much as possible. Additionally, wet chemical deposition can lead to non-uniformity issues. For example, spin-on deposition can provide a photoresist layer with a non-uniform thickness or non-uniform distribution of metal carbonyl oxygen molecules. Additionally, metal carbonyl oxide photoresist material systems have been shown to decrease in thickness after exposure, which is troublesome during lithography processes. In addition, in the spin-coating process, the metal percentage in the photoresist is fixed and cannot be easily tuned.

Accordingly, embodiments of the present disclosure provide a processing tool that enables a vacuum deposition process for providing a photoresist layer on a wafer. The vacuum deposition process solves the above shortcomings of the wet deposition process. In particular, the vacuum deposition process provides the following advantages: 1) eliminates the generation of wet by-products; 2) provides a highly uniform photoresist layer; 3) resists thickness reduction after exposure; and 4) provides a tunable photoresist medium. Mechanism of metal percentage.

Embodiments disclosed herein include a processing tool that includes an architecture particularly suited for optimizing vapor deposition. For example, a processing tool may include a pedestal for supporting a temperature-controlled wafer. In some embodiments, the temperature of the base can be maintained between about -40°C and about 300°C. Additionally, edge purge flows and shadow rings may be provided around the perimeter of the pillars supporting the substrate. Edge purge flows and shadow rings prevent photoresist deposition along the edges or backside of the wafer. In one embodiment, the base may also provide any desired clamping structure, such as, but not limited to, vacuum clamping, monopolar clamping, or bipolar clamping, depending on how the processing tool is operated.

In some embodiments, the processing tool may be adapted for thermal vapor deposition processes (ie, without plasma). Such processes may include chemical vapor deposition (CVD) or atomic layer deposition (ALD). Alternatively, the processing tool may include a plasma source to enable plasma enhanced operations, such as plasma enhanced CVD (PE-CVD) or plasma enhanced ALD (PE-ALD). Furthermore, while the embodiments disclosed herein are particularly suitable for depositing metal carbonyl oxide photoresists for EUV patterning, it should be understood that the embodiments are not limited to such configurations. For example, the processing tools described herein may be adapted to deposit photoresist materials using vapor phase processes for any lithography protocol.

Referring now to FIG. 1 , a cross-sectional view of a processing tool 100 is illustrated in accordance with an embodiment. In one embodiment, processing tool 100 may include chamber 105 . Chamber 105 may be any suitable chamber capable of supporting sub-atmospheric pressure (eg, vacuum pressure). In one embodiment, an exhaust device (not shown) including a vacuum pump may be coupled to chamber 105 to provide sub-atmospheric pressure. In one embodiment, the lid may seal chamber 105. For example, the cover may include a spray head assembly 140 or the like. The showerhead assembly 140 may include fluid paths to enable process gas and/or inert gas to flow into the chamber 105 . In some embodiments where the processing tool 100 is suitable for plasma enhancement operation, the showerhead assembly 140 may be electrically coupled to the RF source and matching circuitry 150 . In yet another embodiment, tool 100 may be configured in an RF bottom feed architecture. That is, base 130 is connected to the RF source, and showerhead assembly 140 is grounded. In such embodiments, the filtering circuitry may still be connected to the base.

In one embodiment, displaceable posts for supporting wafer 101 are disposed in chamber 105 . In one embodiment, wafer 101 may be any substrate having a photoresist material deposited thereon. For example, wafer 101 may be a 300 mm wafer or a 450 mm wafer, although other wafer diameters may be used. Additionally, wafer 101 may be replaced with a substrate having a non-circular shape in some embodiments. The displaceable column may include a post 114 extending out of the chamber 105 . The column 114 may have ports to provide electrical and fluid paths from outside the chamber 105 to various components of the column.

In one embodiment, the column may include a base plate 110 . Base plate 110 may be grounded. As will be described in greater detail below, the base plate 110 may include fluid channels to allow inert gas flow to provide an edge purge flow.

In one embodiment, the insulating layer 115 is disposed on the base plate 110 . Insulating layer 115 may be any suitable dielectric material. For example, the insulating layer 115 may be a ceramic plate or the like. In one embodiment, the base 130 is disposed on the insulating layer 115 . Base 130 may comprise a single material, or base 130 may be formed from different materials. In one embodiment, base 130 may utilize any suitable clamping system to secure wafer 101 . For example, base 130 may be a vacuum chuck or a monopole chuck. In embodiments where plasma is not generated in chamber 105, base 130 may utilize a bipolar chuck architecture.

The base 130 may include a plurality of cooling channels 131 . Cooling channels 131 may be connected to fluid input and fluid output (not shown) through strut 114 . In one embodiment, cooling channels 131 allow the temperature of wafer 101 to be controlled during operation of processing tool 100 . For example, cooling channels 131 may allow the temperature of wafer 101 to be controlled between about -40°C and about 300°C. In one embodiment, the base 130 is connected to ground via filter circuitry 145, which enables DC and/or RF biasing of the base relative to the ground.

In one embodiment, the edge ring 120 surrounds the insulating layer 115 and the periphery of the base 130 . Edge ring 120 may be a dielectric material, such as ceramic. In one embodiment, edge ring 120 is supported by base plate 110 . Edge ring 120 may support shadow ring 135 . The inner diameter of shadow ring 135 is smaller than the diameter of wafer 101 . Thus, shadow ring 135 prevents photoresist from being deposited onto a portion of the outer edge of wafer 101 . A gap is provided between shadow ring 135 and wafer 101 . This gap prevents shadow ring 135 from contacting wafer 101 and provides an outlet for edge purge flow, which is described in more detail below.

Although shadow ring 135 provides some protection for the top surface and edges of wafer 101 , process gases may flow/diffuse downwardly along the path between edge ring 120 and wafer 101 . Accordingly, embodiments disclosed herein may include a fluid path between edge ring 120 and base 130 to achieve edge purge flow. Providing an inert gas in the fluid path increases the local pressure in the fluid path and prevents the process gas from reaching the edge of the wafer 101 . Therefore, photoresist is prevented from being deposited along the edges of the wafer 101 .

Referring now to FIG. 2 , an enlarged cross-sectional view of a portion of a post 260 within a processing tool is illustrated, according to an embodiment. In Figure 2, only the left edge of post 260 is illustrated. However, it should be understood that the right edge of post 260 may substantially mirror the left edge.

In an embodiment, post 260 may include base plate 210 . The insulation layer 215 may be provided on the base plate 210 . In one embodiment, the base 230 may include a first part _230A and a second part _230B . Cooling channels 231 may be provided in the second part _230B . First portion 230 _A may include features for clamping wafer 201 .

In one embodiment, edge ring 220 surrounds base plate 210 , insulation layer 215 , base 230 and wafer 201 . In one embodiment, edge ring 220 is spaced apart from other components of column 250 to provide a fluid path 212 from base plate 210 to the top side of column 260 . For example, fluid path 212 may exit the pillar between wafer 201 and shadow ring 235 . In certain embodiments, the inner surface of fluid path 212 includes edges of insulating layer 215 , edges of base 230 (ie, first portion 230 _A and second portion 230 _B ), and edges of wafer 201 . In one embodiment, the outer surface of fluid path 212 includes the inner edge of edge ring 220 . In one embodiment, the fluid path 212 may also continue on a portion of the top surface of the susceptor 230 as it proceeds to the edge of the wafer 201 . As such, when an inert gas (eg, helium, argon, etc.) flows through fluid path 212 , the process gas is prevented from flowing/diffusing downward along the sides of wafer 201 .

In one embodiment, the width W of the fluid path 212 is minimized to prevent plasma impingement along the fluid path 212 . For example, the width W of fluid path 212 may be about 1 mm or less. In one embodiment, seal 217 prevents fluid path 212 from exiting the bottom of column 260. A seal 217 may be located between the edge ring 220 and the base plate 210 . Seal 217 may be a flexible material, such as a gasket material or the like. In certain embodiments, seal 217 includes silicone.

In one embodiment, channels 211 are provided in base plate 210 . Channel 211 routes the inert gas from the center of column 260 to the inner edge of edge ring 220. It should be understood that only a portion of channel 211 is illustrated in Figure 2 . A more complete description of channel 211 is provided below with respect to Figure 4B.

In one embodiment, edge ring 220 and shadow ring 235 may have features suitable for aligning shadow ring 235 relative to wafer 201 . For example, notches 221 in the top surface of edge ring 220 may interface with protrusions 236 on the bottom surface of shadow ring 235 . The notches 221 and protrusions 236 may have tapered surfaces to allow for a rough alignment of the two components that is sufficient to provide a more precise alignment when the edge ring 220 comes into contact with the shadow ring 235 . In other embodiments, alignment features (not shown) may also be disposed between the base 230 and the edge ring 220 . Alignment features between base 230 and edge ring 220 may include tapered notches and protrusion structures similar to the alignment features between edge ring 220 and shadow ring 235 .

Referring now to Figures 3A and 3B, illustrated is a pair of cross-sectional views depicting portions of a processing tool with the base in different positions (in the Z-direction), in accordance with an embodiment. In Figure 3A, the base is located lower within the chamber. The position of the pedestal in Figure 3A is where the wafer is inserted into or removed from the chamber via the slit valve. In Figure 3B, the base is in a raised position within the chamber. The base position in Figure 3B is where the wafer is handled.

Referring now to Figure 3A, a cross-sectional view of the displaceable post 360 in a first position is illustrated, according to one embodiment. As shown in Figure 3A, the pillar includes a base plate 310, an insulating layer 315, a base 330 (ie, a first portion 330 _A and a second portion 330 _B ) and an edge ring 320. Such components may be substantially similar to the similarly named components described above. For example, cooling channels 331 may be provided in the second portion _330B of the base 330 , channels 311 may be provided in the base plate 310 , and seals 317 may be provided between the edge ring 320 and the base plate 310 .

As shown in Figure 3A, wafer 301 is placed on the top surface of susceptor 330. Wafer 301 may be inserted into the chamber through a slit valve (not shown). Additionally, shadow ring 335 is illustrated in a raised position above edge ring 320 . Because the inner diameter of shadow ring 335 is smaller than the diameter of wafer 301 , wafer 301 needs to be placed on the susceptor before shadow ring 335 comes into contact with edge ring 320 .

In one embodiment, shadow ring 335 is supported by chamber liner 370. Chamber liner 370 may surround the outer perimeter of post 360. In one embodiment, retainer 371 is located on the top surface of chamber liner 370. Retainer 371 is configured to retain shadow ring 335 in a raised position above edge ring 320 when post 360 is in the first position. In one embodiment, shadow ring 335 includes protrusions 336 for alignment with notches 321 in edge ring 320 .

Referring now to Figure 3B, a cross-sectional view of post 360 after engaging shadow ring 335 is illustrated, according to one embodiment. As shown, post 360 is displaced in the vertical direction (ie, the Z direction) until shadow ring 335 engages edge ring 320 . The additional vertical displacement of post 360 lifts shadow ring 335 from retainer 371 on chamber liner 370 . In one embodiment, shadow ring 335 is correctly aligned due to alignment features in shadow ring 335 and edge ring 320 (ie, notches 321 and protrusions 336). In other embodiments, alignment features (not shown) may also be disposed between the base 330 and the edge ring 320 . Alignment features between base 330 and edge ring 320 may include tapered notches and protrusion structures similar to the alignment features between edge ring 320 and shadow ring 335 .

While in the second position, wafer 301 may be processed. In particular, the process may include vapor deposition of photoresist material on the top surface of wafer 301 . For example, the process may be a CVD process, a PE-CVD process, an ALD process or a PE-ALD process. In certain embodiments, the photoresist is a metal carbonyl oxide photoresist suitable for EUV patterning. However, it should be understood that the photoresist can be any type of photoresist and the patterning can include any lithography scheme. During deposition of photoresist onto wafer 301 , an inert gas may flow along fluid channels between the inner surface of edge ring 310 and the outer surfaces of insulating layer 315 , susceptor 330 and wafer 301 . In this manner, photoresist deposition along the edges or backside of wafer 301 is substantially eliminated. In one embodiment, the temperature of the wafer 301 can be maintained between about -40°C and about 300°C by the cooling channel 331 in the second part of the base _330B . In other embodiments, the temperature of wafer 301 may be between about -40°C and about 200°C. In certain embodiments, the temperature of wafer 301 may be maintained at approximately 40°C.

Referring now to Figure 4A, a cross-sectional view of a processing tool 400 is illustrated in accordance with further embodiments. As shown in Figure 4A, the column includes a base plate 410. The base plate 410 may be supported by struts 414 extending out of the chamber. That is, in some embodiments, the base plate 410 and the posts 414 may be separate components rather than a single unitary part as shown in FIG. 1 . Pillar 414 may have a central channel for routing electrical connections and fluids (eg, cooling fluid and inert gas for purge flow).

In one embodiment, the insulating layer 415 is disposed on the base plate 410 , and the base 430 (ie, the first portion 430 _A and the second portion 430 _B ) is disposed on the insulating layer 415 . In one embodiment, coolant channels 431 are provided in the second portion _430B of the base 430. Wafer 401 is placed on susceptor 430 .

In one embodiment, edge ring 420 is disposed around base plate 410 , insulation layer 415 , base 430 and wafer 401 . Edge ring 420 may be coupled to base plate 410 by fastening mechanisms 413 (such as bolts, pins, screws, etc.). In one embodiment, seal 417 prevents purge gas from exiting the column at the bottom of the gap between base plate 410 and edge ring 420 .

In the illustrated embodiment, base 430 is in the first position. As such, shadow ring 435 is supported by retainer 471 and chamber liner 470 . When base 430 is displaced vertically, edge ring 420 will engage shadow ring 435 and lift shadow ring 435 away from retainer 471 .

Referring now to Figure 4B, a cross-sectional view of chamber 400 is illustrated in accordance with further embodiments. In the illustration of FIG. 4B , the insulating layer 415 and the base 430 are omitted so that the structure of the base plate 410 can be seen more clearly. As shown, the base plate 410 may include a plurality of channels 411 that provide fluid paths from the center of the base plate 410 to the edges of the base plate 410 . In the illustrated embodiment, a plurality of first channels connects the center of the base plate 410 to a first annular channel, and a plurality of second channels connects the first annular channel to the outer edge of the base plate 410 . In one embodiment, the first channel and the second channel are not aligned with each other. Although a specific configuration of channels 411 is illustrated in Figure 4B, it should be understood that any channel configuration may be used to route the inert gas from the center of the base plate 410 to the edges of the base plate 410.

Figure 5 illustrates a graphical representation of a machine in the form of an illustrative computer system 500 in which a set of instructions may be executed for causing the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine may be connected (eg, networked) to other machines in a local area network (LAN), intranet, extranet, or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment, or as a peer machine in a peer (or distributed) network environment. The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network equipment, server, network A router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specifies actions to be taken by that machine. Furthermore, although a single machine is illustrated, the term "machine" shall also be taken to include a machine that alone or jointly executes a set (or sets) of instructions to perform any one or more of the methodologies described herein ( For example, any collection of computers).

The exemplary computer system 500 includes a processor 502, a main memory 504 (eg, read-only memory (ROM), flash memory, dynamic random access memory (DRAM)), Such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 506 (for example, flash memory, static random access memory (static random access memory, SRAM), MRAM, etc.), and auxiliary memory 518 (eg, data storage device), which communicate with each other via bus 530 .

Processor 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processor 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (very long instruction word) , VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processor 502 can also be one or more special-purpose processing devices, such as application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (digital signal processor) signal processor (DSP), network processor, etc. Processor 502 is configured to execute processing logic 526 to perform the operations described herein.

Computer system 500 may also include a network interface device 508. The computer system 500 may also include a video display unit 510 (for example, a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), a letter Numeric input device 512 (eg, keyboard), cursor control device 514 (eg, mouse), and signal generation device 516 (eg, speaker).

Secondary memory 518 may include a machine-accessible storage medium (or, more specifically, a computer-readable storage medium) 532 having stored thereon a method embodying any one or more of the methods described herein. or one or more sets of instructions for functionality (e.g., software 522). During execution by computer system 500, software 522 may also reside fully or at least partially within main memory 504 and/or processor 502, which also constitute machine-readable storage media. Software 522 may also be sent or received over network 520 via network interface device 508.

Although machine-accessible storage medium 532 is illustrated in the illustrative embodiment as a single medium, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that stores one or more sets of instructions ( For example, centralized or distributed databases, and/or associated caches and servers). The term "machine-readable storage medium" shall also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. method. Accordingly, the term "machine-readable storage medium" should be understood to include, but not be limited to, solid-state memory and optical and magnetic media.

According to embodiments of the present disclosure, a machine-accessible storage medium has instructions stored thereon that cause a data processing system to perform a method of depositing photoresist on a wafer. In one embodiment, the method includes loading the wafer onto the susceptor via a slit valve in the chamber. The base is then lifted vertically. Raising the base causes the shadow ring to engage the edge ring surrounding the base. Photoresist can then be deposited on the wafer using a vapor phase process. During photoresist deposition, an edge purge flow is provided around the perimeter of the wafer to prevent photoresist from depositing on the edges or backside of the wafer.

Accordingly, methods have been disclosed for photoresist deposition using vapor phase processes with tools including shadow rings and edge purge flows.

100:Processing Tools 101:wafer 105: Chamber 110: Base plate 114:Pillar 115:Insulation layer 120: Edge ring 130:Pedestal 131: Cooling channel 135:Shadow Ring 140:Nozzle assembly 145: Filter circuit system 150: Matching circuit system 201:wafer 210: Base plate 211:Channel 212:Fluid path 215:Insulation layer 217:Seals 220: Edge ring 221: Notch 230A:Part 1 230B:Part 2 231: Cooling channel 235:Shadow Ring 236:Protrusion 260: column 301:wafer 310: Edge ring 311:Channel 315:Insulation layer 317:Seals 320: Edge ring 321: Notch 330:Pedestal 330A:Part 1 330B:Part 2 331: Cooling channel 335:Shadow Ring 336:Protrusion 360: column 370: Chamber liner 371:Retainer 400: Processing Tools 401:wafer 410: Base plate 411:Channel 413: Fastening mechanism 414: column 415:Insulation layer 417:Seals 420: Edge ring 430:Pedestal 430A:Part 1 430B:Part 2 431: Coolant channel 435:Shadow Ring 470: Chamber liner 471:Retainer 500:Computer system 502: Processor 504: Main memory 506: Static memory 508:Network interface device 510: Video display unit 512: Alphanumeric input device 514: Cursor control device 516: Signal generating device 518: Auxiliary memory 520:Internet 522:Software 526: Processing logic 530:Bus 532: The machine can access storage media W: Width

Figure 1 is a cross-sectional view of a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

Figure 2 is an enlarged view of an edge of a displaceable post in a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

Figure 3A is an enlarged view of an edge of a displaceable post in a processing tool according to an embodiment of the disclosure, with the hatched ring not engaging the edge ring.

Figure 3B is an enlarged view of an edge of a displaceable post in a processing tool in accordance with an embodiment of the present disclosure, with the hatched ring engaging the edge ring.

Figure 4A is a cross-sectional view of a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

Figure 4B is a cross-sectional view of a processing tool with the base removed to expose channels in the base plate, in accordance with an embodiment of the present disclosure.

Figure 5 illustrates a block diagram of an exemplary computer system in accordance with embodiments of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Processing Tools

101:wafer

105: Chamber

110: Base plate

114:Pillar

115:Insulation layer

120: Edge ring

130:Pedestal

131: Cooling channel

135:Shadow Ring

140:Nozzle assembly

145: Filter circuit system

150: Matching circuit system

Claims (20)

A semiconductor processing tool, including: a chamber; a displaceable column, the displaceable column passing through a surface of the chamber, wherein the displaceable column includes: a base plate; an insulating layer, the insulating layer on the base plate; a base on the insulating layer; and an edge ring surrounding the base plate, the insulating layer and a periphery of the base, wherein between the edge ring and the A fluid path is provided between the bases and is prevented from exiting a bottom of the displaceable column. The semiconductor processing tool of claim 1, further comprising: a shadow ring, the shadow ring being above the edge ring. The semiconductor processing tool of claim 2, wherein the shadow ring has a central protrusion interfaced with a central notch in the edge ring. The semiconductor processing tool of claim 1, wherein the base includes a plurality of channels, the plurality of channels are configured to circulate a coolant in the base, the coolant maintains a wafer temperature between about Between -40℃ and about 200℃. The semiconductor processing tool as described in claim 1, further comprising: Channels are disposed in a surface of the base plate, wherein the channels are fluidly coupled to the fluid path. The semiconductor processing tool of claim 1, further comprising: a gasket between the edge ring and the base plate. The semiconductor processing tool of claim 1, wherein a width of the fluid path is about 1 mm or less. The semiconductor processing tool of claim 1, wherein the base is a bipolar chuck, a unipolar chuck, or a vacuum chuck. The semiconductor processing tool of claim 1, further comprising: a nozzle assembly, the nozzle assembly being above the displaceable column. The semiconductor processing tool of claim 1, wherein the shower head assembly is electrically coupled to an RF source. The semiconductor processing tool of claim 1, wherein the base plate is grounded. The semiconductor processing tool of claim 11, wherein the base is coupled to an RF bias source and/or a DC bias source. An assembly for holding a substrate in a semiconductor processing tool, wherein the assembly includes: a base plate; an insulating layer above the base plate; a base above the insulating layer; an edge ring surrounding the base plate, the insulating layer and the base a periphery of the seat; and a fluid path from the bottom of the component to the top of the component, wherein the fluid path passes through a first channel between the base plate and the insulating layer, through the edge ring With a second channel between the insulating layer, and through a third channel between the edge ring and the base, the fluid path is prevented from exiting a bottom of the displaceable post. The component of claim 13, wherein a width of the second channel and a width of the third channel are about 1 mm or less. The assembly of claim 13, further comprising: a gasket between the base plate and the edge ring, wherein the gasket is exposed to a portion of the fluid path. The component of claim 13, further comprising: a shadow ring, the shadow ring being above the edge ring. The assembly of claim 16, wherein the shadow ring has a central protrusion that interfaces with a central notch in the edge ring. A semiconductor processing tool, including: a chamber; a showerhead assembly sealing the chamber, wherein the showerhead assembly is electrically coupled to an RF source; a displaceable column passing through the chamber And opposite to the nozzle assembly, the displaceable column includes: a base plate; an insulating layer, the insulating layer is on the base plate; a base on the insulating layer; and an edge ring surrounding the base plate, the insulating layer and a periphery of the base, wherein an edge ring is provided between the edge ring and the base A fluid path is prevented from exiting a bottom of the displaceable column. The semiconductor processing tool of claim 18, further comprising: a pad surrounding the edge ring; and a shadow ring. The semiconductor processing tool of claim 19, wherein the shadow ring is supported by the liner when the displaceable post is in a first position relative to the showerhead assembly, and wherein when the displaceable post is in a first position relative to the showerhead assembly The shadow ring is supported by the edge ring when the shower head assembly is in a second position, wherein the base is closer when the displaceable post is in the second position than when the displaceable post is in the first position. The sprinkler head assembly.