TWI833106B - Apparatus design for photoresist deposition - Google Patents

Apparatus design for photoresist deposition Download PDF

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Publication number
TWI833106B
TWI833106B TW110129398A TW110129398A TWI833106B TW I833106 B TWI833106 B TW I833106B TW 110129398 A TW110129398 A TW 110129398A TW 110129398 A TW110129398 A TW 110129398A TW I833106 B TWI833106 B TW I833106B
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base
base plate
processing tool
edge ring
semiconductor processing
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TW110129398A
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Chinese (zh)
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TW202212990A (en
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法札德 霍姆德
安納薩 沙布藍尼
勁文 陳
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美商應用材料股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4585Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4586Elements in the interior of the support, e.g. electrodes, heating or cooling devices
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45519Inert gas curtains
    • C23C16/45521Inert gas curtains the gas, other than thermal contact gas, being introduced the rear of the substrate to flow around its periphery
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor
    • G03F7/167Coating processes; Apparatus therefor from the gas phase, by plasma deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67109Apparatus for thermal treatment mainly by convection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67126Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68721Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins

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  • Chemical & Material Sciences (AREA)
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Abstract

In an embodiment, the a semiconductor processing tool is disclosed. In an embodiment, the semiconductor processing tool comprises a chamber, and a displaceable column that passes through a surface of the chamber. In an embodiment, the column comprises a base plate, an insulator layer over the base plate, a pedestal over the insulator layer, and an edge ring surrounding a perimeter of the ground plate, the insulator and the pedestal. In an embodiment, a fluidic path is provided between the edge ring and the pedestal.

Description

用於光阻沉積的設備設計Equipment design for photoresist deposition

本申請主張2020年8月13日提交的美國臨時申請第63/065,278號的權益,該美國臨時申請的全部內容據此以引用方式併入本文。This application claims the benefit of U.S. Provisional Application No. 63/065,278, filed on August 13, 2020, the entire contents of which are hereby incorporated by reference.

本揭示案的實施例屬於半導體處理領域,並且特定言之係關於用於以氣相製程將光阻劑沉積到基板上的處理工具。Embodiments of the present disclosure are in the field of semiconductor processing, and particularly relate to processing tools for depositing photoresist onto a substrate in a vapor phase process.

微影術已經在半導體行業中用於在微電子元件中創建2D及3D圖案達數十年。微影製程涉及膜(光阻劑)的旋塗沉積,藉由能量源(曝光)用選定的圖案照射膜,以及藉由溶於溶劑中移除(蝕刻)膜的經曝光(正色調)或未曝光(負色調)區域。將進行烘焙以驅除殘留的溶劑。Lithography has been used in the semiconductor industry for decades to create 2D and 3D patterns in microelectronic components. The lithography process involves the spin-on deposition of a film (photoresist), irradiating the film with a selected pattern by an energy source (exposure), and removing (etching) the exposed (positive tone) or Unexposed (negative toned) areas. Baking will be performed to drive out residual solvents.

光阻劑應為輻射敏感材料,並且在照射時,在膜的曝光部分中發生化學轉變,此實現了曝光區域與非曝光區域之間的溶解度變化。使用此種溶解度變化,光阻劑的曝光區域或非曝光區域被移除(蝕刻掉)。現在對光阻劑進行顯影,並且可以藉由蝕刻將圖案轉移至下層薄膜或基板。在圖案轉移之後,移除殘留的光阻劑,並且重複該製程多次可以得到要用於微電子元件中的2D及3D結構。The photoresist should be a radiation-sensitive material and, upon irradiation, undergo a chemical transformation in the exposed portion of the film, which achieves a solubility change between exposed and non-exposed areas. Using this change in solubility, exposed or unexposed areas of the photoresist are removed (etched away). The photoresist is now developed and the pattern can be transferred to the underlying film or substrate by etching. After pattern transfer, the remaining photoresist is removed and the process is repeated several times to obtain 2D and 3D structures to be used in microelectronic components.

微影製程中有幾個重要的特性。此類重要特性包括靈敏度、分辨率、較低的線邊緣粗糙度(line-edge roughness, LER)、抗蝕刻性及形成較薄層的能力。當靈敏度較高時,改變沉積態膜的溶解度所需的能量較低。此實現了微影製程中更高的效率。分辨率及LER確定了可以如何藉由微影製程實現窄特徵。圖案轉移需要更高的抗蝕刻材料來形成深結構。更高的抗蝕刻材料亦實現了更薄的膜。更薄的膜增加了微影製程的效率。There are several important characteristics in the lithography process. Such important properties include sensitivity, resolution, low line-edge roughness (LER), etch resistance and the ability to form thinner layers. When the sensitivity is higher, the energy required to change the solubility of the as-deposited film is lower. This enables greater efficiency in the lithography process. Resolution and LER determine how narrow features can be achieved through the lithography process. Pattern transfer requires higher etch-resistant materials to create deep structures. Higher etch-resistant materials also enable thinner films. Thinner films increase the efficiency of the lithography process.

本揭示案的實施例包括用於以氣相製程在基板上沉積光阻劑的方法及設備。Embodiments of the present disclosure include methods and apparatus for depositing photoresist on a substrate using a vapor phase process.

在一實施例中,揭示了一種半導體處理工具。在一實施例中,半導體處理工具包括腔室及穿過該腔室的表面的可移位柱。在一實施例中,該柱包括基底板、基底板上的絕緣層、絕緣層上的基座,以及圍繞接地板、絕緣體及基座的周邊的邊緣環。在一實施例中,在邊緣環與基座之間提供流體路徑。In one embodiment, a semiconductor processing tool is disclosed. In one embodiment, a semiconductor processing tool includes a chamber and a displaceable post extending through a surface of the chamber. In one embodiment, the post includes a base plate, an insulating layer on the base plate, a pedestal on the insulating layer, and an edge ring surrounding the perimeter of the ground plate, insulator, and pedestal. In one embodiment, a fluid path is provided between the edge ring and the base.

實施例亦可包括用於在半導體處理工具中保持基板的組件。在一實施例中,該組件包括基底板、基底板上的絕緣層、絕緣層上的基座,圍繞基底板、絕緣層及基座的周邊的邊緣環,以及從組件的底部至組件的頂部的流體路徑。在一實施例中,流體路徑穿過基底板與絕緣層之間的第一通道、穿過邊緣環與絕緣層之間的第二通道,並且穿過邊緣環與基座之間的第三通道。Embodiments may also include components for retaining substrates in semiconductor processing tools. In one embodiment, the assembly includes a base plate, an insulating layer on the base plate, a base on the insulating layer, an edge ring surrounding the perimeter of the base plate, the insulating layer, and the base, and extending from the bottom of the assembly to the top of the assembly. fluid path. In one embodiment, the fluid path passes through a first channel between the base plate and the insulating layer, through a second channel between the edge ring and the insulating layer, and through a third channel between the edge ring and the base .

實施例亦可包括一種半導體處理工具,該半導體處理工具包括腔室及密封腔室的噴頭組件,其中該噴頭組件電耦合至RF源。在一實施例中,處理工具亦包括可移位柱,該可移位柱穿過腔室並與噴頭組件相對。在一實施例中,該柱包括基底板、基底板上的絕緣層、絕緣層上的基座,以及圍繞接地板、絕緣體及基座的周邊的邊緣環。在一實施例中,在邊緣環與基座之間提供流體路徑。Embodiments may also include a semiconductor processing tool that includes a chamber and a showerhead assembly that seals the chamber, wherein the showerhead assembly is electrically coupled to an RF source. In one embodiment, the processing tool also includes a displaceable post extending through the chamber opposite the showerhead assembly. In one embodiment, the post includes a base plate, an insulating layer on the base plate, a pedestal on the insulating layer, and an edge ring surrounding the perimeter of the ground plate, insulator, and pedestal. In one embodiment, a fluid path is provided between the edge ring and the base.

描述了用於以氣相製程將光阻劑沉積到基板上的處理工具。在以下描述中,闡述了用於實施氣相沉積的處理工具的許多特定細節,以便提供對本揭示案的實施例的透徹理解。對於熟習此項技術者而言將顯而易見的是,本揭示案的實施例可以在沒有該等特定細節的情況下實踐。在其他情況下,為了不會不必要地模糊本揭示案的實施例,沒有詳細描述眾所周知的態樣,諸如積體電路製造。此外,應當理解的是,附圖中所示的各種實施例是說明性的表示,並且不一定按比例繪製。Processing tools for depositing photoresist onto substrates in a vapor phase process are described. In the following description, numerous specific details of processing tools for performing vapor deposition are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments illustrated in the drawings are illustrative representations and have not necessarily been drawn to scale.

為了提供情境,在極紫外(extreme ultraviolet, EUV)微影中使用的光阻劑系統具有低效率。亦即,用於EUV微影術的現有光阻劑材料系統需要高劑量,以便提供允許使光阻劑材料顯影的所需溶解度切換。有機-無機混合材料(例如,金屬羰氧材料系統)已由於增加的對EUV輻射的敏感性而被提議作為用於EUV微影術的材料系統。此類材料系統通常包含金屬(例如,Sn、Hf、Zr等)、氧及碳。基於金屬羰氧的有機-無機混合材料亦已被圖示為提供較低的LER及較高的分辨率,較低的LER及較高的分辨率是形成窄特徵所必需的特性。To give context, photoresist systems used in extreme ultraviolet (EUV) lithography have inefficiencies. That is, existing photoresist material systems for EUV lithography require high dosages in order to provide the required solubility switching that allows development of the photoresist material. Organic-inorganic hybrid materials (eg, metal carbonyl oxygen material systems) have been proposed as material systems for EUV lithography due to increased sensitivity to EUV radiation. Such material systems typically include metals (eg, Sn, Hf, Zr, etc.), oxygen, and carbon. Organic-inorganic hybrid materials based on metal carbonyl oxides have also been shown to provide lower LER and higher resolution, properties necessary for forming narrow features.

金屬羰氧材料系統目前使用濕法製程設置在基板上。使用濕法化學沉積製程,諸如旋塗製程,將金屬羰氧材料系統溶於溶劑中並分佈在基板(例如,晶圓)上。光阻劑的濕法化學沉積有幾個缺點。濕法化學沉積的一個不利態樣是生成了大量的濕副產物。濕副產物是非期望的,並且半導體行業正積極努力以儘可能減少濕副產物。此外,濕法化學沉積可能導致不均勻性問題。例如,旋塗沉積可以提供具有不均勻的厚度或不均勻的金屬羰氧分子分佈的光阻劑層。此外,已經表明金屬羰氧光阻劑材料系統在曝光後厚度減小,此在微影製程中是麻煩的。此外,在旋塗製程中,光阻劑中的金屬百分比是固定的,並且不容易調諧。Metallic carbonyl oxygen material systems are currently disposed on substrates using wet processes. The metal carbonyl oxygen material system is dissolved in a solvent and distributed on a substrate (eg, a wafer) using a wet chemical deposition process, such as a spin coating process. Wet chemical deposition of photoresists has several disadvantages. One disadvantage of wet chemical deposition is the generation of large amounts of wet by-products. Wet by-products are undesirable, and the semiconductor industry is actively working to reduce them as much as possible. Additionally, wet chemical deposition can lead to non-uniformity issues. For example, spin-on deposition can provide a photoresist layer with a non-uniform thickness or non-uniform distribution of metal carbonyl oxygen molecules. Additionally, metal carbonyl oxide photoresist material systems have been shown to decrease in thickness after exposure, which is troublesome during lithography processes. In addition, in the spin-coating process, the metal percentage in the photoresist is fixed and cannot be easily tuned.

因此,本揭示案的實施例提供了一種處理工具,該處理工具使得能夠進行用於在晶圓上提供光阻劑層的真空沉積製程。真空沉積製程解決了上述濕法沉積製程的缺點。特別地,真空沉積製程提供了以下優點:1)消除濕副產物的生成;2)提供高度均勻的光阻劑層;3)抵抗曝光後的厚度減小;及4)提供調諧光阻劑中的金屬百分比的機制。Accordingly, embodiments of the present disclosure provide a processing tool that enables a vacuum deposition process for providing a photoresist layer on a wafer. The vacuum deposition process solves the above shortcomings of the wet deposition process. In particular, the vacuum deposition process provides the following advantages: 1) eliminates the generation of wet by-products; 2) provides a highly uniform photoresist layer; 3) resists thickness reduction after exposure; and 4) provides a tunable photoresist medium. Mechanism of metal percentage.

本文所揭示的實施例包括一種處理工具,該處理工具包括特別適合於最佳化氣相沉積的架構。例如,處理工具可包括用於支撐溫控的晶圓的基座。在一些實施例中,基座的溫度可以保持在介於約-40℃與約300℃之間。另外,邊緣淨化流及陰影環可以設置為圍繞支撐基板的柱的周邊。邊緣淨化流及陰影環防止光阻劑沿著晶圓的邊緣或背面沉積。在一實施例中,取決於處理工具的操作方式,基座亦可以提供任何期望的卡緊架構,諸如但不限於真空卡緊、單極卡緊或雙極卡緊。Embodiments disclosed herein include a processing tool that includes an architecture particularly suited for optimizing vapor deposition. For example, a processing tool may include a pedestal for supporting a temperature-controlled wafer. In some embodiments, the temperature of the base can be maintained between about -40°C and about 300°C. Additionally, edge purge flows and shadow rings may be provided around the perimeter of the pillars supporting the substrate. Edge purge flows and shadow rings prevent photoresist deposition along the edges or backside of the wafer. In one embodiment, the base may also provide any desired clamping structure, such as, but not limited to, vacuum clamping, monopolar clamping, or bipolar clamping, depending on how the processing tool is operated.

在一些實施例中,處理工具可適用於熱氣相沉積製程(亦即,沒有電漿)。此類製程可包括化學氣相沉積(chemical vapor deposition, CVD)或原子層沉積(atomic layer deposition, ALD)。或者,處理工具可包括電漿源以實現電漿增強操作,諸如電漿增強CVD (plasma enhanced CVD, PE-CVD)或電漿增強ALD (plasma enhanced ALD, PE-ALD)。此外,儘管本文所揭示的實施例特別適用於沉積金屬羰氧光阻劑以供用於EUV圖案化,但是應當理解的是,實施例不限於此類配置。例如,本文所述的處理工具可適用於使用氣相製程沉積光阻劑材料以用於任何微影術方案。In some embodiments, the processing tool may be adapted for thermal vapor deposition processes (ie, without plasma). Such processes may include chemical vapor deposition (CVD) or atomic layer deposition (ALD). Alternatively, the processing tool may include a plasma source to enable plasma enhanced operations, such as plasma enhanced CVD (PE-CVD) or plasma enhanced ALD (PE-ALD). Furthermore, while the embodiments disclosed herein are particularly suitable for depositing metal carbonyl oxide photoresists for EUV patterning, it should be understood that the embodiments are not limited to such configurations. For example, the processing tools described herein may be adapted to deposit photoresist materials using vapor phase processes for any lithography protocol.

現在參考第1圖,圖示了根據一實施例的處理工具100的橫截面圖。在一實施例中,處理工具100可包括腔室105。腔室105可為能夠支持次大氣壓(例如,真空壓力)的任何合適的腔室。在一實施例中,包括真空泵的排氣裝置(未圖示)可以耦接至腔室105以提供次大氣壓。在一實施例中,蓋可密封腔室105。例如,蓋可包括噴頭組件140等。噴頭組件140可包括流體路徑,以使處理氣體及/或惰性氣體能夠流入腔室105。在處理工具100適於電漿增強操作的一些實施例中,噴頭組件140可以電耦合至RF源及匹配電路系統150。在又一個實施例中,工具100可以配置在RF底部饋電架構中。亦即,基座130連接至RF源,並且噴頭組件140接地。在此類實施例中,濾波電路系統仍可連接至基座。Referring now to FIG. 1 , a cross-sectional view of a processing tool 100 is illustrated in accordance with an embodiment. In one embodiment, processing tool 100 may include chamber 105 . Chamber 105 may be any suitable chamber capable of supporting sub-atmospheric pressure (eg, vacuum pressure). In one embodiment, an exhaust device (not shown) including a vacuum pump may be coupled to chamber 105 to provide sub-atmospheric pressure. In one embodiment, the lid may seal chamber 105. For example, the cover may include a spray head assembly 140 or the like. The showerhead assembly 140 may include fluid paths to enable process gas and/or inert gas to flow into the chamber 105 . In some embodiments where the processing tool 100 is suitable for plasma enhancement operation, the showerhead assembly 140 may be electrically coupled to the RF source and matching circuitry 150 . In yet another embodiment, tool 100 may be configured in an RF bottom feed architecture. That is, base 130 is connected to the RF source, and showerhead assembly 140 is grounded. In such embodiments, the filtering circuitry may still be connected to the base.

在一實施例中,用於支撐晶圓101的可移位柱設置在腔室105中。在一實施例中,晶圓101可為其上沉積有光阻劑材料的任何基板。例如,晶圓101可為300 mm晶圓或450 mm晶圓,但是亦可以使用其他的晶圓直徑。此外,在一些實施例中晶圓101可以用具有非圓形形狀的基板代替。可移位柱可包括延伸出腔室105的支柱114。支柱114可以具有埠以提供從腔室105外部至柱的各種部件的電氣及流體路徑。In one embodiment, displaceable posts for supporting wafer 101 are disposed in chamber 105 . In one embodiment, wafer 101 may be any substrate having a photoresist material deposited thereon. For example, wafer 101 may be a 300 mm wafer or a 450 mm wafer, although other wafer diameters may be used. Additionally, wafer 101 may be replaced with a substrate having a non-circular shape in some embodiments. The displaceable column may include a post 114 extending out of the chamber 105 . The column 114 may have ports to provide electrical and fluid paths from outside the chamber 105 to various components of the column.

在一實施例中,柱可包括基底板110。基底板110可為接地的。如下文將更詳細描述的,基底板110可包括流體通道以允許惰性氣體流動,從而提供邊緣淨化流。In one embodiment, the column may include a base plate 110 . Base plate 110 may be grounded. As will be described in greater detail below, the base plate 110 may include fluid channels to allow inert gas flow to provide an edge purge flow.

在一實施例中,絕緣層115設置在基底板110上。絕緣層115可為任何合適的介電材料。例如,絕緣層115可為陶瓷板等。在一實施例中,基座130設置在絕緣層115上。基座130可包含單一材料,或者基座130可以由不同材料形成。在一實施例中,基座130可以利用任何合適的卡緊系統來緊固晶圓101。例如,基座130可為真空卡盤或單極卡盤。在腔室105中不生成電漿的實施例中,基座130可以利用雙極卡盤架構。In one embodiment, the insulating layer 115 is disposed on the base plate 110 . Insulating layer 115 may be any suitable dielectric material. For example, the insulating layer 115 may be a ceramic plate or the like. In one embodiment, the base 130 is disposed on the insulating layer 115 . Base 130 may comprise a single material, or base 130 may be formed from different materials. In one embodiment, base 130 may utilize any suitable clamping system to secure wafer 101 . For example, base 130 may be a vacuum chuck or a monopole chuck. In embodiments where plasma is not generated in chamber 105, base 130 may utilize a bipolar chuck architecture.

基座130可包括複數個冷卻通道131。冷卻通道131可以連接到穿過支柱114的流體輸入及流體輸出(未圖示)。在一實施例中,冷卻通道131允許在操作處理工具100期間控制晶圓101的溫度。例如,冷卻通道131可允許晶圓101的溫度被控制在介於約-40℃與約300℃之間。在一實施例中,基座130經由濾波電路系統145接地,此實現了基座相對於地面的DC及/或RF偏置。The base 130 may include a plurality of cooling channels 131 . Cooling channels 131 may be connected to fluid input and fluid output (not shown) through strut 114 . In one embodiment, cooling channels 131 allow the temperature of wafer 101 to be controlled during operation of processing tool 100 . For example, cooling channels 131 may allow the temperature of wafer 101 to be controlled between about -40°C and about 300°C. In one embodiment, the base 130 is connected to ground via filter circuitry 145, which enables DC and/or RF biasing of the base relative to the ground.

在一實施例中,邊緣環120圍繞絕緣層115及基座130的周邊。邊緣環120可為介電材料,諸如陶瓷。在一實施例中,邊緣環120由基底板110支撐。邊緣環120可以支撐陰影環135。陰影環135的內徑小於晶圓101的直徑。因此,陰影環135阻止光阻劑沉積到晶圓101的外部邊緣的一部分上。在陰影環135與晶圓101之間提供間隙。該間隙防止陰影環135接觸晶圓101,並提供用於邊緣淨化流的出口,此將在下面更詳細地描述。In one embodiment, the edge ring 120 surrounds the insulating layer 115 and the periphery of the base 130 . Edge ring 120 may be a dielectric material, such as ceramic. In one embodiment, edge ring 120 is supported by base plate 110 . Edge ring 120 may support shadow ring 135 . The inner diameter of shadow ring 135 is smaller than the diameter of wafer 101 . Thus, shadow ring 135 prevents photoresist from being deposited onto a portion of the outer edge of wafer 101 . A gap is provided between shadow ring 135 and wafer 101 . This gap prevents shadow ring 135 from contacting wafer 101 and provides an outlet for edge purge flow, which is described in more detail below.

儘管陰影環135為晶圓101的頂表面及邊緣提供了一定保護,但是處理氣體可以沿著在邊緣環120與晶圓101之間的路徑向下流動/擴散。因此,本文所揭示的實施例可包括在邊緣環120與基座130之間的流體路徑以實現邊緣淨化流。在流體路徑中提供惰性氣體增加了流體路徑中的局部壓力,並且防止處理氣體到達晶圓101的邊緣。因此,防止了光阻劑沿著晶圓101的邊緣沉積。Although shadow ring 135 provides some protection for the top surface and edges of wafer 101 , process gases may flow/diffuse downwardly along the path between edge ring 120 and wafer 101 . Accordingly, embodiments disclosed herein may include a fluid path between edge ring 120 and base 130 to achieve edge purge flow. Providing an inert gas in the fluid path increases the local pressure in the fluid path and prevents the process gas from reaching the edge of the wafer 101 . Therefore, photoresist is prevented from being deposited along the edges of the wafer 101 .

現在參考第2圖,根據一實施例,圖示了處理工具內的柱260的一部分的放大橫截面圖。在第2圖中,僅圖示了柱260的左邊緣。然而,應當理解的是,柱260的右邊緣可以基本上鏡像於左邊緣。Referring now to FIG. 2 , an enlarged cross-sectional view of a portion of a post 260 within a processing tool is illustrated, according to an embodiment. In Figure 2, only the left edge of post 260 is illustrated. However, it should be understood that the right edge of post 260 may substantially mirror the left edge.

在一實施例中,柱260可以包括基底板210。絕緣層215可以設置在基底板210上。在一實施例中,基座230可包括第一部分230 A及第二部分230 B。冷卻通道231可以設置在第二部分230 B中。第一部分230 A可包括用於卡緊晶圓201的特徵。 In an embodiment, post 260 may include base plate 210 . The insulation layer 215 may be provided on the base plate 210 . In one embodiment, the base 230 may include a first part 230A and a second part 230B . Cooling channels 231 may be provided in the second part 230B . First portion 230 A may include features for clamping wafer 201 .

在一實施例中,邊緣環220圍繞基底板210、絕緣層215、基座230及晶圓201。在一實施例中,邊緣環220與柱250的其他部件間隔開,以提供從基底板210到柱260的頂側的流體路徑212。例如,流體路徑212可以離開在晶圓201與陰影環235之間的柱。在特定實施例中,流體路徑212的內表面包括絕緣層215的邊緣、基座230(亦即,第一部分230 A及第二部分230 B)的邊緣以及晶圓201的邊緣。在一實施例中,流體路徑212的外表面包括邊緣環220的內邊緣。在一實施例中,當流體路徑212前進到晶圓201的邊緣時,該流體路徑亦可以在基座230的一部分的頂表面上繼續。如此,當惰性氣體(例如,氦、氬等)流過流體路徑212時,防止了處理氣體沿晶圓201的側面向下流動/擴散。 In one embodiment, edge ring 220 surrounds base plate 210 , insulation layer 215 , base 230 and wafer 201 . In one embodiment, edge ring 220 is spaced apart from other components of column 250 to provide a fluid path 212 from base plate 210 to the top side of column 260 . For example, fluid path 212 may exit the pillar between wafer 201 and shadow ring 235 . In certain embodiments, the inner surface of fluid path 212 includes edges of insulating layer 215 , edges of base 230 (ie, first portion 230 A and second portion 230 B ), and edges of wafer 201 . In one embodiment, the outer surface of fluid path 212 includes the inner edge of edge ring 220 . In one embodiment, the fluid path 212 may also continue on a portion of the top surface of the susceptor 230 as it proceeds to the edge of the wafer 201 . As such, when an inert gas (eg, helium, argon, etc.) flows through fluid path 212 , the process gas is prevented from flowing/diffusing downward along the sides of wafer 201 .

在一實施例中,使流體路徑212的寬度W最小化,以防止電漿沿著流體路徑212撞擊。例如,流體路徑212的寬度W可為約1 mm或更小。在一實施例中,密封件217阻止流體路徑212離開柱260的底部。密封件217可以位於邊緣環220與基底板210之間。密封件217可為可撓性材料,諸如墊圈材料等。在特定實施例中,密封件217包含矽樹脂。In one embodiment, the width W of the fluid path 212 is minimized to prevent plasma impingement along the fluid path 212 . For example, the width W of fluid path 212 may be about 1 mm or less. In one embodiment, seal 217 prevents fluid path 212 from exiting the bottom of column 260. A seal 217 may be located between the edge ring 220 and the base plate 210 . Seal 217 may be a flexible material, such as a gasket material or the like. In certain embodiments, seal 217 includes silicone.

在一實施例中,通道211設置在基底板210中。通道211將惰性氣體從柱260的中心按路線輸送至邊緣環220的內邊緣。應當理解的是,在第2圖中僅圖示了通道211的一部分。下面相對於第4B圖提供了通道211的更全面的說明。In one embodiment, channels 211 are provided in base plate 210 . Channel 211 routes the inert gas from the center of column 260 to the inner edge of edge ring 220. It should be understood that only a portion of channel 211 is illustrated in Figure 2 . A more complete description of channel 211 is provided below with respect to Figure 4B.

在一實施例中,邊緣環220及陰影環235可以具有適於相對於晶圓201對準陰影環235的特徵。例如,邊緣環220的頂表面中的凹口221可以與陰影環235的底表面上的突起236介面連接。凹口221及突起236可以具有錐形表面,以允許該兩個部件的粗略對準,該粗略對準足以用於在邊緣環220與陰影環235接觸時提供更精確的對準。在另外的實施例中,對準特徵(未圖示)亦可以設置在基座230與邊緣環220之間。基座230與邊緣環220之間的對準特徵可以包括類似於邊緣環220與陰影環235之間的對準特徵的錐形凹口及突起架構。In one embodiment, edge ring 220 and shadow ring 235 may have features suitable for aligning shadow ring 235 relative to wafer 201 . For example, notches 221 in the top surface of edge ring 220 may interface with protrusions 236 on the bottom surface of shadow ring 235 . The notches 221 and protrusions 236 may have tapered surfaces to allow for a rough alignment of the two components that is sufficient to provide a more precise alignment when the edge ring 220 comes into contact with the shadow ring 235 . In other embodiments, alignment features (not shown) may also be disposed between the base 230 and the edge ring 220 . Alignment features between base 230 and edge ring 220 may include tapered notches and protrusion structures similar to the alignment features between edge ring 220 and shadow ring 235 .

現在參考第3A圖及第3B圖,根據個實施例,圖示了一對橫截面圖,該一對橫截面圖描繪了基座處於不同位置(在Z方向上)的處理工具的各部分。在第3A圖中,基座位於腔室內的較低位置處。第3A圖中基座的位置是晶圓經由狹縫閥插入腔室或從腔室中移除的位置。在第3B圖中,基座位於腔室內的升高位置處。第3B圖中的基座位置是處理晶圓的位置。Referring now to Figures 3A and 3B, illustrated is a pair of cross-sectional views depicting portions of a processing tool with the base in different positions (in the Z-direction), in accordance with an embodiment. In Figure 3A, the base is located lower within the chamber. The position of the pedestal in Figure 3A is where the wafer is inserted into or removed from the chamber via the slit valve. In Figure 3B, the base is in a raised position within the chamber. The base position in Figure 3B is where the wafer is handled.

現在參考第3A圖,根據一個實施例,圖示了處於第一位置的可移位柱360的橫截面圖。如第3A圖所示,該柱包括基底板310、絕緣層315、基座330(亦即,第一部分330 A及第二部分330 B)及邊緣環320。此類部件可以基本上類似於上述類似命名的部件。例如,冷卻通道331可以設置在基座330的第二部分330 B中,通道311可以設置在基底板310中,並且密封件317可以設置在邊緣環320與基底板310之間。 Referring now to Figure 3A, a cross-sectional view of the displaceable post 360 in a first position is illustrated, according to one embodiment. As shown in Figure 3A, the pillar includes a base plate 310, an insulating layer 315, a base 330 (ie, a first portion 330 A and a second portion 330 B ) and an edge ring 320. Such components may be substantially similar to the similarly named components described above. For example, cooling channels 331 may be provided in the second portion 330B of the base 330 , channels 311 may be provided in the base plate 310 , and seals 317 may be provided between the edge ring 320 and the base plate 310 .

如第3A圖所示,晶圓301放置在基座330的頂表面上。晶圓301可以經狹縫閥(未圖示)插入腔室中。此外,陰影環335被圖示在邊緣環320上方的升高位置處。因為陰影環335的內徑小於晶圓301的直徑,所以晶圓301需要在陰影環335與邊緣環320接觸之前被放置在基座上。As shown in Figure 3A, wafer 301 is placed on the top surface of susceptor 330. Wafer 301 may be inserted into the chamber through a slit valve (not shown). Additionally, shadow ring 335 is illustrated in a raised position above edge ring 320 . Because the inner diameter of shadow ring 335 is smaller than the diameter of wafer 301 , wafer 301 needs to be placed on the susceptor before shadow ring 335 comes into contact with edge ring 320 .

在一實施例中,陰影環335由腔室襯墊370支撐。腔室襯墊370可以圍繞柱360的外周。在一實施例中,保持器371位於腔室襯墊370的頂表面上。保持器371被配置為當柱360處於第一位置時將陰影環335保持在邊緣環320上方的升高位置處。在一實施例中,陰影環335包括突起336以用於與邊緣環320中的凹口321對準。In one embodiment, shadow ring 335 is supported by chamber liner 370. Chamber liner 370 may surround the outer perimeter of post 360. In one embodiment, retainer 371 is located on the top surface of chamber liner 370. Retainer 371 is configured to retain shadow ring 335 in a raised position above edge ring 320 when post 360 is in the first position. In one embodiment, shadow ring 335 includes protrusions 336 for alignment with notches 321 in edge ring 320 .

現在參考第3B圖,根據一個實施例,圖示了接合陰影環335之後的柱360的橫截面圖。如圖所示,柱360在豎直方向(亦即,Z方向)上移位,直到陰影環335接合邊緣環320。柱360的額外豎直位移將陰影環335從腔室襯墊370上的保持器371上提起。在一實施例中,由於陰影環335及邊緣環320中的對準特徵(亦即,凹口321及突起336),陰影環335被正確地對準。在另外的實施例中,對準特徵(未圖示)亦可以設置在基座330與邊緣環320之間。基座330與邊緣環320之間的對準特徵可包括類似於邊緣環320與陰影環335之間的對準特徵的錐形凹口及突起架構。Referring now to Figure 3B, a cross-sectional view of post 360 after engaging shadow ring 335 is illustrated, according to one embodiment. As shown, post 360 is displaced in the vertical direction (ie, the Z direction) until shadow ring 335 engages edge ring 320 . The additional vertical displacement of post 360 lifts shadow ring 335 from retainer 371 on chamber liner 370 . In one embodiment, shadow ring 335 is correctly aligned due to alignment features in shadow ring 335 and edge ring 320 (ie, notches 321 and protrusions 336). In other embodiments, alignment features (not shown) may also be disposed between the base 330 and the edge ring 320 . Alignment features between base 330 and edge ring 320 may include tapered notches and protrusion structures similar to the alignment features between edge ring 320 and shadow ring 335 .

當處於第二位置時,可以處理晶圓301。特別地,該處理可包括光阻劑材料在晶圓301的頂面上的氣相沉積。例如,該製程可為CVD製程、PE-CVD製程、ALD製程或PE-ALD製程。在特定實施例中,光阻劑是適用於EUV圖案化的金屬羰氧光阻劑。然而,應當理解的是,光阻劑可為任何類型的光阻劑,並且圖案化可包括任何微影術方案。在將光阻劑沉積到晶圓301上期間,惰性氣體可以沿著邊緣環310的內表面與絕緣層315、基座330及晶圓301的外表面之間的流體通道流動。如此,實質上消除了沿著晶圓301的邊緣或背面的光阻劑沉積。在一實施例中,藉由基座330 B的第二部分中的冷卻通道331,可以將晶圓301的溫度保持在介於約-40℃與約300℃之間。在另外的實施例中,晶圓301的溫度可以介於約-40℃與約200℃之間。在特定的實施例中,晶圓301的溫度可以保持在約40℃。 While in the second position, wafer 301 may be processed. In particular, the process may include vapor deposition of photoresist material on the top surface of wafer 301 . For example, the process may be a CVD process, a PE-CVD process, an ALD process or a PE-ALD process. In certain embodiments, the photoresist is a metal carbonyl oxide photoresist suitable for EUV patterning. However, it should be understood that the photoresist can be any type of photoresist and the patterning can include any lithography scheme. During deposition of photoresist onto wafer 301 , an inert gas may flow along fluid channels between the inner surface of edge ring 310 and the outer surfaces of insulating layer 315 , susceptor 330 and wafer 301 . In this manner, photoresist deposition along the edges or backside of wafer 301 is substantially eliminated. In one embodiment, the temperature of the wafer 301 can be maintained between about -40°C and about 300°C by the cooling channel 331 in the second part of the base 330B . In other embodiments, the temperature of wafer 301 may be between about -40°C and about 200°C. In certain embodiments, the temperature of wafer 301 may be maintained at approximately 40°C.

現在參考第4A圖,圖示了根據另外的實施例的處理工具400的截面圖。如第4A圖所示,該柱包括基底板410。基底板410可以由延伸出腔室的支柱414支撐。亦即,在一些實施例中,基底板410及柱414可為分立的部件,而不是如第1圖所示的單個整體零件。支柱414可以具有用於選路傳輸電氣連接及流體(例如,冷卻流體及用於淨化流的惰性氣體)的中央通道。Referring now to Figure 4A, a cross-sectional view of a processing tool 400 is illustrated in accordance with further embodiments. As shown in Figure 4A, the column includes a base plate 410. The base plate 410 may be supported by struts 414 extending out of the chamber. That is, in some embodiments, the base plate 410 and the posts 414 may be separate components rather than a single unitary part as shown in FIG. 1 . Pillar 414 may have a central channel for routing electrical connections and fluids (eg, cooling fluid and inert gas for purge flow).

在一實施例中,絕緣層415設置在基底板410上,並且基座430(亦即,第一部分430A及第二部分430B)設置在絕緣層415上。在一實施例中,冷卻劑通道431設置在基座430的第二部分430B中。晶圓401設置在基座430上。 In one embodiment, the insulating layer 415 is disposed on the base plate 410 , and the base 430 (ie, the first portion 430 A and the second portion 430 B ) is disposed on the insulating layer 415 . In one embodiment, coolant channels 431 are provided in the second portion 430B of the base 430. Wafer 401 is placed on susceptor 430 .

在一實施例中,邊緣環420設置為圍繞基底板410、絕緣層415、基座430及晶圓401。邊緣環420可以藉由緊固機構413(諸如螺栓、銷、螺釘等)耦接至基底板410。在一實施例中,密封件417阻止淨化氣體在基底板410與邊緣環420之間的間隙的底部處離開柱。 In one embodiment, edge ring 420 is disposed around base plate 410 , insulation layer 415 , base 430 and wafer 401 . Edge ring 420 may be coupled to base plate 410 by fastening mechanisms 413 (such as bolts, pins, screws, etc.). In one embodiment, seal 417 prevents purge gas from exiting the column at the bottom of the gap between base plate 410 and edge ring 420 .

在所圖示的實施例中,基座430處於第一位置中。如此,陰影環435由保持器471及腔室襯墊470支撐。當基座430豎直移位時,邊緣環420將與陰影環435接合,並將陰影環435從保持器471上提起。 In the illustrated embodiment, base 430 is in the first position. As such, shadow ring 435 is supported by retainer 471 and chamber liner 470 . When base 430 is displaced vertically, edge ring 420 will engage shadow ring 435 and lift shadow ring 435 away from retainer 471 .

現在參考第4B圖,圖示了根據另外的實施例的腔室400的截面圖。在第4B圖的圖示中,省略了絕緣層415及基座430,以便更清楚地看到基底板410的構造。如圖所示,基底板410可包括複數個通道411,該複數個通道提供從基底板410的中心到基底板410的邊緣的流體路徑。在所圖示的實施例中,複數個第一通道將基底板410的中心連接到第一環形通道,並且複數個第二通道將第一環形通道連接到基底板410的外邊緣。在一實施例中,第一通道及第二通道彼此不對準。儘管第4B圖中圖示了通道411的特定構造,但是應當理解的是,任何通道構造都可以用於將惰性氣體從基底板410的中心選路傳輸到基底板410的邊緣。Referring now to Figure 4B, a cross-sectional view of chamber 400 is illustrated in accordance with further embodiments. In the illustration of FIG. 4B , the insulating layer 415 and the base 430 are omitted so that the structure of the base plate 410 can be seen more clearly. As shown, the base plate 410 may include a plurality of channels 411 that provide fluid paths from the center of the base plate 410 to the edges of the base plate 410 . In the illustrated embodiment, a plurality of first channels connects the center of the base plate 410 to a first annular channel, and a plurality of second channels connects the first annular channel to the outer edge of the base plate 410 . In one embodiment, the first channel and the second channel are not aligned with each other. Although a specific configuration of channels 411 is illustrated in Figure 4B, it should be understood that any channel configuration may be used to route the inert gas from the center of the base plate 410 to the edges of the base plate 410.

第5圖以電腦系統500的例示性形式圖示了機器的圖形表示,在該電腦系統中可以執行用於使機器執行本文所述的方法中的任何一或多種方法的一組指令。在替代實施例中,機器可以連接(例如,聯網)到局域網路(Local Area Network, LAN)、內聯網、外聯網或網際網路中的其他機器。該機器可以以用戶端-伺服器網路環境中的伺服器或用戶端機器的容量操作,或者作為同級間(或分佈式)網路環境中的同級機器操作。該機器可為個人電腦(personal computer, PC)、平板PC、機上盒(set-top box, STB)、個人數位助理(Personal Digital Assistant, PDA)、蜂窩電話、網路設備、伺服器、網路路由器、交換機或網橋,或者能夠執行指定要由該機器採取的動作的一組指令(順序的或以其他方式)的任何機器。此外,儘管僅圖示了單個機器,但是術語「機器」亦應當被理解為包括單獨或聯合執行一組(或多組)指令以執行本文所述的方法中的任何一或多種方法的機器(例如,電腦)的任何集合。Figure 5 illustrates a graphical representation of a machine in the form of an illustrative computer system 500 in which a set of instructions may be executed for causing the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine may be connected (eg, networked) to other machines in a local area network (LAN), intranet, extranet, or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment, or as a peer machine in a peer (or distributed) network environment. The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network equipment, server, network A router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specifies actions to be taken by that machine. Furthermore, although a single machine is illustrated, the term "machine" shall also be taken to include a machine that alone or jointly executes a set (or sets) of instructions to perform any one or more of the methodologies described herein ( For example, any collection of computers).

例示性電腦系統500包括處理器502、主記憶體504(例如,唯讀記憶體(read-only memory, ROM)、快閃記憶體、動態隨機存取記憶體(dynamic random access memory, DRAM),諸如同步DRAM (synchronous DRAM, SDRAM)或Rambus DRAM (RDRAM))等)、靜態記憶體506(例如,快閃記憶體、靜態隨機存取記憶體(static random access memory, SRAM)、MRAM等)、及輔助記憶體518(例如,資料儲存裝置),它們經由匯流排530與彼此通訊。The exemplary computer system 500 includes a processor 502, a main memory 504 (eg, read-only memory (ROM), flash memory, dynamic random access memory (DRAM)), Such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 506 (for example, flash memory, static random access memory (static random access memory, SRAM), MRAM, etc.), and auxiliary memory 518 (eg, data storage device), which communicate with each other via bus 530 .

處理器502代表一或多個通用處理裝置,諸如微處理器、中央處理單元等。更特別地,處理器502可為複雜指令集計算(complex instruction set computing, CISC)微處理器、精簡指令集計算(reduced instruction set computing, RISC)微處理器、超長指令字(very long instruction word, VLIW)微處理器、實施其他指令集的處理器、或實施指令集的組合的處理器。處理器502亦可為一或多個專用處理裝置,諸如特殊應用積體電路(application specific integrated circuit, ASIC)、現場可程式化閘陣列(field programmable gate array, FPGA)、數位信號處理器(digital signal processor, DSP)、網路處理器等。處理器502被配置為執行處理邏輯526以執行本文所述的操作。Processor 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processor 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (very long instruction word) , VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processor 502 can also be one or more special-purpose processing devices, such as application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (digital signal processor) signal processor (DSP), network processor, etc. Processor 502 is configured to execute processing logic 526 to perform the operations described herein.

電腦系統500亦可以包括網路介面裝置508。電腦系統500亦可以包括視訊顯示單元510(例如,液晶顯示器(liquid crystal display, LCD)、發光二極體顯示器(light emitting diode display, LED)或陰極射線管(cathode ray tube, CRT))、字母數字輸入裝置512(例如,鍵盤)、游標控制裝置514(例如,滑鼠)及信號生成裝置516(例如,揚聲器)。Computer system 500 may also include a network interface device 508. The computer system 500 may also include a video display unit 510 (for example, a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), a letter Numeric input device 512 (eg, keyboard), cursor control device 514 (eg, mouse), and signal generation device 516 (eg, speaker).

輔助記憶體518可包括機器可存取儲存媒體(或者更特別地,電腦可讀取儲存媒體)532,該機器可存取儲存媒體上存儲了體現本文所述的方法中的任何一種或多種方法或功能的一或多組指令(例如,軟體522)。在由電腦系統500執行期間,軟體522亦可以完全或至少部分地駐留在主記憶體504及/或處理器502內,主記憶體504及處理器502亦構成機器可讀取儲存媒體。軟體522亦可以經由網路介面裝置508在網路520上發送或接收。Secondary memory 518 may include a machine-accessible storage medium (or, more specifically, a computer-readable storage medium) 532 having stored thereon a method embodying any one or more of the methods described herein. or one or more sets of instructions for functionality (e.g., software 522). During execution by computer system 500, software 522 may also reside fully or at least partially within main memory 504 and/or processor 502, which also constitute machine-readable storage media. Software 522 may also be sent or received over network 520 via network interface device 508.

雖然機器可存取儲存媒體532在例示性實施例中被圖示為單個媒體,但是術語「機器可讀取儲存媒體」應該被理解為包括儲存一或多組指令的單個媒體或多個媒體(例如,集中式或分佈式資料庫,及/或相關聯的快取及伺服器)。術語「機器可讀取儲存媒體」亦應被理解為包括能夠儲存或編碼一組指令的任何媒體,該一組指令用於供機器執行並使機器執行本揭示案的方法中的任何一或多種方法。因此,術語「機器可讀取儲存媒體」應被理解為包括但不限於固態記憶體以及光學及磁性媒體。Although machine-accessible storage medium 532 is illustrated in the illustrative embodiment as a single medium, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that stores one or more sets of instructions ( For example, centralized or distributed databases, and/or associated caches and servers). The term "machine-readable storage medium" shall also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. method. Accordingly, the term "machine-readable storage medium" should be understood to include, but not be limited to, solid-state memory and optical and magnetic media.

根據本揭示案的實施例,機器可存取儲存媒體具有儲存在其上的指令,該等指令使得資料處理系統執行在晶圓上沉積光阻劑的方法。在一實施例中,該方法包括經由腔室中的狹縫閥將晶圓裝載到基座上。隨後將基座豎直提升。升高基座導致陰影環接合圍繞基座的邊緣環。隨後可以用氣相製程在晶圓上沉積光阻劑。在光阻劑沉積期間,圍繞晶圓的周邊提供邊緣淨化流,以防止光阻劑沉積在晶圓的邊緣或背面上。According to embodiments of the present disclosure, a machine-accessible storage medium has instructions stored thereon that cause a data processing system to perform a method of depositing photoresist on a wafer. In one embodiment, the method includes loading the wafer onto the susceptor via a slit valve in the chamber. The base is then lifted vertically. Raising the base causes the shadow ring to engage the edge ring surrounding the base. Photoresist can then be deposited on the wafer using a vapor phase process. During photoresist deposition, an edge purge flow is provided around the perimeter of the wafer to prevent photoresist from depositing on the edges or backside of the wafer.

因此,已經揭示了使用氣相製程以包括陰影環及邊緣淨化流的工具進行光阻劑沉積的方法。Accordingly, methods have been disclosed for photoresist deposition using vapor phase processes with tools including shadow rings and edge purge flows.

100:處理工具 101:晶圓 105:腔室 110:基底板 114:支柱 115:絕緣層 120:邊緣環 130:基座 131:冷卻通道 135:陰影環 140:噴頭組件 145:濾波電路系統 150:匹配電路系統 201:晶圓 210:基底板 211:通道 212:流體路徑 215:絕緣層 217:密封件 220:邊緣環 221:凹口 230A:第一部分 230B:第二部分 231:冷卻通道 235:陰影環 236:突起 260:柱 301:晶圓 310:邊緣環 311:通道 315:絕緣層 317:密封件 320:邊緣環 321:凹口 330:基座 330A:第一部分 330B:第二部分 331:冷卻通道 335:陰影環 336:突起 360:柱 370:腔室襯墊 371:保持器 400:處理工具 401:晶圓 410:基底板 411:通道 413:緊固機構 414:柱 415:絕緣層 417:密封件 420:邊緣環 430:基座 430A:第一部分 430B:第二部分 431:冷卻劑通道 435:陰影環 470:腔室襯墊 471:保持器 500:電腦系統 502:處理器 504:主記憶體 506:靜態記憶體 508:網路介面裝置 510:視訊顯示單元 512:字母數字輸入裝置 514:游標控制裝置 516:信號生成裝置 518:輔助記憶體 520:網路 522:軟體 526:處理邏輯 530:匯流排 532:機器可存取儲存媒體 W:寬度 100:Processing Tools 101:wafer 105: Chamber 110: Base plate 114:Pillar 115:Insulation layer 120: Edge ring 130:Pedestal 131: Cooling channel 135:Shadow Ring 140:Nozzle assembly 145: Filter circuit system 150: Matching circuit system 201:wafer 210: Base plate 211:Channel 212:Fluid path 215:Insulation layer 217:Seals 220: Edge ring 221: Notch 230A:Part 1 230B:Part 2 231: Cooling channel 235:Shadow Ring 236:Protrusion 260: column 301:wafer 310: Edge ring 311:Channel 315:Insulation layer 317:Seals 320: Edge ring 321: Notch 330:Pedestal 330A:Part 1 330B:Part 2 331: Cooling channel 335:Shadow Ring 336:Protrusion 360: column 370: Chamber liner 371:Retainer 400: Processing Tools 401:wafer 410: Base plate 411:Channel 413: Fastening mechanism 414: column 415:Insulation layer 417:Seals 420: Edge ring 430:Pedestal 430A:Part 1 430B:Part 2 431: Coolant channel 435:Shadow Ring 470: Chamber liner 471:Retainer 500:Computer system 502: Processor 504: Main memory 506: Static memory 508:Network interface device 510: Video display unit 512: Alphanumeric input device 514: Cursor control device 516: Signal generating device 518: Auxiliary memory 520:Internet 522:Software 526: Processing logic 530:Bus 532: The machine can access storage media W: Width

第1圖是根據本揭示案的實施例的用於以氣相製程在基板上沉積光阻劑層的處理工具的橫截面圖。Figure 1 is a cross-sectional view of a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

第2圖是根據本揭示案的實施例的用於以氣相製程在基板上沉積光阻劑層的處理工具中的可移位柱的邊緣的放大圖。Figure 2 is an enlarged view of an edge of a displaceable post in a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

第3A圖是根據本揭示案的實施例的處理工具中的可移位柱的邊緣的放大圖,其中陰影環不與邊緣環接合。Figure 3A is an enlarged view of an edge of a displaceable post in a processing tool according to an embodiment of the disclosure, with the hatched ring not engaging the edge ring.

第3B圖是根據本揭示案的實施例的處理工具中的可移位柱的邊緣的放大圖,其中陰影環與邊緣環接合。Figure 3B is an enlarged view of an edge of a displaceable post in a processing tool in accordance with an embodiment of the present disclosure, with the hatched ring engaging the edge ring.

第4A圖是根據本揭示案的實施例的用於以氣相製程在基板上沉積光阻劑層的處理工具的截面圖。Figure 4A is a cross-sectional view of a processing tool for depositing a photoresist layer on a substrate in a vapor phase process, in accordance with an embodiment of the present disclosure.

第4B圖是根據本揭示案的實施例的處理工具的截面圖,其中基座被移除以暴露基底板中的通道。Figure 4B is a cross-sectional view of a processing tool with the base removed to expose channels in the base plate, in accordance with an embodiment of the present disclosure.

第5圖圖示了根據本揭示案的實施例的示例性電腦系統的方塊圖。Figure 5 illustrates a block diagram of an exemplary computer system in accordance with embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:處理工具 100:Processing Tools

101:晶圓 101:wafer

105:腔室 105: Chamber

110:基底板 110: Base plate

114:支柱 114:Pillar

115:絕緣層 115:Insulation layer

120:邊緣環 120: Edge ring

130:基座 130:Pedestal

131:冷卻通道 131: Cooling channel

135:陰影環 135:Shadow Ring

140:噴頭組件 140:Nozzle assembly

145:濾波電路系統 145: Filter circuit system

150:匹配電路系統 150: Matching circuit system

Claims (20)

一種半導體處理工具,包括:一腔室;一可移位柱,該可移位柱穿過該腔室的一表面,其中該可移位柱包括:一基底板;一絕緣層,該絕緣層在該基底板上;一基座,該基座在該絕緣層上;以及一邊緣環,該邊緣環圍繞該基底板、該絕緣層及該基座的一周邊,其中在該邊緣環與該基座之間提供一流體路徑,該流體路徑被阻止離開該可移位柱的一底部。 A semiconductor processing tool, including: a chamber; a displaceable column, the displaceable column passing through a surface of the chamber, wherein the displaceable column includes: a base plate; an insulating layer, the insulating layer on the base plate; a base on the insulating layer; and an edge ring surrounding the base plate, the insulating layer and a periphery of the base, wherein between the edge ring and the A fluid path is provided between the bases and is prevented from exiting a bottom of the displaceable column. 如請求項1所述之半導體處理工具,進一步包括:一陰影環,該陰影環在該邊緣環上方。 The semiconductor processing tool of claim 1, further comprising: a shadow ring, the shadow ring being above the edge ring. 如請求項2所述之半導體處理工具,其中該陰影環具有一居中突起,該居中突起與該邊緣環中的一居中凹口介面連接。 The semiconductor processing tool of claim 2, wherein the shadow ring has a central protrusion interfaced with a central notch in the edge ring. 如請求項1所述之半導體處理工具,其中該基座包括複數個通道,該複數個通道被配置為在該基座中循環一冷卻劑,該冷卻劑將一晶圓溫度保持在介於約-40℃與約200℃之間。 The semiconductor processing tool of claim 1, wherein the base includes a plurality of channels, the plurality of channels are configured to circulate a coolant in the base, the coolant maintains a wafer temperature between about Between -40℃ and about 200℃. 如請求項1所述之半導體處理工具,進一步包括: 通道,該等通道設置在該基底板的一表面中,其中該等通道流體耦接至該流體路徑。 The semiconductor processing tool as described in claim 1, further comprising: Channels are disposed in a surface of the base plate, wherein the channels are fluidly coupled to the fluid path. 如請求項1所述之半導體處理工具,進一步包括:一墊圈,該墊圈在該邊緣環與該基底板之間。 The semiconductor processing tool of claim 1, further comprising: a gasket between the edge ring and the base plate. 如請求項1所述之半導體處理工具,其中該流體路徑的一寬度為約1mm或更小。 The semiconductor processing tool of claim 1, wherein a width of the fluid path is about 1 mm or less. 如請求項1所述之半導體處理工具,其中該基座是一雙極卡盤、一單極卡盤、或一真空卡盤。 The semiconductor processing tool of claim 1, wherein the base is a bipolar chuck, a unipolar chuck, or a vacuum chuck. 如請求項1所述之半導體處理工具,進一步包括:一噴頭組件,該噴頭組件在該可移位柱上方。 The semiconductor processing tool of claim 1, further comprising: a nozzle assembly, the nozzle assembly being above the displaceable column. 如請求項1所述之半導體處理工具,其中該噴頭組件電耦合至一RF源。 The semiconductor processing tool of claim 1, wherein the shower head assembly is electrically coupled to an RF source. 如請求項1所述之半導體處理工具,其中該基底板是接地的。 The semiconductor processing tool of claim 1, wherein the base plate is grounded. 如請求項11所述之半導體處理工具,其中該基座耦合至一RF偏置源及/或一DC偏置源。 The semiconductor processing tool of claim 11, wherein the base is coupled to an RF bias source and/or a DC bias source. 一種用於在一半導體處理工具中保持一基板的組件,其中該組件包括:一基底板;一絕緣層,該絕緣層在該基底板上方;一基座,該基座在該絕緣層上方;一邊緣環,該邊緣環圍繞該基底板、該絕緣層及該基 座的一周邊;以及一流體路徑,該流體路徑從該組件的底部至該組件的頂部,其中該流體路徑穿過該基底板與該絕緣層之間的一第一通道、穿過該邊緣環與該絕緣層之間的一第二通道,並且穿過該邊緣環與該基座之間的一第三通道,該流體路徑被阻止離開該可移位柱的一底部。 An assembly for holding a substrate in a semiconductor processing tool, wherein the assembly includes: a base plate; an insulating layer above the base plate; a base above the insulating layer; an edge ring surrounding the base plate, the insulating layer and the base a periphery of the seat; and a fluid path from the bottom of the component to the top of the component, wherein the fluid path passes through a first channel between the base plate and the insulating layer, through the edge ring With a second channel between the insulating layer, and through a third channel between the edge ring and the base, the fluid path is prevented from exiting a bottom of the displaceable post. 如請求項13所述之組件,其中該第二通道的一寬度及該第三通道的一寬度是約1mm或更小。 The component of claim 13, wherein a width of the second channel and a width of the third channel are about 1 mm or less. 如請求項13所述之組件,進一步包括:一墊圈,該墊圈在該基底板與該邊緣環之間,其中該墊圈暴露於該流體路徑的一部分。 The assembly of claim 13, further comprising: a gasket between the base plate and the edge ring, wherein the gasket is exposed to a portion of the fluid path. 如請求項13所述之組件,進一步包括:一陰影環,該陰影環在該邊緣環上方。 The component of claim 13, further comprising: a shadow ring, the shadow ring being above the edge ring. 如請求項16所述之組件,其中該陰影環具有一居中突起,該居中突起與該邊緣環中的一居中凹口介面連接。 The assembly of claim 16, wherein the shadow ring has a central protrusion that interfaces with a central notch in the edge ring. 一種半導體處理工具,包括:一腔室;一噴頭組件,該噴頭組件密封該腔室,其中該噴頭組件電耦合至一RF源;一可移位柱,該可移位柱穿過該腔室並且與該噴頭組件相對,其中該可移位柱包括:一基底板;一絕緣層,該絕緣層在該基底板上; 一基座,該基座在該絕緣層上;以及一邊緣環,該邊緣環圍繞該基底板、該絕緣層及該基座的一周邊,其中在該邊緣環與該基座之間提供一流體路徑,該流體路徑被阻止離開該可移位柱的一底部。 A semiconductor processing tool, including: a chamber; a showerhead assembly sealing the chamber, wherein the showerhead assembly is electrically coupled to an RF source; a displaceable column passing through the chamber And opposite to the nozzle assembly, the displaceable column includes: a base plate; an insulating layer, the insulating layer is on the base plate; a base on the insulating layer; and an edge ring surrounding the base plate, the insulating layer and a periphery of the base, wherein an edge ring is provided between the edge ring and the base A fluid path is prevented from exiting a bottom of the displaceable column. 如請求項18所述之半導體處理工具,進一步包括:一襯墊,該襯墊圍繞該邊緣環;以及一陰影環。 The semiconductor processing tool of claim 18, further comprising: a pad surrounding the edge ring; and a shadow ring. 如請求項19所述之半導體處理工具,其中當該可移位柱相對於該噴頭組件處於一第一位置時,該陰影環由該襯墊支撐,並且其中當該可移位柱相對於該噴頭組件處於一第二位置時,該陰影環由該邊緣環支撐,其中當該可移位柱處於該第二位置時,該基座比當該可移位柱處於該第一位置時更靠近該噴頭組件。 The semiconductor processing tool of claim 19, wherein the shadow ring is supported by the liner when the displaceable post is in a first position relative to the showerhead assembly, and wherein when the displaceable post is in a first position relative to the showerhead assembly The shadow ring is supported by the edge ring when the shower head assembly is in a second position, wherein the base is closer when the displaceable post is in the second position than when the displaceable post is in the first position. The sprinkler head assembly.
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