TWI832376B - Method for increasing resolution by n bits performed by processing circuit of motor driving system and motor driving system - Google Patents

Abstract

A method for increasing a resolution by N bits performed by a processing circuit of a motor driving system includes: performing a conversion upon an analog command, to generate a command count value; performing a first N-bit right-shifting operation upon the command count value, to generate an initial output value; performing a logical operation upon the command count value, to generate a low bit value; generating an overflow value according to the low bit value; and determining a final output value according to the initial output value and the overflow value; wherein each of a plurality of pulse width modulation (PWM) signals is output from the processing circuit to a driving circuit according to the final output value, and a driving voltage is generated by the driving circuit according to the plurality of PWM signals, for driving a brushless direct current (DC) motor.

Description

A method used to improve the resolution by N bits through the processing circuit of the motor drive system. method and motor drive system

The present invention relates to a brushless direct current (DC) motor, and in particular, to a method for improving a resolution by N bits through a processing circuit of a motor drive system and related motor drives. System, where the resolution can be pulse width modulation (PWM) resolution or speed resolution, and N is a positive integer.

For a brushless DC motor, a processing circuit of the brushless DC motor (such as a micro control unit (MCU)) can output a plurality of pulse width modulation signals to a circuit coupled to the brushless DC motor. The driving circuit is used to generate a driving voltage to drive the brushless DC motor, wherein the driving voltage is proportional to the rotation speed of the brushless DC motor. When a pulse width modulation signal is used to drive a brushless DC motor, if the resolution of the pulse width modulation signal is insufficient, the voltage resolution will also be insufficient, which will cause the brushless DC motor to operate not smoothly and the brushless DC motor will not operate smoothly. The motor will become unstable.

In the existing method for improving the pulse width modulation resolution, the pulse width modulation resolution can be improved by increasing the operating frequency of the processing circuit. However, this method will increase the processing circuit Power consumption and manufacturing cost. In addition, when the speed resolution of the processing circuit is insufficient, the brushless DC motor may not be able to operate at the low speed required by the low speed command when the processing circuit receives a low speed command, and In response to the processing circuit receiving a high speed command, the speed ripple of the brushless DC motor may be large, which affects the output efficiency of the brushless DC motor. Therefore, there is a great need for a method to improve a resolution, which may be pulse width modulation resolution or rotational speed resolution, without increasing the operating frequency of the processing circuit of the brushless DC motor.

Therefore, one object of the present invention is to provide a method for improving a resolution by N bits through a processing circuit of a motor drive system and a related motor drive system to solve the above problems, wherein the resolution can be is the pulse width modulation resolution or speed resolution, and N is a positive integer.

According to an embodiment of the present invention, a method is provided for improving a resolution by N bits through a processing circuit of a motor drive system, where N is a positive integer. The method may include: performing a conversion on an analog command to generate a command count value; performing a first N-bit right shift operation on the command count value to generate an initial output value; performing a logic operation on the command count value. Operation to generate a low bit value; generate an overflow value based on the low bit value; and determine a final output value based on the initial output value and the overflow value; wherein the motor drive system includes a processing circuit, a drive circuit and a In the brushless DC motor, each pulse width modulation signal of the plurality of pulse width modulation signals is output from the processing circuit to the driving circuit according to the final output value, and a driving voltage is passed through the driving circuit according to the plurality of pulse width modulation signals. Produced to drive brushless DC motors.

According to an embodiment of the present invention, a motor driving system is provided. The motor drive system may include a brushless DC motor, a drive circuit and a device for improving a resolution by N bits. management circuit. The driving circuit can be coupled to the brushless DC motor and can be used to generate a driving voltage according to a plurality of pulse width modulation signals, wherein the driving voltage is used to drive the brushless DC motor. The processing circuit can be coupled to the driving circuit, and can be used to perform the following operations to increase a resolution by N bits: perform a conversion on an analog command to generate a command count value; perform an N-bit right conversion on the command count value. Shift operation to generate an initial output value; perform a logical operation on the command count value to generate a low-bit value; generate an overflow value based on the low-bit value; determine a final output based on the initial output value and overflow value value; and output each pulse width modulation signal of the plurality of pulse width modulation signals to the drive circuit according to the final output value; where N is a positive integer; where the resolution and analog command are respectively a pulse width modulation resolution and a pulse width modulation command, and the pulse width modulation command is used to control a voltage value of the driving voltage; or the resolution and the analog command are respectively a speed resolution and a speed command, and the speed command is used to control the brushless DC Motor speed.

One of the benefits of the present invention is that the pulse width modulation resolution can be increased by X bits (for example, X is a positive integer) through the method of the present invention without increasing the operating frequency of the processing circuit, which can reduce the power of the processing circuit. consumption and manufacturing costs, and makes the brushless DC motor run smoothly. In addition, the method of the present invention can improve the rotational speed resolution by Y bits (for example, Y is a positive integer). Since the method of the present invention can achieve a rotational speed that cannot be achieved due to insufficient rotational speed resolution, the brushless DC motor can be improved. speed ripple. In addition, since the number of bits used to improve the pulse width modulation resolution or rotational speed resolution can be determined according to design requirements, the method of the present invention has considerable design flexibility.

10: Motor drive system

50: Input voltage generation circuit

52:AC power supply

54:Bridge circuit

100,200: Processing circuit

110: Drive circuit

112: Gate driver circuit

114:Power transistor circuit

120: Brushless DC motor

122:Stator

PWM_1~PWM_N: Pulse width modulation signal

V_AC: AC voltage

V_IN: input voltage

V_DRV: driving voltage

R ₁ : shunt resistor

GND: ground voltage

a, b, c: stator winding

210: Speed command module after improving resolution

212:Control loop

214: Feedback calculation module after improving resolution

220: High-resolution voltage conversion module

230: High-resolution angle conversion module

240: Pulse width modulation generation circuit

RC: speed command

ARC: amplified speed command

FS: feedback signal

PWM_C: pulse width modulation command

FCR: feedback calculation result

HVR: High resolution voltage conversion results

HAR: High-resolution angle conversion results

S300~S312, S400~S410: steps

Figure 1 is a schematic diagram of a motor driving system according to an embodiment of the present invention.

Figure 2 is a schematic diagram of a processing circuit according to an embodiment of the present invention.

FIG. 3 is a flow chart of a method for improving pulse width modulation resolution by X bits according to an embodiment of the present invention.

FIG. 4 is a flowchart of a method for improving rotational speed resolution by Y bits according to an embodiment of the present invention.

Figure 1 is a schematic diagram of a motor driving system 10 according to an embodiment of the present invention. As shown in FIG. 1 , the motor driving system 10 may include an input voltage generating circuit 50 , a processing circuit 100 (such as a micro control unit (MCU)), a driving circuit 110 and a brushless DC motor ( brushless direct current (DC) motor) 120, wherein the brushless DC motor 120 may include a rotor (not shown) and a stator 122. The rotor may be a permanent magnet, and the stator 122 may be a three-phase stator. winding. The stator 122 may have a star connection structure (Y-connection structure) or a delta-connection structure (delta-connection structure), and may include a stator winding a, a stator winding b, and a stator winding c. In this embodiment, The stator 122 has a star connection structure, but the present invention is not limited to this.

1)輸出至驅動電路110。驅動電路110可耦接於無刷直流馬達120的定子122(尤其是，定子繞組a、定子繞組b以及定子繞組c)，並且可用以根據脈衝寬度調變訊號 PWM_1~PWM_N來產生一驅動電壓V_DRV以供驅動無刷直流馬達120，其中驅動電壓V_DRV與無刷直流馬達120的轉速成正比。舉例來說，驅動電路110可包含有一閘極驅動器電路112以及一功率電晶體電路114，其中閘極驅動器電路112可耦接於處理電路100，以及功率電晶體電路114可耦接於橋接電路54、閘極驅動器電路112以及無刷直流馬達120的定子122(尤其是，定子繞組a、定子繞組b以及定子繞組c)，並且可用以接收輸入電壓V_IN。 The input voltage generating circuit 50 can be coupled to the processing circuit 100 and the driving circuit 110, and can be used to generate an input voltage V_IN, and output the input voltage V_IN to the processing circuit 100 and the driving circuit 110. For example, the input voltage generating circuit 50 It may include an alternating current (AC) power supply 52 and a bridge circuit 54. The bridge circuit 54 may be used to receive an AC voltage V_AC from the AC power supply 52 and process the AC voltage V_AC to generate the output voltage V_IN. However, the invention is not limited thereto. this. The processing circuit 100 can be coupled to the driving circuit 110 and can be used to convert a series of pulse width modulation (pulse width modulation, PWM) signals PWM_1 to PWM_N (N

1) Output to the driving circuit 110. The driving circuit 110 can be coupled to the stator 122 of the brushless DC motor 120 (especially, the stator winding a, the stator winding b and the stator winding c), and can be used to generate a driving voltage V_DRV according to the pulse width modulation signals PWM_1~PWM_N. To drive the brushless DC motor 120 , the driving voltage V_DRV is proportional to the rotation speed of the brushless DC motor 120 . For example, the driving circuit 110 may include a gate driver circuit 112 and a power transistor circuit 114 , wherein the gate driver circuit 112 may be coupled to the processing circuit 100 , and the power transistor circuit 114 may be coupled to the bridge circuit 54 , the gate driver circuit 112 and the stator 122 of the brushless DC motor 120 (especially, the stator winding a, the stator winding b and the stator winding c), and may be used to receive the input voltage V_IN.

The motor driving system 10 may further include a shunt resistor R ₁ , wherein one end of the shunt resistor R ₁ may be coupled to the power transistor circuit 114 , and the other end of the shunt resistor R ₁ may be coupled to a reference voltage ( For example, a ground voltage GND). The processing circuit 100 can be coupled to both ends of the shunt resistor R ₁ and can be used to receive a plurality of feedback currents from the brushless DC motor 120 through the shunt resistor R ₁ .

1)，並且該演算法可以表示如下：PWM_OUT=(PWM_COMMAND＊PWM_COUNT) >>X+(Σ(PWM _COMMAND ＊PWM _COUNT )&(2 ^X -1))>>X其中PWM_OUT是脈衝寬度調變訊號PWM_1~PWM_N的每一個脈衝寬度調變訊號 的一輸出(亦即一脈衝寬度調變輸出值)，PWM_COMMAND是脈衝寬度調變命令，PWM_COUNT是脈衝寬度調變計數值，以及“>>X”代表一X位元右移操作。 Assume that the processing circuit 100 is an integer system, the operating frequency of the processing circuit 100 is 32 megahertz (MHz), and the operating frequency of the pulse width modulation signals PWM_1 ~ PWM_N is 100 kilohertz (kilohertz, kHz), where the processing The circuit 100 receives an analog command (for example, a pulse width modulation command). The pulse width modulation command is a 16-bit signed number (that is, the maximum value of the pulse width modulation command is 32767 (2 ¹⁵ -1) ) is used to control the voltage value of the driving voltage V_DRV, and a pulse width modulation count value of the processing circuit 100 is 320 (that is, 32MHz/100kHz). The processing circuit 100 may execute an algorithm to perform a method for increasing the pulse width modulation resolution by X bits without increasing the operating frequency of the processing circuit 100, where X may be a positive integer (i.e.,

1), and the algorithm can be expressed as follows: PWM _OUT =( _{PWM COMMAND} ＊PWM _COUNT ) >> X +(Σ( PWM _COMMAND ＊ PWM _COUNT )&(2 ^X -1)) >> An output of each pulse width modulation signal of the width modulation signals PWM_1~PWM_N (that is, a pulse width modulation output value), PWM _COMMAND is the pulse width modulation command, PWM _COUNT is the pulse width modulation count value, and ">>X" represents an X-bit right shift operation.

For better understanding, in this embodiment, it is assumed that the pulse width modulation resolution is increased by 15 bits through the algorithm (that is, X=15), and the number of pulse width modulation signals PWM_1~PWM_N is 9 ( That is, N=9), and for each pulse width modulation signal of the pulse width modulation signals PWM_1~PWM_9, the pulse width modulation command is 24444.

Table 1 illustrates an example of relevant values related to a method for improving the pulse width modulation resolution by 15 bits by executing an algorithm on the processing circuit 100 . For example, for the pulse width modulation signal PWM_1, the pulse width modulation command (ie 24444) and the pulse width modulation count value (ie 320) are multiplied to generate a command count value CCV (ie CCV =PWM _COMMAND * PWM _COUNT =24444 * 320=7822080), and perform a 15-bit right shift operation on the command count value CCV to generate an initial output value IOV (that is, IOV=(PWM _COMMAND * PWM _COUNT )>>15 =7822080>>15=238), then perform an AND operation on the command count value CCV and 2 ¹⁵ -1 to generate a low bit value LBV (that is, LBV=7822080 & (2 ¹⁵ -1)=23296 ), and accumulate (accumulate) the low bit value LBV to generate an accumulated low bit value ALBV. For the pulse width modulation signal PWM_1, since the pulse width modulation signal PWM_1 is a series of pulse width modulation signals PWM_1~PWM_9. The first pulse width modulation signal of Overflow value (overflow value) OV (that is, OV=23296>>15=0), where the overflow value OV can be 0 or 1.

According to the overflow value OV is 1, add 1 to the initial output value IOV to generate the pulse width modulation output value (that is, if OV=1, then PWM _OUT =IOV+1), and the accumulated low-bit value ALBV and 2 ¹⁵ -1 performs an AND operation to generate a remaining low bit value RLBV (that is, ALBV & (2 ¹⁵ -1)=RLBV), in which the remaining low bit value RLBV is accumulated to the next pulse width modulation signal . Since the overflow value OV is 0, the pulse width modulation output value is equal to the initial output value IOV (that is, if OV=0, then PWM _OUT =IOV), and the accumulated low-bit value ALBV is used as the remaining low-bit value RLBV to be accumulated to the next pulse width modulation signal. For the pulse width modulation signal PWM_1, since the overflow value OV is 0, the pulse width modulation output value is equal to the initial output value IOV (that is, PWM _OUT =IOV=238), and the accumulated low bit value ALBV (= 23296) is accumulated into the pulse width modulation signal PWM_2 as the remaining low bit value RLBV.

For the pulse width modulation signal PWM_2, the command count value CCV, initial output value IOV and low bit value LBV of the pulse width modulation signal PWM_2 and the command count value CCV, initial output value IOV and low bit value of the pulse width modulation signal PWM_1 The element value LBV is the same, that is, the command count value CCV, the initial output value IOV and the low bit value LBV of the pulse width modulation signal PWM_2 are equal to 7822080, 238 and 23296 respectively. For the sake of brevity, similar content will not be repeated here in detail. describe. It should be noted that the remaining low bit value RLBV (=23296) of the pulse width modulation signal PWM_1 is accumulated to the low bit value LBV (=23296) of the pulse width modulation signal PWM_2 to generate the accumulation of the pulse width modulation signal PWM_2 The last low-order bit value is ALBV (that is, ALBV=23296+23296=46592). Then, perform a 15-bit right shift operation on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV=46592>>15=1). According to the overflow value OV being 1, add 1 to the initial output value. IOV is used to generate a pulse width modulation output value (that is, PWM _OUT =238+1=239), and an AND operation is performed on the accumulated low-bit value ALBV and 2 ¹⁵ -1 to generate the remaining low-bit value RLBV ( That is, RLBV=46592 & (2 ¹⁵ -1)=13825), in which the remaining low-bit value RLBV is accumulated to the pulse width modulation signal PWM_3.

For the pulse width modulation signal PWM_3, the command count value CCV, initial output value IOV and low bit value LBV of the pulse width modulation signal PWM_3 and the command count value CCV, initial output value IOV and low bit value of the pulse width modulation signal PWM_1 The element value LBV is the same, that is, the command count value CCV, the initial output value IOV and the low bit value LBV of the pulse width modulation signal PWM_3 are equal to 7822080, 238 and 23296 respectively. For the sake of brevity, similar content will not be repeated here in detail. describe. It should be noted that the remaining low bit value RLBV (=13825) of the pulse width modulation signal PWM_2 is accumulated to the low bit value LBV (=23296) of the pulse width modulation signal PWM_3 to generate the accumulation of the pulse width modulation signal PWM_3 The last low-order bit value is ALBV (that is, ALBV=23296+13825=37121). Then, perform a 15-bit right shift operation on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV=37121>>15=1). Since the overflow value OV is 1, add 1 to the initial output value. IOV is used to generate a pulse width modulation output value (that is, PWM _OUT =238+1=239), and an AND operation is performed on the accumulated low-bit value ALBV and 2 ¹⁵ -1 to generate the remaining low-bit value RLBV ( That is, RLBV=37121 & (2 ¹⁵ -1)=4354), in which the remaining low-bit value RLBV is accumulated to the pulse width modulation signal PWM_4. For the sake of brevity, the similar content of the pulse width modulation signals PWM_4~PWM_9 will not be described in detail here.

In this embodiment, when the pulse width modulation command is 24444, the ideal pulse width modulation output value is (24444/32767) * 320 = 238.718. For the method of the present invention, the pulse width modulation signal PWM_1~ An average pulse width modulation output value of PWM_9 is 238.67 (238+239+239+238+239+239+238+239+239/9=238.67). Consider a case in which the processing circuit 100 executes an existing algorithm. The existing algorithm can be expressed as follows: PWM _OUT = (PWM _COMMAND *PWM _COUNT ) >> X where the pulse width modulation output values of the pulse width modulation signals PWM_1 ~ PWM_9 are both equal to 238, and the average pulse width modulation output value of the pulse width modulation signals PWM_1~PWM_9 is 238 (238+238+238+238+238+238+238+238+238/9=238), which sacrifices The accuracy is 0.718 (238.718-238=0.718).

Compared with this case, the average pulse width modulation output value of the method of the present invention only sacrifices 0.051 accuracy (238.718-238.67=0.051), which is far less than the accuracy sacrificed by the existing algorithm. In addition, the method of the present invention can The number of bits used to improve the pulse width modulation resolution is determined according to the design requirements. Therefore, the method of the present invention has considerable design flexibility.

In addition to outputting the pulse width modulation signals PWM_1 ~ PWM_N to the driving circuit 110 for generating the driving voltage V_DRV for driving the brushless DC motor 120 , the processing circuit 100 can also be used to generate the driving voltage V_DRV from the brushless DC through the shunt resistor R ₁ The motor 120 receives a plurality of feedback currents to output pulse width modulation signals PWM_1 ~ PWM_N to control the angle (ie, rotation speed) of the brushless DC motor 120 . In the angle calculation of the brushless DC motor performed by the processing circuit 100, the angle of the brushless DC motor 120 can be obtained by using the plurality of feedback currents to look up the table. Therefore, the rotational speed resolution of the processing circuit 100 may be Limited by the least significant bit (LSB) of the angle.

1)，並且Y可以與上述X不同。此外，本發明之方法可根據設計需求來決定用以提高轉速解析度的位元數，因此，本發明之方法的設計彈性相當大。 Assuming that the least significant bit of the angle is a 16-bit unsigned number, an analog command (such as a speed command RC used to control the speed of the brushless DC motor 120) is also a 16-bit unsigned number (that is, the speed The number of command RCs (=65536 corresponds to 360 degrees), the sampling frequency of the processing circuit 100 is 50kHz (that is, the sampling period of the processing circuit 100 is 0.00002 seconds), and the number of poles of the brushless DC motor 120 is 5 . For the rotation speed command RC, in the processing circuit 100, one unit angle is approximately equal to 0.0055 degrees (360 degrees/65535=0.0055 degrees), and one rotation speed resolution is approximately equal to 274.66 degrees/second (0.0055/0.00002=274.66 degrees/second ), where the speed resolution can be converted into 9.155 revolutions per minute (RPM) ((274.66/360/5) * 60=9.155RPM), that is, when the speed command RC is 1 or the speed command RC When the change amount is 1 (for example, from 1 to 2), the brushless DC motor 120 can run at 9.155 RPM. However, when the rotational speed resolution in the processing circuit 100 is 9.155RPM, if the processing circuit 100 controls the rotational speed of the brushless DC motor 120 to 100RPM, the rotational speed of the brushless DC motor 120 will ripple. will be very large, which may affect the output efficiency of the brushless DC motor 120. Therefore, in addition to the pulse width modulation resolution, the processing circuit 100 may execute another algorithm to analyze the rotation speed in the processing circuit 100. A method to increase Y bits, where Y can be a positive integer (that is, Y

1), and Y can be different from X above. In addition, the method of the present invention can determine the number of bits used to improve the rotational speed resolution according to design requirements. Therefore, the method of the present invention has considerable design flexibility.

Please refer to Figure 2. Figure 2 is a schematic diagram of a processing circuit 200 according to an embodiment of the present invention. The processing circuit 100 shown in Figure 1 can be implemented by the processing circuit 200 shown in Figure 2. As shown in Figure 2, the processing circuit 200 may include a plurality of circuits, such as an improved resolution speed command module 210, a control loop 212, an enhanced resolution feedback calculation module 214, a high resolution kWh The voltage conversion module 220, a high-resolution angle conversion module 230 and a pulse width modulation generation circuit 240. After the resolution is improved, the rotation speed command module 210 can be used to receive the rotation speed command RC, and perform a Y-bit processing on the rotation speed command RC. Element left shift operation to generate an amplified rotational speed command ARC.

Assume that the speed command RC is a 16-bit unsigned number, and the Y system is equal to 3. After performing a 3-bit left shift operation on the speed command RC, an amplified speed command ARC can be generated, and the number of amplified speed commands ARC ( 65536<<3=524288) corresponds to 360 degrees. When the speed resolution corresponding to the speed command RC is 9.155RPM, the speed resolution corresponding to the amplified speed command ARC is 1.144RPM (9.155/8=1.144 ), that is, when the amplified rotational speed command ARC is 1, the brushless DC motor 120 can run at 1.144RPM.

The control loop 212 can be used to calculate how much voltage (such as the voltage value of the driving voltage V_DRV) needs to be output to the brushless DC motor 120 according to a feedback signal FS (such as a plurality of feedback currents) to obtain the pulse width modulation command ( For brevity, labeled "PWM_C" in Figure 2). The high-resolution voltage conversion module 220 can receive the pulse width modulation command from the control loop 212 and execute the above algorithm to perform the method of improving the pulse width modulation resolution by X bits. For simplicity, Similar content will not be described in detail here.

The improved resolution feedback calculation module 214 can be used to calculate the angle and feedback speed of the brushless DC motor 120 based on a plurality of feedback currents and amplified speed commands ARC to generate a feedback calculation result FCR. The high-resolution angle conversion module 230 can be used to execute another algorithm according to the feedback calculation result FCR to perform a method for improving the speed resolution in the processing circuit 200 by Y bits, where Y can be a positive integer (e.g. Y=3), and this other algorithm can be expressed as follows: COMMAND _ANGLE =REAL _VELOCITY >>Y+(Σ(REAL _VELOCITY )&(2 ^Y -1))>>Y where COMMAND _ANGLE is high resolution An output of the angle conversion module 230, REAL _VELOCITY is the amplified rotational speed command ARC, and ">>Y" represents a Y-bit right shift operation.

Table 2 illustrates an example of relevant values related to the method of improving the rotational speed resolution by 3 bits by executing the algorithm of the processing circuit 200 . For better understanding, it is assumed that the number of sampling performed by the processing circuit 200 is 8, and for each sampling, the amplified rotational speed command ARC is 1. For the first sampling (marked as "n=0" in Table 2), a 3-bit right shift operation is performed on the amplified speed command ARC to generate an initial output value IOV (that is, IOV=REAL _VELOCITY >>3=1>>3=0)), and perform an AND operation on the amplified speed command ARC and 2 ³ -1 to generate a low-bit value LBV (that is, LBV=1 & (2 ³ -1 )=1), then, accumulate the low-bit value LBV to generate an accumulated low-bit value ALBV. For the first sampling (n=0), the accumulated low-bit value ALBV is equal to the low-bit value LBV (that is, ALBV=LBV=1), finally, perform a 3-bit right shift operation on the accumulated low-bit value ALBV to generate an overflow value OV (that is, OV=1>>3=0), where the overflow value OV can be is 0 or 1.

Since the overflow value OV is 1, add 1 to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (that is, if OV=1, then COMMAND _ANGLE =IOV+1), and the accumulated low bit The element value ALBV and 2 ³ -1 perform an AND operation to generate a remaining low-bit value RLBV (that is, ALBV & (2 ³ -1)=RLBV), in which the remaining low-bit value RLBV is accumulated to the next Sampling. Since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, if OV=0, then COMMAND _ANGLE =IOV), and the accumulated low-bit value ALBV is used as the remainder. The low bit value RLBV is accumulated to the next sample. For the first sampling (n=0), since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE =IOV=0), and is accumulated The last low-bit value ALBV (ALBV=1) is accumulated to the second sampling (marked as “n=1” in Table 2) as the remaining low-bit value RLBV.

For the second sampling (n=1), the initial output value IOV and low-bit value LBV of the second sampling are the same as the initial output value IOV and low-bit value LBV of the first sampling, that is, the second sampling The sampled initial output value IOV and the low-bit value LBV are 0 and 1 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low-bit value RLBV of the first sampling (that is, RLBV=1) is accumulated to the low-bit value LBV of the second sampling (that is, LBV=1) to produce the accumulated value of the second sampling. The low bit value ALBV (that is, ALBV=1+1=2), and then a 3-bit right shift operation is performed on the accumulated low bit value ALBV to generate the overflow value OV (that is, OV=2>>3=0 ), corresponding to the overflow value OV being 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE =IOV=0), and the accumulated low-bit value ALBV is used as the remaining low-bit value RLBV to be accumulated to the 3rd sampling (marked as “n=2” in Table 2). For the sake of simplicity, for the 3rd to 7th sampling (marked as “n=6” in Table 2) Similar content will not be described in detail here.

For the 8th sampling (marked as “n=7” in Table 2), the initial output value IOV and low-bit value LBV of the 8th sampling are the same as the initial output value IOV and low-bit value LBV of the 1st sampling. The same, that is, the initial output value IOV and the low-bit value LBV of the eighth sampling are 0 and 1 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low-bit value RLBV of the 7th sampling (n=6) (that is, RLBV=7) is accumulated to the low-bit value LBV of the 8th sampling (that is, LBV=1) to generate the The accumulated low-bit value ALBV of 8 samples (that is, ALBV=1+7=8), and then a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV= 8>>3=1), since the overflow value OV is 1, add 1 to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (that is, COMMAND _ANGLE =0+1=1).

When the output of the high-resolution angle conversion module 230 is equal to 0, the brushless DC motor 120 will run at 0RPM, and when the output of the high-resolution angle conversion module 230 is equal to 1, the brushless DC motor 120 will run at 9.155 RPM, in 8 times of sampling, the average speed of the brushless DC motor 120 is 1.144RPM ((0+0+0+0+0+0+0+9.155)/8=1.144). In this way, although there is no The real rotation speed of the brush DC motor 120 is still 9.155RPM, but in the process of 8 samplings, the method of the present invention can be used to reach a rotation speed that cannot be achieved due to insufficient rotation speed resolution (for example, 1.144RPM). Therefore, the brushless system can be improved. The speed ripple of DC motor 120.

Table 3 illustrates another example of related values related to the method of improving the speed resolution by 3 bits by executing the algorithm of the processing circuit 200 . For better understanding, assume that the number of samplings performed by the processing circuit 200 is 8, and for each sampling, the amplified rotational speed command ARC is 2 (which corresponds to 2.288RPM). For the first sampling (marked as "n=0" in Table 3), a 3-bit right shift operation is performed on the amplified speed command ARC to generate the initial output value IOV (that is, IOV=REAL _VELOCITY >>3=2>>3=0)), and perform an AND operation on the amplified speed command ARC and 2 ³ -1 to generate the low bit value LBV (that is, LBV=2 & (2 ³ -1)= 2), then, accumulate the low-bit value LBV to generate the accumulated low-bit value ALBV. For the first sampling (n=0), the accumulated low-bit value ALBV is equal to the low-bit value LBV (that is, ALBV=LBV =2), finally, perform a 3-bit right shift operation on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV=2>>3=0). Since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE =IOV=0), and the accumulated low-bit value ALBV (that is, ALBV=2) is as The remaining low-bit value RLBV is accumulated to the second sample (marked as “n=1” in Table 3).

For the second sampling (n=1), the initial output value IOV and low-bit value LBV of the second sampling are the same as the initial output value IOV and low-bit value LBV of the first sampling, that is, the second sampling The sampled initial output value IOV and the low-bit value LBV are 0 and 2 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low-bit value RLBV of the first sampling (that is, RLBV=2) is accumulated to the low-bit value LBV of the second sampling (that is, LBV=2) to generate the accumulation of the second sampling. The last low-bit value ALBV (that is, ALBV=2+2=4), and then a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV=4>>3= 0), since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE =IOV=0), and the accumulated low-bit value ALBV (that is, ALBV= 4) As the remaining low bit value RLBV, it is accumulated to the third sampling (marked as "n=2" in Table 3). For the sake of brevity, the similar content of the third sampling will not be repeated in detail here. .

For the fourth sampling (marked as “n=3” in Table 3), the initial output value IOV and low-bit value LBV of the fourth sampling are the same as the initial output value IOV and low-bit value LBV of the first sampling. The same, that is, the initial output value IOV and the low-bit value LBV of the fourth sampling are 0 and 2 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low bit value RLBV of the 3rd sample (n=2) (that is, RLBV=6) is accumulated to the bit value LBV of the 4th sample (that is, LBV=2) to generate the 4th sample. The accumulated low-bit value ALBV of 4 samples (that is, ALBV=2+6=8), and then a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV= 8>>3=1), since the overflow value OV is 1, add 1 to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (that is, COMMAND _ANGLE =0+1=1), and for After accumulation, the low-bit value ALBV and 2 ³ -1 perform an AND operation to generate the remaining low-bit value RLBV (that is, RLBV=8 & (2 ³ -1)=0), in which the remaining low-bit value RLBV is accumulated. to the next sampling.

Similarly, for the 5th sampling (marked as “n=4” in Table 3) to the 8th sampling (marked as “n=7” in Table 3), the high-resolution angle conversion module 230 The outputs are 0, 0, 0 and 1 respectively. When the output of the high-resolution angle conversion module 230 is 0, the brushless DC motor 120 will run at 0RPM, and when the output of the high-resolution angle conversion module 230 is 1, the brushless DC motor 120 will run at 9.155 RPM, in 8 times of sampling, the average speed of the brushless DC motor 120 is 2.288RPM ((0+0+0+9.155+0+0+0+9.155)/8=2.288). In this way, although there is no The real rotation speed of the brush DC motor 120 is still 9.155RPM, but in the process of 8 samplings, the method of the present invention can be used to reach a rotation speed that cannot be achieved due to insufficient rotation speed resolution (for example, 2.288RPM). Therefore, the brushless system can be improved. The speed ripple of DC motor 120.

The pulse width modulation generation circuit 240 may be used to receive a high-resolution voltage conversion result HVR and a high-resolution angle conversion result HAR from the high-resolution voltage conversion module 220 and the high-resolution angle conversion module 230 to generate pulses. width modulation signals PWM_1~PWM_N, and output the pulse width modulation signals PWM_1~PWM_N to the driving circuit 110. For the sake of simplicity, for this implementation Similar content of the embodiment will not be described in detail here.

FIG. 3 is a flow chart of a method for improving pulse width modulation resolution by X bits according to an embodiment of the present invention, where X is a positive integer. If the same result can be obtained, the steps do not have to be executed in sequence according to the process shown in Figure 3. For example, the method shown in Figure 3 can be performed by the processing circuit 100 shown in Figure 1 or the processing circuit 100 shown in Figure 1. This is achieved by using the processing circuit 200 (especially the high-resolution voltage conversion module 220) shown in FIG. 2 .

In step S300, a pulse width modulation command is received from the control loop 212.

In step S302, the pulse width modulation command is multiplied by a pulse width modulation count value to generate a command count value CCV, wherein the pulse width modulation count value is divided by an operating frequency of the processing circuit 200 Generated at an operating frequency of the pulse width modulation signal.

In step S304, an X-bit right shift operation is performed on the command count value CCV to generate an initial output value IOV.

In step S306, an AND operation is performed on the command count value CCV and 2 ^X -1 to generate a low bit value LBV.

In step S308, the low bit value LBV is accumulated to generate an accumulated low bit value ALBV.

In step S310, an X-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV.

In step S312, according to the overflow value OV is 1, 1 is added to the initial output value IOV to generate a pulse width modulation output value, and according to the overflow value OV is 0, the pulse width modulation output value is equal to the initial output value IOV. .

Since those skilled in the art can easily understand the operation of each step shown in Figure 3 through the above description of the processing circuit 100 shown in Figure 1 or the processing circuit 200 shown in Figure 2, for the sake of simplicity, here Similar content in the embodiment will not be repeated here.

Figure 4 is a flowchart of a method for improving the speed resolution by Y bits according to an embodiment of the present invention, where Y is a positive integer. If the same result can be obtained, the steps do not have to be executed in sequence according to the process shown in Figure 4. For example, the method shown in Figure 4 can be performed by the processing circuit 100 shown in Figure 1 or the processing circuit 100 shown in Figure 1. This is achieved by using the processing circuit 200 (especially the high-resolution angle conversion module 230) shown in FIG. 2 .

In step S400, a rotational speed command RC is received by the processing circuit 200, and a Y-bit left shift operation is performed on the rotational speed command RC to generate an amplified rotational speed command ARC.

In step S402, a Y-bit right shift operation is performed on the amplified rotational speed command ARC to generate an initial output value IOV.

In step S404, an AND operation is performed on the amplified rotational speed command ARC and 2 ^Y -1 to generate a low bit value LBV.

In step S406, the low bit value LBV is accumulated to generate an accumulated low bit value ALBV.

In step S408, a Y-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV.

In step S410, in response to the overflow value OV being 1, 1 is added to the initial output value IOV to generate an output of the high-resolution angle conversion module 230, and in response to the overflow value OV being 0, the high-resolution angle conversion module This output of 230 is equal to the initial output value IOV.

Since those skilled in the art can easily understand the operations of each step shown in Figure 4 through the above description of the processing circuit 100 shown in Figure 1 or the processing circuit 200 shown in Figure 2, for the sake of simplicity, here Similar content in the embodiment will not be repeated here.

In summary, through the method of the present invention, the pulse width modulation resolution can be increased by X bits (for example, X is a positive integer) without increasing the operating frequency of the processing circuit, which can reduce the power consumption and manufacturing cost of the processing circuit. , and makes the brushless DC motor run smoothly. In addition, the method of the present invention can improve the rotational speed resolution by Y bits (for example, Y is a positive integer). Since the method of the present invention can achieve a rotational speed that cannot be achieved due to insufficient rotational speed resolution, the brushless DC motor can be improved. speed ripple. In addition, since the number of bits used to improve the pulse width modulation resolution or rotational speed resolution can be determined according to design requirements, the method of the present invention has considerable design flexibility. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

S300~S312: steps

Claims (12)

A method for improving a resolution by N bits through a processing circuit of a motor drive system, where N is a positive integer, and the method includes: performing a conversion on an analog command to generate a command Count value; perform a first N-bit right shift operation on the command count value to generate an initial output value; perform a logical operation on the command count value to generate a low-bit value; generate according to the low-bit value an overflow value; and determining a final output value based on the initial output value and the overflow value; wherein the motor drive system includes the processing circuit, a drive circuit and a brushless DC motor, and a plurality of pulse width modulation Each pulse width modulation signal of the signal is output from the processing circuit to the driving circuit according to the final output value, and a driving voltage is generated by the driving circuit according to the plurality of pulse width modulation signals for driving. The brushless DC motor; wherein the step of generating the overflow value according to the low bit value includes: accumulating the low bit value to generate an accumulated low bit value; and performing a second N on the accumulated low bit value. Bit right shift operation to generate the overflow value. As described in the method described in item 1 of the patent application, the resolution is a pulse width modulation resolution, and the analog command is a pulse width modulation command for controlling a voltage value of the driving voltage. For the method described in item 2 of the patent application, the step of performing the conversion on the analog command to generate the command count value includes: multiplying the pulse width modulation command and a pulse width modulation count value. , to generate the command A count value, wherein the pulse width modulation count value is generated by dividing an operating frequency of the processing circuit by an operating frequency of the plurality of pulse width modulation signals. For the method described in item 2 of the patent application, the step of performing the logical operation on the command count value to generate the low-bit value includes: performing an AND (AND) on the command count value and 2 ^N -1 Operate to produce the low-bit value. For the method described in item 2 of the patent application, the step of determining the final output value based on the initial output value and the overflow value includes: according to the overflow value being 1, adding 1 to the initial output value. produces this final output value. For the method described in item 2 of the patent application, the step of determining the final output value based on the initial output value and the overflow value includes: since the overflow value is 0, the final output value is equal to the initial output value. For the method described in item 1 of the patent application, the resolution is a rotational speed resolution, and the analog command is a rotational speed command for controlling the rotational speed of the brushless DC motor. For the method described in item 7 of the patent application, the step of performing the conversion on the analog command to generate the command count value includes: performing an N-bit left shift operation on the rotational speed command to generate an amplified The speed command is used as the command count value. For the method described in Item 7 of the patent application, the step of performing the logical operation on the command count value to generate the low-bit value includes: performing an AND (AND) on the command count value and 2 ^N -1 Operate to produce the low-bit value. For the method described in Item 7 of the patent application, the step of determining the final output value based on the initial output value and the overflow value includes: according to the overflow value being 1, adding 1 to the initial output value. produces this final output value. For the method described in Item 7 of the patent application, the step of determining the final output value based on the initial output value and the overflow value includes: since the overflow value is 0, the final output value is equal to the initial output. value. A motor driving system includes: a brushless DC motor; a driving circuit coupled to the brushless DC motor and used to generate a driving voltage according to a plurality of pulse width modulation signals, wherein the driving voltage is used to Driving the brushless DC motor; and a processing circuit coupled to the driving circuit and used to perform the following operations to improve a resolution by N bits: performing a conversion on an analog command to generate a command count value; Perform an N-bit right shift operation on the command count value to generate an initial output value; perform a logical operation on the command count value to generate a low-bit value; generate an overflow value based on the low-bit value; Determine a final output value according to the initial output value and the overflow value; and convert each pulse of the plurality of pulse width modulation signals according to the final output value. The width modulation signal is output to the driving circuit; where N is a positive integer; where the resolution and the analog command are respectively a pulse width modulation resolution and a pulse width modulation command, and the pulse width modulation command uses To control a voltage value of the driving voltage; or the resolution and the analog command are respectively a speed resolution and a speed command, and the speed command is used to control the speed of the brushless DC motor; wherein according to the low bit value The steps to generate the overflow value include: accumulating the low-bit value to generate an accumulated low-bit value; and performing a second N-bit right shift operation on the accumulated low-bit value to generate the overflow value. .

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