TW202410626A - Method for increasing resolution by n bits performed by processing circuit of motor driving system and motor driving system - Google Patents

Abstract

A method for increasing a resolution by N bits performed by a processing circuit of a motor driving system includes: performing a conversion upon an analog command, to generate a command count value; performing a first N-bit right-shifting operation upon the command count value, to generate an initial output value; performing a logical operation upon the command count value, to generate a low bit value; generating an overflow value according to the low bit value; and determining a final output value according to the initial output value and the overflow value; wherein each of a plurality of pulse width modulation (PWM) signals is output from the processing circuit to a driving circuit according to the final output value, and a driving voltage is generated by the driving circuit according to the plurality of PWM signals, for driving a brushless direct current (DC) motor.

Description

Method for increasing resolution by N bits by processing circuit of motor drive system and motor drive system

The present invention relates to brushless direct current (DC) motors, and in particular to a method for improving a resolution by N bits through a processing circuit of a motor drive system and related motor drives. system, where the resolution can be pulse width modulation (PWM) resolution or speed resolution, and N is a positive integer.

For a brushless DC motor, a processing circuit (such as a micro control unit (MCU)) of the brushless DC motor can output a plurality of pulse width modulation signals to a circuit coupled to the brushless DC motor. The driving circuit is used to generate a driving voltage to drive the brushless DC motor, wherein the driving voltage is proportional to the rotation speed of the brushless DC motor. When a pulse width modulation signal is used to drive a brushless DC motor, if the resolution of the pulse width modulation signal is insufficient, the voltage resolution will also be insufficient, which will cause the brushless DC motor to operate not smoothly and the brushless DC motor will not operate smoothly. The motor will become unstable.

In the existing method for improving the PWM resolution, the PWM resolution can be improved by increasing the operating frequency of the processing circuit. However, this method will increase the power consumption and manufacturing cost of the processing circuit. In addition, when the speed resolution of the processing circuit is insufficient, in response to the processing circuit receiving a low speed command, the brushless DC motor may not be able to operate at a low speed required by the low speed command, and in response to the processing circuit receiving a high speed command, the speed ripple of the brushless DC motor may be large, which affects the output efficiency of the brushless DC motor. Therefore, a method for improving a resolution without increasing the operating frequency of the processing circuit of the brushless DC motor is highly needed, wherein the resolution can be the PWM resolution or the speed resolution.

Therefore, one of the objects of the present invention is to provide a method for increasing a resolution by N bits by a processing circuit of a motor drive system and a related motor drive system to solve the above-mentioned problem, wherein the resolution can be a pulse width modulation resolution or a rotational speed resolution, and N is a positive integer.

According to an embodiment of the present invention, a method is provided for improving a resolution by N bits through a processing circuit of a motor drive system, where N is a positive integer. The method may include: performing a conversion on an analog command to generate a command count value; performing a first N-bit right shift operation on the command count value to generate an initial output value; performing a logic operation on the command count value. Operation to generate a low bit value; generate an overflow value based on the low bit value; and determine a final output value based on the initial output value and the overflow value; wherein the motor drive system includes a processing circuit, a drive circuit and a In the brushless DC motor, each pulse width modulation signal of the plurality of pulse width modulation signals is output from the processing circuit to the driving circuit according to the final output value, and a driving voltage is passed through the driving circuit according to the plurality of pulse width modulation signals. Produced to drive brushless DC motors.

According to an embodiment of the present invention, a motor drive system is provided. The motor drive system may include a brushless DC motor, a drive circuit, and a processing circuit for increasing a resolution by N bits. The drive circuit may be coupled to the brushless DC motor and may be used to generate a drive voltage according to a plurality of pulse width modulation signals, wherein the drive voltage is used to drive the brushless DC motor. The processing circuit can be coupled to the driving circuit and can be used to perform the following operations to increase a resolution by N bits: perform a conversion on an analog command to generate a command count value; perform an N-bit right shift operation on the command count value to generate an initial output value; perform a logical operation on the command count value to generate a low-bit value; generate an overflow value according to the low-bit value; determine a final output value according to the initial output value and the overflow value; and The final output value is used to output each pulse width modulation signal of the plurality of pulse width modulation signals to the driving circuit; wherein N is a positive integer; wherein the resolution and the analog command are respectively a pulse width modulation resolution and a pulse width modulation command, and the pulse width modulation command is used to control a voltage value of the driving voltage; or the resolution and the analog command are respectively a speed resolution and a speed command, and the speed command is used to control the speed of the brushless DC motor.

One of the advantages of the present invention is that the method of the present invention can improve the pulse width modulation resolution by X bits (for example, X is a positive integer) without increasing the operating frequency of the processing circuit, which can reduce the power consumption and manufacturing cost of the processing circuit and make the brushless DC motor run smoothly. In addition, the method of the present invention can improve the speed resolution by Y bits (for example, Y is a positive integer). Since the method of the present invention can achieve a speed that cannot be achieved with insufficient speed resolution, the speed ripple of the brushless DC motor can be improved. In addition, since the number of bits used to improve the pulse width modulation resolution or the speed resolution can be determined according to the design requirements, the design flexibility of the method of the present invention is quite large.

Figure 1 is a schematic diagram of a motor driving system 10 according to an embodiment of the present invention. As shown in FIG. 1 , the motor driving system 10 may include an input voltage generating circuit 50 , a processing circuit 100 (such as a micro control unit (MCU)), a driving circuit 110 and a brushless DC motor ( brushless direct current (DC) motor) 120, wherein the brushless DC motor 120 may include a rotor (not shown) and a stator 122. The rotor may be a permanent magnet, and the stator 122 may be a three-phase stator. winding. The stator 122 may have a star connection structure (Y-connection structure) or a delta-connection structure (delta-connection structure), and may include a stator winding a, a stator winding b, and a stator winding c. In this embodiment, The stator 122 has a star connection structure, but the present invention is not limited to this.

The input voltage generating circuit 50 can be coupled to the processing circuit 100 and the driving circuit 110, and can be used to generate an input voltage V_IN, and output the input voltage V_IN to the processing circuit 100 and the driving circuit 110. For example, the input voltage generating circuit 50 It may include an alternating current (AC) power supply 52 and a bridge circuit 54. The bridge circuit 54 may be used to receive an AC voltage V_AC from the AC power supply 52 and process the AC voltage V_AC to generate the output voltage V_IN. However, the invention is not limited thereto. this. The processing circuit 100 can be coupled to the driving circuit 110 and can be used to output a series of pulse width modulation (pulse width modulation, PWM) signals PWM_1 ~ PWM_N (N ≥ 1) to the driving circuit 110 . The driving circuit 110 can be coupled to the stator 122 of the brushless DC motor 120 (especially, the stator winding a, the stator winding b and the stator winding c), and can be used to generate a driving voltage V_DRV according to the pulse width modulation signals PWM_1~PWM_N. To drive the brushless DC motor 120 , the driving voltage V_DRV is proportional to the rotation speed of the brushless DC motor 120 . For example, the driving circuit 110 may include a gate driver circuit 112 and a power transistor circuit 114 , wherein the gate driver circuit 112 may be coupled to the processing circuit 100 , and the power transistor circuit 114 may be coupled to the bridge circuit 54 , the gate driver circuit 112 and the stator 122 of the brushless DC motor 120 (especially, the stator winding a, the stator winding b and the stator winding c), and may be used to receive the input voltage V_IN.

The motor driving system 10 may further include a shunt resistor R ₁ , wherein one end of the shunt resistor R ₁ may be coupled to the power transistor circuit 114 , and the other end of the shunt resistor R ₁ may be coupled to a reference voltage ( For example, a ground voltage GND). The processing circuit 100 can be coupled to both ends of the shunt resistor R ₁ and can be used to receive a plurality of feedback currents from the brushless DC motor 120 through the shunt resistor R ₁ .

Assume that the processing circuit 100 is an integer system, the operating frequency of the processing circuit 100 is 32 megahertz (MHz), and the operating frequency of the pulse width modulation signals PWM_1 ~ PWM_N is 100 kilohertz (kHz), where the processing The circuit 100 receives an analog command (for example, a pulse width modulation command). The pulse width modulation command is a 16-bit signed number (that is, the maximum value of the pulse width modulation command is 32767 (2 ¹⁵ -1) ) for controlling the voltage value of the driving voltage V_DRV, and a pulse width modulation count value of the processing circuit 100 is 320 (that is, 32 MHz/100 kHz). The processing circuit 100 may execute an algorithm to perform a method for increasing the pulse width modulation resolution by X bits without increasing the operating frequency of the processing circuit 100 , where X may be a positive integer (i.e., X ≥ 1), and the algorithm can be expressed as follows: Among them, PWM _OUT is an output of each pulse width modulation signal of the pulse width modulation signals PWM_1~PWM_N (that is, a pulse width modulation output value), PWM _COMMAND is the pulse width modulation command, and PWM _COUNT is the pulse width modulation command. variable count value, and ">>X" represents an X bit right shift operation.

For better understanding, in this embodiment, it is assumed that the pulse width modulation resolution is increased by 15 bits through the algorithm (that is, X = 15), and the number of pulse width modulation signals PWM_1~PWM_N is 9 ( That is, N=9), and for each pulse width modulation signal of the pulse width modulation signals PWM_1~PWM_9, the pulse width modulation command is 24444. Table I PWM_1 PWM_2 PWM_3 PWM_4 PWM_5 PWM_6 PWM_7 PWM_8 PWM_9 LBV 23296 23296 23296 23296 23296 23296 23296 23296 23296 RLBV 23296 13825 4354 27650 18179 8708 32004 22533 13062 PWM _OUT 238 239 239 238 239 239 238 239 239

Table 1 illustrates an example of relevant values related to a method for improving the pulse width modulation resolution by 15 bits by executing an algorithm on the processing circuit 100 . For example, for the pulse width modulation signal PWM_1, the pulse width modulation command (ie 24444) and the pulse width modulation count value (ie 320) are multiplied to generate a command count value CCV (ie CCV = PWM _COMMAND * PWM _COUNT = 24444 * 320 = 7822080), and perform a 15-bit right shift operation on the command count value CCV to generate an initial output value IOV (that is, IOV = (PWM _COMMAND * PWM _COUNT ) >> 15 = 7822080 >> 15 = 238), then perform an AND operation on the command count value CCV and 2 ¹⁵ -1 to generate a low bit value LBV (that is, LBV = 7822080 & (2 ¹⁵ -1) = 23296 ), and accumulate (accumulate) the low bit value LBV to generate an accumulated low bit value ALBV. For the pulse width modulation signal PWM_1, the pulse width modulation signal PWM_1 is a series of pulse width modulation signals PWM_1~PWM_9. The first pulse width modulation signal of Overflow value (overflow value) OV (that is, OV = 23296 >> 15 = 0), where the overflow value OV can be 0 or 1.

According to the overflow value OV is 1, add 1 to the initial output value IOV to generate the pulse width modulation output value (that is, if OV = 1, then PWM _OUT = IOV + 1), and the accumulated low-bit value ALBV and 2 ¹⁵ -1 performs an AND operation to generate a remaining low bit value RLBV (that is, ALBV & (2 ¹⁵ -1) = RLBV), in which the remaining low bit value RLBV is accumulated to the next pulse width modulation signal . Since the overflow value OV is 0, the pulse width modulation output value is equal to the initial output value IOV (that is, if OV = 0, then PWM _OUT = IOV), and the accumulated low-bit value ALBV is used as the remaining low-bit value RLBV to be accumulated to the next pulse width modulation signal. For the pulse width modulation signal PWM_1, since the overflow value OV is 0, the pulse width modulation output value is equal to the initial output value IOV (that is, PWM _OUT = IOV = 238), and the accumulated low bit value ALBV (= 23296) is accumulated into the pulse width modulation signal PWM_2 as the remaining low bit value RLBV.

For the pulse width modulation signal PWM_2, the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_2 are the same as the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_1, that is, the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_2 are equal to 7822080, 238 and 23296 respectively. For the sake of brevity, similar contents will not be repeated here in detail. It should be noted that the remaining low-bit value RLBV (=23296) of the pulse width modulation signal PWM_1 is accumulated to the low-bit value LBV (=23296) of the pulse width modulation signal PWM_2 to generate the accumulated low-bit value ALBV of the pulse width modulation signal PWM_2 (ie, ALBV = 23296 + 23296 = 46592). Next, a 15-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV (i.e., OV = 46592 >> 15 = 1). Since the overflow value OV is 1, 1 is added to the initial output value IOV to generate a pulse width modulation output value (i.e., PWM _OUT = 238 + 1 = 239), and an AND operation is performed on the accumulated low-bit value ALBV and 2 ¹⁵ -1 to generate a residual low-bit value RLBV (i.e., RLBV = 46592 & (2 ¹⁵ -1) = 13825), wherein the residual low-bit value RLBV is accumulated to the pulse width modulation signal PWM_3.

For the pulse width modulation signal PWM_3, the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_3 are the same as the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_1, that is, the command count value CCV, the initial output value IOV and the low-bit value LBV of the pulse width modulation signal PWM_3 are equal to 7822080, 238 and 23296 respectively. For the sake of brevity, similar contents will not be repeated in detail here. It should be noted that the remaining low-bit value RLBV (=13825) of the pulse width modulation signal PWM_2 is accumulated to the low-bit value LBV (=23296) of the pulse width modulation signal PWM_3 to generate the accumulated low-bit value ALBV of the pulse width modulation signal PWM_3 (ie, ALBV = 23296 + 13825 = 37121). Next, a 15-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV (i.e., OV = 37121 >> 15 = 1). Since the overflow value OV is 1, 1 is added to the initial output value IOV to generate a pulse width modulation output value (i.e., PWM _OUT = 238 + 1 = 239), and an AND operation is performed on the accumulated low-bit value ALBV and 2 ¹⁵ -1 to generate a residual low-bit value RLBV (i.e., RLBV = 37121 & (2 ¹⁵ -1) = 4354), wherein the residual low-bit value RLBV is accumulated to the pulse width modulation signal PWM_4. For the sake of brevity, similar contents of the pulse width modulation signals PWM_4~PWM_9 will not be repeated in detail.

In this embodiment, when the PWM command is 24444, the ideal PWM output value is (24444/32767) * 320 = 238.718. For the method of the present invention, an average PWM output value of the PWM signals PWM_1 to PWM_9 is 238.67 (238 + 239 + 239 + 238 + 239 + 239 + 238 + 239 + 239 / 9 = 238.67). Considering a case where the processing circuit 100 executes a conventional algorithm, the conventional algorithm can be expressed as follows: The pulse width modulation output values of the pulse width modulation signals PWM_1 to PWM_9 are all equal to 238, and an average pulse width modulation output value of the pulse width modulation signals PWM_1 to PWM_9 is 238 (238 + 238 + 238 + 238 + 238 + 238 + 238 + 238 / 9 = 238), which sacrifices the accuracy of 0.718 (238.718 – 238 = 0.718).

Compared with this case, the average PWM output value of the method of the present invention only sacrifices 0.051 accuracy (238.718 – 238.67 = 0.051), which is much smaller than the accuracy sacrificed by the existing algorithm. In addition, the method of the present invention can determine the number of bits used to improve the PWM resolution according to design requirements. Therefore, the design flexibility of the method of the present invention is quite large.

In addition to outputting the pulse width modulation signals PWM_1-PWM_N to the driving circuit 110 for generating the driving voltage V_DRV for driving the brushless DC motor 120, the processing circuit 100 can also be used to output the pulse width modulation signals PWM_1-PWM_N according to a plurality of feedback currents received from the brushless DC motor 120 through the shunt resistor _R1 to control the angle (i.e., the rotation speed) of the brushless DC motor 120. In the angle calculation of the brushless DC motor performed by the processing circuit 100, the angle of the brushless DC motor 120 can be obtained by using the plurality of feedback currents to look up a table, so the rotation speed resolution of the processing circuit 100 may be limited by the least significant bit (LSB) of the angle.

Assume that the least significant bit of the angle is a 16-bit unsigned number, an analog command (e.g., a speed command RC for controlling the speed of the brushless DC motor 120) is also a 16-bit unsigned number (i.e., the number of speed commands RC (=65536) corresponds to 360 degrees), the sampling frequency of the processing circuit 100 is 50 kHz (i.e., the sampling period of the processing circuit 100 is 0.00002 seconds), and the pole number (pole) of the brushless DC motor 120 is 5. For the speed command RC, in the processing circuit 100, a unit angle is approximately equal to 0.0055 degrees (360 degrees / 65535 = 0.0055 degrees), and a speed resolution is approximately equal to 274.66 degrees/second (0.0055 / 0.00002 = 274.66 degrees/second), wherein the speed resolution can be converted into 9.155 revolutions per minute (RPM) ((274.66 / 360 / 5) * 60 = 9.155 RPM), that is, when the speed command RC is 1 or the change in the speed command RC is 1 (for example, from 1 to 2), the brushless DC motor 120 can operate at 9.155 RPM. However, when the speed resolution of the processing circuit 100 is 9.155 RPM, if the speed of the brushless DC motor 120 is controlled at 100 RPM by the processing circuit 100, the speed ripple of the brushless DC motor 120 will be very large, which may affect the output efficiency of the brushless DC motor 120. Therefore, in addition to the pulse width modulation resolution, the processing circuit 100 can execute another algorithm to perform a method for increasing the speed resolution of the processing circuit 100 by Y bits, where Y can be a positive integer (i.e., Y ≥ 1), and Y can be different from the above X. In addition, the method of the present invention can determine the number of bits used to increase the speed resolution according to the design requirements, so the design flexibility of the method of the present invention is quite large.

Please refer to Figure 2. Figure 2 is a schematic diagram of a processing circuit 200 according to an embodiment of the present invention. The processing circuit 100 shown in Figure 1 can be implemented by the processing circuit 200 shown in Figure 2. As shown in Figure 2, the processing circuit 200 may include a plurality of circuits, such as an improved resolution speed command module 210, a control loop 212, an enhanced resolution feedback calculation module 214, a high resolution There is a degree voltage conversion module 220, a high-resolution angle conversion module 230 and a pulse width modulation generation circuit 240. After the resolution is improved, the speed command module 210 can be used to receive the speed command RC and perform a Y on the speed command RC. A bit left shift operation is performed to generate an amplified rotational speed command ARC.

Assuming that the speed command RC is a 16-bit unsigned number and Y is equal to 3, after the speed command RC is shifted left by 3 bits, the amplified speed command ARC can be generated, and the number of the amplified speed command ARC (65536 << 3 = 524288) corresponds to 360 degrees, wherein when the speed resolution corresponding to the speed command RC is 9.155 RPM, the speed resolution corresponding to the amplified speed command ARC is 1.144 RPM (9.155 / 8 = 1.144), that is, when the amplified speed command ARC is 1, the brushless DC motor 120 can operate at 1.144 RPM.

The control loop 212 can be used to calculate how much voltage (such as the voltage value of the driving voltage V_DRV) needs to be output to the brushless DC motor 120 according to a feedback signal FS (such as a plurality of feedback currents) to obtain the pulse width modulation command ( Labeled "PWM_C" in Figure 2 for brevity). The high-resolution voltage conversion module 220 can receive the pulse width modulation command from the control loop 212 and execute the above algorithm to perform the method of improving the pulse width modulation resolution by X bits. For simplicity, Similar content will not be described in detail here.

The improved resolution feedback calculation module 214 can be used to calculate the angle and feedback speed of the brushless DC motor 120 based on a plurality of feedback currents and amplified speed commands ARC to generate a feedback calculation result FCR. The high-resolution angle conversion module 230 can be used to execute another algorithm according to the feedback calculation result FCR to perform a method for improving the speed resolution in the processing circuit 200 by Y bits, where Y can be a positive integers (e.g. Y = 3), and this alternative algorithm can be expressed as follows: Among them, COMMAND _ANGLE is an output of the high-resolution angle conversion module 230, REAL _VELOCITY is the amplified rotational speed command ARC, and ">>Y" represents a Y-bit right shift operation. Table II n=0 n=1 n=2 n=3 n=4 n=5 n=6 n=7 LBV 1 1 1 1 1 1 1 1 RLBV 1 2 3 4 5 6 7 0 COMMAND _ANGLE 0 0 0 0 0 0 0 1

Table 2 illustrates an example of relevant values related to the method of improving the rotational speed resolution by 3 bits by executing the algorithm of the processing circuit 200 . For better understanding, it is assumed that the number of samplings performed by the processing circuit 200 is 8, and for each sampling, the amplified rotational speed command ARC is 1. For the first sampling (marked as "n=0" in Table 2), a 3-bit right shift operation is performed on the amplified speed command ARC to generate an initial output value IOV (that is, IOV = REAL _VELOCITY > ＞ 3 = 1 ＞＞ 3 = 0)), and perform an AND operation on the amplified speed command ARC and 2 ³ -1 to generate a low-bit value LBV (that is, LBV = 1 & (2 ³ -1 ) = 1), then, accumulate the low bit value LBV to generate an accumulated low bit value ALBV. For the first sampling (n = 0), the accumulated low bit value ALBV is equal to the low bit value LBV (that is, ALBV = LBV = 1), finally, perform a 3-bit right shift operation on the accumulated low-bit value ALBV to generate an overflow value OV (that is, OV = 1 >> 3 = 0), where the overflow value OV can be is 0 or 1.

According to the overflow value OV is 1, add 1 to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (that is, if OV = 1, then COMMAND _ANGLE = IOV + 1), and the accumulated low bit The element value ALBV and 2 ³ -1 perform an AND operation to generate a remaining low-bit value RLBV (that is, ALBV & (2 ³ -1) = RLBV), in which the remaining low-bit value RLBV is accumulated to the next Sampling. Since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, if OV = 0, then COMMAND _ANGLE = IOV), and the accumulated low-bit value ALBV is used as the remainder. The low bit value RLBV is accumulated to the next sample. For the first sampling (n = 0), since the overflow value OV is 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE = IOV = 0), and is accumulated The last low-bit value ALBV (ALBV = 1) is accumulated to the second sample (marked as “n=1” in Table 2) as the remaining low-bit value RLBV.

For the second sampling (n=1), the initial output value IOV and low-bit value LBV of the second sampling are the same as the initial output value IOV and low-bit value LBV of the first sampling, that is, the second sampling The sampled initial output value IOV and the low-bit value LBV are 0 and 1 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low-bit value RLBV of the first sampling (that is, RLBV = 1) is accumulated to the low-bit value LBV of the second sampling (that is, LBV = 1) to produce the accumulated value of the second sampling. The low-bit value ALBV (that is, ALBV = 1 + 1 = 2), and then a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV = 2 >> 3 = 0 ), corresponding to the overflow value OV being 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE = IOV = 0), and the accumulated low-bit value ALBV is used as the remaining low-bit value RLBV to be accumulated to the 3rd sampling (marked as “n=2” in Table 2). For the sake of simplicity, for the 3rd to 7th sampling (marked as “n=6” in Table 2) Similar content will not be described in detail here.

For the 8th sampling (marked as "n=7" in Table 2), the initial output value IOV and the low-bit value LBV of the 8th sampling are the same as the initial output value IOV and the low-bit value LBV of the 1st sampling, that is, the initial output value IOV and the low-bit value LBV of the 8th sampling are 0 and 1, respectively. For the sake of brevity, similar content will not be repeated in detail here. It should be noted that the residual low-bit value RLBV of the 7th sample (n=6) (i.e., RLBV = 7) is accumulated to the low-bit value LBV of the 8th sample (i.e., LBV = 1) to generate the accumulated low-bit value ALBV of the 8th sample (i.e., ALBV = 1 + 7 = 8). Then, a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (i.e., OV = 8 >> 3 = 1). Since the overflow value OV is 1, 1 is added to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (i.e., COMMAND _ANGLE = 0 + 1 = 1).

When the output of the high-resolution angle conversion module 230 is equal to 0, the brushless DC motor 120 will operate at 0 RPM, and when the output of the high-resolution angle conversion module 230 is equal to 1, the brushless DC motor 120 will operate at 9.155 RPM. In 8 samplings, the average speed of the brushless DC motor 120 is 1.144 RPM ((0 + 0 + 0 + 0 + 0 + 0 + 0 + 9.155) / 8 = 1.144). In this way, although the actual speed of the brushless DC motor 120 is still 9.155 RPM, the method of the present invention can be used to achieve a speed that cannot be achieved due to insufficient speed resolution (for example, 1.144 RPM) during the 8 samplings. Therefore, the speed ripple of the brushless DC motor 120 can be improved. Table 3 n=0 n=1 n=2 n=3 n=4 n=5 n=6 n=7 LBV 2 2 2 2 2 2 2 2 R 2 4 6 0 2 4 6 0 COMMAND _ANGLE 0 0 0 1 0 0 0 1

Table 3 shows another example of the relevant values involved in the method for increasing the speed resolution by 3 bits by the algorithm executed by the processing circuit 200. For better understanding, it is assumed that the number of samples performed by the processing circuit 200 is 8, and for each sample, the amplified speed command ARC is 2 (which corresponds to 2.288 RPM). For the first sampling (marked as "n=0" in Table 3), a 3-bit right shift operation is performed on the amplified rotation speed command ARC to generate an initial output value IOV (i.e., IOV = REAL _VELOCITY >> 3 = 2 >> 3 = 0), and an AND operation is performed on the amplified rotation speed command ARC and 2 ³ -1 to generate a low-bit value LBV (i.e., LBV = 2 & (2 ³ -1) = 2). Then, the low-bit value LBV is accumulated to generate an accumulated low-bit value ALBV. For the first sampling (n = 0), the accumulated low-bit value ALBV is equal to the low-bit value LBV (i.e., ALBV = LBV = 2). Finally, a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV (i.e., OV = 2 >> 3 = 0). In response to the overflow value OV being 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (i.e., COMMAND _ANGLE = IOV = 0), and the accumulated low-bit value ALBV (i.e., ALBV = 2) is accumulated to the second sampling (marked as "n=1" in Table 3) as the residual low-bit value RLBV.

For the second sampling (n=1), the initial output value IOV and low-bit value LBV of the second sampling are the same as the initial output value IOV and low-bit value LBV of the first sampling, that is, the second sampling The sampled initial output value IOV and the low-bit value LBV are 0 and 2 respectively. For the sake of simplicity, similar content will not be described in detail here. It should be noted that the remaining low-bit value RLBV of the first sample (that is, RLBV = 2) is accumulated to the low-bit value LBV of the second sample (that is, LBV = 2) to generate the accumulation of the second sample. Then, a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (that is, OV = 4 >> 3 = 0), corresponding to the overflow value OV being 0, the output of the high-resolution angle conversion module 230 is equal to the initial output value IOV (that is, COMMAND _ANGLE = IOV = 0), and the accumulated low bit value ALBV (that is, ALBV = 4) As the remaining low bit value RLBV, it is accumulated to the third sampling (marked as "n=2" in Table 3). For the sake of brevity, the similar content of the third sampling will not be described in detail here. .

For the 4th sampling (marked as "n=3" in Table 3), the initial output value IOV and the low-bit value LBV of the 4th sampling are the same as the initial output value IOV and the low-bit value LBV of the 1st sampling, that is, the initial output value IOV and the low-bit value LBV of the 4th sampling are 0 and 2 respectively. For the sake of brevity, similar content will not be repeated in detail here. It should be noted that the residual low-bit value RLBV of the third sampling (n=2) (i.e., RLBV = 6) is accumulated to the bit value LBV of the fourth sampling (i.e., LBV = 2) to generate the accumulated low-bit value ALBV of the fourth sampling (i.e., ALBV = 2 + 6 = 8). Then, a 3-bit right shift operation is performed on the accumulated low-bit value ALBV to generate the overflow value OV (i.e., OV = 8 >> 3 = 1). Since the overflow value OV is 1, 1 is added to the initial output value IOV to generate the output of the high-resolution angle conversion module 230 (i.e., COMMAND _ANGLE = 0 + 1 = 1), and an AND operation is performed on the accumulated low-bit value ALBV and 2 ³ -1 to generate the residual low-bit value RLBV (i.e., RLBV = 8 & (2 ³ -1) = 0), where the remaining low-bit value RLBV is accumulated to the next sampling.

Similarly, for the 5th sample (labeled as “n=4” in Table 3) to the 8th sample (labeled as “n=7” in Table 3), the outputs of the high-resolution angle conversion module 230 are 0, 0, 0, and 1, respectively. When the output of the high-resolution angle conversion module 230 is 0, the brushless DC motor 120 will operate at 0 RPM, and when the output of the high-resolution angle conversion module 230 is 1, the brushless DC motor 120 will operate at 9.155 RPM. In 8 samplings, the average speed of the brushless DC motor 120 is 2.288 RPM ((0 + 0 + 0 + 9.155 + 0 + 0 + 0 + 9.155) / 8 = 2.288). In this way, although the actual speed of the brushless DC motor 120 is still 9.155 RPM, the method of the present invention can be used to achieve a speed (for example, 2.288 RPM) that cannot be achieved due to insufficient speed resolution during the 8 samplings. Therefore, the speed ripple of the brushless DC motor 120 can be improved.

The pulse width modulation generating circuit 240 can be used to receive a high-resolution voltage conversion result HVR and a high-resolution angle conversion result HAR from the high-resolution voltage conversion module 220 and the high-resolution angle conversion module 230 respectively to generate pulse width modulation signals PWM_1~PWM_N, and output the pulse width modulation signals PWM_1~PWM_N to the driving circuit 110. For the sake of brevity, similar contents of this embodiment will not be repeated in detail.

FIG. 3 is a flow chart of a method for improving pulse width modulation resolution by X bits according to an embodiment of the present invention, where X is a positive integer. If the same result can be obtained, the steps do not have to be executed in sequence according to the process shown in Figure 3. For example, the method shown in Figure 3 can be performed by the processing circuit 100 shown in Figure 1 or the processing circuit 100 shown in Figure 1. This is achieved by using the processing circuit 200 (especially the high-resolution voltage conversion module 220) shown in FIG. 2 .

In step S300, the control loop 212 receives a PWM command.

In step S302, the PWM command is multiplied by a PWM count value to generate a command count value CCV, wherein the PWM count value is generated by dividing an operating frequency of the processing circuit 200 by an operating frequency of the PWM signal.

In step S304, an X-bit right shift operation is performed on the command count value CCV to generate an initial output value IOV.

In step S306, an AND operation is performed on the command count value CCV and 2 ^x -1 to generate a low bit value LBV.

In step S308, the low bit value LBV is accumulated to generate an accumulated low bit value ALBV.

In step S310, an X-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV.

In step S312, in response to the overflow value OV being 1, 1 is added to the initial output value IOV to generate a PWM output value, and in response to the overflow value OV being 0, the PWM output value is equal to the initial output value IOV.

Since a skilled person can easily understand the operation of each step shown in FIG. 3 through the above description of the processing circuit 100 shown in FIG. 1 or the processing circuit 200 shown in FIG. 2, for the sake of brevity, similar contents in this embodiment will not be repeated here.

Figure 4 is a flowchart of a method for improving the speed resolution by Y bits according to an embodiment of the present invention, where Y is a positive integer. If the same result can be obtained, the steps do not have to be executed in sequence according to the process shown in Figure 4. For example, the method shown in Figure 4 can be performed by the processing circuit 100 shown in Figure 1 or the processing circuit 100 shown in Figure 1. This is implemented by the processing circuit 200 shown in Figure 2 (especially, the high-resolution angle conversion module 230).

In step S400, a rotation speed command RC is received by the processing circuit 200, and a Y-bit left shift operation is performed on the rotation speed command RC to generate an amplified rotation speed command ARC.

In step S402, a Y-bit right shift operation is performed on the amplified rotational speed command ARC to generate an initial output value IOV.

In step S404, an AND operation is performed on the amplified rotation speed command ARC and 2 ^Y - 1 to generate a low bit value LBV.

In step S406, the low-bit value LBV is accumulated to generate an accumulated low-bit value ALBV.

In step S408, a Y-bit right shift operation is performed on the accumulated low-bit value ALBV to generate an overflow value OV.

In step S410, in response to the overflow value OV being 1, 1 is added to the initial output value IOV to generate an output of the high-resolution angle conversion module 230, and in response to the overflow value OV being 0, the high-resolution angle conversion module This output of 230 is equal to the initial output value IOV.

Since those skilled in the art can easily understand the operations of each step shown in Figure 4 through the above description of the processing circuit 100 shown in Figure 1 or the processing circuit 200 shown in Figure 2, for the sake of simplicity, here Similar content in the embodiment will not be repeated here.

In summary, the method of the present invention can improve the pulse width modulation resolution by X bits (for example, X is a positive integer) without increasing the operating frequency of the processing circuit, which can reduce the power consumption and manufacturing cost of the processing circuit and make the brushless DC motor run smoothly. In addition, the method of the present invention can improve the speed resolution by Y bits (for example, Y is a positive integer). Since the method of the present invention can achieve a speed that cannot be achieved with insufficient speed resolution, the speed ripple of the brushless DC motor can be improved. In addition, since the number of bits used to improve the pulse width modulation resolution or the speed resolution can be determined according to the design requirements, the design flexibility of the method of the present invention is quite large. The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Motor drive system 50: Input voltage generation circuit 52: AC power supply 54: Bridge circuit 100, 200: Processing circuit 110: Drive circuit 112: Gate driver circuit 114: Power transistor circuit 120: Brushless DC motor 122: Stator PWM_1~PWM_N: Pulse width modulation signal V_AC: AC voltage V_IN: Input voltage V_DRV: Drive voltage R ₁ : Shunt resistor GND: Ground voltage a, b, c: Stator winding 210: Speed command module 212 after improving resolution: Control loop 214: Improved resolution feedback calculation module 220: High-resolution voltage conversion module 230: High-resolution angle conversion module 240: Pulse width modulation generation circuit RC: Speed command ARC: Amplified speed command FS: Feedback signal PWM_C: Pulse width modulation command FCR: Feedback calculation result HVR: High-resolution voltage conversion result HAR: High-resolution angle conversion result S300~S312, S400~S410: Steps

Figure 1 is a schematic diagram of a motor driving system according to an embodiment of the present invention. Figure 2 is a schematic diagram of a processing circuit according to an embodiment of the present invention. FIG. 3 is a flow chart of a method for improving pulse width modulation resolution by X bits according to an embodiment of the present invention. FIG. 4 is a flowchart of a method for improving rotational speed resolution by Y bits according to an embodiment of the present invention.

S300~S312: steps

Claims (14)

A method for improving a resolution by N bits through a processing circuit of a motor drive system, where N is a positive integer, and the method includes: perform a conversion on an analog command to generate a command count value; Perform a first N-bit right shift operation on the command count value to generate an initial output value; Perform a logical operation on the command count value to generate a low-bit value; Generate an overflow value based on the low bit value; and Determine a final output value based on the initial output value and the overflow value; The motor driving system includes the processing circuit, a driving circuit and a brushless DC motor, and each pulse width modulation signal of the plurality of pulse width modulation signals is output from the processing circuit to the driver according to the final output value. circuit, and a driving voltage is generated by the driving circuit according to the plurality of pulse width modulation signals for driving the brushless DC motor. As described in the method described in item 1 of the patent application, the resolution is a pulse width modulation resolution, and the analog command is a pulse width modulation command for controlling a voltage value of the driving voltage. As described in the method of item 2 of the patent application scope, the step of converting the analog command to generate the command count value includes: Multiplying the pulse width modulation command with a pulse width modulation count value to generate the command count value, wherein the pulse width modulation count value is generated by dividing an operating frequency of the processing circuit by an operating frequency of the plurality of pulse width modulation signals. For the method described in item 2 of the patent application, the step of performing the logical operation on the command count value to generate the low-bit value includes: performing an AND (AND) on the command count value and 2 ^N -1 Operate to produce the low-bit value. As described in item 2 of the patent application scope, the step of generating the overflow value according to the low-bit value includes: Accumulating the low-bit value to generate an accumulated low-bit value; and Performing a second N-bit right shift operation on the accumulated low-bit value to generate the overflow value. As described in item 2 of the patent application scope, the step of determining the final output value based on the initial output value and the overflow value includes: In response to the overflow value being 1, adding 1 to the initial output value to generate the final output value. For the method described in item 2 of the patent application, the steps of determining the final output value based on the initial output value and the overflow value include: Since the overflow value is 0, the final output value is equal to the initial output value. The method as described in claim 1, wherein the resolution is a speed resolution, and the analog command is a speed command for controlling the speed of the brushless DC motor. As described in item 8 of the patent application scope, the step of converting the analog command to generate the command count value includes: Performing an N-bit left shift operation on the speed command to generate an amplified speed command as the command count value. For the method described in item 8 of the patent application, the step of performing the logical operation on the command count value to generate the low-bit value includes: performing an AND (AND) on the command count value and 2 ^N -1 Operate to produce the low-bit value. As described in item 8 of the patent application scope, the step of generating the overflow value according to the low-bit value includes: Accumulating the low-bit value to generate an accumulated low-bit value; and Performing a second N-bit right shift operation on the accumulated low-bit value to generate the overflow value. For the method described in Item 8 of the patent application, the steps of determining the final output value based on the initial output value and the overflow value include: Since the overflow value is 1, 1 is added to the initial output value to generate the final output value. As described in item 8 of the patent application scope, the step of determining the final output value based on the initial output value and the overflow value includes: In response to the overflow value being 0, the final output value is equal to the initial output value. A motor drive system including: a brushless DC motor; A driving circuit coupled to the brushless DC motor and used to generate a driving voltage according to a plurality of pulse width modulation signals, wherein the driving voltage is used to drive the brushless DC motor; and A processing circuit is coupled to the driving circuit and used to perform the following operations to increase a resolution by N bits: perform a conversion on an analog command to generate a command count value; Perform an N-bit right shift operation on the command count value to generate an initial output value; Perform a logical operation on the command count value to generate a low-bit value; Generate an overflow value based on the low-bit value; Determine a final output value based on the initial output value and the overflow value; and Output each pulse width modulation signal of the plurality of pulse width modulation signals to the driving circuit according to the final output value; Where N is a positive integer; wherein the resolution and the analog command are respectively a pulse width modulation resolution and a pulse width modulation command, and the pulse width modulation command is used to control a voltage value of the driving voltage; or the resolution and the analog The commands are respectively a rotational speed resolution and a rotational speed command, and the rotational speed command is used to control the rotational speed of the brushless DC motor.

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