TWI832355B - Input clock buffer and clock signal buffereing method - Google Patents

Abstract

An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

Description

Input clock buffer and clock signal buffering method

The present invention relates to an input clock buffer and a clock signal buffering method, and in particular to an input clock buffer and a clock signal buffering method that can compensate for the DC (Direct Current) level of a differential input signal.

A conventional input clock buffer is used to provide an output clock signal with a desired duty ratio. However, if one of the input terminals of the input clock buffer is coupled to a predetermined voltage level (for example, ground potential), or the DC level of the input signal received at the input terminal changes unexpectedly, the output clock signal may account for The air ratio may become inaccurate.

Therefore, an object of the present invention is to provide an input clock buffer that can generate a clock signal with a precise duty cycle.

Another object of the present invention is to provide a clock signal buffering method that can generate a clock signal with a precise duty cycle.

An embodiment of the present invention provides an input clock buffer, including: a first capacitor: a second capacitor: a first amplifier for generating a first output signal, including coupling the first capacitor a first input terminal and a second input terminal coupled to the second capacitor, wherein the first capacitor and the second capacitor receive a differential input signal and form a first pair of signal paths for the differential input signal ; A second amplifier, used to generate a second output signal, including a first input terminal and a second input terminal, wherein the first input terminal of the second amplifier and the second input terminal of the second amplifier a second pair of signal paths forming the differential input signal; a frequency detection circuit for generating a frequency detection signal according to a frequency of the differential input signal; and a switch located at an output of the first amplifier and an output of the second amplifier for turning on or off according to the frequency detection signal.

Another embodiment of the present invention provides a clock signal buffering method, including: (a) filtering a DC part of a differential input signal; (b) after filtering the DC part, using a first The input terminal of an amplifier forms a first pair of signal paths for the differential input signal; (c) the first amplifier is used to generate a first output signal; (d) the input terminal of a second amplifier is used to form the differential input a second pair of signal paths for signals; (e) generating a second output signal with the second amplifier; (f) generating a frequency detection signal based on a frequency of the differential input signal; and (g) based on the frequency The detection signal is selectively coupled to an output of the first amplifier and an output of the second amplifier.

According to the aforementioned embodiments, even if the DC level of the differential input signal changes, the duty cycle of the output clock signal can remain accurate.

100, 400: Input clock buffer

200:Circuit

103: Frequency detection circuit

AP1: first amplifier

AP2: Second amplifier

AP3: The third amplifier

AP4: The fourth amplifier

AP5: fifth amplifier

AP6: The sixth amplifier

C1: first capacitor

C2: second capacitor

C3: The third capacitor

C4: The fourth capacitor

C5: The fifth capacitor

C6: The sixth capacitor

DCLK: differential clock signal

DIN: Differential input signal

FD: frequency detection signal

IN1: first input signal

IN2: second input signal

IN1': signal

OS1: first output signal

OS2: Second output signal

R1, R2, R3, R4: Resistors

RCLK: reference clock signal

SW: switch

X1: Delay circuit

XCLK, XCLKN: clock signal

FIG. 1 illustrates a block diagram of an input clock buffer according to an embodiment of the present invention.

FIG. 2 illustrates a circuit diagram of a circuit for providing the differential input signal shown in FIG. 1 according to an embodiment of the present invention.

Figure 3 is a schematic diagram illustrating how to generate the frequency detection signal shown in Figure 1 according to an embodiment of the present invention.

FIG. 4 illustrates a block diagram of an input clock buffer according to another embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the operation of the input clock buffer shown in FIG. 4 when the switch is turned off according to an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating the operation of the input clock buffer shown in FIG. 4 when the switch is turned on according to an embodiment of the present invention.

FIG. 7 illustrates a flow chart of a clock signal buffering method according to an embodiment of the present invention.

The content of the present invention will be described in multiple embodiments below. Please also note that the components in each embodiment can be implemented through hardware (such as a device or circuit) or firmware (such as at least one program written in a microprocessor). to implement. In addition, “first”, “second” and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps. It is not intended to limit the order. For example, the first device and the second device may be different devices having the same structure.

FIG. 1 illustrates a block diagram of an input clock buffer according to an embodiment of the present invention. As shown in FIG. 1 , the input clock buffer 100 includes a first capacitor C1 , a second capacitor C2 , a first amplifier AP1 , a second amplifier AP2 , a frequency detection circuit 103 and a switch SW. The first amplifier AP1 is used to generate a first output signal OS1, which includes a first input terminal coupled to the first capacitor C1 and a second input terminal coupled to the second capacitor C2. The first capacitor C1 and the second capacitor C2 receive the differential input signal DIN and form a first pair of signal paths for the differential input signal DIN. As shown in Figure 1, the differential input signal DIN is composed of a first input signal IN1 and a second input signal IN2.

The second amplifier AP2 is used to generate the second output signal OS2, and also includes a first input terminal and a second input terminal. The first input terminal of the second amplifier AP2 and the second input terminal of the second amplifier AP2 form a second pair of signal paths for the differential input signal DIN. The frequency detection circuit 103 is used to generate a frequency detection signal FD according to the frequency of the differential input signal DIN. Switch SW is located between the output of the first amplifier AP1 and the second The output of the amplifier AP2 is used to turn on (conduct) and turn off (non-conduct) according to the frequency detection signal FD. Details of the frequency detection action are described below.

In the embodiment shown in FIG. 1 , the frequency detection circuit 103 generates the frequency detection signal FD according to the reference clock signal RCLK. The frequency of the reference clock signal RCLK corresponds to the frequency of the first output signal OS1, and the frequency of the first output signal OS1 corresponds to the frequency of the differential input signal DIN. Therefore, the frequency detection circuit 103 can generate the frequency detection signal FD according to the reference clock signal RCLK, thereby generating the frequency detection signal FD according to the frequency of the differential input signal DIN. However, please note that the frequency detection circuit 103 may generate the frequency detection signal FD according to the frequency of the differential input signal DIN through any other mechanism instead of the mechanism shown in FIG. 1 .

In one embodiment, if the frequency of the first output signal OS1 is lower than the critical frequency, the switch SW is turned on, and if the frequency of the first output signal OS1 is higher than the critical frequency, the switch SW is turned off. In other words, if the frequency of the first output signal OS1 is a low frequency, the switch SW is turned on, and if the frequency of the first output signal OS1 is a high frequency, the switch SW is turned off. In this way, since the first output signal OS1 and the second output signal OS2 are combined to generate the reference clock signal RCLK, if the switch SW is turned on when the first output signal OS1 has a low frequency, the second output signal OS2 can be combined with the reference clock signal RCLK. pulse signal RCLK. Therefore, non-ideal factors such as leakage current at the input end of the first amplifier AP1 can be improved.

In one embodiment, the first input signal IN1 is a clock signal, and the second input signal IN2 is an inverted signal of the first input signal IN1. However, the first input signal IN1 and the second input signal IN2 may be other types of signals. FIG. 2 illustrates a circuit diagram of a circuit for providing the differential input signal DIN shown in FIG. 1 according to an embodiment of the present invention. In the embodiment of FIG. 2, the circuit 200 for providing the differential input signal DIN includes a third capacitor C3, a fourth capacitor C4, a third amplifier AP3 and a fourth amplifier AP4. The third amplifier AP3 includes a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier AP3 and the second input terminal of the third amplifier AP3 form a third pair of signal paths of the differential clock signal DCLK. The differential clock signal DCLK is formed by the clock signal XCLK and the clock signal XCLKN, and the clock signal Signal XCLKN is the inverted signal of clock signal XCLK.

The fourth amplifier AP4 includes a first input terminal and a second input terminal, wherein the first input terminal of the fourth amplifier AP4 and the second input terminal of the fourth amplifier AP4 form a fourth signal path pair of the differential clock signal DCLK. . The differential input signal DIN is generated based on the output of the third amplifier AP3 and the output of the fourth amplifier AP4. Specifically, the first input signal IN1 that can be used to generate the differential input signal DIN is generated based on the outputs of the third amplifier AP3 and the fourth amplifier AP4.

In an embodiment, if the clock signal XCLK and the clock signal XCLKN received by the third amplifier AP3 both have changes (ie, have rising edges and falling edges), the first input signal IN1 is based on the output 3 of the third amplifier AP3 and the output of the fourth amplifier AP4. However, if one of the clock signal XCLK and the clock signal XCLKN does not change (ie, there is no rising edge or falling edge), for example, the clock signal XCLK is a predetermined voltage level, such as ground potential, then the third amplifier The output of AP3 will not reflect the difference between the clock signal XCLK and the clock signal XCLKN, but due to the existence of the third capacitor C3 and the fourth capacitor C4, the output of the fourth amplifier AP4 still reflects the clock signal XCLK and the clock signal Differences between XCLKN. In this case, since the outputs of the third amplifier AP3 and the fourth amplifier AP4 are connected together, the output of the third amplifier AP3 affects the value of the first input signal IN1. As a result, the duty cycle of the first input signal IN1 will be different from the duty cycle of the clock signal XCLKN.

In the embodiment of FIG. 2, the circuit 200 includes a fifth capacitor C5, a sixth capacitor C6, a fifth amplifier AP5 and a sixth amplifier AP6, but is not limited thereto. The fifth capacitor C5, the sixth capacitor C6, the fifth amplifier AP5 and the sixth amplifier AP6 can be used to generate the second input signal IN2, and its structure and operation are the same as the circuit that generates the first input signal IN1. Therefore, no further details will be given here.

In one embodiment, the input signal used to generate the differential input signal DIN may be generated by only one amplifier. For example, the first input signal IN1 or the second input signal IN2 may be generated only according to the amplifier having the third amplifier AP3 structure. For another example, the first input signal IN1 or the second input signal IN2 may be generated only according to the amplifier having the structure of the fourth amplifier AP4. Such changes should also fall within the scope of the present invention within the perimeter.

The frequency detection circuit 103 shown in Figure 1 can be implemented by various circuits. Please refer to FIG. 1 again. In one embodiment, the input clock buffer 100 further includes a delay circuit X1 for generating a delay signal of the first output signal OS1. If the switch SW is turned off, the delayed signal is the reference clock signal RCLK. If the switch SW is turned on, the reference clock signal RCLK is a combination of the first output signal OS1 and the second output signal OS2. The frequency detection circuit 103 generates the frequency detection signal FD according to the edge of the delayed signal.

Figure 3 is a schematic diagram illustrating how to generate the frequency detection signal FD shown in Figure 1 according to an embodiment of the present invention. In this case, the frequency detection circuit 103 may include multiple logic gates (such as NAND gates and NOR gates) and multiple inverters to perform the operations shown in FIG. 3 . As shown in Figure 3, the switch SW is turned on when the frequency detection signal FD is a high logic level, and is turned off when the frequency detection signal FD is a low logic level. In addition, the rising edge of the frequency detection signal FD corresponds to the delayed phase of the rising/falling edge of the reference clock signal RCLK. In one embodiment, there is a time difference td1 between the rising edge of the frequency detection signal FD and the rising edge of the reference clock signal RCLK. In addition, there is a time difference td2 between the next rising edge of the frequency detection signal FD and the falling edge of the reference clock signal RCLK.

Therefore, in the embodiment of FIG. 3, the time interval of the high logic level of the frequency detection signal FD can be set by setting the time differences td1 and td2. Furthermore, in the embodiment of Figure 3, the critical frequency can be set by setting the time differences td1 and td2. If the frequency of the reference clock signal RCLK is greater than the critical frequency, the single signal interval of the reference clock signal RCLK is reduced, and therefore the time interval in which the frequency detection signal FD has a high logic level is also reduced. If the time interval of the high logic level of the frequency detection signal FD is less than the time difference td1, the frequency detection signal FD remains at a low logic level, so the switch SW in Figure 2 remains closed. In other words, if the time difference td1 is a fixed value and the frequency of the reference clock signal RCLK is greater than the critical frequency, the switch SW in Figure 1 remains closed. The critical frequency can be set according to different circuit requirements. In one embodiment, the critical frequency is 200MHz.

Figure 4 illustrates blocks of an input clock buffer 400 according to another embodiment of the present invention. Figure. In addition to the components shown in FIG. 1 , the input clock buffer 400 also includes a DC level providing circuit coupled to the first capacitor C1 , the second capacitor C2 , the first input terminal and the second input terminal of the first amplifier AP1 end. The DC level providing circuit is used to provide a DC level to the differential input signal DIN after the DC part of the differential input signal DIN is filtered. In the embodiment of Figure 4, the DC level providing circuit includes resistors R1, R2, R3, R4, which form a voltage divider. In addition, in one embodiment, the resistors R1, R2, R3, and R4 provide a DC level of VDD/2.

FIG. 5 is a schematic diagram illustrating the operation of the input clock buffer shown in FIG. 4 when the switch is turned off according to an embodiment of the present invention. That is, in the embodiment of Figure 5, the frequency of the differential input signal DIN is higher than the critical frequency. Please note that to simplify the illustration, only the first input signal IN1 is shown, but the second input signal IN2 which is the inverted signal of the first input signal IN1 is not shown. In addition, the signal IN1' received by the first terminal of the first amplifier AP1 refers to a DC level signal provided by the DC level providing circuit after the DC part of the first input signal IN1 is filtered by the first capacitor C1.

As shown in Figure 5, the frequency detection signal FD remains at a low logic level, so the switch SW is closed. In this way, the output of the second amplifier AP2 is not coupled to the output of the first amplifier AP1, and the output clock signal input to the clock buffer 400 is only affected by the output of the first amplifier AP1. Therefore, the duty cycle of the output clock signal RCLK (reference clock signal) can be close to the desired value (the duty cycle of the first input signal IN1).

FIG. 6 is a schematic diagram illustrating the operation of the input clock buffer shown in FIG. 4 when the switch is turned on according to an embodiment of the present invention. That is, in the embodiment of Figure 6, the frequency of the differential input signal DIN is lower than the critical frequency. Please note that in order to simplify the illustration, only the first input signal IN1 is shown, but the second input signal IN2 which is the inverted signal of the first input signal IN1 is not shown. In addition, the signal IN1' received by the first terminal of the first amplifier AP1 refers to a DC level signal provided by the DC level providing circuit after the DC part of the first input signal IN1 is filtered by the first capacitor C1.

In the embodiment of Figure 6, due to the lower frequency of the differential input signal DIN, some leakage current may flow through the DC level supply circuit to ground. Therefore, the DC level of the first input signal IN1 decreases, The DC level of signal IN1' also decreases accordingly. In this case, the switch SW is turned on corresponding to the high logic level of the frequency detection signal FD. In this way, since the output terminal of the first amplifier AP1 is coupled to the output terminal of the second amplifier AP2, the DC level of the signal IN1' can be compensated.

Figure 7 illustrates a flow chart of a clock signal buffering method according to an embodiment of the present invention, including the following steps:

Step 701

Filtering a DC portion of a differential input signal DIN

Step 703

After filtering the DC part, a first pair of signal paths for the differential input signal DIN is formed with an input end of a first amplifier AP1.

Step 705

The first amplifier AP1 is used to generate the first output signal OS1.

Step 707

An input terminal of a second amplifier AP2 forms a second pair of signal paths for the differential input signal DIN.

Step 709

The second amplifier AP2 is used to generate the second output signal OS2.

Step 711

The frequency detection signal FD is generated according to the frequency of the differential input signal DIN.

Step 713

The output of the first amplifier AP1 and the output of the second amplifier AP2 are selectively coupled according to the frequency detection signal FD.

Other detailed steps can be obtained based on the above embodiments and will not be described again here. Please note that the clock signal buffering method provided by the present invention is not limited to execution with the input clock buffer shown in FIG. 1 and FIG. 4 .

According to the aforementioned embodiments, even if the DC level of the differential input signal changes, the duty cycle of the output clock signal can remain accurate.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100:Input clock buffer

103: Frequency detection circuit

AP1: first amplifier

AP2: Second amplifier

C1: first capacitor

C2: second capacitor

DIN: Differential input signal

FD: frequency detection signal

IN1: first input signal

IN2: second input signal

IN1': signal

OS1: first output signal

OS2: Second output signal

RCLK: reference clock signal

SW: switch

X1: Delay circuit

Claims (16)

An input clock buffer includes a first capacitor, a second capacitor, and a first amplifier for generating a first output signal, including a first input terminal coupled to the first capacitor and a first input terminal coupled to the first capacitor. a second input terminal of two capacitors, wherein the first capacitor and the second capacitor receive a differential input signal and form a first pair of signal paths of the differential input signal; a second amplifier for generating a first Two output signals include a first input terminal and a second input terminal, wherein the first input terminal of the second amplifier and the second input terminal of the second amplifier form a second pair of the differential input signal a signal path; a frequency detection circuit for generating a frequency detection signal according to a frequency of the differential input signal; and a switch located between an output of the first amplifier and an output of the second amplifier, Used to turn on or off based on the frequency detection signal. The input clock buffer of claim 1, further comprising: a DC level providing circuit coupled to the first capacitor, the second capacitor, the first input terminal of the first amplifier and the first amplifier The second input terminal is used to provide a DC level of the differential input signal. The input clock buffer of claim 1, further comprising: a third amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier and the third amplifier The second input terminal forms a third pair of signal paths for a differential clock signal; The differential input signal is generated according to an output of the third amplifier. The input clock buffer of claim 1 further includes: a third capacitor; a fourth capacitor; a fourth amplifier including a first input terminal and a second input terminal, wherein the fourth amplifier The first input terminal and the second input terminal of the fourth amplifier form a fourth pair of signal paths for the differential clock signal; wherein the differential input signal is generated according to an output of the fourth amplifier. The input clock buffer of claim 1, further comprising: a third amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier and the third amplifier The second input terminal forms a third pair of signal paths for a differential clock signal; a third capacitor: a fourth capacitor; a fourth amplifier including a first input terminal and a second input terminal, wherein The first input terminal of the fourth amplifier and the second input terminal of the fourth amplifier form a fourth pair of signal paths for the differential clock signal; the differential input signal is selectively configured according to the third amplifier An output of and an output of the fourth amplifier are generated. The input clock buffer of claim 1 further includes: a delay circuit for generating a delay signal of the first input signal; The frequency detection circuit generates the frequency detection signal according to the edge of the delayed signal. The input clock buffer of claim 1, wherein if the frequency of the differential input signal is lower than a critical frequency, the switch is turned on, and if the frequency of the differential input signal is higher than the critical frequency, then The switch is off. The input clock buffer of claim 7, wherein when the switch is turned on, the DC level of the second output signal compensates the DC level of the first output signal. A clock signal buffering method includes: (a) filtering the DC part of a differential input signal; (b) after filtering the DC part, forming the difference with the input end of a first amplifier a first pair of signal paths for a differential input signal; (c) using the first amplifier to generate a first output signal; (d) using an input end of a second amplifier to form a second pair of signal paths for the differential input signal ; (c) using the second amplifier to generate a second output signal; (f) generating a frequency detection signal according to a frequency of the differential input signal; and (g) selectively coupling according to the frequency detection signal Connect an output of the first amplifier and an output of the second amplifier. The clock signal buffering method as described in claim 9 further includes: providing a DC level of the differential input signal after filtering the DC part. The clock signal buffering method as described in request item 9 further includes: An input terminal of a third amplifier forms a third pair of signal paths for a differential clock signal; the differential input signal is generated according to an output of the third amplifier. The clock signal buffering method as described in claim 9 further includes: filtering the DC part of a differential clock signal; using an input end of a fourth amplifier to form a fourth component of the differential clock signal. For the signal path; generate the differential input signal according to an output of the fourth amplifier. The clock signal buffering method as claimed in claim 9, further comprising: using an input end of a third amplifier to form a third pair of signal paths for a differential clock signal; and a direct current portion for the differential clock signal. filtering; after filtering the DC part of the differential clock signal, forming a fourth pair of signal paths of the differential clock signal with the input end of a fourth amplifier; and selectively according to the An output of the third amplifier and an output of the fourth amplifier are generated. The clock signal buffering method of claim 9 further includes: generating a delayed signal of the first input signal; and generating the frequency detection signal according to the edge of the delayed signal. The clock signal buffering method of claim 9, wherein if the frequency of the differential input signal is lower than a critical frequency, then step (g) couples the output of the first amplifier and the second amplifier The output; wherein if the frequency of the differential input signal is higher than the critical frequency, then step (g) does not couple the output of the first amplifier and the output of the second amplifier. The clock signal buffering method of claim 15, wherein when the step (g) couples the output of the first amplifier and the output of the second amplifier, the DC level of the second output signal compensates the DC level of the first output signal.