CN117544141A - Input clock buffer and clock signal buffering method - Google Patents
Input clock buffer and clock signal buffering method Download PDFInfo
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- CN117544141A CN117544141A CN202210915206.1A CN202210915206A CN117544141A CN 117544141 A CN117544141 A CN 117544141A CN 202210915206 A CN202210915206 A CN 202210915206A CN 117544141 A CN117544141 A CN 117544141A
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- 239000000872 buffer Substances 0.000 title claims abstract description 32
- 230000003139 buffering effect Effects 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000001514 detection method Methods 0.000 claims abstract description 49
- 239000003990 capacitor Substances 0.000 claims abstract description 47
- 238000001914 filtration Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 12
- 230000000630 rising effect Effects 0.000 description 7
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 4
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- Manipulation Of Pulses (AREA)
Abstract
An input clock buffer and a clock signal buffering method. The input clock buffer includes: a first capacitor: a second capacitor: a first amplifier for generating a first output signal, comprising an input terminal coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receive a differential input signal; a second amplifier for generating a second output signal according to the differential input signal; a frequency detection circuit for generating a frequency detection signal according to a frequency of the differential input signal; and a switch, which is positioned between an output of the first amplifier and an output of the second amplifier, and is used for being turned on or turned off according to the frequency detection signal.
Description
Technical Field
The present invention relates to an input clock buffer and a clock signal buffering method, and more particularly, to an input clock buffer and a clock signal buffering method capable of compensating DC (Direct Current) level of a differential input signal.
Background
Conventional input clock buffers are used to provide an output clock signal having a desired duty cycle (duty ratio). However, if one of the inputs of the input clock buffer is coupled to a predetermined voltage level (e.g., ground potential), or if there is an unexpected change in the DC level of the input signal received by the input, the duty cycle of the output clock signal may become inaccurate.
Disclosure of Invention
It is therefore an object of the present invention to provide an input clock buffer that can generate a clock signal with an accurate duty cycle.
Another object of the present invention is to provide a clock signal buffering method capable of generating a clock signal with an accurate duty cycle.
An embodiment of the present invention provides an input clock buffer, including: a first capacitor: a second capacitor: a first amplifier for generating a first output signal, comprising a first input terminal coupled to the first capacitor and a second input terminal coupled to the second capacitor, wherein the first capacitor and the second capacitor receive a differential input signal and form a first pair of signal paths of the differential input signal; a second amplifier for generating a second output signal, comprising a first input terminal and a second input terminal, wherein the first input terminal of the second amplifier and the second input terminal of the second amplifier form a second pair of signal paths of the differential input signal; a frequency detection circuit for generating a frequency detection signal according to a frequency of the differential input signal; and a switch, which is positioned between an output of the first amplifier and an output of the second amplifier, and is used for being turned on or turned off according to the frequency detection signal.
Another embodiment of the present invention provides a clock signal buffering method, including: (a) filtering a DC portion of a differential input signal; (b) Forming a first pair of signal paths of the differential input signal with an input of a first amplifier after filtering the DC portion; (c) generating a first output signal with the first amplifier; (d) Forming a second pair of signal paths of the differential input signal by the input end of a second amplifier; (e) generating a second output signal with the second amplifier; (f) Generating a frequency detection signal according to a frequency of the differential input signal; and (g) selectively coupling an output of the first amplifier and an output of the second amplifier according to the frequency detection signal.
According to the foregoing embodiments, even if the DC level of the differential input signal changes, the duty ratio of the output clock signal can be kept accurate.
Drawings
FIG. 1 is a block diagram of an input clock buffer according to an embodiment of the invention.
Fig. 2 is a circuit diagram of a circuit for providing the differential input signal shown in fig. 1 according to an embodiment of the invention.
FIG. 3 is a schematic diagram showing how to generate the frequency detection signal shown in FIG. 1 according to an embodiment of the present invention.
FIG. 4 is a block diagram of an input clock buffer according to another embodiment of the invention.
FIG. 5 is a schematic diagram showing the operation of the input clock buffer shown in FIG. 4 when the switch is turned off according to an embodiment of the present invention.
FIG. 6 is a schematic diagram showing the operation of the input clock buffer shown in FIG. 4 when the switch is turned on according to an embodiment of the present invention.
FIG. 7 is a flowchart of a clock signal buffering method according to an embodiment of the invention.
[ symbolic description ]
100. 400 input clock buffer
200 circuit
103 frequency detection circuit
AP1 first amplifier
AP2 second amplifier
AP3 third amplifier
AP4 fourth amplifier
AP5 fifth amplifier
AP6 sixth amplifier
C1 first capacitor
C2 second capacitor
C3 third capacitor
C4 fourth capacitor
C5 fifth capacitor
C6 sixth capacitor
DCLK differential clock signal
DIN differential input signal
FD frequency detection signal
IN1 first input signal
IN2 second input signal
IN1' signal
OS1 first output signal
OS2 second output signal
R1, R2, R3, R4 resistors
RCLK reference clock signal
SW switch
X1 delay circuit
XCLK, XCLKN clock signal
Detailed Description
In the following, various embodiments of the present invention will be described, and it should be noted that the elements of each embodiment may be implemented in hardware (e.g., a device or a circuit) or firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used merely to define various elements, parameters, data, signals, or steps. And are not intended to limit the order in which they are presented. For example, the first device and the second device may be the same structure but different devices.
FIG. 1 is a block diagram of an input clock buffer according to an embodiment of the invention. As shown in fig. 1, the input clock buffer 100 includes a first capacitor C1, a second capacitor C2, a first amplifier AP1, a second amplifier AP2, a frequency detection circuit 103, and a switch SW. The first amplifier AP1 is configured to generate a first output signal OS1, and includes a first input terminal coupled to the first capacitor C1 and a second input terminal coupled to the second capacitor C2. The first capacitor C1 and the second capacitor C2 receive the differential input signal DIN and form a first pair of signal paths of the differential input signal DIN. As shown IN fig. 1, the differential input signal DIN is composed of a first input signal IN1 and a second input signal IN2.
The second amplifier AP2 is configured to generate a second output signal OS2, and further includes a first input terminal and a second input terminal. The first input of the second amplifier AP2 and the second input of the second amplifier AP2 form a second pair of signal paths of the differential input signal DIN. The frequency detection circuit 103 is configured to generate a frequency detection signal FD according to the frequency of the differential input signal DIN. The switch SW is located between the output of the first amplifier AP1 and the output of the second amplifier AP2 to be turned on (on) and off (off) according to the frequency detection signal FD. Details of the frequency detection action will be described below.
In the embodiment shown in fig. 1, the frequency detection circuit 103 generates the frequency detection signal FD from the reference clock signal RCLK. The frequency of the reference clock signal RCLK corresponds to the frequency of the first output signal OS1, and the frequency of the first output signal OS1 corresponds to the frequency of the differential input signal DIN. Accordingly, the frequency detection circuit 103 may generate the frequency detection signal FD according to the reference clock signal RCLK, thereby generating the frequency detection signal FD according to the frequency of the differential input signal DIN. Note, however, that the frequency detection circuit 103 may generate the frequency detection signal FD by any other mechanism than the mechanism shown in fig. 1 according to the frequency of the differential input signal DIN.
In one embodiment, the switch SW is on if the frequency of the first output signal OSl is below a threshold frequency, and the switch SW is off if the frequency of the first output signal OSl is above the threshold frequency. In other words, the switch SW is turned on if the frequency of the first output signal OS1 is low, and is turned off if the frequency of the first output signal OS1 is high. In this way, since the first output signal OS1 and the second output signal OS2 are combined to generate the reference clock signal RCLK, if the switch SW is turned on when the first output signal OS1 has a low frequency, the second output signal OS2 can be combined to the reference clock signal RCLK. Thereby, non-ideal factors such as leakage current of the input terminal of the first amplifier AP1 can be improved.
IN one embodiment, the first input signal IN1 is a clock signal and the second input signal IN2 is an inverse of the first input signal IN 1. However, the first input signal IN1 and the second input signal IN2 may be other types of signals. Fig. 2 is a circuit diagram of a circuit for providing the differential input signal DIN shown in fig. 1 according to an embodiment of the invention. In the embodiment of fig. 2, the circuit 200 for providing the differential input signal DIN includes a third capacitor C3, a fourth capacitor C4, a third amplifier AP3 and a fourth amplifier AP4. The third amplifier AP3 comprises a first input and a second input, wherein the first input of the third amplifier AP3 and the second input of the third amplifier AP3 form a third pair of signal paths of the differential clock signal DCLK. The differential clock signal DCLK is formed of a clock signal XCLK and a clock signal XCLKN, which is an inverted signal of the clock signal XCLK.
The fourth amplifier AP4 comprises a first input and a second input, wherein the first input of the fourth amplifier AP4 and the second input of the fourth amplifier AP4 form a fourth signal path pair clock of the differential clock signal DCLK. The differential input signal DIN is generated based on the output of the third amplifier AP3 and the output of the fourth amplifier AP4. Specifically, the first input signal IN1, which can be used to generate the differential input signal DIN, is generated from the outputs of the third amplifier AP3 and the fourth amplifier AP4.
In an embodiment, if the clock signal XCLK and the clock signal XCLKN received by the third amplifier AP3 both have variations (i.e., have rising and falling edges), the first input signal INl is generated from the output 3 of the third amplifier AP3 and the output of the fourth amplifier AP4. However, if one of the clock signal XCLK and the clock signal XCLKN does not change (i.e., there is no rising and falling edge), for example, the clock signal XCLK is a predetermined voltage level, such as a ground potential, the output of the third amplifier AP3 does not reflect the difference between the clock signal XCLK and the clock signal XCLKN, but the output of the fourth amplifier AP4 still reflects the difference between the clock signal XCLK and the clock signal XCLKN due to the presence of the third capacitor C3 and the fourth capacitor C4. IN this case, since the outputs of the third amplifier AP3 and the fourth amplifier AP4 are connected together, the output of the third amplifier AP3 affects the value of the first input signal IN 1. IN this way, the duty cycle of the first input signal IN1 is different from the duty cycle of the clock signal XCLKN.
In the embodiment of fig. 2, the circuit 200 includes, but is not limited to, a fifth capacitor C5, a sixth capacitor C6, a fifth amplifier AP5, and a sixth amplifier AP 6. The fifth capacitor C5, the sixth capacitor C6, the fifth amplifier AP5 and the sixth amplifier AP6 may be used to generate the second input signal IN2, and have the same structure and operation as the circuit generating the first input signal IN 1. Therefore, the description thereof is omitted.
In an embodiment, the input signal for generating the differential input signal DIN may be generated by only one amplifier. For example, the first input signal IN1 or the second input signal IN2 may be generated only according to an amplifier having the structure of the third amplifier AP 3. As another example, the first input signal IN1 or the second input signal IN2 may be generated only according to an amplifier having the structure of the fourth amplifier AP4. Such variations are also intended to fall within the scope of the present invention.
The frequency detection circuit 103 shown in fig. 1 can be implemented by various circuits. Referring to fig. 1 again, in an embodiment, the input clock buffer 100 further includes a delay circuit X1 for generating a delay signal of the first output signal OS 1. If the switch SW is turned off, the delay signal is the reference clock signal RCLK, and if the switch SW is turned on, the reference clock signal RCLK is a combination of the first output signal OS1 and the second output signal OS2. The frequency detection circuit 103 generates a frequency detection signal FD according to the edge of the delay signal.
Fig. 3 is a schematic diagram showing how to generate the frequency detection signal FD shown in fig. 1 according to an embodiment of the present invention. In this case, the frequency detection circuit 103 may include a plurality of logic gates (e.g., a nand gate and a nor gate) and a plurality of inverters to perform the actions shown in fig. 3. As shown in fig. 3, the switch SW is turned on when the frequency detection signal FD is at a high logic level, and is turned off when the frequency detection signal FD is at a low logic level. Further, the rising edge of the frequency detection signal FD corresponds to the delay phase of the rising/falling edge of the reference clock signal RCLK. In one embodiment, there is a time difference td1 between the rising edge of the frequency detection signal FD and the rising edge of the reference clock signal RCLK. Further, there is a time difference td2 between the next rising edge of the frequency detection signal FD and the falling edge of the reference clock signal RCLK.
Therefore, in the embodiment of fig. 3, the time interval of the high logic level of the frequency detection signal FD can be set by setting the time differences tdl and td2. Further, in the embodiment of fig. 3, the critical frequency may be set by setting the time differences td1 and td2. If the frequency of the reference clock signal RCLK is greater than the critical frequency, the single signal interval of the reference clock signal RCLK decreases, and thus the time interval in which the frequency detection signal FD has a high logic level also decreases. If the time interval of the high logic level of the frequency detection signal FD is smaller than the time difference td1, the frequency detection signal FD is kept at the low logic level, and thus the switch SW in fig. 2 is kept off. In other words, if the time difference td1 is a fixed value and the frequency of the reference clock signal RCLK is greater than the critical frequency, the switch SW in fig. 1 is kept closed. The critical frequency may be set according to different circuit requirements. In one embodiment, the critical frequency is 200MHz.
FIG. 4 is a block diagram of an input clock buffer 400 according to another embodiment of the invention. In addition to the elements shown in fig. 1, the input clock buffer 400 further includes a DC level providing circuit coupled to the first capacitor C1, the second capacitor C2, the first input terminal and the second input terminal of the first amplifier AP 1. The DC level providing circuit is configured to provide the DC level to the differential input signal DIN after the DC portion of the differential input signal DIN is filtered. In the embodiment of fig. 4, the DC level providing circuit comprises resistors R1, R2, R3, R4, which form a voltage divider. Furthermore, in one embodiment, resistors R1, R2, R3, R4 provide a DC level of VDD/2.
FIG. 5 is a schematic diagram showing the operation of the input clock buffer shown in FIG. 4 when the switch is turned off according to an embodiment of the present invention. That is, in the embodiment of fig. 5, the frequency of the differential input signal DIN is higher than the critical frequency. Note that, for simplicity of illustration, only the first input signal IN1 is shown, and the second input signal IN2 is not shown as an inverse of the first input signal IN 1. IN addition, the signal IN1' received by the first end of the first amplifier AP1 refers to a signal that is provided with a DC level by the DC level providing circuit after the DC portion of the first input signal IN1 is filtered by the first capacitor C1.
As shown in fig. 5, the frequency detection signal FD is maintained at a low logic level, and thus the switch SW is turned off. As such, the output of the second amplifier AP2 is not coupled to the output of the first amplifier AP1, and the output clock signal of the input clock buffer 400 is affected only by the output of the first amplifier AP 1. Accordingly, the duty ratio of the output clock signal RCLK (reference clock signal) may be close to the desired value (the duty ratio of the first input signal IN 1).
FIG. 6 is a schematic diagram showing the operation of the input clock buffer shown in FIG. 4 when the switch is turned on according to an embodiment of the present invention. That is, in the embodiment of fig. 6, the frequency of the differential input signal DIN is lower than the critical frequency. Note that, for simplicity of illustration, only the first input signal IN1 is shown, and the second input signal IN2, which is not shown as an inverse of the first input signal IN1, is shown. IN addition, the signal IN1' received by the first end of the first amplifier AP1 refers to a signal that is provided with a DC level by the DC level providing circuit after the DC portion of the first input signal IN1 is filtered by the first capacitor C1.
In the embodiment of fig. 6, some leakage current may flow to ground through the DC level supply circuit due to the lower frequency of the differential input signal DIN. Accordingly, the DC level of the first input signal IN1 decreases, and the DC level of the signal IN1' also decreases accordingly. In this case, the switch SW is turned on corresponding to the high logic level of the frequency detection signal FD. IN this way, since the output terminal of the first amplifier AP1 is coupled to the output terminal of the second amplifier AP2, the DC level of the signal IN1' can be compensated.
FIG. 7 is a flowchart showing a clock signal buffering method according to an embodiment of the invention, which comprises the following steps:
step 701
Filtering a DC portion of a differential input signal DIN
Step 703
After filtering the DC portion, a first pair of signal paths for the differential input signal DIN are formed with the input of a first amplifier AP 1.
Step 705
The first output signal OSl is generated by the first amplifier APl.
Step 707
A second pair of signal paths for the differential input signal DIN is formed by the inputs of a second amplifier AP 2.
Step 709
The second output signal OS2 is generated with the second amplifier AP 2.
Step 711
The frequency detection signal FD is generated according to the frequency of the differential input signal DIN.
Step 713
The output of the first amplifier AP1 and the output of the second amplifier AP2 are selectively coupled according to the frequency detection signal FD.
Other detailed steps may be obtained based on the above embodiments, and will not be described here again. Note that the clock signal buffering method provided by the present invention is not limited to be implemented with the input clock buffers shown in fig. 1 and 4.
According to the foregoing embodiments, even if the DC level of the differential input signal changes, the duty ratio of the output clock signal can be kept accurate.
The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.
Claims (16)
1. An input clock buffer comprising:
a first capacitance:
and a second capacitor:
a first amplifier for generating a first output signal, comprising a first input terminal coupled to the first capacitor and a second input terminal coupled to the second capacitor, wherein the first capacitor and the second capacitor receive a differential input signal and form a first pair of signal paths of the differential input signal;
the second amplifier is used for generating a second output signal and comprises a first input end and a second input end, wherein the first input end of the second amplifier and the second input end of the second amplifier form a second pair of signal paths of the differential input signal;
a frequency detection circuit for generating a frequency detection signal according to the frequency of the differential input signal; and
the switch is positioned between the output of the first amplifier and the output of the second amplifier and is used for being turned on or turned off according to the frequency detection signal.
2. The input clock buffer of claim 1, further comprising:
the DC level providing circuit is coupled to the first capacitor, the second capacitor, the first input terminal of the first amplifier and the second input terminal of the first amplifier for providing the DC level of the differential input signal.
3. The input clock buffer of claim 1, further comprising:
a third amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier and the second input terminal of the third amplifier form a third pair of signal paths of a differential clock signal;
wherein the differential input signal is generated based on the output of the third amplifier.
4. The input clock buffer of claim 1, further comprising:
a third capacitor;
a fourth capacitor;
a fourth amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the fourth amplifier and the second input terminal of the fourth amplifier form a fourth pair of signal paths of the differential clock signal;
wherein the differential input signal is generated based on the output of the fourth amplifier.
5. The input clock buffer of claim 1, further comprising:
a third amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier and the second input terminal of the third amplifier form a third pair of signal paths of a differential clock signal;
and a third capacitor:
a fourth capacitor;
a fourth amplifier including a first input terminal and a second input terminal, wherein the first input terminal of the fourth amplifier and the second input terminal of the fourth amplifier form a fourth pair of signal paths of the differential clock signal;
the differential input signal is selectively generated according to the output of the third amplifier and the output of the fourth amplifier.
6. The input clock buffer of claim 1, further comprising:
a delay circuit for generating a delay signal of the first input signal;
the frequency detection circuit generates the frequency detection signal according to the edge of the delay signal.
7. The input clock buffer of claim 1, wherein the switch is turned on if the frequency of the differential input signal is below a threshold frequency, and is turned off if the frequency of the differential input signal is above the threshold frequency.
8. The input clock buffer of claim 7, wherein the DC level of the second output signal compensates for the DC level of the first output signal when the switch is on.
9. A clock signal buffering method, comprising:
(a) Filtering the DC portion of the differential input signal;
(b) Forming a first pair of signal paths of the differential input signal with the input of a first amplifier after filtering the DC portion;
(c) Generating a first output signal with the first amplifier;
(d) Forming a second pair of signal paths of the differential input signal with the input of a second amplifier;
(e) Generating a second output signal with the second amplifier;
(f) Generating a frequency detection signal according to the frequency of the differential input signal; and
(g) The output of the first amplifier and the output of the second amplifier are selectively coupled according to the frequency detection signal.
10. The clock signal buffering method of claim 9, further comprising:
after filtering the DC portion, a DC level of the differential input signal is provided.
11. The clock signal buffering method of claim 9, further comprising:
forming a third pair of signal paths of the differential clock signal with the input end of a third amplifier;
the differential input signal is generated according to the output of the third amplifier.
12. The clock signal buffering method of claim 9, further comprising:
filtering the DC portion of the differential clock signal;
forming a fourth pair of signal paths of the differential clock signal with the input of a fourth amplifier;
the differential input signal is generated based on the output of the fourth amplifier.
13. The clock signal buffering method of claim 9, further comprising:
forming a third pair of signal paths of the differential clock signal with the input end of a third amplifier;
filtering the DC portion of the differential clock signal;
forming a fourth pair of signal paths of the differential clock signal with the input of a fourth amplifier after filtering the DC portion of the differential clock signal; and
selectively based on the output of the third amplifier and the output of the fourth amplifier.
14. The clock signal buffering method of claim 9, further comprising:
generating a delay signal of the first input signal;
the frequency detection signal is generated according to the edge of the delay signal.
15. The method of buffering a clock signal according to claim 9,
wherein if the frequency of the differential input signal is below a threshold frequency, the step (g) is coupled to the output of the first amplifier and the output of the second amplifier;
wherein if the frequency of the differential input signal is higher than the threshold frequency, the step (g) is not coupled to the output of the first amplifier and the output of the second amplifier.
16. The clock signal buffering method of claim 15, wherein when step (g) is coupled to the output of the first amplifier and the output of the second amplifier, the DC level of the second output signal compensates for the DC level of the first output signal.
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| CN202210915206.1A CN117544141A (en) | 2022-08-01 | 2022-08-01 | Input clock buffer and clock signal buffering method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210915206.1A CN117544141A (en) | 2022-08-01 | 2022-08-01 | Input clock buffer and clock signal buffering method |
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| CN117544141A true CN117544141A (en) | 2024-02-09 |
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| CN202210915206.1A Pending CN117544141A (en) | 2022-08-01 | 2022-08-01 | Input clock buffer and clock signal buffering method |
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