TWI831502B - Plate having alignment mark and manufacturing method of the same - Google Patents

Abstract

A plate having an alignment mark includes a substrate and an alignment mark. The substrate includes a circuit layout region. The alignment mark is located outside the circuit layout region. The alignment mark includes a recognition pattern region and a dummy pattern region, and a brightness of the dummy pattern region is smaller than a brightness of the recognition pattern region.

Description

Plate with alignment marks and method of manufacturing same

The present disclosure relates to a plate with alignment marks and a manufacturing method thereof.

In the semiconductor manufacturing process or electronic equipment manufacturing process, alignment marks (Alignment Mark) are used for optical alignment. However, as the grain size shrinks, the grain size in the semiconductor manufacturing process shrinks. When performing defect detection or alignment, noise generated between two adjacent dies can easily lead to poor identification accuracy of alignment marks.

In view of this, how to provide an alignment mark that can overcome the above problems is still one of the current research goals in the industry.

One technical aspect of the disclosure is a plate with alignment marks.

In an embodiment of the present disclosure, a board with alignment marks includes a substrate and alignment marks. The substrate contains the circuit design area. The alignment marks are located outside the circuit design area of the substrate. The alignment mark includes an identification pattern area and a dummy pattern area, where the brightness of the dummy pattern area is smaller than the brightness of the identification pattern area.

In an embodiment of the present disclosure, the identification pattern area includes a bright area and an identification structure, and the identification structure has edges and corners.

In an embodiment of the present disclosure, the area of the bright area is 80% to 90% of the area of the alignment mark, and the area of the dummy pattern area is 10% to 20% of the area of the alignment mark.

In an embodiment of the present disclosure, the dummy pattern area includes a plurality of blocks.

In an embodiment of the disclosure, the substrate includes a first layer and a second layer. The dummy pattern area includes a first dummy pattern layer located on the first layer and a second dummy pattern layer located on the second layer. The first dummy pattern layer and the second dummy pattern layer of the dummy pattern area are interlaced in the top view.

One technical aspect of the present disclosure is a method of manufacturing a plate with alignment marks.

In an embodiment of the present disclosure, a method of manufacturing a board with alignment marks includes providing a substrate, wherein the substrate includes a circuit design area; forming alignment marks on the substrate, wherein the alignment marks are located outside the circuit design area, And forming the alignment mark also includes forming an identification pattern area and forming a dummy pattern area. The brightness of the dummy pattern area is smaller than the brightness of the recognition pattern area.

In an embodiment of the disclosure, forming the alignment mark further includes forming a first metal layer material, forming a first anti-reflective layer material on the first metal layer material, and patterning the first metal layer material and the first anti-reflective layer material. To form a plurality of blocks of the first dummy pattern layer and the identification pattern area of the dummy pattern area. The recognition pattern area also contains recognition structures. The recognition structure has an edge.

In an embodiment of the present disclosure, forming the dummy pattern area further includes making the area of the dummy pattern area 10% to 20% of the area of the alignment mark.

In an embodiment of the present disclosure, before forming the first dummy pattern layer, a second dummy pattern layer is formed in the dummy pattern area, so that the first dummy pattern layer and the second dummy pattern layer in the dummy pattern area are in the top view. staggered.

In an embodiment of the present disclosure, forming the identification pattern area further includes patterning the first anti-reflection layer in the identification pattern area to form a bright area, and the area of the bright area is 80% to 90% of the area of the alignment mark.

In the above embodiments, the alignment mark of the present disclosure has an identification pattern area and a dummy pattern area. The brightness of the dummy pattern area is smaller than the brightness of the recognition pattern area. Therefore, a high contrast is formed by the difference in brightness between the recognition pattern area and the dummy pattern area, which is helpful for the inspection machine to identify the position of the alignment mark. The alignment marks disclosed in the present disclosure can meet the alignment requirements in small-size die manufacturing processes.

A plurality of embodiments of the present invention will be disclosed in the drawings below. For clarity of explanation, many practical details will be explained in the following description. However, it will be understood that these practical details should not limit the invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings. Also, the thicknesses of layers and regions in the drawings may be exaggerated for clarity, and like reference numerals refer to the same elements in the description of the drawings.

Figure 1 is a top view of a plate 10 with alignment marks according to an embodiment of the present disclosure. The board 10 includes a substrate 100 and an alignment mark 200 . The substrate 100 has a circuit design area 110 . Alignment mark 200 is outside circuit design area 110 . Alignment marks 200 are used to align the stacks formed in different process steps. In this embodiment, the substrate 100 is a wafer. In the circuit design area 110 are die. The substrate 100 also has cutting lines 120 , and the cutting lines 120 surround the circuit design area 110 . The circuit design areas 110 are arranged along the first direction D1 and the second direction D2 to form an array. The first direction D1 is perpendicular to the second direction D2. The cutting track 120 extends in the first direction D1 and the second direction D2. In this embodiment, the alignment mark 200 is located on the cutting lane 120, but the disclosure is not limited thereto. In other embodiments, the area where the die 112 was originally located may also be replaced with the alignment mark 200 .

The plate 10 of the present disclosure may include translucent materials, semiconductor materials or compound semiconductor materials. The plate 10 may be used for alignment requirements in semiconductor manufacturing processes (eg, silicon substrate manufacturing processes), compound semiconductor manufacturing processes, printed circuit boards, or display manufacturing processes. Compound semiconductor processes include gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), silicon-based gallium nitride (GaN on Si) or silicon carbide-based gallium nitride (GaN on SIC), but this disclosure Not limited to this. The alignment mark 200 of the present disclosure can be applied to alignment requirements in electron microscopes (SEM), automated optical inspection (AOI), or other defect detection tools.

Figure 2 is an enlarged view of the alignment mark 200 and a part of the circuit design area 110 of Figure 1 , that is, an enlarged view of the framed area R1 in Figure 1 . The alignment mark 200 includes an identification pattern area 210 and a dummy pattern area 220 . In the embodiment of FIG. 2, two identification pattern areas 210 and three dummy pattern areas 220 are taken as an example. The number and area size of the identification pattern areas 210 and the dummy pattern areas 220 in Figure 2 are examples, and the relative positions of the identification pattern areas 210 and the dummy pattern areas 220 are only examples and are not intended to limit the present invention.

Figure 3 is a partial enlarged view of the recognition pattern area 210 in Figure 2, that is, an enlarged view of the framed area R2 in Figure 2. The identification pattern area 210 includes a plurality of bright areas 212 and identification structures 214 . The bright areas 212 are separated from each other. In this embodiment, the identification pattern area 210 and the bright area 212 are substantially rectangular, but the disclosure is not limited thereto. The bright area 212 includes a material with high reflectivity (such as a metal material). Therefore, the bright area 212 reflects most of the light in the inspection frame of the inspection machine, thereby providing an area with high brightness in the alignment mark 200 .

Refer to Figures 2 and 3 at the same time. The identification structure 214 is located at the edge of the identification pattern area 210 . For example, the identification structure 214 in this embodiment corresponds to the four corners of a rectangle. The bright area 212 is between the identification structures 214 . In other words, the bright area 212 is located inside the identification pattern area 210 , and the identification structure 214 is located outside the identification pattern area 210 . The identification structure 214 has edges and corners 2142 . The edge angle 2142 is generally close to 90 degrees, but is not limited thereto. The identification structure 214 with edges and corners 2142 can improve alignment capabilities. The identification structure 214 is a darker area relative to the bright area 212 .

Refer to Figure 2. The dummy pattern area 220 is composed of a metal material and an anti-reflection layer located on the metal material. In other words, the surface of the dummy pattern area 220 is a material with low reflectivity. Therefore, the dummy pattern area 220 hardly reflects light in the inspection image of the inspection machine, thereby providing a dark area in the alignment mark 200 .

Through the above structural design, the brightness of the dummy pattern area 220 is smaller than the brightness of the identification pattern area 210 . Specifically, the dummy pattern area 220 is the darkest area in the alignment mark 200 , and the identification pattern area 210 is the brightest area in the alignment mark 200 . The brightness difference between the recognition pattern area 210 and the dummy pattern area 220 forms a high contrast. In this way, it is helpful for the inspection machine to identify the position of the alignment mark 200 .

As grain sizes shrink, noise between adjacent grains can easily affect the accuracy of alignment mark recognition. Therefore, the present disclosure can meet the alignment requirements in small-size die manufacturing processes by using the alignment mark 200 with high contrast. For example, the alignment mark 200 in the disclosure can be applied in a process where the grain size is less than 1000 microns by 1000 microns, but the disclosure is not limited thereto.

In this embodiment, the total area of the multiple bright areas 212 of the recognition pattern area 210 is 80% to 90% of the area of the alignment mark 200 , and the area of the dummy pattern area 220 is 10% of the area of the alignment mark 200 to 20%. In other words, the ratio of the total area of the bright area 212 to the area of the dummy pattern area 220 is in the range of 4~9. With such an area configuration, the contrast of the alignment mark 200 can be improved.

Refer to Figure 2. The identification pattern area 210 and the dummy pattern area 220 are arranged adjacent to each other. In this embodiment, at least one side of the recognition pattern area 210 is adjacent to the dummy pattern area 220 . When the identification structure 214 of the identification pattern area 210 is located between the bright area 212 and the dummy pattern area 220, the high contrast generated between the identification pattern area 210 and the dummy pattern area 220 can be more conducive to the detection machine to identify the identification structure. 214. For example, the distance between the identification pattern area 210 and the dummy pattern area 220 is 5 microns, but the disclosure is not limited thereto.

Figure 4A is a partial enlarged view of the dummy pattern area 220 in Figure 2, that is, an enlarged view of the framed area R3 in Figure 2. Figure 5 is a cross-sectional view along line 5-5 in Figure 2. Refer also to Figure 4A and Figure 5 . In this embodiment, the dummy pattern area 220 is formed by stacking a multi-layer structure. The substrate 100 includes a first layer 102, a second layer 104 and a third layer 106. For example, the first layer 102, the second layer 104, and the third layer 106 are made of insulating materials. The second layer 104 is stacked on the third layer 106 in the third direction D3, and the first layer 102 is stacked on the second layer 104 in the third direction D3. The third direction D3 is the vertical direction.

Refer also to Figure 4A and Figure 5 . What is shown in FIG. 4A is the first dummy pattern layer 222 of the dummy pattern area 220 . The first dummy pattern layer 222 is located on the first layer 102 . The first dummy pattern layer 222 may include a plurality of blocks 2221 separated from each other, and the blocks 2221 include a first anti-reflective layer 2222 and a first metal layer 2224. The first anti-reflective layer 2222 covers the first metal layer 2224.

Refer also to Figure 4B and Figure 5. Figure 4B shows the second dummy pattern layer 224 located below Figure 4A. The second dummy pattern layer 224 is located on the second layer 104 . The second dummy pattern layer 224 also includes a plurality of blocks 2241 separated from each other, and the blocks 2241 include a second anti-reflective layer 2242 and a second metal layer 2244.

Refer also to Figure 4C and Figure 5. Figure 4C shows the third dummy pattern layer 226 located below Figure 4B. The third dummy pattern layer 226 is located on the third layer 106 . The third dummy pattern layer 226 also includes a plurality of blocks 2261 separated from each other, and the blocks 2261 include a third anti-reflective layer 2262 and a third metal layer 2264.

As shown in FIGS. 4A, 4B and 5, the first dummy pattern layer 222 and the second dummy pattern layer 224 stacked together are staggered in the top view. In other words, the vertical projection of the first dummy pattern layer 222 on the second layer 104 does not substantially overlap the second dummy pattern layer 224 . That is to say, the vertical projection of the first dummy pattern layer 222 on the second layer 104 is located between the blocks 2241 of the second dummy pattern layer 224 . In other embodiments, the first dummy pattern layer 222 and the second dummy pattern layer 224 may also partially overlap in the top view.

As shown in FIG. 4B, FIG. 4C, and FIG. 5, the second dummy pattern layer 224 and the third dummy pattern layer 226 are staggered in the top view. In other words, the vertical projection of the second dummy pattern layer 224 on the third layer 106 does not substantially overlap with the third dummy pattern layer 226 . The third dummy pattern layer 226 in this embodiment is substantially the same as the first dummy pattern layer 222, but the disclosure is not limited thereto. In other embodiments, the second dummy pattern layer 224 and the third dummy pattern layer 226 may also partially overlap in the top view.

When the first dummy pattern layer 222, the second dummy pattern layer 224 and the third dummy pattern layer 226 in Figures 4A to 4C are stacked together, it can be seen in the inspection screen of the inspection machine that almost no light is reflected. Dummy pattern area 220. Therefore, the first dummy pattern layer 222 , the second dummy pattern layer 224 and the third dummy pattern layer 226 may together form a dummy pattern area 220 with low brightness. In other words, the dummy pattern area 220 is divided into a plurality of areas separated from each other and dispersed in a multi-layer structure. In this way, it is possible to avoid using a large area of metal material and adversely affecting the circuit design area 110 and at the same time provide the dark area required for the alignment mark 200 to improve contrast. In this embodiment, the length and width of each block 2221, 2241, 2261 are 5 microns, and the distance between adjacent blocks 2221, 2241, 2261 is also 5 microns, but this disclosure does not take this as an example. limit.

Figures 6A to 6C are partial enlarged views of the dummy pattern area 220a according to another embodiment of the present disclosure. The dummy pattern area 220a also includes a first dummy pattern layer 222a, a second dummy pattern layer 224a, and a third dummy pattern layer 226a. The difference between the dummy pattern area 220a and the dummy pattern area 220 shown in FIGS. 4A to 4C lies in the shape of the blocks. The blocks of the dummy pattern area 220a are rectangular with missing corners. The blocks of the first dummy pattern layer 222a are similar to the blocks of three first dummy pattern layers 222 being combined. The length of the long side of the block of the first dummy pattern layer 222a is 10 microns, and the length of the short side of the block is 5 micron, but the present disclosure is not limited thereto. The spacing between adjacent blocks is also 5 microns, but the disclosure is not limited thereto.

Figures 7A to 7C are partial enlarged views of the dummy pattern area 220b according to another embodiment of the present disclosure. The dummy pattern area 220b also includes a first dummy pattern layer 222b, a second dummy pattern layer 224b and The third dummy pattern layer 226b. The difference between the dummy pattern area 220a and the dummy pattern area 220 shown in FIGS. 4A to 4C lies in the shape of the blocks. The blocks of the dummy pattern area 220b are horizontally U-shaped. For example, the thickness of each block is 5 microns, and the length of the periphery of the blocks is 15 microns.

Figures 8 to 10 are cross-sectional views of intermediate steps of a method of manufacturing a plate with alignment marks according to an embodiment of the present disclosure. As shown in FIG. 1 , the steps of the manufacturing method begin with providing a substrate 100 including a circuit design area 110 . The board 10 is, for example, a wafer, and the circuit design area 110 includes dies. Next, alignment marks 200 are formed on the substrate 100 .

As shown in Figure 8, the dummy pattern area 220 in this embodiment takes the three-layer structure shown in Figure 5 as an example. The manufacturing method continues with the step of forming alignment marks 200 . The step of forming the alignment mark 200 includes first forming the third layer 106 and the second layer 104 of the substrate 100, and forming the third dummy pattern layer 226 and the second dummy pattern layer 224 respectively in the dummy pattern area 220.

As shown in FIG. 8 , the step of forming the third dummy pattern layer 226 includes forming a third metal layer 2264 and a third anti-reflection layer of the third dummy pattern layer 226 as shown in FIG. 4C through a deposition and patterning process. 2262. The insulating material of the third layer 106 covers the third dummy pattern layer 226 . During the above deposition and patterning processes, the structure of the circuit design area 110 or the identification pattern area 210 located in the third layer 106 can be formed simultaneously according to actual needs.

As shown in FIG. 8 , the step of forming the second dummy pattern layer 224 includes forming the second metal layer 2244 and the second anti-reflective layer of the second dummy pattern layer 224 as shown in FIG. 4B through a deposition and patterning process. 2242. The insulating material of the second layer 104 covers the second dummy pattern layer 224 . During the above deposition and patterning processes, the structure of the circuit design area 110 or the identification pattern area 210 located in the second layer 104 can be formed simultaneously according to actual needs.

As shown in FIG. 8 , the step of forming the alignment mark 200 includes successively forming a first metal layer material 2224M, and forming a first anti-reflective layer material 2222M on the first metal layer material 2224M. The first metal layer 2224 and the first anti-reflection layer 2222 are located in the dummy pattern area 220 and the identification pattern area 210 .

As shown in FIG. 9 , the steps of the manufacturing method are to pattern the first metal layer material 2224M and the first anti-reflection layer material 2222M to simultaneously form the first dummy pattern layer 222 and the identification pattern area 210 of the dummy pattern area 220 . The first dummy pattern layer 222 includes a plurality of blocks 2221 as shown in FIG. 4A. As mentioned above, the area of the dummy pattern area 220 is 10% to 20% of the area of the alignment mark 200 . The identification pattern area 210 also includes an identification structure 214, and the identification structure 214 has an edge 2142 of approximately 90 degrees.

As shown in FIG. 10 , the steps of the manufacturing method are to pattern the first anti-reflective layer 2222 in the identification pattern area 210 to form the bright area 212 . The first metal layer 2224 of the bright area 212 is exposed from the first anti-reflection layer 2222, thereby making the brightness of the dummy pattern area 220 smaller than the brightness of the identification pattern area 210. As mentioned above, the total area of the bright area 212 is 80% to 90% of the area of the alignment mark 200 . Referring to FIG. 5 , after the dummy pattern area 220 is formed, the insulating material of the first layer 102 covers the first dummy pattern layer 222 . After the above steps, the first layer 102 can be subjected to required planarization or patterning processes, which will not be described again.

In summary, the alignment mark of the present disclosure has an identification pattern area and a dummy pattern area. The brightness of the dummy pattern area is smaller than the brightness of the recognition pattern area. Therefore, a high contrast is formed by the difference in brightness between the recognition pattern area and the dummy pattern area, which is helpful for the inspection machine to identify the position of the alignment mark. The alignment marks disclosed in the present disclosure can meet the alignment requirements in small-size die manufacturing processes. In addition, when the recognition structure of the recognition pattern area is located between the bright area and the dummy pattern area, the high contrast generated between the recognition pattern area and the dummy pattern area can be more conducive to the detection machine to recognize the recognition structure. The first dummy pattern layer, the second dummy pattern layer and the third dummy pattern layer may together form a low-brightness dummy pattern area. In other words, the dummy pattern area is divided into a plurality of areas separated from each other and dispersed in the multi-layer structure. In this way, it is possible to avoid using a large area of metal material that would have a negative impact on the circuit design area, and at the same time provide a dark area required for alignment marks to improve contrast.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is The scope shall be determined by the appended patent application scope.

10:Plate 100:Substrate 102:First floor 104:Second floor 106:Third floor 110:Circuit design area 120: Cutting lane 200: Alignment mark 210: Identify pattern area 212: bright area 214: Identifying structures 2142:Edges 220, 220a, 220b: Dummy pattern area 222, 222a, 222b: first dummy pattern layer 2221:Block 2222: First anti-reflective layer 2222M: First anti-reflective layer material 2224: First metal layer 2224M: First metal layer material 224, 224a, 224b: second dummy pattern layer 2241:Block 2242: Second anti-reflective layer 2244: Second metal layer 226,226a,226b: The third dummy pattern layer 2261:Block 2262:Third anti-reflective layer 2264: The third metal layer R1,R2,R3: frame selection area D1: first direction D2: second direction D3: Third direction 5-5: Line segment

Figure 1 is a top view of a plate with alignment marks according to an embodiment of the present disclosure. Figure 2 is an enlarged view of the alignment marks and a portion of the circuit design area in Figure 1. Figure 3 is a partial enlarged view of the recognition pattern area in Figure 2. Figures 4A to 4C are partial enlarged views of the dummy pattern area in Figure 2. Figure 5 is a cross-sectional view along line 5-5 in Figure 2. Figures 6A to 6C are partial enlarged views of a dummy pattern area according to another embodiment of the present disclosure. Figures 7A to 7C are partial enlarged views of a dummy pattern area according to another embodiment of the present disclosure. Figures 8 to 10 are cross-sectional views of intermediate steps of a method of manufacturing a plate with alignment marks according to an embodiment of the present disclosure.

100:Substrate

110:Circuit design area

200: Alignment mark

210: Identify pattern area

214: Identifying structures

2142:Edges

220: Dummy pattern area

R1, R2, R3: frame selection area

D1: first direction

D2: second direction

5-5: Line segment

Claims (8)

A plate with alignment marks, including: a substrate including a circuit design area; and an alignment mark located outside the circuit design area of the substrate, wherein the alignment mark includes: an identification pattern area, wherein the identification The pattern area includes a bright area and an identification structure, and the identification structure has an edge; and a dummy pattern area, wherein the brightness of the dummy pattern area is smaller than the brightness of the identification pattern area. The plate with alignment marks as described in claim 1, wherein an area of the bright area is 80% to 90% of an area of the alignment marks, and an area of the dummy pattern area is 80% to 90% of an area of the alignment marks. 10% to 20% of the area. The plate with alignment marks as described in any one of claims 1 to 2, wherein the dummy pattern area includes a plurality of blocks. The board with alignment marks as described in any one of claims 1 to 2, wherein the substrate includes a first layer and a second layer, and the dummy pattern area includes a first dummy pattern located on the first layer. The pattern layer and a second dummy pattern layer located on the second layer, and the first dummy pattern layer and the second dummy pattern layer of the dummy pattern area are interlaced in a top view. A method of manufacturing a board with alignment marks, including: providing a substrate, wherein the substrate includes a circuit design area; and forming an alignment mark on the substrate, wherein the alignment mark is located outside the circuit design area , and forming the alignment mark further includes: forming a first metal layer material; forming a first anti-reflective layer material on the first metal layer material; and patterning the first metal layer material and the first anti-reflective layer layer material to form a plurality of blocks of a first dummy pattern layer of an identification pattern area and a dummy pattern area, wherein the brightness of the dummy pattern area is smaller than the brightness of the identification pattern area, and the identification pattern area also includes an identification structure , the recognition structure has an edge. The method of manufacturing a plate with alignment marks as described in claim 5, wherein forming the dummy pattern area further includes: making an area of the dummy pattern area 10% to 20% of an area of the alignment mark. The manufacturing method of a plate with alignment marks as claimed in claim 5, wherein forming the dummy pattern area further includes: forming a second dummy pattern layer in the dummy pattern area before forming the first dummy pattern layer, The first dummy pattern layer and the second dummy pattern layer in the dummy pattern area are interlaced in a top view. The manufacturing method of a plate with alignment marks as described in claim 7, wherein forming the identification pattern area further includes: patterning the first anti-reflection layer material in the identification pattern area to form a bright area, and the bright area An area of the zone is 80% to 90% of an area of the alignment mark.

Images