TWI830176B - Data clock tracking system and phase error generation improving method - Google Patents

Abstract

A data clock tracking system including a linear phase detection circuit and a bang-bang phase detection (BBPD) circuit. Based on the linear phase detection circuit as the base, the BBPD circuit is turned on at different data edges through a design of allocating detection circuits at specific edges to provide additional loop gain. The data clock tracking system appropriately allocates the number of linear phase detection circuits and binary phase detection circuits used on the plurality of transition edges of a plurality of data.

Description

Data clock tracking system and phase error generation improvement method

The present invention relates to data clock tracking, and in particular to a data clock tracking system and a phase error generation improvement method.

Generally speaking, the current phase detection circuit mainly has the following two design architectures: one is the binary phase detection (Bang-Bang Phase Detection, BBPD) architecture, and the other is the linear phase detection (Linear Phase Detection). Linear PD) architecture. Please refer to FIGS. 1 and 2 , which respectively illustrate comparison diagrams of the phase error and phase detection gain of the traditional binary phase detection (BBPD) architecture and the linear phase detection (Linear PD) architecture.

The traditional binary phase detection architecture will generate fixed integral gain (Integral Gain) and proportional gain (Proportional Gain) after each comparison of the phase lead/lag relationship between the system clock and the input data, regardless of the phase lead/lag. Why do all the amplitudes and sizes output the same gain adjustment system clock signal? Therefore, the traditional binary phase detection architecture will not have phase offset caused by circuit delay in the judgment of phase lead/lag, and the fixed phase lead/lag gain ratio is also better resistant to process variations. .

However, the disadvantage of the traditional binary phase detection architecture is that it will constantly maintain a dynamic balance of phase lead/lag. Even when the circuit is stable, the clock jitter generated by it is still very large, resulting in the traditional binary phase detection architecture. The phase detection architecture has a strong dependence on the data pattern (Pattern), so it is difficult to achieve a better balance between clock jitter and signal tracking capabilities. Please refer to Figure 3, which is a schematic diagram illustrating the data lock status and the differences between different data types.

As for the traditional linear phase detection architecture, it usually has smaller clock jitter and better signal tracking capability. The reason is that when the detection phase error (Phase Error) of the traditional linear phase detection architecture itself is close to zero, It will produce a small integral gain (Integral Gain) - that is, the amount of tracking variation of frequency changes. When encountering a large phase lead/lag, a large integral gain will be provided to follow the signal. Therefore, when the circuit is stable, it will It only produces small clock jitter by itself.

However, the traditional linear phase detection architecture may also cause additional phase offset (Phase Offset) due to the delay of its own circuit, and is therefore susceptible to process variation (Process Voltage Temperature, PVT) such as non-ideal factors, and this Phase offset cannot be reflected in the lead/lag calibration in the traditional linear phase detection architecture, and this phenomenon will become more significant as the bandwidth design increases and the data clock becomes higher. As shown in Figure 4, the phase error generated by the traditional linear phase detection architecture is normally stable, causing the setup time (Setup time) T _setup and retention time (Hold time) T _hold of the sampling data to be compressed.

From the above, it can be seen that the above-mentioned problems encountered by the previous technology still need to be further solved.

Therefore, the present invention proposes a data clock tracking system and a phase error generation improvement method that can combine the advantages of the binary phase detection (BBPD) architecture and the linear phase detection (Linear PD) architecture, so as to effectively solve the problems of the prior art. Encountered the above problems.

A preferred embodiment according to the present invention is a data clock tracking system. In this embodiment, the data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. Based on the linear phase detection circuit, through the design of the specific edge distribution detection circuit, the binary phase detection circuit is activated at different data edges to provide additional loop gain. The data clock tracking system appropriately allocates the number of linear phase detection circuits and binary phase detection circuits to the plurality of data edges of the plurality of pieces of data.

In one embodiment, different locking schemes are used on the plurality of data edges.

In one embodiment, the same locking scheme is used on the plurality of data edges.

In one embodiment, the plurality of pieces of data have different data conversion densities.

In one embodiment, the plurality of pieces of data have the same data conversion density.

In one embodiment, a binary phase detection circuit generates a binary phase detection signal and simultaneously provides an integral gain of the loop and a proportional gain of the loop.

In one embodiment, the linear phase detection circuit also generates a linear phase detection signal synchronously, and simultaneously provides the integral gain of the loop and the proportional gain of the loop.

In one embodiment, the data clock tracking system is a clock data recovery circuit (Clock Data Recovery, CDR), a phase-frequency lock loop (Phase-Lock Loop, PLL), and/or other circuits with phase tracking functions.

In one embodiment, the data clock tracking system may include a phase error judgment circuit, respectively coupled to a linear phase detection circuit and a binary phase detection circuit, for judging whether the phase error is greater than a preset value. If the judgment result If yes, the binary phase detection circuit is activated for phase detection at the same time to provide additional loop gain.

In one embodiment, the binary phase detection circuit can be synchronized and normally enabled on different data edges.

Another preferred embodiment according to the present invention is a method for improving phase error generation. In this embodiment, the phase error generation improvement method is applied to the data clock tracking system. The data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. The phase error generation improvement method includes the following steps: (a) activating the linear phase detection circuit for phase detection; (b) activating the binary phase detection circuit on different data edges; and (c) binary phase detection The detection circuit assists the linear phase detection circuit in locking on different data edges. The phase error generation improvement method appropriately allocates the number of linear phase detection circuits and binary phase detection circuits on multiple data edges.

In one embodiment, different locking schemes are used on the plurality of data edges.

In one embodiment, the same locking scheme is used on the plurality of data edges.

In one embodiment, the plurality of pieces of data have different data conversion densities.

In one embodiment, the plurality of pieces of data have the same data conversion density.

In one embodiment, a binary phase detection circuit generates a binary phase detection signal and simultaneously provides an integral gain of the loop and a proportional gain of the loop.

In one embodiment, the linear phase detection circuit also generates a linear phase detection signal synchronously, and simultaneously provides the integral gain of the loop and the proportional gain of the loop.

In one embodiment, the data clock tracking system is a data clock recovery circuit, a phase frequency tracking loop and/or other circuits with phase tracking functions.

In one embodiment, step (b) may first determine whether the phase error at the edge of the data is greater than a preset value. If the determination result is yes, the binary phase detection circuit is activated to perform phase detection at the same time to provide additional loop gain.

In one embodiment, step (b) can enable the binary phase detection circuit synchronously and normally on different data edges.

Compared with the prior art, the data clock tracking system and the phase error generation improvement method of the present invention hybridize the advantages of the linear phase detection circuit and the binary phase detection circuit architecture, allowing for better tracking. In addition to the locking capability, it can also produce smaller clock jitter to maintain circuit stability, and it also has lower dependence on changes in data conversion density, thereby enhancing the circuit's resistance to process variations during mass production.

The present invention provides a novel loop locking circuit architecture design, which mixes the advantages of a linear phase detection circuit (Linear Phase Detector, LINPD or PFD) and a binary phase detection circuit (Bang-Bang Phase Detector, BBPD), and Through the design of the circuit architecture to reduce the generation of phase errors and reduce their dependence on data density, the lock-tracing capability and circuit stability can be improved.

A preferred embodiment according to the present invention is a data clock tracking system. In this embodiment, the data clock tracking system of the present invention at least includes a linear phase detection circuit and a binary phase detection circuit. In fact, the data clock tracking system can be a data clock recovery circuit (Clock Data Recovery, CDR), a phase-frequency lock loop (Phase-Lock Loop, PLL) and/or other circuits with phase tracking functions, and there is no specific restrictions.

It should be noted that the data clock tracking system of the present invention mainly uses a linear phase detection circuit for phase locking and a binary phase detection circuit to synchronously detect the lead/lag of the data phase. Once the detected phase If the error is too large, the binary phase detection circuit will be turned on to assist in loop locking. Therefore, when the circuit is stable, it not only has the advantage of smaller jitter of the linear phase detection circuit, but also has the advantage of smaller phase error of the binary phase detection circuit itself.

Specifically, the data clock tracking system of the present invention is based on a linear phase detection circuit, and is designed to appropriately allocate linear phase detection on multiple data edges of multiple pieces of data through the allocation detection circuit of specific data edges. The number of detection circuits and binary phase detection circuits is increased to provide additional loop gain by activating the binary phase detection circuits at different data edges.

For example, as shown in Figure 5, assuming that the data signal DAT sequentially includes a plurality of pieces of data D0~D9 and the plurality of pieces of data D0~D9 have a plurality of data edges E0~E10, the data clock tracking system 5 can selectively It is allocated that binary phase detection is used on the data edges E1, E3, E5, E7, and E9 and mixed mode phase detection is used on the data edges E2, E4, E6, E8, and E10, but is not limited to this.

When the data clock tracking system 5 uses binary phase detection on the data edges E1, E3, E5, E7, and E9, the data clock tracking system 5 performs phase locking by the binary phase detection unit 52. Bypass the linear phase detection unit 50 . When the data clock tracking system 5 uses mixed mode phase detection on the data edges E2, E4, E6, E8, and E10, the data clock tracking system 5 mainly uses the linear phase detection circuit 50 for phase locking. As shown in FIG. 6 , once the synchronized detected phase error is too large (for example, greater than KΦ), the (auxiliary) binary phase detection circuit 52 will be activated to assist loop locking to provide additional phase detection gain.

Therefore, compared with the traditional data clock tracking circuit that configures a phase detection circuit at the data edge of each data to ensure that the change of each data edge is tracked, the present invention can configure the detection circuit of different data edges according to the user. The test architecture can be applied to different types of data according to needs. By designing the locking pattern at the edge of each data, it can effectively reduce its dependence on the data.

In practical applications, the data clock tracking system of the present invention can adopt different or the same locking structure on the plurality of data edges, and the plurality of data can have different or the same data conversion density without specific restrictions. The binary phase detection circuit generates a binary phase detection signal and simultaneously provides the integral gain of the loop and the proportional gain of the loop. Similarly, the linear phase detection circuit also synchronously generates a linear phase detection signal and simultaneously provides the loop's integral gain and the loop's proportional gain.

Please refer to FIG. 7 , which is a schematic diagram of a data clock tracking system in a preferred embodiment of the present invention. As shown in Figure 7, in this embodiment, the data clock tracking system 7 includes a linear phase detection circuit 70, a binary phase detection circuit 72, a phase error judgment circuit 74, a first charge pump CP1, a second charge pump Pump CP2 and voltage controlled oscillator VCO. The linear phase detection circuit 70 is coupled to the first charge pump CP1. The binary phase detection circuit 72 is coupled to the second charge pump CP2. The first charge pump CP1 and the second charge pump CP2 are both coupled to the voltage controlled oscillator VCO. The voltage controlled oscillator VCO is coupled to the linear phase detection circuit 70 and the binary phase detection circuit 72 respectively.

The phase error determination circuit 74 is respectively coupled to the linear phase detection circuit 70 and the binary phase detection circuit 72 for determining whether the phase error is greater than a preset value. If the judgment result of the phase error judgment circuit 74 is yes, that is, the phase error is greater than the preset value, in addition to the originally activated linear phase detection circuit 70, the data clock tracking system 7 will also activate the binary phase at the same time. The detection circuit 72 is phase locked to provide additional loop gain. If the judgment result of the phase error judgment circuit 74 is no, that is, the phase error is not greater than the preset value, only the linear phase detection circuit 70 remains activated. The first charge pump CP1 and the second charge pump CP2 respectively generate a first current ICP1 and a second current ICP2 to the voltage controlled oscillator VCO, and the first current ICP1>>second current ICP2. The voltage controlled oscillator VCO outputs m phase clock pulses to the binary phase detection circuit 72 .

Please refer to FIG. 8 , which illustrates a timing diagram in which the present invention deploys the detection architecture of different data edges according to the user to apply to different types of data according to needs. As shown in Figure 8, it is assumed that the data signal DAT includes (n+1) pieces of data D0~Dn in sequence and the (n+1) pieces of data D0~Dn have (n+1) data edges E0~En. At the data edge E1 between data D0 and D1, the linear phase detection circuit is activated and the linear phase detection signal output by it includes a rising signal UP and a falling signal DN. At this time, since the phase error Φ of the rising signal UP leading the falling signal DN is not greater than the preset value (delay time) Td, the auxiliary binary phase detection circuit and the binary phase detection circuit will not be activated. At the data edge E2 between data D1 and D2, the linear phase detection circuit is still activated and the phase error Φ of the rising signal UP it outputs leads the falling signal DN is greater than the preset value (delay time) Td, so the auxiliary binary The phase detection circuit will start at the same time and output the rising signal UP. By analogy, at the data edge En between data Dn-1 and Dn, the linear phase detection circuit will start and the phase error Φ of its output falling signal DN leading the rising signal UP is greater than the preset value Td, so the auxiliary circuit 2 The elemental phase detection circuit will start at the same time and output the falling signal DN.

Please refer to FIG. 9 , which is a schematic diagram of another embodiment of the data clock tracking system of the present invention. As shown in FIG. 9 , the data clock tracking system 9 may include a plurality of linear phase detection circuits 90 , a plurality of phase error judgment circuits 92 and a plurality of binary phase detection circuits 94 . The linear phase detection circuit 90 is coupled to the phase error determination circuit 92 . The phase error judgment circuit 92 is coupled to the binary phase detection circuit 94 . The linear phase detection circuit 90 and the phase error judgment circuit 92 both receive the delayed clock signal CLK[d] and operate according to the delayed clock signal CLK[d]. The linear phase detection circuit 90 outputs the linear phase detection signal (including the rising signal UP and the falling signal DN) to the phase error judgment circuit 92 . The phase error judgment circuit 92 judges whether the phase error Φ between the rising signal UP and the falling signal DN is greater than the preset value (delay time) Td, and then outputs a high-level or low-level flag signal FLAG to 2 based on the judgment result. The binary phase detection circuit 94 is used to control the binary phase detection circuit 94 to turn on or off.

Please refer to FIG. 10 , which illustrates an embodiment of a phase error determination circuit. As shown in Figure 10, the phase error judgment circuit 92 includes input terminals IN1~IN3, output terminals OUT, delays td1~td2, D-type flip-flops DFF1~DFF2 and inverters NAND1~NAND2. The input terminal IN1 is coupled to the delayer td1 and the D-type flip-flop DFF2 respectively. The input terminal IN2 is coupled to the delayer td2 and the D-type flip-flop DFF1 respectively. The delayer td1 is coupled to the D-type flip-flop DFF1. The delayer td2 is coupled to the D-type flip-flop DFF2. The output terminals of the D-type flip-flops DFF1 and DFF2 are respectively coupled to the two input terminals of the inverter NAND1. The output terminal of the NAND gate NAND1 is coupled to the output terminal OUT. The two input terminals of the NAND gate NAND2 are respectively coupled to the output terminal and the input terminal IN3 of the NAND gate NAND1. The output terminals of the NAND gate NAND2 are coupled to the D-type flip-flops DFF1 and DFF2 respectively.

The input terminals IN1~IN3 respectively receive the rising signal UP, the falling signal DN and the delayed clock signal CLK[d]. The delayer td1 receives the rising signal UP and delays it by a preset value (delay time) to become a delayed rising signal UPd and then outputs it to the input terminal D of the D-type flip-flop DFF1. The delayer td2 receives the falling signal DN and delays it by a preset value (delay time) to become a delayed falling signal DNd and then outputs it to the input terminal D of the D-type flip-flop DFF2. The input terminal CLK of the D-type flip-flop DFF1 receives the falling signal DN. The input terminal CLK of the D-type flip-flop DFF2 receives the rising signal UP. The output terminal of the NAND gate NAND1 outputs a flag signal FLAG to control the binary phase detection circuit BBPD to turn on or off.

As shown in Figure 11, since the phase error Φ of the falling signal DN output by the linear phase detection circuit leads the rising signal UP is less than the preset value (delay time) Td, the flag signal FLAG is maintained at a low level and will not turn on both at the same time. Yuan type phase detection circuit. As shown in Figure 12, since the phase error Φ of the falling signal DN output by the linear phase detection circuit leads the rising signal UP is greater than the preset value (delay time) Td, the flag signal FLAG will change from low level to high level at the same time as the rising signal UP. to a high level to simultaneously turn on the binary phase detection circuit. Until the delayed clock signal CLK[d] changes from a high level to a low level, the flag signal FLAG will change from a high level to a low level to turn off the binary phase. Detection circuit.

In practical applications, the binary phase detection circuit can be synchronized and normally activated on different data edges, but is not limited to this.

Another preferred embodiment according to the present invention is a method for improving phase error generation. In this embodiment, the phase error generation improvement method is applied to a data clock tracking system and the data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. In fact, the data clock tracking system can be a data clock recovery circuit, a phase frequency tracking loop and/or other circuits with phase tracking functions, but is not limited thereto.

Please refer to FIG. 13 , which illustrates a flow chart of a phase error generation improvement method in this embodiment. As shown in Figure 13, the phase error generation improvement method may include the following steps:

Step S10: Start the linear phase detection circuit for phase detection;

Step S12: Determine whether the circuit frequency is locked;

Step S14: If the determination result of step S12 is yes, activate the binary phase detection circuit on different data edges; and

Step S16: The binary phase detection circuit assists the linear phase detection circuit in locking on different data edges;

If the judgment result in step S12 is no, return to step S10.

Among them, the phase error generation improvement method is to appropriately allocate the number of linear phase detection circuits and binary phase detection circuits on the plurality of data edges.

In practical applications, the binary phase detection circuit can use different or the same locking structure on the plurality of data edges to assist the linear phase detection circuit in locking, without specific restrictions. In addition, the plurality of pieces of data can have different or the same data conversion density, and there is no specific limit.

In this embodiment, the binary phase detection circuit generates binary phase detection signals (such as rising signal UP and falling signal DN) and simultaneously provides the integral gain of the loop and the proportional gain of the loop. Similarly, the linear phase detection circuit will also synchronously generate linear phase detection signals (such as rising signal UP and falling signal DN) and simultaneously provide the loop's integral gain and the loop's proportional gain.

It should be noted that step S14 may first determine whether the phase error at the edge of the data (for example, the phase difference between the rising signal UP and the falling signal DN) is greater than a preset value (for example, the delay time). If the determination result is yes, at the same time Activate the binary phase detection circuit for phase detection to provide additional loop gain. In addition, step S14 may also activate the binary phase detection circuit synchronously and normally on different data edges, but is not limited to this.

Compared with the prior art, the data clock tracking system and the phase error generation improvement method of the present invention hybridize the advantages of the linear phase detection circuit and the binary phase detection circuit architecture, allowing for better tracking. In addition to the locking capability, it can also produce smaller clock jitter to maintain circuit stability, and it also has lower dependence on changes in data conversion density, thereby enhancing the circuit's resistance to process variations during mass production.

UP: rising signal DN: falling signal DAT: data signal D0~Dn: data CLK: clock signal Thold: retention time Tsetup: setup time E0~En: data edge 5: data clock tracking system 50: linear phase detection circuit 52: (auxiliary) binary phase detection circuit 7: data clock tracking system 70: linear phase detection circuit 72: binary phase detection circuit 74: phase error judgment circuit CP1: first charge pump CP2: third Two charge pumps VCO: voltage controlled oscillator R: resistor C: capacitor I _CP1 : first current I _CP2 : second current Φ: phase error Td: preset value (delay time) FLAG: flag signal SDATA[n:0 ]: Data signal 9: Data clock tracking system 90: Linear phase detection circuit 92: Phase error judgment circuit 94: Binary phase detection circuit CLK[d]: Delayed clock signal IN1~IN3: Input terminal OUT: Output terminals td1~td2: delayer DFF1~DFF2: D-type flip-flop NAND1~NAND2: inverter UPd: delayed rising signal DNd: delayed falling signal S10~S16: steps

Figure 1 shows a comparison diagram of phase error and phase detection gain of a conventional binary phase detection (BBPD) architecture.

Figure 2 shows a comparison diagram of phase error and phase detection gain of a conventional linear phase detection architecture.

Figure 3 is a schematic diagram illustrating the data lock status and the differences between different data types.

Figure 4 is a schematic diagram illustrating the stability characteristics of a conventional linear phase detection architecture.

FIG. 5 is a schematic diagram illustrating the data clock tracking system of the present invention appropriately allocating the number of linear phase detection circuits and binary phase detection circuits on multiple data edges.

FIG. 6 shows a comparison diagram of phase error and phase detection gain of the mixed-mode phase detection architecture of the present invention.

FIG. 7 is a schematic diagram of a data clock tracking system in a preferred embodiment of the present invention.

FIG. 8 shows a timing diagram in which the present invention deploys the detection architecture of different data edges according to the user to apply to different types of data according to needs.

FIG. 9 is a schematic diagram of another embodiment of the data clock tracking system of the present invention.

FIG. 10 illustrates an embodiment of the phase error determination circuit.

Figure 11 shows a timing diagram when the phase error is less than the delay time.

Figure 12 shows a timing diagram when the phase error is greater than the delay time.

FIG. 13 is a flowchart illustrating a method for improving phase error generation in another preferred embodiment of the present invention.

5: Data clock tracking system

50: Linear phase detection circuit

52: (auxiliary) binary phase detection circuit

DAT: data signal

D0~D9: information

E0~E10: data edge

Claims (20)

A data clock tracking system includes: a linear phase detection circuit; and a binary phase detection circuit; wherein, based on the linear phase detection circuit as a base, through specific edge distribution detection circuit design, in different The data edge activates the binary phase detection circuit to provide additional loop gain; wherein, the data clock tracking system appropriately distributes the use of the linear phase detection circuit and the two data edges on the plurality of data edges. The number of elemental phase detection circuits. The data clock tracking system of claim 1, wherein different locking structures are used on the plurality of data edges. The data clock tracking system of claim 1, wherein the same locking structure is used on the plurality of data edges. The data clock tracking system of claim 1, wherein the plurality of pieces of data have different data conversion densities. The data clock tracking system of claim 1, wherein the plurality of pieces of data have the same data conversion density. The data clock tracking system of claim 1, wherein the binary phase detection circuit generates a binary phase detection signal and simultaneously provides an integral gain of the loop and a proportional gain of the loop. The data clock tracking system as described in claim 1, wherein the linear phase The bit detection circuit also generates a linear phase detection signal synchronously, and simultaneously provides the integral gain of the loop and the proportional gain of the loop. The data clock tracking system as described in claim 1, wherein the data clock tracking system is a data clock recovery circuit (Clock Data Recovery, CDR), a phase-frequency locking loop (Phase-Lock Loop, PLL) and/or Other circuits with phase tracking capabilities. The data clock tracking system of claim 1 may include: a phase error determination circuit, respectively coupled to the linear phase detection circuit and the binary phase detection circuit, for determining whether the phase error is greater than a preset value , if the judgment result is yes, the binary phase detection circuit is simultaneously activated to perform phase detection to provide additional loop gain. The data clock tracking system of claim 1, wherein the binary phase detection circuit (BBPD) can be synchronized on different data edges and is normally enabled. A phase error generation improvement method is applied to a data clock tracking system. The data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. The phase error generation improvement method includes the following steps: (a) starting The linear phase detection circuit performs phase detection; (b) the binary phase detection circuit is enabled on different data edges; and (c) the binary phase detection circuit assists the binary phase detection circuit on different data edges. Linear phase detection circuit for locking; Wherein, the phase error generation improvement method appropriately allocates the number of the linear phase detection circuit and the binary phase detection circuit on a plurality of data edges of a plurality of pieces of data. The phase error generation improvement method as claimed in claim 11, wherein different locking structures are used on the plurality of data edges. The phase error generation improvement method as claimed in claim 11, wherein the same locking structure is used on the plurality of data edges. The phase error generation improvement method as claimed in claim 11, wherein the plurality of pieces of data have different data conversion densities. The phase error generation improvement method as claimed in claim 11, wherein the plurality of pieces of data have the same data conversion density. The phase error generation improvement method as claimed in claim 11, wherein the binary phase detection circuit generates a binary phase detection signal and simultaneously provides an integral gain of the loop and a proportional gain of the loop. The method for improving phase error generation as described in claim 11, wherein the linear phase detection circuit also generates a linear phase detection signal synchronously and simultaneously provides the integral gain of the loop and the proportional gain of the loop. The phase error generation improvement method as described in claim 11, wherein the data clock tracking system is a data clock recovery circuit (Clock Data Recovery, CDR), a phase-frequency tracking loop (Phase-Lock Loop, PLL) and/or Other circuits with phase tracking capabilities. The phase error generation improvement method according to claim 11, wherein Step (b) can first determine whether the phase error at the edge of the data is greater than a preset value. If the determination result is yes, the binary phase detection circuit is simultaneously activated for phase detection to provide additional loop gain. The phase error generation improvement method as claimed in claim 11, wherein step (b) can synchronously and normally activate the binary phase detection circuit on different data edges.

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