TWI829106B - Electronic device including driver circuit and driving method thereof - Google Patents

Abstract

The disclosure provides an electronic device including a driver circuit and a driving method thereof. The driver circuit includes an electronic unit, a driver unit, and a detection and protection circuit. The driver unit is electrically connected to the electronic unit. The detection and protection circuit is electrically connected to the electronic unit by a first node, and electrically connected to a gate terminal of the driver unit by a second node. When a voltage of the first node is pulled down, the detection and protection circuit controls the driver unit to turn off. The detection and protection circuit of the driver circuit of the disclosure protects the electronic unit from excessive current.

Description

Electronic device including driving circuit and driving method thereof

The present disclosure relates to an electronic device, and in particular to a driving circuit including a detection protection circuit and a driving method thereof.

Driving circuits generally used to drive display panels or backlight panels, such as those used to drive active-matrix organic light emitting diodes (AMLED), do not have the function of detecting current. When electronic units such as light-emitting units or other electronic components are short-circuited or damaged, the passing current may rise sharply, resulting in risks such as increased power consumption and overheating and burning of the electronic unit. In view of this, in order to quickly cut off the power supply source to protect the electronic unit from being affected by excessive current, several embodiment solutions will be proposed below.

The present disclosure proposes an electronic device including a driving circuit and a driving method thereof, which can detect the voltage passing through the electronic unit and protect the electronic unit from being affected by excessive current.

According to an embodiment of the present disclosure, the electronic device of the present disclosure includes a driving circuit, and the driving circuit includes an electronic unit, a driving unit and a detection and protection circuit. The driving unit is electrically connected to the electronic unit. The detection and protection circuit is electrically connected to the electronic unit via a first node, and is electrically connected to the gate terminal of the driving unit via a second node. When the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to turn off.

According to an embodiment of the present disclosure, the driving method of the driving circuit of the present disclosure includes: supplying a reset voltage to the first node during the reset period through the detection protection circuit; detecting during the scanning period through the detection protection circuit The voltage of the first node; and when the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to turn off.

Based on the above, the driving circuit of the present disclosure can be electrically connected to the electronic unit through the first node through the detection and protection circuit, and electrically connected to the gate terminal of the driving unit through the second node. When the detection and protection circuit determines that the voltage of the first node is pulled down, the driving unit can be controlled to turn off. In this way, power supply to the electronic unit can be stopped immediately to protect the electronic unit from being affected by excessive current.

The present disclosure can be understood by referring to the following detailed description in combination with the accompanying drawings. It should be noted that, in order to make it easy for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a part of the electronic device. And certain elements in the drawings are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

100, 200, 300, 400, 500, 600, 700, 800, P1, P2, Pn: drive circuit

100D: Electronic devices

100S:Substrate module

110: Electronic unit

120: Drive unit

130: Detection protection circuit

131, 132: Reset circuit

140: Pixel circuit

C1, C2, C3, C4, C5: capacitor

D1, D2, D3: Diode

DT: data voltage

DIS, DIS_b: reset signal

EM: Enable signal

N1, N2, N3, N4: nodes

R1, R2, R3: Resistors

S310, S320, S330: steps

SCN: scan signal

T1, T2, T3, T4, T5, T6, T7, T8, T9: transistor

TD: detection period

TDI: data writing period

TE: lighting period

TR: reset period

TS: During scanning

ARVDD, ARVSS: voltage

VRST: reset voltage

VREF: reference voltage

FIG. 1 is a circuit block diagram of a driving circuit according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of an implementation scenario of a driving circuit according to an embodiment of the present disclosure.

FIG. 3 is a schematic flowchart of a driving method according to an embodiment of the present disclosure.

FIG. 4 is a circuit schematic diagram of a driving circuit according to an embodiment of the present disclosure.

FIG. 5 is a schematic diagram of an operation waveform of a driving circuit according to an embodiment of the present disclosure.

FIG. 6 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 7 is a schematic diagram of operation waveforms of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 8 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 9 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 10 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 11 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

FIG. 12 is a circuit schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

Throughout this disclosure and the appended claims, certain words are used to refer to particular elements. Those skilled in the art will appreciate that display device manufacturers may refer to the same components by different names. This article is not intended to differentiate between components that have the same function but have different names. In the following description and claims, the words "including" and "include" are open-ended words, and therefore they should be interpreted to mean "including but not limited to...".

In some embodiments of the present disclosure, terms related to joining and connecting, such as "coupling", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that the two structures are not in direct contact. , there are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed. In addition, the term "coupling" includes any direct and indirect means of electrical connection.

The ordinal numbers used in the description and claims, such as "first", "second", etc., are used to modify elements. They themselves do not imply or represent that the element has any previous ordinal number, nor does it represent a certain The order of an element with another element, or the order of a manufacturing method, the use of multiple ordinal numbers is only used to clearly distinguish an element with a certain name from another element with the same name. The claims and the description may not use the same words. Accordingly, the first component in the description may be the second component in the claim. It should be noted that in the following embodiments, the technical features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure.

FIG. 1 is a circuit block diagram of a driving circuit 100 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 1 , the driving circuit 100 includes an electronic unit 110 , a driving unit 120 and a detection and protection circuit 130 . According to design requirements, in some embodiments, the electronic unit 110 may include one or more light-emitting units or other electronic components, and their number and arrangement may be determined according to actual requirements. Depending on the actual application, the one or more light-emitting units may include light-emitting diodes (LEDs), micro-LEDs (micro-LEDs), or organic light-emitting diodes (OLEDs). , Inorganic Light Emitting Diode (ILED), sub-millimeter light-emitting diode (Mini-LED), micro-LED (Micro-LED), electroluminescence (EL) components, laser This embodiment is not limited to diodes (Laser Diodes) or other types of light-emitting elements.

In this embodiment, the driving unit 120 is electrically connected to the electronic unit 110, and the driving unit 120 can turn on or off the voltage or current signal used to drive the electronic unit 110. The detection protection circuit 130 is electrically connected to the electronic unit 110 via node N1 (first node), and is electrically connected to the gate terminal (control terminal) of the driving unit 120 via node N2 (second node). The detection and protection circuit 130 can detect whether the voltage of the first node N1 changes (for example, a voltage pull-down) occurs to determine whether a short circuit or damage occurs in the electronic unit 110 . When the voltage of the first node N1 is pulled down, the detection protection circuit 130 can control the driving unit 120 to turn off, for example, through the second node N2 to control the driving unit 120 to turn off, so as to stop supplying power to the electronic unit 110, thereby protecting the electronic unit 110 from damage. due to excessive current.

FIG. 2 is a schematic diagram of an implementation scenario of an electronic device 100D according to an embodiment of the present disclosure. In the embodiment shown in FIG. 2 , one or more driving circuits P1, P2, ..., Pn can be configured in any electronic device 100D. In some embodiments, the electronic device 100D may include a plurality of driving circuits P1 to Pn. A plurality of driving circuits P1 ~ Pn can be disposed on a substrate to form a substrate module 100S. The plurality of driving circuits P1 to Pn can be arranged in a matrix, but the present invention is not limited to this. At least one of the plurality of driving circuits P1 to Pn may be the above-mentioned driving circuit 100, that is, may include the above-mentioned electronic unit 110, the above-mentioned driving unit 120, and the above-mentioned detection and protection circuit 130. According to some embodiments, each of the plurality of driving circuits P1 ~ Pn may be the above-mentioned driving circuit 100 . According to some embodiments, the electronic unit 110 may be a light-emitting unit to form an electronic device 100D with a display function. For example, the substrate module 100S itself can constitute a display panel for image display. Alternatively, according to some embodiments, the electronic unit 110 may be a light-emitting unit, and the substrate module 100S itself may serve as a backlight module. The substrate module 100S as a backlight module can be combined with a liquid crystal display panel to form an electronic device 100D with a display function. For example, when the driving circuits P1 to Pn are used as display panels to display images, one driving circuit may only include a single light-emitting unit. When the driving circuits P1 to Pn are used as backlight modules, one driving circuit may include multiple light-emitting units connected in series, but this embodiment does not set a limit. According to some embodiments, the electronic unit 110 may be a non-light-emitting unit. According to some embodiments, the electronic device 100D may be an antenna device, a liquid crystal display device, or a varactor device.

Figure 3 is a driving method of a driving circuit according to an embodiment of the present disclosure. process diagram. For the driving circuit 100 shown in FIG. 1 , reference may be made to the relevant description of FIG. 3 . Please refer to both Figure 1 and Figure 3. In step S310, the driving circuit 100 may supply the reset voltage (or reference voltage) to the first node N1 during the reset period through the detection protection circuit 130. In step S320, the detection protection circuit 130 may detect the voltage of the first node N1 during scanning. In step S330, when the detection protection circuit 130 detects that the voltage of the first node N1 is pulled down, the detection protection circuit 130 may turn off the driving unit 120 via the second node N2.

Please refer to Figure 4 and Figure 5. FIG. 4 is a circuit schematic diagram of a driving circuit 200 according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of an operation waveform of a driving circuit according to an embodiment of the present disclosure. The driving circuit 200 shown in FIG. 4 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . The embodiment shown in Fig. 5 can be used as the driving circuit 200 shown in Fig. 4, the driving circuit 400 shown in Fig. 8, the driving circuit 500 shown in Fig. 9, the driving circuit 600 shown in Fig. 10, the driving circuit 700 shown in Fig. 11 and (or Yes) A schematic diagram of the operation waveform of the driving circuit 800 shown in FIG. 12 . In the embodiment shown in FIG. 4 , the driving circuit 200 includes a pixel circuit 140 and a detection and protection circuit 130 . The pixel circuit 140 may include an electronic unit 110 and a driving unit 120. According to actual requirements, in some embodiments, the pixel circuit 140 may also include a switch unit T6, a control unit T7, a capacitor C3, and/or other components not shown in FIG. 4. This embodiment is not limited. In this embodiment, the electronic unit 110 may include multiple electronic units (for example, four in this embodiment) connected in series, but their number and arrangement are just an example, and this embodiment is not limiting. According to some embodiments, the electronic unit 110 may include a plurality of light emitting units.

In this embodiment, the driving unit 120 may include a transistor T8. For convenience of explanation, here, the switch unit T6 , the control unit T7 , and the transistor T8 are all P-type transistors as an example, but this embodiment is not limiting. In this embodiment, the first terminal of the switch unit T6 can receive the data voltage DT. The control end of the switch unit T6 can receive the scan signal SCN. The first terminal of transistor T8 can receive voltage ARVDD (first voltage). The driving unit 120 (for example, the control terminal of the transistor T8) can be electrically connected to the second terminal of the switching unit T6 through the second node N2. One end of the capacitor C3 can receive the first voltage ARVDD, and the other end of the capacitor C3 can be electrically connected to the second node N2. In this embodiment, the driving unit 120 (for example, the second terminal of the transistor T8) can be electrically connected to the first node N1 through the first terminal of the control unit T7. The control terminal of the control unit T7 can receive the enable signal EM. One end of the electronic unit 110 (for example, the anode ends of the plurality of light-emitting units) can be electrically connected to the second end of the control unit T7 through the first node N1. The other end of the electronic unit 110 (eg, the cathode end of the plurality of light-emitting units) may receive the voltage ARVSS (the second voltage). In this embodiment, the voltage level of the first voltage ARVDD may be higher than the voltage level of the second voltage ARVSS. For example, in some embodiments, the first voltage ARVDD may be a DC high level, and the second voltage ARVSS may be a DC low level or a ground level. In some embodiments, the switch unit T6, the control unit T7 and/or the transistor T8 may also be N-type transistors. In some embodiments, the voltage level of the first voltage ARVDD may also be lower than the voltage level of the second voltage ARVSS. For example, when the conductive type of the transistor T8 is N-type, the first voltage ARVDD may be a DC low level or a ground level, and the second voltage ARVSS may be a DC high level.

In this way, for the pixel circuit 140, the switch unit T6 can transmit the data voltage DT to the second node N2 according to the scan signal SCN. That is, the switch unit T6 can be used to supply the data voltage DT to the second node N2 during the scanning period TS. The capacitor C3 can stabilize the voltage level on the second node N2 according to the first voltage ARVDD. The transistor T8 in the driving unit 120 can transmit the first voltage ARVDD to the second terminal of the transistor T8 according to the voltage level on the second node N2. The control unit T7 can transmit the voltage level on the second end of the transistor T8 to the electronic unit 110 through the first node N1 according to the enable signal EM, so that the electronic unit 110 can transmit the voltage level between the first node N1 and the second voltage ARVSS according to the enable signal EM. potential difference to drive. That is, the control unit T7 is used to turn off TDI during data writing to stop power supply to the first node N1. In some embodiments, the electronic unit 110 may be a light-emitting unit. Thus, the electronic unit 110 may emit light according to the potential difference between the first node N1 and the second voltage ARVSS.

According to actual design requirements, in some embodiments, the detection and protection circuit 130 may include a transistor T1 (first transistor), a transistor T2 (a second transistor), a transistor T4 (a third transistor), a capacitor C1 ( The first capacitor), the capacitor C2 (the second capacitor), the reset unit 131, the reset unit 132 and/or other components not shown in FIG. 4 are not limited in this embodiment. The first transistor T1 may be electrically connected to the second node N2 for supplying the first voltage ARVDD to the second node N2 to turn off the driving unit 120 . The reset unit 131 may be electrically connected to the other end of the first capacitor C1 through the fourth node N4, and the reset unit 132 may be electrically connected to the first node N1. In this embodiment, the reset unit 131 may include a transistor T3, and the reset unit 132 may The transistor T5 may be included, but this embodiment is not limited thereto. For convenience of explanation, here, the transistors T1 to T5 are all P-type thin film transistors (Thin Film Transistor, TFT) as an example, but this embodiment is not limited. In some embodiments, at least one of the transistors T1 to T5 may also be an N-type transistor with a conductive type. In this embodiment, the first terminal of the first transistor T1 can receive the first voltage ARVDD. The second terminal of the first transistor T1 can be electrically connected to the control terminal of the transistor T8 in the driving unit 120 through the second node N2. In this embodiment, one end of the first capacitor C1 has a node N3 (third node), and the first capacitor C1 can be electrically connected to the gate terminal (control terminal) of the first transistor T1 through the third node N3. In this embodiment, one end of the second capacitor C2 can be electrically connected to the other end of the first capacitor C1 through the fourth node N4. In some embodiments, the other end of the second capacitor C2 may receive the second voltage ARVSS. In other embodiments, the other end of the second capacitor C2 can also receive the first voltage ARVDD or other DC levels, and this embodiment is not limited.

In some embodiments, the first terminal of the second transistor T2 may receive the first voltage ARVDD. The second terminal of the second transistor T2 may be electrically connected to the third node N3. The control terminal of the second transistor T2 can receive the reset signal DIS. In some embodiments, the first terminal of the transistor T3 in the reset unit 131 may receive the reset voltage VRST. The second terminal of the transistor T3 can be electrically connected to the fourth node N4. The control terminal of transistor T3 can receive the reset signal DIS. In some embodiments, the first terminal of the third transistor T4 may be electrically connected to the fourth node N4. The control terminal of the third transistor T4 can receive the scan signal SCN. In some embodiments, the first terminal of transistor T5 in reset unit 132 may receive reset voltage VRST. Transistor T5 No. The two terminals may be electrically connected to the first node N1 together with the second terminal of the third transistor T4. The control terminal of transistor T5 can receive the reset signal DIS. The reset voltage VRST may be a DC level between the first voltage ARVDD and the second voltage ARVSS. In some embodiments, the reset voltage VRST may be less than a voltage level required to drive the electronic unit 110 to prevent the electronic unit 110 from being driven by the reset voltage VRST. For example, in some embodiments, the first voltage ARVDD may be set to 15 volts (volt), and the second voltage ARVSS may be set to 0 volts, assuming that the voltage level required to drive the electronic unit 110 is 10 volts (2.5*4) , then the reset voltage VRST can be set to 9 volts, but this embodiment does not set a limit.

In this way, for the detection and protection circuit 130, the second transistor T2 can transmit the first voltage ARVDD to the third node N3 according to the reset signal DIS. The transistor T3 in the reset unit 131 may transmit the reset voltage VRST to the fourth node N4 according to the reset signal DIS. The transistor T5 in the reset unit 132 may transmit the reset voltage VRST to the first node N1 according to the reset signal DIS. The second capacitor C2 can be used as a voltage stabilizing capacitor to stabilize the voltage level on the fourth node N4 according to the second voltage ARVSS (or the first voltage ARVDD or other DC levels). The third transistor T4 can conduct the fourth node N4 and the first node N1 according to the scan voltage SCN. And the first transistor T1 can provide the first voltage ARVDD to the second node N2 according to the voltage level of the third node N3. If at least one of the plurality of electronic units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 will be pulled down instantaneously, and the voltage level of the fourth node N4 will also be pulled down. At this time, based on the coupling (coupled) of the first capacitor C1, the voltage level of the third node N3 is also lowered. pull. For example, assuming that the voltage level of the first node N1 is pulled down from the reset voltage VRST to the short-circuit voltage VST (VST<VRST), the voltage level of the third node N3 is ARVDD+(VST-VRST). Then when the potential difference between the control terminal and the second terminal of the first transistor T1 is lower than the threshold voltage VTH (Threshold voltage) of the first transistor T1, that is, ARVDD+(VST-VRST)<ARVDD-VTH, the first voltage Crystal T1 is turned on. The first transistor T1 will supply the first voltage ARVDD to the second node N2 to cut off (turn off) the transistor T8 in the driving unit 120, so that the transistor T8 stops supplying power to the first node N1, thereby protecting the electronic unit 110 from being damaged. Effect of excessive current.

For the waveform diagram of the above action, reference may be made to the embodiment shown in FIG. 5 . The horizontal axis shown in Figure 5 represents time. In the embodiment shown in FIG. 5 , when the electronic unit 110 shown in FIG. 4 is to be driven, the enable signal EM can first be switched from a logic low level to a logic high level, so that the driving circuit 200 enters the data writing period TDI. At this time, the control unit T7 in the pixel circuit 140 is turned off, that is, switched from an on state to an off state, so as to stop supplying power to the first node N1. During the data writing period TDI, when the reset signal DIS switches from a logic high level to a logic low level, the driving circuit 200 enters the reset period TR. At this time, the second transistor T2 in the detection and protection circuit 130 can supply the first voltage ARVDD to the third node N3 (ie, one end of the first capacitor C1), and the transistor T3 in the reset unit 131 can supply the reset voltage VRST. The reset voltage VRST is transmitted to the fourth node N4 (ie, the other end of the first capacitor C1 ), and the transistor T5 in the reset unit 132 may supply the reset voltage VRST to the first node N1 . The first node N1 and the fourth node N4 are both charged to the reset voltage VRST, and the third node N3 is charged After charging to the first voltage ARVDD (assumed to be a logic high level here), the first transistor T1 is in the off state.

Assuming that the electronic unit 110 is operating normally at this time (for example, all light-emitting units can emit light normally), the voltage level of the first node N1 will remain unchanged (reset voltage VRST). Then, when the scan signal SCN switches from a logic high level to a logic low level, the driving circuit 200 enters the scan period TS (herein equal to the detection period TD). The switch unit T6 in the pixel circuit 140 can transmit the data voltage DT to the second node N2, and the third transistor T4 can conduct the first node N1 and the fourth node N4 (ie, the other end of the first capacitor C1). That is, according to some embodiments, the third transistor T4 is electrically connected to the first node N1, and the third transistor T4 is used to conduct the other side of the first node N1 and the first capacitor C1 during the detection period TD or the scanning period TS. One end. Since the voltage levels of the first node N1 and the fourth node N4 are the same, the first capacitor C1 is in a floating state, so the voltage level of the third node N3 will also remain unchanged (the first voltage ARVDD), so that the first voltage Crystal T1 remains in the off state. Finally, when the data voltage DT is completely written and the enable signal EM switches from a logic high level to a logic low level, the driving circuit 200 enters the lighting period TE. At this time, the control unit T7 will switch from the off state to the on state, and the transistor T8 in the driving unit 120 will transmit the first voltage ARVDD to the first node N1 through the control unit T7 according to the data voltage DT to drive the electronic unit 110. Therefore, when no voltage abnormality occurs in the electronic unit 110, the detection protection circuit 130 will not affect the normal operation of the pixel circuit 140.

Also assuming that at least any one of the plurality of light-emitting units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 will be instantly pulled down. Then be a sweeper When the scanning signal SCN switches from a logic high level to a logic low level, the driving circuit 200 enters the scanning period TS. The switch unit T6 will transmit the data voltage DT to the second node N2, and the third transistor T4 will conduct the first node N1 and the fourth node N4. Since the voltage level of the first node N1 is pulled down, the voltage levels of the fourth node N4 and the third node N3 will also be pulled down sequentially. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 will be charged (charging) to the first voltage ARVDD through the first transistor T1, causing the transistor T8 to enter a cut-off state. . Finally, when the enable signal EM switches from a logic high level to a logic low level, the driving circuit 200 enters the lighting period TE. Although the control unit T7 will switch from the off state to the on state at this time, since the transistor T8 still maintains the off state at this time, no current will flow through the electronic unit 110, which can protect the electronic unit 110 from being affected by excessive current.

Please refer to Figure 6 and Figure 7. FIG. 6 is a schematic circuit diagram of a driving circuit 300 according to yet another embodiment of the present disclosure. FIG. 7 is a schematic diagram of operation waveforms of a driving circuit according to yet another embodiment of the present disclosure. The driving circuit 300 shown in FIG. 6 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 6 , the driving circuit 300 includes a pixel circuit 140 and a detection and protection circuit 130 . For the implementation of the pixel circuit 140, reference can be made to the relevant description of the pixel circuit 140 shown in FIG. 4 and will not be described again here. What is different from the embodiment shown in FIG. 4 is that the control end of the third transistor T4 shown in FIG. 6 can also receive a reset signal DIS_b that is different from the scan signal SCN. According to actual requirements, in some embodiments, the detection and protection circuit 130 shown in FIG. 6 may also include a capacitor C4 (third capacitor) and/or a resistor R1. The third capacitor C4 One end of the third capacitor C4 can be electrically connected to the third node N3, and the other end of the third capacitor C4 can receive the first voltage ARVDD. The third capacitor C4 can stabilize the current on the third node N3. One end of the resistor R1 can be electrically connected to the first end of the third transistor T4, and the other end of the resistor R1 can be electrically connected to the other end of the first capacitor C1 through the fourth node N4. For the resistor R1, its resistance across voltage is the potential difference between the first node N1 and the fourth node N4.

For the waveform diagram of the operation of the embodiment shown in FIG. 6, reference can be made to the embodiment shown in FIG. 7. The horizontal axis shown in Figure 7 represents time. In the embodiment shown in FIG. 7 , the implementation of the enable signal EM, the reset signal DIS, and the scan signal SCN may refer to the relevant descriptions of the enable signal EM, the reset signal DIS, and the scan signal SCN shown in FIG. 5 . What is different from the embodiment shown in FIG. 5 is that the action waveform diagram shown in FIG. 7 also includes a reset signal DIS_b. In detail, when the enable signal EM switches from a logic low level to a logic high level, the driving circuit 300 shown in FIG. 6 enters the data writing period TDI. At this time, the control unit T7 will switch from the on state to the off state to stop supplying power to the electronic unit 110 . During the data writing period TDI, when both the reset signal DIS and the reset signal DIS_b switch from a logic high level to a logic low level, the driving circuit 300 enters the reset period TR. At this time, the third node N3 will be charged to the first voltage ARVDD through the second transistor T2, the first transistor T1 is in the off state, and the third capacitor C4 can stabilize the voltage level of the third node N3 according to the first voltage ARVDD. The fourth node N4 will be charged to the reset voltage VRST through the transistor T3, and the first node N1 will be charged to the reset voltage VRST through the transistor T5.

Then, when the reset signal DIS switches from a logic low level to a logic high level, While the reset signal DIS_b remains at a logic low level, the driving circuit 300 enters the detection period TD (which is different from the detection period TD in FIG. 5 and is equal to the scanning period TS). At this time, the second transistor T2, the transistor T3 and the transistor T5 It will switch from the on state to the off state, and the third transistor T4 maintains the on state. Assuming that at least one of the plurality of light-emitting units in the electronic unit 110 is short-circuited or damaged at this time, the voltage level of the first node N1 and the voltage level of one end of the resistor R1 (electrically connected to the third transistor T4) The voltage levels of the fourth node N4 and the third node N3 will also be pulled down in sequence. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 will be charged to the first voltage ARVDD through the first transistor T1 to turn off the transistor T8, thereby stopping power supply to the The electronic unit 110 is used to protect the electronic unit 110 from being affected by excessive current. This embodiment uses the driving circuit 300 in FIG. 6 to illustrate the situation where the detection protection circuit 130 controls the driving unit 120 to turn off when the voltage of the first node N1 is pulled down. However, according to some embodiments, similar to the driving circuit 300 of FIG. 6 , the driving circuit 200 of FIG. 5 can also detect the situation where the protection circuit 130 controls the driving unit 120 to turn off when the voltage of the first node N1 is pulled down. Here, No more details.

FIG. 8 is a circuit schematic diagram of a driving circuit 400 according to yet another embodiment of the present disclosure. The driving circuit 400 shown in FIG. 8 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 8 , the driving circuit 400 includes a pixel circuit 140 and a detection and protection circuit 130 . For the implementation of the pixel circuit 140, reference can be made to the relevant description of the pixel circuit 140 shown in FIG. 4 and will not be described again here. What is different from the embodiment shown in Figure 4 is that, according to actual needs, the detection and protection circuit 130 shown in Figure 8 can One or more diodes D1 (for example, three in this embodiment) connected in series and/or a capacitor C5 are used to replace the first capacitor C1 and/or a capacitor C5 in the embodiment shown in FIG. 4 second capacitor C2. In detail, one end (such as the anode end) of one or more diodes D1 can be electrically connected to the third node N3, and the other end (such as the cathode end) of the one or more diodes D1 can pass through the fourth node. N4 is electrically connected to the first terminal of the third transistor T4. One end of the capacitor C5 can be electrically connected to the third node N3, and the other end of the capacitor C5 can receive the second voltage ARVSS or other voltage levels. The capacitor C5 can be used as a voltage stabilizing capacitor to stabilize the voltage level on the third node N3 according to the second voltage ARVSS or other voltage levels. In some embodiments, one or more diodes D1 may be implemented using transistors, and this embodiment is not limited thereto.

For detailed operation waveforms of the embodiment shown in FIG. 8, reference may be made to the embodiment shown in FIG. 5. It should be noted that during the reset period TR, the third node N3 shown in Figure 8 will be charged to the first voltage ARVDD through the second transistor T2, and the fourth node N4 will be charged to the reset state through the transistor T3. Voltage VRST. In some embodiments, the potential difference ARVDD-VRST between the third node N3 and the fourth node N4 at this time may be less than the voltage level that turns on one or more diodes D1 to avoid one or more diodes D1 TR is driven during reset. And during the scanning period TS, the third transistor T4 may conduct (for example, through the fourth node N4) the first node N1 and the other end of the one or more diodes D1. Suppose that when at least one of the plurality of light-emitting units in the electronic unit 110 is short-circuited or damaged, the voltage levels of the first node N1 and the fourth node N4 will be instantly pulled down from the reset voltage VRST to the short-circuit voltage VST, and then Assuming that the voltage level of the third node N3 is Vc' at this time, then the voltage level of one or more diodes D1 The cross voltage, that is, the potential difference Vc'-VST between the third node N3 and the fourth node N4, may be greater than or equal to the voltage level that turns on one or more diodes D1. As a result, since one or more diodes D1 are turned on, the voltage level of the third node N3 will also be pulled down. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 will be charged to the first voltage ARVDD to turn off the transistor T8, thereby stopping power supply to the first node N1. Regarding the remaining driving circuit 400 shown in FIG. 8 , when the electronic unit 110 is operating normally or at least one of the plurality of light-emitting units is short-circuited or damaged, the detailed operations and waveforms of the driving circuit 400 can be obtained from the above-mentioned FIG. 4 and FIG. 5 . The relevant descriptions of the embodiments are analogized and will not be repeated here.

FIG. 9 is a circuit schematic diagram of a driving circuit 500 according to yet another embodiment of the present disclosure. The driving circuit 500 shown in FIG. 9 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 9 , the driving circuit 500 includes a pixel circuit 140 and a detection and protection circuit 130 . For the implementation of the pixel circuit 140, reference can be made to the relevant description of the pixel circuit 140 shown in FIG. 4 and will not be described again here. What is different from the embodiment shown in FIG. 4 is that, according to actual requirements, the reset circuit 132 shown in FIG. 9 may include a transistor T5 and/or a resistor R2. In details, the first end of the transistor T5 can receive the reference voltage VREF, the second end of the transistor T5 can be electrically connected to one end of the resistor R2, and the other end of the resistor R2 can be electrically connected to the first node N1. The control terminal of crystal T5 can receive the reset signal DIS. In other embodiments, the reset unit 132 may not include the resistor R2 and use a smaller reference voltage VREF, which is not limited in this embodiment.

For detailed operation waveforms of the embodiment shown in Figure 9, please refer to Figure 5 Example. It should be noted that, in some embodiments, the reference voltage VREF shown in FIG. 9 may be smaller than the reset voltage VRST. In addition, in some embodiments, the voltage level (VREF′) reached by the first node N1 when TR is charged through the reset unit 132 during the reset period may be smaller than the voltage level required to drive the electronic unit 110 to avoid electrons. Unit 110 is driven early. In some embodiments, the first voltage ARVDD may be set to 15 volts, and the second voltage ARVSS may be set to 0 volts. Assuming that the voltage level required to drive the electronic unit 110 is 10 volts, the reset voltage VRST may be set to 9 volts. volts, the reference voltage VREF can be set to 4 volts, and the voltage level VREF' of the first node N1 TR during the reset period can be 8 volts (or any DC level between 7.5 and 10 volts), that is, the voltage The level VREF′ is smaller than the voltage level required to drive the electronic unit 110, or VREF<VREF′<VRST<ARVDD, but this embodiment does not set a limit. In this way, during the reset period TR, the first node N1 and the fourth node N4 in the detection control circuit 130 can be charged to different voltage levels according to actual application requirements, that is, the reference voltage VREF can be changed through the reset unit 132 It is supplied to the first node N1 to determine the voltage level of the first node N1 by using the reference voltage VREF or the voltage division of the reference voltage VREF and the resistor R2, thereby increasing the application scope of the detection and protection circuit 130. In addition, using the reference voltage VREF, which is smaller than the reset voltage VRST, to charge the first node N1 can improve the sensitivity of the first node N1, increase the potential difference between the first node N1 and the fourth node N4, and increase the first The cross voltage on capacitor C1 thereby improves the response speed and closing speed of transistor T8. Regarding the driving circuit 500 shown in FIG. 9 when the electronic unit 110 is operating normally or at least one of the plurality of light-emitting units is short-circuited or damaged. Next, the detailed operations and waveforms of the driving circuit 500 can be inferred from the relevant descriptions of the embodiments shown in FIG. 4 and FIG. 5 , and will not be described again here.

FIG. 10 is a schematic circuit diagram of a driving circuit 600 according to yet another embodiment of the present disclosure. The driving circuit 600 shown in FIG. 10 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 10 , the driving circuit 600 includes a pixel circuit 140 and a detection and protection circuit 130 . For the implementation of the pixel circuit 140, reference can be made to the relevant description of the pixel circuit 140 shown in FIG. 4 and will not be described again here. What is different from the embodiment shown in FIG. 4 is that, according to actual requirements, the reset circuit 132 shown in FIG. 10 may include a transistor T5 and/or one or more diodes D2 (for example, in this embodiment Two) connected in series. In detail, the first terminal of the transistor T5 can receive the reference voltage VREF, and the second terminal of the transistor T5 can be electrically connected to one terminal (such as the cathode terminal) of one or more diodes D2. One or more diodes D2 The other end of the pole body D2 (for example, the anode end) can be electrically connected to the first node N1, and the control end of the transistor T5 can receive the reset signal DIS. In some embodiments, one or more diodes D2 may be implemented using transistors, and this embodiment is not limited thereto. Regarding the driving circuit 600 shown in FIG. 10 , when the electronic unit 110 is operating normally or at least one of the plurality of light-emitting units is short-circuited or damaged, the detailed operations and waveforms of the driving circuit 600 can be shown in the above-mentioned FIG. 9 and FIG. 5 The relevant descriptions of the embodiments are analogous and will not be repeated here.

FIG. 11 is a schematic circuit diagram of a driving circuit 700 according to yet another embodiment of the present disclosure. The driving circuit 700 shown in FIG. 11 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 11 , the driving circuit 700 includes a pixel circuit 140 and a detection and protection circuit 130 . The implementation of the pixel circuit 140 may be referred to The relevant description of the pixel circuit 140 shown in FIG. 4 will not be repeated here. What is different from the embodiment shown in FIG. 4 is that, according to actual requirements, the reset circuit 131 shown in FIG. 11 may include a transistor T9 and/or a resistor R3. In details, the first end of the transistor T9 can receive the first voltage ARVDD, the second end of the transistor T9 can be electrically connected to one end of the resistor R3, and the other end of the resistor R3 can be electrically connected to the fourth node N4. The control terminal of transistor T9 can receive the reset signal DIS.

For detailed operation waveforms of the embodiment shown in Fig. 11, reference can be made to the embodiment shown in Fig. 5. It should be noted that in some embodiments, the voltage level ARVDD′ reached by the fourth node N4 shown in FIG. 11 during the reset period when TR is charged through the reset unit 131 may be greater than the reset voltage VRST, and due to the reset The unit 131 has a resistor R3, and the voltage level ARVDD' must be smaller than the first voltage ARVDD, that is, VRST<ARVDD'<ARVDD, but this embodiment does not set a limit. During the scanning period TS, if any one or more of the plurality of light-emitting units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 will be pulled down, and at the same time, the voltage level of the fourth node N4 will be driven down. Also pulled down. When the potential difference between the control terminal and the second terminal of the first transistor T1 is lower than the threshold voltage VTH of the first transistor T1, that is, ARVDD+(VST-ARVDD')<ARVDD-VTH, the first transistor T1 is turned on. The first voltage ARVDD is supplied to the second node N2 to turn off the transistor T8, thereby stopping power supply to the first node N1. In this way, during the reset period TR, the first node N1 and the fourth node N4 in the detection control circuit 130 can be charged to different voltage levels according to actual application requirements, that is, the first voltage can be changed through the reset unit 131 ARVDD is supplied to the fourth node N4 (the other end of the first capacitor C1) to adopt the first voltage The voltage division of ARVDD and resistor R3 determines the voltage level of the fourth node N4, thereby increasing the application scope of the detection and protection circuit 130. Regarding the driving circuit 700 shown in FIG. 11 , when the electronic unit 110 is operating normally or at least one of the plurality of light-emitting units is short-circuited or damaged, the detailed operations and waveforms of the driving circuit 700 can be shown in the above-mentioned FIG. 4 and FIG. 5 The relevant descriptions of the embodiments are analogous and will not be repeated here.

FIG. 12 is a circuit schematic diagram of a driving circuit 800 according to yet another embodiment of the present disclosure. The driving circuit 800 shown in FIG. 12 can be used as an implementation example of the driving circuit 100 shown in FIG. 1 . In the embodiment shown in FIG. 12 , the driving circuit 800 includes a pixel circuit 140 and a detection and protection circuit 130 . For the implementation of the pixel circuit 140, reference can be made to the relevant description of the pixel circuit 140 shown in FIG. 4 and will not be described again here. What is different from the embodiment shown in FIG. 4 is that, according to actual requirements, the reset circuit 131 shown in FIG. 12 may include a transistor T9 and/or one or more diodes D3 (for example, in this embodiment three) connected in series. In detail, the first terminal of the transistor T9 can receive the first voltage ARVDD, the second terminal of the transistor T9 can be electrically connected to one terminal (such as an anode terminal) of one or more diodes D3, and one or more The other end of the diode D3 (eg, the cathode end) can be electrically connected to the fourth node N4, and the control end of the transistor T9 can receive the reset signal DIS. In some embodiments, one or more diodes D3 may be implemented using transistors, and this embodiment is not limited thereto. Regarding the driving circuit 800 shown in FIG. 12 , when the electronic unit 110 is operating normally or at least one of the plurality of light-emitting units is short-circuited or damaged, the detailed operations and waveforms of the driving circuit 800 can be shown in the above-mentioned FIG. 11 and FIG. 5 The relevant descriptions of the embodiments are analogous and will not be repeated here.

In summary, in the driving device and its driving method according to the embodiments of the present disclosure, the detection and protection circuit 130 can be configured to be electrically connected to the electronic unit 110 and the driving unit 120 through the first node N1 and the second node N2 respectively. When the voltage of the first node N1 is pulled down, the detection protection circuit 130 may control the driving unit 120 to turn off. According to some embodiments, during the reset period TR, the detection protection circuit 130 may supply the reset voltage VRST to the first node N1, and during the scan period TS, the detection protection circuit 130 may detect the voltage of the first node N1. According to some embodiments, through the driving circuit of the present disclosure, when the electronic unit 110 is short-circuited or damaged, power supply to the electronic unit 110 can be stopped, thereby protecting the electronic unit 110 from being affected by excessive current.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. Scope. Furthermore, features of various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

100:Drive circuit

110: Electronic unit

120: Drive unit

130: Detection protection circuit

N1: first node

N2: second node

Claims (14)

An electronic device includes a drive circuit. The drive circuit includes: an electronic unit; a drive unit electrically connected to the electronic unit; and a detection protection circuit electrically connected to the electronic unit via a first node and via a second node. The node is electrically connected to the gate terminal of the driving unit, wherein when the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to turn off, wherein the detection protection circuit includes: a first transistor , is electrically connected to the second node, and the first transistor is used to supply a first voltage to the second node to turn off the driving unit. The electronic device of claim 1, wherein the detection and protection circuit further includes: a first capacitor, one end of the first capacitor has a third node, and the third node is connected to the gate terminal of the first transistor. Electrical connection. The electronic device according to claim 2, wherein the detection and protection circuit further includes: a second capacitor, one end of the second capacitor is electrically connected to the other end of the first capacitor, and the other end of the second capacitor One end receives the second voltage. The electronic device as claimed in claim 2, wherein the detection and protection circuit further includes: A second transistor is electrically connected to the third node, and the second transistor is used to supply the first voltage to the third node during the reset period. The electronic device according to claim 4, wherein the detection and protection circuit further includes: a third capacitor, one end of the third capacitor is electrically connected to the third node, and the other end of the third capacitor receives the the first voltage. The electronic device according to claim 2, wherein the detection protection circuit further includes: a third transistor electrically connected to the first node, the third transistor is used to conduct during the detection period or the scanning period. The first node and the other end of the first capacitor. The electronic device according to claim 6, wherein the detection and protection circuit further includes: a resistor electrically connected to the third transistor and the other end of the first capacitor. The electronic device according to claim 2, wherein the detection and protection circuit further includes: a reset unit electrically connected to the other end of the first capacitor, the reset unit is used to reset the A voltage or the first voltage is supplied to the other end of the first capacitor. The electronic device as claimed in claim 2, wherein the detection and protection circuit further includes: A reset unit is electrically connected to the first node, and is used to supply a reset voltage or a reference voltage to the first node during the reset period. The electronic device according to claim 2, wherein the detection and protection circuit further includes: a diode, one end of the diode is electrically connected to the third node. The electronic device according to claim 10, wherein the detection protection circuit further includes: a third transistor electrically connected to the first node, the third transistor is used to conduct the first node during scanning. node to the other end of the diode. The electronic device of claim 1, wherein the driving unit is electrically connected to the switching unit via the second node, and the driving unit is electrically connected to the first node via the control unit, wherein the switching unit used to supply data voltage to the second node during scanning; and the control unit is used to shut down to stop power supply to the first node during data writing. The electronic device according to claim 1, wherein the electronic unit includes a light emitting unit. A driving method for a driving circuit, characterized in that the driving circuit includes an electronic unit, a driving unit and a detection and protection circuit, wherein the driving unit is electrically connected to the electronic unit, and the detection and protection circuit is connected to the first node via a first node. The electronic unit is electrically connected and electrically connected to the gate terminal of the driving unit via a second node, and the driving method includes: supplying a reset voltage to the third through the detection protection circuit during the reset period. A node; detecting the voltage of the first node during scanning through the detection protection circuit; and when the voltage of the first node is pulled down, turning off the driving unit through the detection protection circuit.

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