CN115588390A

CN115588390A - Electronic device including driving circuit and driving method thereof

Info

Publication number: CN115588390A
Application number: CN202210237941.1A
Authority: CN
Inventors: 曾名骏; 罗闵馨; 廖宏昇; 高启伦
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2021-06-23
Filing date: 2022-03-10
Publication date: 2023-01-10
Also published as: TWI829106B; TW202301904A

Abstract

The present disclosure provides an electronic device including a driving circuit and a driving method thereof. The drive circuit comprises an electronic unit, a drive unit and a detection protection circuit. The driving unit is electrically connected with the electronic unit. The detection protection circuit is electrically connected with the electronic unit through a first node and is electrically connected with the grid end of the driving unit through a second node. When the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to be closed. The detection protection circuit of the driving circuit can protect the electronic unit from being influenced by excessive current.

Description

Electronic device including driving circuit and driving method thereof

Technical Field

The present disclosure relates to electronic devices, and more particularly to a driving circuit including a detection protection circuit and a driving method thereof.

Background

A driving circuit, such as an Active-matrix organic light emitting diode (AMLED) driving circuit, generally used for driving a display panel or a backlight panel does not have a function of detecting a current. When an electronic unit such as a light emitting unit or other electronic components is short-circuited or damaged, a current passing through the electronic unit may be abruptly increased, thereby increasing power consumption and overheating the electronic unit. In view of this, in order to quickly cut off the power supply to protect the electronic unit from excessive current, several embodiments of solutions will be proposed below.

Disclosure of Invention

The present disclosure provides an electronic device including a driving circuit and a driving method thereof, which can detect a voltage passing through an electronic unit and protect the electronic unit from an excessive current.

According to an embodiment of the present disclosure, an electronic device includes a driving circuit, which includes an electronic unit, a driving unit, and a detection protection circuit. The driving unit is electrically connected with the electronic unit. The detection protection circuit is electrically connected with the electronic unit through a first node and is electrically connected with the grid terminal of the driving unit through a second node. When the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to be turned off.

According to an embodiment of the present disclosure, a driving method of a driving circuit of the present disclosure includes: supplying a reset voltage to the first node during a reset by the detection protection circuit; detecting, by the detection protection circuit, a voltage of the first node during a scan; and when the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to be closed.

Based on the above, the driving circuit of the present disclosure can be electrically connected to the electronic unit through the first node and the gate terminal of the driving unit through the detection protection circuit respectively. When the detection protection circuit judges that the voltage of the first node is pulled down, the driving unit can be controlled to be closed. Therefore, the power supply to the electronic unit can be stopped in real time so as to protect the electronic unit from being influenced by overlarge current.

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity, the various figures of the present disclosure depict only a portion of a display device and are not necessarily drawn to scale. In addition, the number and size of the components in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

Drawings

FIG. 1 is a block diagram of a driving circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating an implementation scenario of a driving circuit according to an embodiment of the disclosure;

FIG. 3 is a flow chart illustrating a driving method according to an embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating operation waveforms of a driving circuit according to an embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating operation waveforms of a driving circuit according to another embodiment of the present disclosure;

FIG. 8 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure;

FIG. 9 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure;

FIG. 10 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure;

FIG. 11 is a circuit diagram of a driving circuit according to another embodiment of the present disclosure;

fig. 12 is a circuit diagram of a driving circuit according to another embodiment of the disclosure.

Description of the reference numerals

100. 200, 300, 400, 500, 600, 700, 800, P1, P2, pn: a drive circuit;

110: an electronic unit;

120: a drive unit;

130: detecting a protection circuit;

131. 132: a reset circuit;

140: a pixel circuit;

c1, C2, C3, C4, C5: a capacitor;

d1, D2: a diode;

DT: a data voltage;

DIS, DIS _ b: a reset signal;

EM: enabling a signal;

n1, N2, N3, N4: a node;

r1, R2, R3: a resistance;

s310, S320, S330: a step of;

SCN: scanning a signal;

t1, T2, T3, T4, T5, T6, T7, T8, T9: a transistor;

TD: a detection period;

TDI: a data write period;

TE: a lighting period;

TR: a reset period;

TS: during the scanning period;

ARVDD, ARVSS: a voltage;

VRST: a reset voltage;

VREF: a reference voltage.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that display device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "includes" and "includes" are open-ended words, and thus should be interpreted to mean "including, but not limited to …".

In some embodiments of the present disclosure, terms concerning bonding, connecting, and the like, such as "coupled," "interconnected," and the like, may refer to two structures being in direct contact or may not be in direct contact, unless otherwise specified, wherein other structures are interposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the term "coupled" includes any direct and indirect electrical connection.

The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify a component does not by itself connote any preceding ordinal number of the component, nor the order in which a component is sequenced from one component to another or in a method of manufacture, and the use of a plurality of ordinal numbers is used merely to distinguish one named component from another component with a clear distinction. The claims may not use the same words in the specification and accordingly, a first element in a specification may be a second element in a claim. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

Fig. 1 is a block diagram of a driving circuit 100 according to an embodiment of the disclosure. In the embodiment shown in fig. 1, the driving circuit 100 includes an electronic unit 110, a driving unit 120, and a detection protection circuit 130. According to design requirements, in some embodiments, the electronic unit 110 may include one or more light emitting units or other electronic components, and the number and arrangement thereof may be determined according to actual requirements. Depending on practical applications, the one or more Light Emitting units may include a Light Emitting Diode (LED), a Micro-LED, an Organic Light Emitting Diode (OLED), an Inorganic Light Emitting Diode (ILED), a sub-millimeter Light Emitting Diode (Mini-LED), a Micro-LED, an Electroluminescence (EL) device, a Laser Diode (Laser Diode), or other types of Light Emitting devices, which are not limited in this embodiment.

In the present embodiment, the driving unit 120 is electrically connected to the electronic unit 110, and the driving unit 120 can turn on or off a voltage or current signal for driving the electronic unit 110. The detection protection circuit 130 is electrically connected to the electronic unit 110 via a node N1 (a first node), and is electrically connected to the gate terminal (a control terminal) of the driving unit 120 via a node N2 (a second node). The detection protection circuit 130 can detect whether a voltage change (e.g., a voltage pull-down) occurs at the first node N1, so as to determine whether the electronic unit 110 has a short circuit or is damaged. When the voltage of the first node N1 is pulled down, the detection protection circuit 130 may control the driving unit 120 to turn off, for example, the driving unit 120 is controlled to turn off by the second node N2, so as to stop supplying power to the electronic unit 110, and thus the electronic unit 110 may be protected from the influence of the excessive current.

FIG. 2 is a schematic diagram illustrating an implementation scenario of an electronic device 100D according to an embodiment of the disclosure. In the embodiment shown in FIG. 2, one or more driving circuits P1, P2, …, pn may be configured in any electronic device 100D. In some embodiments, the electronic device 100D may include a plurality of driving circuits P1 Pn. The plurality of driving circuits P1 to Pn may be disposed on a substrate to form a substrate module 100S. The plurality of driving circuits P1 Pn may be arranged in a matrix, but the invention is not limited thereto. At least one of the driving circuits P1 to Pn may be the driving circuit 100, i.e., may include the electronic unit 110, the driving unit 120, and the detection protection circuit 130. According to some embodiments, each of the plurality of driving circuits P1 Pn may be the driving circuit 100 described above. According to some embodiments, the electronic unit 110 may be a light emitting unit, and constitute the electronic device 100D with a display function. For example, the substrate module 100S itself may constitute a display panel for displaying images. Alternatively, according to some embodiments, the electronic unit 110 may be a light-emitting unit, and the substrate module 100S itself may be a backlight module. The substrate module 100S as a backlight module can be combined with a liquid crystal display panel to form an electronic device 100D with a display function. For example, when the driving circuits P1 to Pn are used as a display panel for displaying images, one driving circuit may include only a single light emitting unit. When the driving circuits P1 to Pn are used as backlight modules, one driving circuit may include a plurality of light emitting units connected in series, but the embodiment is not limited thereto. According to some embodiments, the electronic unit 110 may be a non-light emitting unit. According to some embodiments, the electronic device 100D may be an antenna device, a liquid crystal display device, or a varactor device (varactor device).

Fig. 3 is a flowchart illustrating a driving method of a driving circuit according to an embodiment of the disclosure. The driving circuit 100 shown in fig. 1 can refer to the related description of fig. 3. Please refer to fig. 1 and fig. 3. In step S310, the driving circuit 100 may supply a reset voltage (or a reference voltage) to the first node N1 during the reset through the detection protection circuit 130. In step S320, the detection protection circuit 130 may detect the voltage of the first node N1 during the scan. In step S330, when the detection protection circuit 130 detects that the voltage of the first node N1 is pulled down, the detection protection circuit 130 may turn off the driving unit 120 via the second node N2.

Please refer to fig. 4 and 5. Fig. 4 is a circuit diagram of a driving circuit 200 according to an embodiment of the disclosure. Fig. 5 is a schematic diagram illustrating operation waveforms of a driving circuit according to an embodiment of the disclosure. The driving circuit 200 shown in fig. 4 can be used as an exemplary embodiment of the driving circuit 100 shown in fig. 1. The embodiment shown in fig. 5 can be used as an operation waveform diagram of the driving circuit 200 shown in fig. 4, the driving circuit 400 shown in fig. 8, the driving circuit 500 shown in fig. 9, the driving circuit 600 shown in fig. 10, the driving circuit 700 shown in fig. 11, and/or the driving circuit 800 shown in fig. 12. In the embodiment shown in fig. 4, the driving circuit 200 includes the pixel circuit 140 and the detection protection circuit 130. The pixel circuit 140 may include an electronic unit 110 and a driving unit 120. According to practical requirements, in some embodiments, the pixel circuit 140 may further include a switch unit T6, a control unit T7, a capacitor C3, and/or other components not shown in fig. 4, which is not limited in this embodiment. In the present embodiment, the electronic unit 110 may include a plurality of electronic units (for example, four electronic units in the present embodiment) connected in series, but the number and the arrangement thereof are merely exemplary, and the present embodiment is not limited thereto. According to some embodiments, the electronic unit 110 may include a plurality of light emitting units.

In the present embodiment, the driving unit 120 may include a transistor T8. For convenience of description, the switch unit T6, the control unit T7 and the transistor T8 are all P-type transistors, but the present embodiment is not limited thereto. In the present embodiment, the first terminal of the switching unit T6 may receive the data voltage DT. The control terminal of the switching unit T6 may receive the scan signal SCN. A first terminal of the transistor T8 may receive a voltage ARVDD (first voltage). The driving unit 120 (e.g., the control terminal of the transistor T8) may be electrically connected to the second terminal of the switch unit T6 through the second node N2. One end of the capacitor C3 may receive the first voltage ARVDD, and the other end of the capacitor C3 may be electrically connected to the second node N2. In the present embodiment, the driving unit 120 (e.g., the second terminal of the transistor T8) may be electrically connected to the first node N1 through the first terminal of the control unit T7. The control terminal of the control unit T7 may receive the enable signal EM. One end of the electronic unit 110 (e.g., the anode end of the plurality of light emitting units) may be electrically connected to the second end of the control unit T7 through the first node N1. The other terminal of the electronic unit 110 (e.g., a cathode terminal of the plurality of light emitting cells) may receive a voltage ARVSS (second voltage). In the present embodiment, the voltage level of the first voltage ARVDD may be higher than the voltage level of the second voltage ARVSS. For example, in some embodiments, the first voltage ARVDD may be a dc high level and the second voltage ARVSS may be a dc low level or a ground level. In some embodiments, the switch unit T6, the control unit T7 and/or the transistor T8 may also be transistors with N-type conductivity. In some embodiments, the voltage level of the first voltage ARVDD may also be lower than the voltage level of the second voltage ARVSS. For example, when the conductivity type of the transistor T8 is N-type, the first voltage ARVDD may be a dc low level or a ground level, and the second voltage ARVSS may be a dc high level.

In this way, for the pixel circuit 140, the switch unit T6 can transmit the data voltage DT to the second node N2 according to the scan signal SCN. That is, the switching unit T6 may be used to supply the data voltage DT to the second node N2 during the scan period TS. The capacitor C3 can stabilize the voltage level at the second node N2 according to the first voltage ARVDD. The transistor T8 in the driving unit 120 may transmit the first voltage ARVDD to the second terminal of the transistor T8 according to the voltage level on the second node N2. The control unit T7 may transmit the voltage level at the second terminal of the transistor T8 to the electronic unit 110 through the first node N1 according to the enable signal EM, so that the electronic unit 110 may be driven according to a potential difference between the first node N1 and the second voltage ARVSS. That is, the control unit T7 is configured to turn off the TDI during the data writing period to stop supplying power to the first node N1. In some embodiments, the electronic unit 110 may be a light emitting unit, and thus the electronic unit 110 may emit light according to a potential difference between the first node N1 and the second voltage ARVSS.

According to practical design requirements, in some embodiments, the detection protection circuit 130 may include a transistor T1 (a first transistor), a transistor T2 (a second transistor), a transistor T4 (a third transistor), a capacitor C1 (a first capacitor), a capacitor C2 (a second capacitor), a reset unit 131, a reset unit 132, and/or other components not shown in fig. 4, which is not limited in this embodiment. The first transistor T1 may be electrically connected to the second node N2 for supplying the first voltage ARVDD to the second node N2 to turn off the driving unit 120. The reset unit 131 may be electrically connected to the other end of the first capacitor C1 through the fourth node N4, and the reset unit 132 may be electrically connected to the first node N1. In this embodiment, the reset unit 131 may include a transistor T3, and the reset unit 132 may include a transistor T5, but the embodiment is not limited thereto. For convenience of description, the transistors T1 to T5 are all Thin Film Transistors (TFTs) with P-type conductivity, but the present embodiment is not limited thereto. In some embodiments, at least one of the transistors T1 to T5 may also be a transistor with N-type conductivity. In this embodiment, the first terminal of the first transistor T1 may receive the first voltage ARVDD. The second terminal of the first transistor T1 may be electrically connected to the control terminal of the transistor T8 in the driving unit 120 through a second node N2. In the present embodiment, one end of the first capacitor C1 has a node N3 (a third node), and the first capacitor C1 can be electrically connected to the gate terminal (a control terminal) of the first transistor T1 through the third node N3. In this embodiment, one end of the second capacitor C2 may be electrically connected to the other end of the first capacitor C1 through the fourth node N4. In some embodiments, the other terminal of the second capacitor C2 may receive the second voltage ARVSS. In other embodiments, the other end of the second capacitor C2 may also receive the first voltage ARVDD or other dc levels, which is not limited in this embodiment.

In some embodiments, the first terminal of the second transistor T2 may receive the first voltage ARVDD. The second terminal of the second transistor T2 may be electrically connected to the third node N3. The control terminal of the second transistor T2 may receive the reset signal DIS. In some embodiments, the first terminal of the transistor T3 in the reset unit 131 may receive the reset voltage VRST. The second terminal of the transistor T3 may be electrically connected to the fourth node N4. The control terminal of the transistor T3 may receive the reset signal DIS. In some embodiments, the first terminal of the third transistor T4 may be electrically connected to the fourth node N4. A control terminal of the third transistor T4 may receive the scan signal SCN. In some embodiments, the first terminal of the transistor T5 in the reset unit 132 may receive the reset voltage VRST. The second terminal of the transistor T5 and the second terminal of the third transistor T4 may be electrically connected to the first node N1. The control terminal of the transistor T5 may receive the reset signal DIS. The reset voltage VRST may be a direct current level between the first voltage ARVDD and the second voltage ARVSS. In some embodiments, the reset voltage VRST may be less than a voltage level required to drive the electronic unit 110 to avoid that the electronic unit 110 may be driven by the reset voltage VRST. For example, in some embodiments, the first voltage ARVDD may be set to 15 volts (volt), the second voltage ARVSS may be set to 0 volt, and the reset voltage VRST may be set to 9 volts assuming that the voltage level required for driving the electronic unit 110 is 10 volts (2.5 × 4), but the embodiment is not limited thereto.

As such, for the detection protection circuit 130, the second transistor T2 can transmit the first voltage ARVDD to the third node N3 according to the reset signal DIS. The transistor T3 in the reset unit 131 may transmit the reset voltage VRST to the fourth node N4 according to the reset signal DIS. The transistor T5 in the reset unit 132 may transmit the reset voltage VRST to the first node N1 according to the reset signal DIS. The second capacitor C2 can be used as a voltage stabilizing capacitor to stabilize the voltage level at the fourth node N4 according to the second voltage ARVSS (or the first voltage ARVDD or other dc level). The third transistor T4 may turn on the fourth node N4 and the first node N1 according to the scan voltage SCN. And the first transistor T1 may supply the first voltage ARVDD to the second node N2 according to a voltage level of the third node N3. If at least one of the electronic units 110 is short-circuited or damaged, the voltage level of the first node N1 is pulled down instantaneously, and the voltage level of the fourth node N4 is also pulled down. The voltage level of the third node N3 is also pulled down at this time based on the first capacitor C1 coupling (coupled). For example, if the voltage level of the first node N1 is pulled down to the short-circuit voltage VST by the reset voltage VRST (VST < VRST), the voltage level of the third node N3 is ARVDD + (VST-VRST). The first transistor T1 is turned on when a potential difference between the control terminal and the second terminal of the first transistor T1 is lower than a Threshold voltage VTH (Threshold voltage) of the first transistor T1, i.e., ARVDD + (VST-VRST) < ARVDD-VTH. The first transistor T1 supplies the first voltage ARVDD to the second node N2 to turn off (close) the transistor T8 in the driving unit 120, so that the transistor T8 stops supplying power to the first node N1, thereby protecting the electronic unit 110 from the excessive current.

The waveform diagram for the above-described operation can be referred to the embodiment shown in fig. 5. The horizontal axis shown in fig. 5 represents time. In the embodiment shown in fig. 5, when the electronic unit 110 shown in fig. 4 is to be driven, the enable signal EM may be switched from a logic low level to a logic high level first, so that the driving circuit 200 enters the data writing period TDI. At this time, the control unit T7 in the pixel circuit 140 is turned off, i.e., switched from the on state to the off state, to stop supplying power to the first node N1. In the data writing period TDI, when the reset signal DIS is switched from a logic high level to a logic low level, the driving circuit 200 enters the reset period TR. At this time, the second transistor T2 in the detection protection circuit 130 may supply the first voltage ARVDD to the third node N3 (i.e., one end of the first capacitor C1), the transistor T3 in the reset unit 131 may transfer the reset voltage VRST to the fourth node N4 (i.e., the other end of the first capacitor C1), and the transistor T5 in the reset unit 132 may supply the reset voltage VRST to the first node N1. The first node N1 and the fourth node N4 are charged (charging) to the reset voltage VRST, the third node N3 is charged to the first voltage ARVDD (assumed to be a logic high level), and the first transistor T1 is turned off.

Assuming that the electronic unit 110 is normally operated (e.g., all the light emitting units can emit light normally), the voltage level of the first node N1 is maintained unchanged (the reset voltage VRST). Then, when the scan signal SCN is switched from a logic high level to a logic low level, the driving circuit 200 enters a scan period TS (which is equivalent to the detection period TD). The switching unit T6 in the pixel circuit 140 may transmit the data voltage DT to the second node N2, and the third transistor T4 may turn on the first node N1 and the fourth node N4 (i.e., the other end of the first capacitor C1). That is, according to some embodiments, the third transistor T4 is electrically connected to the first node N1, and the third transistor T4 is used for turning on the first node N1 and the other end of the first capacitor C1 during the detection period TD or the scanning period TS. Since the voltage levels of the first node N1 and the fourth node N4 are the same, the first capacitor C1 is in a floating state, and thus the voltage level of the third node N3 is also maintained unchanged (the first voltage ARVDD), so that the first transistor T1 is still maintained in a cut-off state. Finally, when the data voltage DT is completely written and the enable signal EM is switched from the logic high level to the logic low level, the driving circuit 200 enters the lighting period TE. At this time, the control unit T7 is switched from the off state to the on state, and the transistor T8 in the driving unit 120 transmits the first voltage ARVDD to the first node N1 through the control unit T7 according to the data voltage DT to drive the electronic unit 110. Therefore, in the case that the electronic unit 110 does not generate the voltage abnormality, the detection protection circuit 130 does not affect the normal operation of the pixel circuit 140.

If at least one of the light emitting units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 is pulled down instantaneously. Then, when the scan signal SCN is switched from a logic high level to a logic low level, the driving circuit 200 enters a scan period TS. The switching unit T6 transmits the data voltage DT to the second node N2, and the third transistor T4 turns on the first node N1 and the fourth node N4. Since the voltage level of the first node N1 is pulled down, the voltage levels of the fourth node N4 and the third node N3 are also pulled down in sequence. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 is charged (charging) to the first voltage ARVDD through the first transistor T1, so that the transistor T8 enters the off state. Finally, when the enable signal EM is switched from the logic high level to the logic low level, the driving circuit 200 enters the lighting period TE. At this time, although the control unit T7 is switched from the off state to the on state, since the transistor T8 is still in the off state, no current flows through the electronic unit 110, so as to protect the electronic unit 110 from the influence of an excessive current.

Please refer to fig. 6 and 7. Fig. 6 is a circuit diagram of a driving circuit 300 according to another embodiment of the present disclosure. Fig. 7 is a schematic diagram of operation waveforms of a driving circuit according to another embodiment of the present disclosure. The driving circuit 300 shown in fig. 6 can be used as an example of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 6, the driving circuit 300 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the control terminal of the third transistor T4 shown in fig. 6 may also receive a reset signal DIS _ b different from the scan signal SCN. According to practical requirements, in some embodiments, the detection protection circuit 130 shown in fig. 6 may further include a capacitor C4 (a third capacitor) and (or) a resistor R1. One end of the third capacitor C4 may be electrically connected to the third node N3, and the other end of the third capacitor C4 may receive the first voltage ARVDD. The third capacitor C4 may stabilize the current on the third node N3. One end of the resistor R1 may be electrically connected to the first end of the third transistor T4, and the other end of the resistor R1 may be electrically connected to the other end of the first capacitor C1 through the fourth node N4. For the resistor R1, the resistance cross voltage is the potential difference between the first node N1 and the fourth node N4.

Waveform diagrams relating to the operation of the embodiment shown in fig. 6 can be referred to the embodiment shown in fig. 7. The horizontal axis shown in fig. 7 represents time. In the embodiment shown in fig. 7, the implementation of the enable signal EM, the reset signal DIS and the scan signal SCN can be described with reference to the related descriptions of the enable signal EM, the reset signal DIS and the scan signal SCN shown in fig. 5. Unlike the embodiment shown in fig. 5, the operation waveform diagram shown in fig. 7 further includes a reset signal DIS _ b. In detail, when the enable signal EM is switched from a logic low level to a logic high level, the driving circuit 300 shown in fig. 6 enters the data writing period TDI. At this time, the control unit T7 is switched from the on state to the off state to stop supplying power to the electronic unit 110. In the data writing period TDI, when both the reset signal DIS and the reset signal DIS _ b are switched from the logic high level to the logic low level, the driving circuit 300 enters the reset period TR. At this time, the third node N3 is charged to the first voltage ARVDD through the second transistor T2, the first transistor T1 is turned off, and the third capacitor C4 can stabilize the voltage level of the third node N3 according to the first voltage ARVDD. The fourth node N4 is charged to the reset voltage VRST through the transistor T3, and the first node N1 is charged to the reset voltage VRST through the transistor T5.

Then, when the reset signal DIS is switched from a logic low level to a logic high level and the reset signal DIS _ b is maintained at a logic low level, the driving circuit 300 enters a detection period TD (different from the scanning period TS, which is the same as the detection period TD in fig. 5), at which the second transistor T2, the transistor T3, and the transistor T5 are switched from an on state to an off state, and the third transistor T4 is maintained at an on state. If at least one of the light emitting units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 and the voltage level of one end of the resistor R1 (electrically connected to the third transistor T4) are pulled down instantaneously, so that the voltage levels of the fourth node N4 and the third node N3 are also pulled down sequentially. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 is charged to the first voltage ARVDD through the first transistor T1 to turn off the transistor T8, thereby stopping supplying power to the electronic unit 110 to protect the electronic unit 110 from excessive current. This embodiment is a case of the driving circuit 300 in fig. 6, which illustrates that the detection protection circuit 130 controls the driving unit 120 to turn off when the voltage of the first node N1 is pulled down. However, according to some embodiments, similar to the driving circuit 300 of fig. 6, the driving circuit 200 of fig. 5 can also implement the situation that the detection protection circuit 130 controls the driving unit 120 to turn off when the voltage of the first node N1 is pulled down, and details thereof are not repeated.

Fig. 8 is a circuit diagram of a driving circuit 400 according to another embodiment of the disclosure. The driving circuit 400 shown in fig. 8 can be used as an exemplary embodiment of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 8, the driving circuit 400 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the detection protection circuit 130 shown in fig. 8 may use one or more diodes D1 (e.g., three diodes in the embodiment) connected in series and/or a capacitor C5 to replace the first capacitor C1 and/or the second capacitor C2 in the embodiment shown in fig. 4 according to practical requirements. In detail, one end (e.g., an anode end) of the one or more diodes D1 may be electrically connected to the third node N3, and the other end (e.g., a cathode end) of the one or more diodes D1 may be electrically connected to the first end of the third transistor T4 through the fourth node N4. One end of the capacitor C5 may be electrically connected to the third node N3, and the other end of the capacitor C5 may receive the second voltage ARVSS or other voltage levels. The capacitor C5 may be used as a voltage stabilizing capacitor to stabilize the voltage level at the third node N3 according to the second voltage ARVSS or other voltage levels. In some embodiments, one or more diodes D1 may be implemented by using a transistor, and the present embodiment is not limited thereto.

Detailed action waveforms with respect to the embodiment shown in fig. 8 can be referred to the embodiment shown in fig. 5. It should be noted that during the reset period TR, the third node N3 shown in fig. 8 is charged to the first voltage ARVDD through the second transistor T2, and the fourth node N4 is charged to the reset voltage VRST through the transistor T3. In some embodiments, the potential difference ARVDD-VRST between the third node N3 and the fourth node N4 may be less than a voltage level for turning on the one or more diodes D1 at this time to prevent the one or more diodes D1 from being driven during the reset period TR. And during the scan period TS, the third transistor T4 may turn on (e.g., via the fourth node N4) the first node N1 and the other end of the one or more diodes D1. Then, if at least one of the light emitting units in the electronic unit 110 is short-circuited or damaged, the voltage levels of the first node N1 and the fourth node N4 are pulled down to the short-circuit voltage VST from the reset voltage VRST instantaneously, and if the voltage level of the third node N3 is Vc ', the voltage across the one or more diodes D1, i.e., the potential difference Vc' -VST between the third node N3 and the fourth node N4, may be greater than or equal to the voltage level for turning on the one or more diodes D1. In this way, since one or more diodes D1 are turned on, the voltage level of the third node N3 is also pulled down. When the voltage level of the third node N3 is low enough to turn on the first transistor T1, the second node N2 is charged to the first voltage ARVDD to turn off the transistor T8, thereby stopping power supply to the first node N1. For the rest of the driving circuit 400 shown in fig. 8, when the electronic unit 110 is in normal operation or at least one of the light emitting units is short-circuited or damaged, the detailed operation and waveform of the driving circuit 400 can be analogized from the description of the embodiment shown in fig. 4 and 5, and will not be described again.

Fig. 9 is a circuit diagram of a driving circuit 500 according to another embodiment of the disclosure. The driving circuit 500 shown in fig. 9 can be used as an example of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 9, the driving circuit 500 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the reset circuit 132 shown in fig. 9 may include a transistor T5 and/or a resistor R2 according to practical requirements. In detail, a first terminal of the transistor T5 may receive the reference voltage VREF, a second terminal of the transistor T5 may be electrically connected to one terminal of the resistor R2, another terminal of the resistor R2 may be electrically connected to the first node N1, and a control terminal of the transistor T5 may receive the reset signal DIS. In other embodiments, the reset unit 132 may not include the resistor R2 and use a smaller reference voltage VREF, which is not limited in this embodiment.

Detailed action waveforms with respect to the embodiment shown in fig. 9 can be referred to the embodiment shown in fig. 5. It should be noted that, in some embodiments, the reference voltage VREF shown in fig. 9 may be smaller than the reset voltage VRST. In addition, in some embodiments, the voltage level (VREF') to which the first node N1 is charged by the reset unit 132 during the reset period TR may be less than a voltage level required to drive the electronic unit 110 to prevent the electronic unit 110 from being driven in advance. In some embodiments, the first voltage ARVDD may be set to 15 volts, the second voltage ARVSS may be set to 0 volts, assuming that the voltage level required for driving the electronic unit 110 is 10 volts, the reset voltage VRST may be set to 9 volts, the reference voltage VREF may be set to 4 volts, and the voltage level VREF ' of the first node N1 during the reset period TR may be 8 volts (or any dc level between 7.5 and 10 volts), even if the voltage level VREF ' is less than the voltage level required for driving the electronic unit 110, or VREF < VREF ' < VRST < ARVDD, but the embodiment is not limited thereto. In this way, during the reset period TR, the first node N1 and the fourth node N4 in the detection control circuit 130 can be charged to different voltage levels according to actual application requirements, i.e., the reset unit 132 can supply the reference voltage VREF to the first node N1, so as to determine the voltage level of the first node N1 by using the reference voltage VREF or the divided voltage of the reference voltage VREF and the resistor R2, thereby increasing the application scope of the detection protection circuit 130. In addition, the first node N1 is charged by using the reference voltage VREF smaller than the reset voltage VRST, so that the sensitivity of the first node N1 can be improved, the potential difference between the first node N1 and the fourth node N4 can be increased, the voltage across the first capacitor C1 can be increased, and the response speed and the turn-off speed of the transistor T8 can be improved. Regarding the driving circuit 500 shown in fig. 9, when the electronic unit 110 is in normal operation or at least one of the light emitting units is short-circuited or damaged, the detailed operation and waveform of the driving circuit 500 can be analogized from the related descriptions of the embodiments shown in fig. 4 and fig. 5, and will not be described herein again.

Fig. 10 is a circuit diagram of a driving circuit 600 according to another embodiment of the disclosure. The driving circuit 600 shown in fig. 10 can be used as an example of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 10, the driving circuit 600 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the reset circuit 132 shown in fig. 10 may include a transistor T5 and (or) one or more diodes D2 (e.g., two diodes in the embodiment) connected in series according to practical requirements. In detail, a first terminal of the transistor T5 may receive the reference voltage VREF, a second terminal of the transistor T5 may be electrically connected to one terminal (e.g., a cathode terminal) of the one or more diodes D2, another terminal (e.g., an anode terminal) of the one or more diodes D2 may be electrically connected to the first node N1, and a control terminal of the transistor T5 may receive the reset signal DIS. In some embodiments, one or more diodes D2 may be implemented by using a transistor, and the present embodiment is not limited thereto. Regarding the driving circuit 600 shown in fig. 10, when the electronic unit 110 is in normal operation or at least one of the light emitting units is short-circuited or damaged, the detailed operation and waveform of the driving circuit 600 can be analogized from the description of the embodiment shown in fig. 9 and 5, and will not be described herein again.

Fig. 11 is a circuit diagram of a driving circuit 700 according to another embodiment of the present disclosure. The driving circuit 700 shown in fig. 11 can be used as an exemplary embodiment of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 11, the driving circuit 700 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the reset circuit 131 shown in fig. 11 may include a transistor T9 and/or a resistor R3 according to practical requirements. In detail, a first terminal of the transistor T9 may receive the first voltage ARVDD, a second terminal of the transistor T9 may be electrically connected to one terminal of the resistor R3, another terminal of the resistor R3 may be electrically connected to the fourth node N4, and a control terminal of the transistor T9 may receive the reset signal DIS.

Detailed operational waveforms with respect to the embodiment shown in fig. 11 can be referred to the embodiment shown in fig. 5. It should be noted that, in some embodiments, the voltage level ARVDD ' reached by the fourth node N4 charged by the reset unit 131 during the reset period TR shown in fig. 11 may be greater than the reset voltage VRST, and since the reset circuit 131 has the resistor R3, the voltage level ARVDD ' is necessarily less than the first voltage ARVDD, i.e., VRST < ARVDD ' < ARVDD, but the present embodiment is not limited thereto. In the scanning period TS, if any one or more of the light emitting units in the electronic unit 110 is short-circuited or damaged, the voltage level of the first node N1 is pulled down, and the voltage level of the fourth node N4 is also pulled down. When the potential difference between the control terminal and the second terminal of the first transistor T1 is lower than the threshold voltage VTH of the first transistor T1, i.e., ARVDD + (VST-ARVDD') < ARVDD-VTH, the first transistor T1 is turned on to supply the first voltage ARVDD to the second node N2 to turn off the transistor T8, thereby stopping the supply of power to the first node N1. In this way, during the reset period TR, the first node N1 and the fourth node N4 in the detection control circuit 130 can be charged to different voltage levels according to actual application requirements, that is, the reset unit 131 can supply the first voltage ARVDD to the fourth node N4 (the other end of the first capacitor C1) to determine the voltage level of the fourth node N4 by using the first voltage ARVDD and the voltage division of the resistor R3, thereby increasing the application range of the detection protection circuit 130. In the case that the electronic unit 110 of the driving circuit 700 shown in fig. 11 is in normal operation or at least one of the light emitting units is short-circuited or damaged, the detailed operation and waveform of the driving circuit 700 can be analogized from the description of the embodiment shown in fig. 4 and 5, and will not be described herein again.

Fig. 12 is a circuit diagram of a driving circuit 800 according to another embodiment of the disclosure. The driving circuit 800 shown in fig. 12 can be used as an example of the driving circuit 100 shown in fig. 1. In the embodiment shown in fig. 12, the driving circuit 800 includes the pixel circuit 140 and the detection protection circuit 130. The implementation of the pixel circuit 140 can refer to the related description of the pixel circuit 140 shown in fig. 4, and is not repeated herein. Unlike the embodiment shown in fig. 4, the reset circuit 131 shown in fig. 12 may include a transistor T9 and (or) one or more diodes D3 (e.g., three diodes in the embodiment) connected in series according to practical requirements. In detail, a first terminal of the transistor T9 may receive the first voltage ARVDD, a second terminal of the transistor T9 may be electrically connected to one terminal (e.g., an anode terminal) of the one or more diodes D3, another terminal (e.g., a cathode terminal) of the one or more diodes D3 may be electrically connected to the fourth node N4, and a control terminal of the transistor T9 may receive the reset signal DIS. In some embodiments, one or more diodes D2 may be implemented by using a transistor, which is not limited in this embodiment. Regarding the driving circuit 800 shown in fig. 12, when the electronic unit 110 is in normal operation or at least one of the light emitting units is short-circuited or damaged, the detailed operation and waveform of the driving circuit 800 can be analogized from the description of the embodiment shown in fig. 11 and fig. 5, and will not be described herein again.

In summary, the driving apparatus and the driving method thereof according to the embodiments of the disclosure may be configured with the detection protection circuit 130 electrically connected to the electronic unit 110 and the driving unit 120 through the first node N1 and the second node N2, respectively. When the voltage of the first node N1 is pulled down, the detection protection circuit 130 may control the driving unit 120 to turn off. According to some embodiments, the detection protection circuit 130 may supply the reset voltage VRST to the first node N1 during the reset period TR, and the detection protection circuit 130 may detect the voltage of the first node N1 during the scan period TS. According to some embodiments, the driving circuit of the present disclosure can stop supplying power to the electronic unit 110 when the electronic unit 110 is short-circuited or damaged, thereby protecting the electronic unit 110 from an excessive current.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure. Moreover, the features of the embodiments can be arbitrarily mixed and matched without departing from the spirit or conflicting requirements of the invention.

Claims

1. An electronic device comprising a driving circuit, wherein the driving circuit comprises:

an electronic unit;

the driving unit is electrically connected with the electronic unit; and

a detection protection circuit electrically connected to the electronic unit via a first node and electrically connected to the gate terminal of the driving unit via a second node,

when the voltage of the first node is pulled down, the detection protection circuit controls the driving unit to be closed.

2. The electronic device of claim 1, wherein the detection protection circuit comprises:

a first transistor electrically connected to the second node, the first transistor configured to supply a first voltage to the second node to turn off the driving unit.

3. The electronic device of claim 2, wherein the detection protection circuit further comprises:

one end of the first capacitor is provided with a third node which is electrically connected with the grid end of the first transistor.

4. The electronic device of claim 3, wherein the detection protection circuit further comprises:

and one end of the second capacitor is electrically connected with the other end of the first capacitor, and the other end of the second capacitor receives a second voltage.

5. The electronic device of claim 3, wherein the detection protection circuit further comprises:

a second transistor electrically connected to the third node, the second transistor to supply the first voltage to the third node during a reset period.

6. The electronic device of claim 5, wherein the detection protection circuit further comprises:

and one end of the third capacitor is electrically connected with the third node, and the other end of the third capacitor receives the first voltage.

7. The electronic device of claim 3, wherein the detection protection circuit further comprises:

and a third transistor electrically connected to the first node, the third transistor being configured to turn on the first node and the other end of the first capacitor during a detection period or a scanning period.

8. The electronic device of claim 7, wherein the detection protection circuit further comprises:

and the resistor is electrically connected to the third transistor and the other end of the first capacitor.

9. The electronic device of claim 3, wherein the detection protection circuit further comprises:

a reset unit electrically connected to the other end of the first capacitor, the reset unit to supply a reset voltage or the first voltage to the other end of the first capacitor during a reset period.

10. The electronic device of claim 3, wherein the detection protection circuit further comprises:

a reset unit electrically connected to the first node, the reset unit to supply a reset voltage or a reference voltage to the first node during a reset period.

11. The electronic device of claim 3, wherein the detection protection circuit further comprises:

and one end of the diode is electrically connected with the third node.

12. The electronic device of claim 11, wherein the detection protection circuit further comprises:

and a third transistor electrically connected to the first node, the third transistor being configured to turn on the first node and the other end of the diode during a scanning period.

13. The electronic device of claim 1, wherein the driving unit is electrically connected to a switching unit via the second node, the driving unit is electrically connected to the first node via a control unit, and the switching unit is configured to supply a data voltage to the second node during the scan period; and the control unit is used for closing during data writing so as to stop supplying power to the first node.

14. The electronic device of claim 1, wherein the electronic unit comprises a light emitting unit.

15. A driving method of a driving circuit, the driving circuit comprising an electronic unit, a driving unit and a detection protection circuit, wherein the driving unit is electrically connected to the electronic unit, the detection protection circuit is electrically connected to the electronic unit via a first node and is electrically connected to a gate terminal of the driving unit via a second node, the driving method comprising:

supplying a reset voltage to the first node during a reset by the detection protection circuit;

detecting, by the detection protection circuit, a voltage of the first node during a scan; and

when the voltage of the first node is pulled down, the driving unit is turned off through the detection protection circuit.