TWI828536B - Transistor structure and manufacturing method thereof - Google Patents

Abstract

A transistor structure including a substrate, a gate dielectric layer, a gate, an isolation structure, a first semiconductor layer, a first drift region, a first doped region, and a second doped region is provided. The gate dielectric layer is located on the substrate. The gate is located on the gate dielectric layer. The isolation structure is located in the substrate on one side of the gate. The isolation structure has a first recess. The first recess is located on one side of the gate. The first semiconductor layer is located on the isolation structure and in the first recess. The first drift region is located in the first semiconductor layer. A portion of the isolation structure is located between the bottom surface of the first drift region and the substrate. The first doped region is located in the first semiconductor layer. The first drift region is located between the first doped region and the gate. The second doped region is located on the other side of the gate.

Description

Transistor structure and manufacturing method

Embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof, and in particular, to a transistor structure and a manufacturing method thereof.

High voltage transistor components are widely used in various electronic products. With the advancement of technology, the size of electronic components continues to shrink, so it becomes more difficult to increase the breakdown voltage of high-voltage transistor components. Therefore, how to improve the breakdown voltage of high-voltage transistor components is the goal of continuous efforts.

The present invention provides a transistor structure and a manufacturing method thereof, which can increase the breakdown voltage.

The invention proposes a transistor structure, which includes a substrate, a gate dielectric layer, a gate electrode, an isolation structure, a first semiconductor layer, a first drift region, a first doping region and a second doping region. The gate dielectric layer is on the substrate. The gate is located on the gate dielectric layer. An isolation structure is located in the substrate on one side of the gate. The isolation structure has a first recess. The first recess is located on one side of the gate. The first semiconductor layer is on the isolation structure and in the first recess. A first drift region is located in the first semiconductor layer. Part of the isolation structure is located between the bottom surface of the first drift region and the substrate. The first doped region is in the first semiconductor layer. The first drift region is located between the first doped region and the gate. The second doped region is on the other side of the gate.

According to an embodiment of the present invention, in the above transistor structure, the first semiconductor layer may be connected to the substrate.

According to an embodiment of the invention, in the above transistor structure, the second doped region may be located in the substrate.

According to an embodiment of the present invention, in the above-mentioned transistor structure, the shape of the top-view pattern of the first drift region may be a finger type.

According to an embodiment of the present invention, the above transistor structure may further include a dielectric layer. The dielectric layer is on the first semiconductor layer and in the first recess.

According to an embodiment of the present invention, in the above transistor structure, the isolation structure may be further located in the substrate on the other side of the gate. The isolation structure may have a second recess. The second recess can be located on the other side of the gate.

According to an embodiment of the present invention, the above-mentioned transistor structure may further include a second semiconductor layer and a second drift region. The second semiconductor layer is on the isolation structure and in the second recess. The second doped region may be located in the second semiconductor layer. The second drift region may be located in the second semiconductor layer. The second drift region may be located between the second doped region and the gate. Part of the isolation structure may be located between the bottom surface of the second drift region and the substrate.

According to an embodiment of the present invention, the above transistor structure may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is on the first semiconductor layer and in the first recess. The second dielectric layer is on the second semiconductor layer and in the second recess.

According to an embodiment of the present invention, the above-mentioned transistor structure may further include a first contact window and a second contact window. The first contact window is electrically connected to the first doped region. The second contact window is electrically connected to the second doped region.

The invention proposes a method for manufacturing a transistor structure, which includes the following steps. Provide a base. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer. Create an isolation structure. An isolation structure is located in the substrate on one side of the gate. The isolation structure has a first recess. The first recess is located on one side of the gate. A first semiconductor layer is formed on the isolation structure and in the first recess. A first drift region is formed in the first semiconductor layer. Part of the isolation structure is located between the bottom surface of the first drift region and the substrate. A first doped region is formed in the first semiconductor layer. The first drift region is located between the first doped region and the gate. A second doped region is formed on the other side of the gate.

According to an embodiment of the present invention, in the above method for manufacturing a transistor structure, the second doped region may be formed in the substrate.

According to an embodiment of the present invention, in the above method for manufacturing a transistor structure, the method for forming an isolation structure may include the following steps. A layer of isolation material is formed in the substrate. The isolation material layer is patterned to form an isolation structure and a first recess.

According to an embodiment of the present invention, in the above method for manufacturing a transistor structure, the method for forming the first semiconductor layer and the first drift region may include the following steps. A layer of semiconductor material filling the first recess is formed. Part of the semiconductor material layer is removed to form a first semiconductor layer. An ion implantation process is performed on the first semiconductor layer to form a first drift region.

According to an embodiment of the present invention, the method for manufacturing the transistor structure may further include the following steps. A dielectric layer is formed on the first semiconductor layer and in the first recess. A portion of the dielectric layer is removed to form a first opening exposing a portion of the first semiconductor layer. An ion implantation process is performed on the first semiconductor layer exposed by the first opening to form a first doped region. A portion of the gate dielectric layer is removed to form a second opening exposing a portion of the second doped region.

According to an embodiment of the present invention, the method for manufacturing the transistor structure may further include the following steps. A first contact window is formed in the first opening. The first contact window is electrically connected to the first doped region. A second contact window is formed in the second opening. The second contact window is electrically connected to the second doped region.

According to an embodiment of the invention, in the method of manufacturing the transistor structure, the isolation structure may be further located in the substrate on the other side of the gate. The isolation structure may have a second recess. The second recess can be located on the other side of the gate.

According to an embodiment of the present invention, the method for manufacturing the transistor structure may further include the following steps. A second semiconductor layer is formed on the isolation structure and in the second recess. A second drift region is formed in the second semiconductor layer. The second doped region may be formed in the second semiconductor layer. The second drift region may be located between the second doped region and the gate. Part of the isolation structure may be located between the bottom surface of the second drift region and the substrate.

According to an embodiment of the present invention, in the above method for manufacturing a transistor structure, the first drift region and the second drift region may be formed simultaneously.

According to an embodiment of the present invention, the method for manufacturing the transistor structure may further include the following steps. A first dielectric layer is formed on the first semiconductor layer and in the first recess. A second dielectric layer is formed on the second semiconductor layer and in the second recess. A portion of the first dielectric layer is removed to form a first opening exposing a portion of the first semiconductor layer. A portion of the second dielectric layer is removed to form a second opening exposing a portion of the second semiconductor layer. An ion implantation process is performed on the first semiconductor layer exposed by the first opening and the second semiconductor layer exposed by the second opening to form a first doped region and a second doped region.

According to an embodiment of the present invention, the method for manufacturing the transistor structure may further include the following steps. A first contact window is formed in the first opening. The first contact window is electrically connected to the first doped region. A second contact window is formed in the second opening. The second contact window is electrically connected to the second doped region.

Based on the above, in the transistor structure and the manufacturing method thereof proposed by the present invention, since part of the isolation structure is located between the bottom surface of the first drift region and the substrate, the electric field in the vertical direction can be reduced, thereby improving the collapse of the transistor structure. voltage.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Examples are listed below and described in detail with reference to the drawings. However, the provided examples are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A to 1L are cross-sectional views of the manufacturing process of a transistor structure according to some embodiments of the present invention. FIG. 2 is a top view of some components of the transistor structure of FIG. 1L. 1A to 1L are cross-sectional views along the line I-I' in FIG. 2 . In the top view of FIG. 2 , some components in the cross-sectional view of FIG. 1L are omitted to clearly illustrate the positional relationship between the components in the top view of FIG. 2 .

Referring to Figure 1A, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Additionally, a well region 102 may be formed in the substrate 100 . In some embodiments, well region 102 may have a first conductivity type (eg, P-type).

Hereinafter, the first conductivity type and the second conductivity type may be one or the other of P-type conductivity type and N-type conductivity type respectively. In this embodiment, the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type, for example, but the invention is not limited thereto. In other embodiments, the first conductivity type may be N-type conductivity type, and the second conductivity type may be P-type conductivity type.

Next, a pad layer 104 may be formed on the substrate 100 . In some embodiments, the material of the pad layer 104 is, for example, a dielectric material such as silicon oxide. In some embodiments, the formation method of the cushion layer 104 is, for example, a thermal oxidation method.

A hard mask layer 106 may then be formed over the pad layer 104 . In some embodiments, the material of the hard mask layer 106 is, for example, a dielectric material such as silicon nitride. In some embodiments, the hard mask layer 106 is formed by a chemical vapor deposition method, for example.

Next, the hard mask layer 106, the pad layer 104 and the substrate 100 may be patterned to form the trench T1. In some embodiments, the hard mask layer 106, the pad layer 104, and the substrate 100 may be patterned through a photolithography process and an etching process (eg, a dry etching process).

Furthermore, an isolation material layer 108 filling the trench T1 may be formed. In some embodiments, the material of the isolation material layer 108 is, for example, a dielectric material such as silicon oxide. In some embodiments, the isolation material layer 108 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1B , the isolation material layer 108 located outside the trench T1 can be removed. Thereby, the isolation material layer 108 can be formed in the substrate 100 . In some embodiments, the isolation material layer 108 located outside the trench T1 is removed by, for example, chemical mechanical polishing.

Next, a patterned photoresist layer 110 may be formed on the hard mask layer 106 and the isolation material layer 108 . The patterned photoresist layer 110 may expose a portion of the isolation material layer 108 . In some embodiments, the patterned photoresist layer 110 may be formed by a photolithography process.

Referring to FIG. 1C , the patterned photoresist layer 110 can be used as a mask to remove part of the isolation material layer 108 . Thereby, the isolation material layer 108 can be patterned to form the isolation structure 108a and the recess R1. As a result, the isolation structure 108a has the recess R1. In some embodiments, the material of the isolation structure 108a is, for example, a dielectric material such as silicon oxide. In some embodiments, part of the isolation material layer 108 is removed by, for example, dry etching.

Next, the patterned photoresist layer 110 can be removed. In some embodiments, the patterned photoresist layer 110 is removed by, for example, dry stripping or wet stripping.

Referring to FIG. 1D , a semiconductor material layer 112 filling the recess R1 may be formed. In some embodiments, the material of the semiconductor material layer 112 is, for example, polycrystalline silicon. In some embodiments, the semiconductor material layer 112 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1E , a portion of the semiconductor material layer 112 can be removed to form the semiconductor layer 112a. Thereby, the semiconductor layer 112a can be formed on the isolation structure 108a and in the recess R1. In some embodiments, the bottom surface S2 of the semiconductor layer 112 a may be lower than the top surface S1 of the substrate 100 . In some embodiments, the material of the semiconductor layer 112a is, for example, polycrystalline silicon. In some embodiments, a method for removing part of the semiconductor material layer 112 is, for example, dry etching. In some embodiments, a method for removing part of the semiconductor material layer 112 is, for example, a combination of chemical mechanical polishing and dry etching.

Referring to FIG. 1F, an ion implantation process can be performed on the semiconductor layer 112a to form the drift region 114. Thereby, the drift region 114 can be formed in the semiconductor layer 112a. The partial isolation structure 108a is located between the bottom surface S3 of the drift region 114 and the substrate 100 . In some embodiments, a portion of the isolation structure 108a may be located between the bottom surface S3 of the drift region 114 and the well region 102 . In some embodiments, drift region 114 may have a second conductivity type (eg, N-type).

Referring to FIG. 1G , a dielectric material layer 116 filling the recess R1 may be formed. In some embodiments, the material of the dielectric material layer 116 is, for example, silicon oxide. In some embodiments, the material of the dielectric material layer 116 may be silicon oxide formed by a spin-on dielectric (SOD).

Referring to FIG. 1H, part of the dielectric material layer 116 can then be removed to form the dielectric layer 116a. Thereby, the dielectric layer 116a can be formed on the semiconductor layer 112a and in the recess R1. In some embodiments, during the process of removing part of the dielectric material layer 116 by dry etching, part of the isolation structure 108a may be removed at the same time, thereby reducing the height of the isolation structure 108a. In some embodiments, the material of the dielectric layer 116a is, for example, silicon oxide.

Referring to Figure 1I, the hard mask layer 106 can be removed. In some embodiments, the hard mask layer 106 is removed by, for example, wet etching. Next, the pad 104 may be removed. In some embodiments, during the process of removing the pad layer 104, part of the isolation structure 108a and part of the dielectric layer 116a may be removed simultaneously, thereby reducing the height of the isolation structure 108a and the height of the dielectric layer 116a. In some embodiments, the pad layer 104 is removed by, for example, wet etching.

Referring to FIG. 1J , a gate dielectric layer 118 is formed on the substrate 100 . In some embodiments, the gate dielectric layer 118 is made of silicon oxide, for example. In some embodiments, the gate dielectric layer 118 is formed by a thermal oxidation method, for example.

Next, the gate electrode 120 is formed on the gate dielectric layer 118 . The isolation structure 108a is located in the substrate 100 on one side of the gate 120. The recess R1 is located on one side of the gate 120 . In some embodiments, the material of the gate 120 is, for example, doped polysilicon. In some embodiments, the method for forming the gate 120 may include the following steps, but the invention is not limited thereto. First, a gate material layer (not shown) may be formed on the gate dielectric layer 118, the isolation structure 108a, and the dielectric layer 116a. Next, the gate material layer may be patterned through a photolithography process and an etching process (eg, a dry etching process) to form the gate electrode 120 .

Then, a doped region 122 is formed on the other side of the gate 120 . In some embodiments, doped region 122 may be formed in substrate 100 . In some embodiments, the doped region 122 may have a second conductivity type (eg, N-type). In some embodiments, the doping region 122 is formed by, for example, an ion implantation method.

Referring to FIG. 1K , a dielectric layer 124 may be formed on the gate 120 , the gate dielectric layer 118 , the isolation structure 108 a and the dielectric layer 116 a. In some embodiments, the material of the dielectric layer 124 is, for example, borophosphosilicate glass (BPSG). In some embodiments, the dielectric layer 124 is formed by a chemical vapor deposition method, for example.

Next, a portion of the dielectric layer 124 and a portion of the dielectric layer 116a can be removed to form an opening OP1 exposing a portion of the semiconductor layer 112a. In some embodiments, the opening OP1 may be formed by removing part of the dielectric layer 124 and part of the dielectric layer 116a through a photolithography process and an etching process (eg, a dry etching process).

Referring to FIG. 1L , an ion implantation process can be performed on the semiconductor layer 112 a exposed by the opening OP1 to form a doped region 126 . Thereby, the doped region 126 can be formed in the semiconductor layer 112a. The drift region 114 is between the doped region 126 and the gate 120 . In some embodiments, doped region 126 may have a second conductivity type (eg, N-type).

Next, a portion of the dielectric layer 124 and a portion of the gate dielectric layer 118 can be removed to form an opening OP2 that exposes a portion of the doped region 122 . In some embodiments, a portion of the dielectric layer 124 and a portion of the gate dielectric layer 118 may be removed through a photolithography process and an etching process (eg, a dry etching process) to form the opening OP2.

Next, a contact window 128 may be formed in the opening OP1. The contact window 128 is electrically connected to the doped region 126 . In addition, a contact window 130 may be formed in the opening OP2. The contact window 130 is electrically connected to the doped region 122 . In some embodiments, the material of the contact window 128 and the material of the contact window 130 is, for example, conductive material such as tungsten. In some embodiments, the method of forming the contact window 128 and the contact window 130 may include the following steps, but the invention is not limited thereto. First, a conductive material layer (not shown) filling the openings OP1 and OP2 may be formed. Next, the conductive material layer located outside the opening OP1 and the outside of the opening OP2 may be removed through a chemical mechanical polishing process to form the contact window 128 and the contact window 130 .

Hereinafter, the transistor structure 10 of the above embodiment will be described with reference to FIG. 1L and FIG. 2 . In addition, although the method for forming the transistor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1L and FIG. 2 , the transistor structure 10 includes a substrate 100 , a gate dielectric layer 118 , a gate electrode 120 , an isolation structure 108 a , a semiconductor layer 112 a , a drift region 114 , a doped region 126 and a doped region 122 . In some embodiments, transistor structure 10 may be a high voltage transistor element. In some embodiments, the transistor structure 10 may be an N-type metal oxide semiconductor (NMOS) transistor or a P-type metal oxide semiconductor (PMOS) transistor. In this embodiment, the transistor structure 10 is an N-type metal oxide semiconductor (NMOS) transistor.

Gate dielectric layer 118 is located on substrate 100 . Gate 120 is located on gate dielectric layer 118 . The isolation structure 108a is located in the substrate 100 on one side of the gate 120. The isolation structure 108a has a recess R1. The recess R1 is located on one side of the gate 120 .

The semiconductor layer 112a is located on the isolation structure 108a and in the recess R1. In some embodiments, semiconductor layer 112a may be connected to substrate 100. The drift region 114 is located in the semiconductor layer 112a. The partial isolation structure 108a is located between the bottom surface S3 of the drift region 114 and the substrate 100, thereby reducing the electric field in the vertical direction, thereby increasing the breakdown voltage of the transistor structure 10. In some embodiments, as shown in FIG. 2 , the shape of the top-view pattern of the drift region 114 may be a finger type, thereby further increasing the breakdown voltage of the transistor structure 10 . Doped region 126 is located in semiconductor layer 112a. The drift region 114 is between the doped region 126 and the gate 120 . The doped region 122 is on the other side of the gate 120 . In some embodiments, doped region 122 may be located in substrate 100 . In some embodiments, the doped region 126 can be used as a drain region, and the doped region 122 can be used as a source region.

The transistor structure 10 may further include a dielectric layer 116a. The dielectric layer 116a is located on the semiconductor layer 112a and in the recess R1. The transistor structure 10 may further include a contact window 128 and a contact window 130 . The contact window 128 is electrically connected to the doped region 126 . The contact window 130 is electrically connected to the doped region 122 .

In addition, the details of each component in the transistor structure 10 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again.

Based on the above embodiments, it can be seen that in the transistor structure 10 and the manufacturing method thereof, since the partial isolation structure 108 a is located between the bottom surface S3 of the drift region 114 and the substrate 100 , the electric field in the vertical direction can be reduced, thereby improving the transistor structure 10 breakdown voltage.

3A to 3L are cross-sectional views of the manufacturing process of a transistor structure according to other embodiments of the present invention. FIG. 4 is a top view of some components of the transistor structure of FIG. 3L. 3A to 3L are cross-sectional views along the II-II' section line in FIG. 4 . In the top view of FIG. 4 , some components in the cross-sectional view of FIG. 3L are omitted to clearly illustrate the positional relationship between the components in the top view of FIG. 4 .

Referring to Figure 3A, a substrate 200 is provided. In some embodiments, the substrate 200 may be a semiconductor substrate, such as a silicon substrate. Additionally, a well region 202 may be formed in the substrate 200 . In some embodiments, well region 202 may have a first conductivity type (eg, P-type).

Next, a pad layer 204 may be formed on the substrate 200 . In some embodiments, the material of the pad layer 204 is, for example, a dielectric material such as silicon oxide. In some embodiments, the formation method of the cushion layer 204 is, for example, a thermal oxidation method.

A hard mask layer 206 may then be formed over the cushion layer 204 . In some embodiments, the material of the hard mask layer 206 is, for example, a dielectric material such as silicon nitride. In some embodiments, the hard mask layer 206 is formed by a chemical vapor deposition method, for example.

Next, the hard mask layer 206, the pad layer 204, and the substrate 200 may be patterned to form the trench T2. In some embodiments, the hard mask layer 206, the pad layer 204, and the substrate 200 may be patterned through a photolithography process and an etching process (eg, a dry etching process).

Furthermore, an isolation material layer 208 filling the trench T2 may be formed. In some embodiments, the material of the isolation material layer 208 is, for example, a dielectric material such as silicon oxide. In some embodiments, the isolation material layer 208 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 3B , the isolation material layer 208 located outside the trench T2 can be removed. Thereby, the isolation material layer 208 can be formed in the substrate 200 . In some embodiments, the isolation material layer 208 located outside the trench T2 is removed by, for example, chemical mechanical polishing.

Next, a patterned photoresist layer 210 may be formed on the hard mask layer 206 and the isolation material layer 208 . The patterned photoresist layer 210 may expose a portion of the isolation material layer 208 . In some embodiments, the patterned photoresist layer 210 may be formed by a photolithography process.

Referring to FIG. 3C , the patterned photoresist layer 210 can be used as a mask to remove part of the isolation material layer 208 . Thereby, the isolation material layer 208 can be patterned to form the isolation structure 208a, the recess R2 and the recess R3. As a result, the isolation structure 208a may have the recess R2 and the recess R3. In some embodiments, the material of the isolation structure 208a is, for example, a dielectric material such as silicon oxide. In some embodiments, part of the isolation material layer 208 is removed by, for example, dry etching.

Next, the patterned photoresist layer 210 can be removed. In some embodiments, the removal method of the patterned photoresist layer 210 is, for example, a dry stripping method or a wet stripping method.

Referring to FIG. 3D , a semiconductor material layer 212 filling the recesses R2 and recesses R3 may be formed. In some embodiments, the material of the semiconductor material layer 212 is, for example, polycrystalline silicon. In some embodiments, the semiconductor material layer 212 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 3E, part of the semiconductor material layer 212 can be removed to form a semiconductor layer 212a and a semiconductor layer 212b. Thereby, the semiconductor layer 212a can be formed on the isolation structure 208a and in the recess R2, and the semiconductor layer 212b can be formed on the isolation structure 208a and in the recess R3. In some embodiments, the bottom surface S5 of the semiconductor layer 212a may be lower than the top surface S4 of the substrate 200, and the bottom surface S6 of the semiconductor layer 212b may be lower than the top surface S4 of the substrate 200. In some embodiments, the materials of the semiconductor layer 212a and the semiconductor layer 212b are, for example, polycrystalline silicon. In some embodiments, a method for removing part of the semiconductor material layer 212 is, for example, dry etching. In some embodiments, a method for removing part of the semiconductor material layer 212 is, for example, a combination of chemical mechanical polishing and dry etching.

Referring to FIG. 3F, an ion implantation process can be performed on the semiconductor layer 212a and the semiconductor layer 212b to form the drift region 214 and the drift region 216. Thereby, the drift region 214 can be formed in the semiconductor layer 212a, and the drift region 216 can be formed in the semiconductor layer 212b. In some embodiments, the drift region 214 and the drift region 216 may be formed simultaneously. The partial isolation structure 208a may be located between the bottom surface S7 of the drift region 214 and the substrate 200, and the partial isolation structure 208a may be located between the bottom surface S8 of the drift region 216 and the substrate 200. In some embodiments, the partial isolation structure 208a may be located between the bottom surface S7 of the drift region 214 and the well region 202, and the partial isolation structure 208a may be located between the bottom surface S8 of the drift region 216 and the well region 202. In some embodiments, the drift regions 214 and 216 may have a second conductivity type (eg, N-type).

Referring to FIG. 3G , a dielectric material layer 218 filling the recesses R2 and R3 may be formed. In some embodiments, the material of the dielectric material layer 218 is, for example, silicon oxide. In some embodiments, the dielectric material layer 218 may be silicon oxide formed from a spin-on dielectric (SOD).

Referring to FIG. 3H, a portion of the dielectric material layer 218 can then be removed to form a dielectric layer 218a and a dielectric layer 218b. Thereby, the dielectric layer 218a can be formed on the semiconductor layer 212a and in the recess R2, and the dielectric layer 218b can be formed on the semiconductor layer 212b and in the recess R3. In some embodiments, during the process of removing part of the dielectric material layer 218 by dry etching, part of the isolation structure 208a may be removed at the same time, thereby reducing the height of the isolation structure 208a. In some embodiments, the material of the dielectric layer 218a and the dielectric layer 218b is, for example, silicon oxide.

Referring to Figure 3I, the hard mask layer 206 can be removed. In some embodiments, the hard mask layer 206 is removed by, for example, wet etching. Next, the pad 204 may be removed. In some embodiments, during the process of removing the pad layer 204, part of the isolation structure 208a, part of the dielectric layer 218a, and part of the dielectric layer 218b may be removed simultaneously, thereby reducing the height of the isolation structure 208a and the thickness of the dielectric layer 218a. The height is the same as the height of dielectric layer 218b. In some embodiments, the pad layer 204 is removed by, for example, wet etching.

Referring to FIG. 3J , a gate dielectric layer 220 is formed on the substrate 200 . In some embodiments, the material of the gate dielectric layer 220 is, for example, silicon oxide. In some embodiments, the gate dielectric layer 220 is formed by a thermal oxidation method, for example.

Next, a gate electrode 222 is formed on the gate dielectric layer 220 . Isolation structure 208a may be located in substrate 200 on one side of gate 222. In some embodiments, the isolation structure 208a may be further located in the substrate 200 on the other side of the gate 222. The recess R2 may be located on one side of the gate 222 , and the recess R3 may be located on the other side of the gate 222 . In some embodiments, the material of the gate 222 is, for example, doped polysilicon. In some embodiments, the method for forming the gate 222 may include the following steps, but the invention is not limited thereto. First, a gate material layer (not shown) may be formed on the gate dielectric layer 220, the isolation structure 208a, the dielectric layer 218a, and the dielectric layer 218b. Next, the gate material layer may be patterned through a photolithography process and an etching process (eg, a dry etching process) to form the gate electrode 222 .

Referring to FIG. 3K, a dielectric layer 224 may be formed on the gate electrode 222, the gate dielectric layer 220, the isolation structure 208a, the dielectric layer 218a and the dielectric layer 218b. In some embodiments, the material of the dielectric layer 224 is, for example, borophosphosilicate glass (BPSG). In some embodiments, the dielectric layer 224 is formed by a chemical vapor deposition method, for example.

Next, a portion of the dielectric layer 224 and a portion of the dielectric layer 218a can be removed to form an opening OP3 exposing a portion of the semiconductor layer 212a. In addition, a portion of the dielectric layer 224 and a portion of the dielectric layer 218b can be removed to form an opening OP4 exposing a portion of the semiconductor layer 212b. In some embodiments, openings OP3 and openings OP4 may be formed by removing portions of dielectric layer 224, portions of dielectric layer 218a, and portions of dielectric layer 218b through a photolithography process and an etching process (eg, a dry etching process). .

Referring to FIG. 3L , an ion implantation process can be performed on the semiconductor layer 212 a exposed by the opening OP3 and the semiconductor layer 212 b exposed by the opening OP4 to form the doped region 226 and the doped region 228 . Thereby, the doped region 226 can be formed in the semiconductor layer 212a, and the doped region 228 can be formed on the other side of the gate electrode 222. In some embodiments, doped region 228 may be formed in semiconductor layer 212b. The drift region 214 may be located between the doped region 226 and the gate 222 , and the drift region 216 may be located between the doped region 228 and the gate 222 . In some embodiments, the doped regions 226 and 228 may have a second conductivity type (eg, N-type).

Next, a contact window 230 may be formed in the opening OP3. The contact window 230 is electrically connected to the doped region 226 . In addition, a contact window 232 may be formed in the opening OP4. The contact window 232 is electrically connected to the doped region 228 . In some embodiments, the material of the contact window 230 and the material of the contact window 232 is, for example, conductive material such as tungsten. In some embodiments, the method for forming the contact window 230 and the contact window 232 may include the following steps, but the invention is not limited thereto. First, a conductive material layer (not shown) filling the openings OP3 and OP4 may be formed. Next, the conductive material layer located outside the opening OP3 and the outside of the opening OP4 may be removed through a chemical mechanical polishing process to form the contact window 230 and the contact window 232 .

Hereinafter, the transistor structure 10 of the above embodiment will be described with reference to FIG. 3L and FIG. 4 . In addition, although the method for forming the transistor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIGS. 3L and 4 , the transistor structure 20 includes a substrate 200, a gate dielectric layer 220, a gate electrode 222, an isolation structure 208a, a semiconductor layer 212a, a drift region 214, a doped region 226 and a doped region 228. In some embodiments, transistor structure 20 may be a high voltage transistor element. In some embodiments, the transistor structure 20 may be an N-type metal oxide semiconductor (NMOS) transistor or a P-type metal oxide semiconductor (PMOS) transistor. In this embodiment, the transistor structure 10 is an N-type metal oxide semiconductor (NMOS) transistor.

The gate dielectric layer 220 is located on the substrate 200 . The gate 222 is located on the gate dielectric layer 220 . Isolation structure 208a is located in substrate 200 on one side of gate 222. Isolation structure 208a has recess R2. The recess R2 is located on one side of the gate 222 . In some embodiments, the isolation structure 208a may be further located in the substrate 200 on the other side of the gate 222. Isolation structure 208a may have recess R3. Recess R3 may be located on the other side of gate 222 .

The semiconductor layer 212a is located on the isolation structure 208a and in the recess R2. In some embodiments, semiconductor layer 212a may be connected to substrate 200. Drift region 214 is located in semiconductor layer 212a. The partial isolation structure 208a is located between the bottom surface S7 of the drift region 214 and the substrate 200, thereby reducing the electric field in the vertical direction, thereby increasing the breakdown voltage of the transistor structure 20. In some embodiments, as shown in FIG. 4 , the shape of the top-view pattern of the drift region 214 may be finger-like, thereby further increasing the breakdown voltage of the transistor structure 20 . Doped region 226 is located in semiconductor layer 212a. The drift region 214 is between the doped region 226 and the gate 222 . The doped region 228 is on the other side of the gate 222 . In some embodiments, doped region 226 can be used as a drain region, and doped region 228 can be used as a source region. In some embodiments, the distance D1 between the gate 222 and the doped region 226 (eg, the drain region) may be greater than the distance D2 between the gate 222 and the doped region 228 (eg, the source region), whereby This can further increase the breakdown voltage of the transistor structure 20 .

The transistor structure 20 may further include a semiconductor layer 212b and a drift region 216. The semiconductor layer 212b is located on the isolation structure 208a and in the recess R3. Semiconductor layer 212b may be connected to substrate 200. Doped region 228 may be located in semiconductor layer 212b. Drift region 216 may be located in semiconductor layer 212b. The drift region 216 may be located between the doped region 228 and the gate 222 . Part of the isolation structure 208a may be located between the bottom surface S8 of the drift region 216 and the substrate 200, thereby reducing the electric field in the vertical direction, thereby increasing the breakdown voltage of the transistor structure 20. In some embodiments, as shown in FIG. 4 , the shape of the top-view pattern of the drift region 216 may be finger-like, thereby further increasing the breakdown voltage of the transistor structure 20 .

The transistor structure 20 may further include a dielectric layer 218a and a dielectric layer 218b. The dielectric layer 218a is located on the semiconductor layer 212a and in the recess R2. The dielectric layer 218b is located on the semiconductor layer 212b and in the recess R3. The transistor structure 20 may further include contact windows 230 and contact windows 232 . The contact window 230 is electrically connected to the doped region 226 . The contact window 232 is electrically connected to the doped region 228 .

In addition, the details of each component in the transistor structure 20 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again.

Based on the above embodiments, it can be known that in the transistor structure 20 and the manufacturing method thereof, since the partial isolation structure 208a is located between the bottom surface S7 of the drift region 214 and the substrate 200, the electric field in the vertical direction can be reduced, thereby improving the transistor structure 20 breakdown voltage.

To sum up, in the transistor structure and the manufacturing method of the above embodiments, since part of the isolation structure is located between the bottom surface of the drift region and the substrate, the electric field in the vertical direction can be reduced, thereby increasing the breakdown voltage of the transistor structure. .

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10,20:Transistor structure 100,200: Base 102,202:Well area 104,204: Cushion 106,206:hard curtain layer 108,208: Isolation material layer 108a,208a: Isolation structure 110,210: Patterned photoresist layer 112,212: Semiconductor material layer 112a, 212a, 212b: semiconductor layer 114,214,216: Drift area 116,218: Dielectric material layer 116a,124,218a,218b,224: dielectric layer 118,220: Gate dielectric layer 120,222: Gate 122,126,226,228: Doped area 128,130,230,232:Contact window D1, D2: distance OP1, OP2, OP3, OP4: opening R1,R2,R3: depression S1, S4: top surface S2, S3, S5, S6, S7, S8: Bottom T1, T2: ditch

1A to 1L are cross-sectional views of the manufacturing process of a transistor structure according to some embodiments of the present invention. FIG. 2 is a top view of some components of the transistor structure of FIG. 1L. 3A to 3L are cross-sectional views of the manufacturing process of a transistor structure according to other embodiments of the present invention. FIG. 4 is a top view of some components of the transistor structure of FIG. 3L.

10: Transistor structure

100:Base

102:Well area

108a: Isolation structure

112a: Semiconductor layer

114:Drift area

116a,124: Dielectric layer

118: Gate dielectric layer

120: Gate

122,126: Doped area

128,130:Contact window

OP1, OP2: Open

R1: depression

S1: Top surface

S2, S3: bottom surface

T1: Ditch

Claims (20)

A transistor structure including: base; a gate dielectric layer located on the substrate; A gate electrode located on the gate dielectric layer; An isolation structure located in the substrate on one side of the gate, wherein the isolation structure has a first recess, and the first recess is located on one side of the gate; A first semiconductor layer located on the isolation structure and in the first recess; A first drift region is located in the first semiconductor layer, wherein part of the isolation structure is located between the bottom surface of the first drift region and the substrate; A first doped region is located in the first semiconductor layer, wherein the first drift region is located between the first doped region and the gate; and The second doped region is located on the other side of the gate. The transistor structure of claim 1, wherein the first semiconductor layer is connected to the substrate. The transistor structure of claim 1, wherein the second doped region is in the substrate. The transistor structure of claim 1, wherein the shape of the top-view pattern of the first drift region includes a finger shape. The transistor structure as described in claim 1 further includes: A dielectric layer is located on the first semiconductor layer and in the first recess. The transistor structure of claim 1, wherein the isolation structure is located in the substrate on the other side of the gate, the isolation structure has a second recess, and the second recess is located at the other side of the gate. The transistor structure as described in claim 6 further includes: A second semiconductor layer is located on the isolation structure and in the second recess, wherein the second doped region is located in the second semiconductor layer; and A second drift region is located in the second semiconductor layer, wherein the second drift region is located between the second doped region and the gate, and part of the isolation structure is located in the second between the bottom surface of the drift zone and the substrate. The transistor structure as described in claim 7 further includes: A first dielectric layer located on the first semiconductor layer and in the first recess; and A second dielectric layer is located on the second semiconductor layer and in the second recess. The transistor structure as described in claim 1 further includes: A first contact window is electrically connected to the first doped region; and The second contact window is electrically connected to the second doped region. A method for manufacturing a transistor structure, including: provide a base; forming a gate dielectric layer on the substrate; forming a gate electrode on the gate dielectric layer; Forming an isolation structure, wherein the isolation structure is located in the substrate on one side of the gate, the isolation structure has a first recess, and the first recess is located on one side of the gate; forming a first semiconductor layer on the isolation structure and in the first recess; forming a first drift region in the first semiconductor layer, wherein part of the isolation structure is located between a bottom surface of the first drift region and the substrate; forming a first doped region in the first semiconductor layer, wherein the first drift region is located between the first doped region and the gate; and A second doped region is formed on the other side of the gate. The method of manufacturing a transistor structure according to claim 10, wherein the second doped region is formed in the substrate. The method for manufacturing a transistor structure as claimed in claim 10, wherein the method for forming the isolation structure includes: forming a layer of isolation material in the substrate; and The isolation material layer is patterned to form the isolation structure and the first recess. The method of manufacturing a transistor structure according to claim 10, wherein the method of forming the first semiconductor layer and the first drift region includes: Forming a layer of semiconductor material filling the first recess; removing a portion of the semiconductor material layer to form the first semiconductor layer; and An ion implantation process is performed on the first semiconductor layer to form the first drift region. The manufacturing method of the transistor structure as described in claim 10 further includes: forming a dielectric layer on the first semiconductor layer and in the first recess; removing a portion of the dielectric layer to form a first opening that exposes a portion of the first semiconductor layer; Perform an ion implantation process on the first semiconductor layer exposed by the first opening to form the first doped region; and A portion of the gate dielectric layer is removed to form a second opening exposing a portion of the second doped region. The manufacturing method of the transistor structure as described in claim 14 further includes: forming a first contact window in the first opening, wherein the first contact window is electrically connected to the first doped region; and A second contact window is formed in the second opening, wherein the second contact window is electrically connected to the second doped region. The manufacturing method of a transistor structure according to claim 10, wherein the isolation structure is located in the substrate on the other side of the gate, the isolation structure has a second recess, and the second The recess is on the other side of the gate. The manufacturing method of the transistor structure as described in claim 16 further includes: forming a second semiconductor layer on the isolation structure and in the second recess; and A second drift region is formed in the second semiconductor layer, wherein the second doped region is formed in the second semiconductor layer, and the second drift region is located between the second doped region and the gate. between the poles, and part of the isolation structure is located between the bottom surface of the second drift region and the substrate. The method of manufacturing a transistor structure according to claim 17, wherein the first drift region and the second drift region are formed simultaneously. The manufacturing method of the transistor structure as described in claim 17 further includes: forming a first dielectric layer on the first semiconductor layer and in the first recess; forming a second dielectric layer on the second semiconductor layer and in the second recess; removing a portion of the first dielectric layer to form a first opening exposing a portion of the first semiconductor layer; removing a portion of the second dielectric layer to form a second opening exposing a portion of the second semiconductor layer; and An ion implantation process is performed on the first semiconductor layer exposed by the first opening and the second semiconductor layer exposed by the second opening to form the first doped region and the second doped region. The manufacturing method of the transistor structure as described in claim 19 further includes: forming a first contact window in the first opening, wherein the first contact window is electrically connected to the first doped region; and A second contact window is formed in the second opening, wherein the second contact window is electrically connected to the second doped region.

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